A distributed multi-process timing violation analysis method

Abstract

The present invention relates to a distributed multi-process timing violation analysis method, belonging to the field of electronic design automation. The method comprises the following steps: S1. Slicing a circuit diagram according to a driver port, wherein the sliced ​​data blocks include timing arcs, pin information, and connection information, wherein the connection data blocks include a start pin and an end pin; S2. Starting multiple processes, each process loads a sliced ​​data block, constructs a corresponding timing subgraph, and analyzes the timing subgraph, and establishes dependencies between the timing subgraphs through data exchange between the processes; S3. Each process reads the timing constraint information and process library file of the corresponding timing subgraph, then performs timing calculation and pin flip value calculation according to the topological sequence, and completes dependency propagation through inter-process communication; S4. Outputting timing information to multiple processes, completing timing reports, and reporting timing violations. The present invention greatly improves analysis efficiency through distributed computing and is applicable to all stages of synthesis.

Description

Technical Field

[0001] The invention belongs to the field of electronic design automation (EDA), and in particular relates to a distributed multi-process timing violation analysis method. Background Art

[0002] With the advancement of integrated circuit technology, the scale of modern integrated circuit design continues to increase. Traditional static timing analysis mainly uses single-machine multi-threading technology. This method is limited by the capabilities of a single machine, and timing analysis takes a long time. Due to the complexity of circuit structures, in order to improve the efficiency of timing analysis, distributed static timing analysis research has emerged. Existing distributed static timing analysis solutions include:

[0003] The invention patent application with application publication number CN112257365A discloses a method for establishing a timing diagram in parallel based on geometric information, including the following steps: dividing the circuit diagram into geometric blocks according to the geometric characteristics of the circuit diagram; starting multiple processes to establish a temporary timing diagram in each geometric block in parallel; and splicing the temporary timing diagram established in each geometric block into a complete timing diagram.

[0004] The invention patent application with application publication number CN113971383A discloses a distributed static timing analysis method, which extracts constraint-associated information and clock information from a circuit design file; determines a topology cone based on the information extracted from two or more cuts of the circuit design; and performs timing analysis on the cuts of the two or more cuts based on the topology cone.

[0005] The above-mentioned existing distributed solutions for static timing analysis usually place the entire path on a single host, which increases the complexity of segmentation. Moreover, due to the large differences in the number of path layers and circuit sizes, the efficiency of parallelization is reduced. In addition, the above-mentioned distributed static timing analysis method also needs to rely on the coordinate information of the device, which can only be applied to the physical stage and cannot be applied to the early stage. Summary of the Invention

[0006] The present invention provides a distributed multi-process timing violation analysis method to solve the problems of low parallel efficiency and inability to be applied in early stages in the existing distributed solutions of static timing analysis.

[0007] In order to solve the above technical problems, the technical solution provided by the present invention is:

[0008] The present invention relates to a distributed multi-process timing violation analysis method, which comprises the following steps:

[0009] S1. Split the circuit diagram according to the driver port. The split data block includes timing arc, pin information and connection information. The connection data block includes the start pin and the end pin.

[0010] S2. Start multiple processes, each of which loads a segmented data block, constructs a corresponding time series subgraph, analyzes the time series subgraph, and establishes dependencies between the time series subgraphs through data exchange between the processes.

[0011] S3. Each process reads the timing constraint information and process library file of the corresponding timing subgraph, then performs timing calculations and pin flip value calculations based on the topological order, completing dependency propagation through inter-process communication.

[0012] S4. Output timing information for multiple processes, complete timing reports, and report timing violations.

[0013] Preferably, the specific steps of S1 dividing the circuit diagram according to the driving ports are:

[0014] S1.1. Build a thread pool. The threads are divided into two parts: one is the producer thread, which is responsible for traversing the circuit diagram, and the other is the consumer thread, which is responsible for processing the traversed data.

[0015] S1.2. Traverse the circuit diagram sequentially using a single thread, read the pin and connection information, and place the obtained pin and connection information into a memory queue;

[0016] S1.3. Synchronously start the thread pool, read the pin and connection information in the above memory queue, extract the pin and connection attributes, and place the pins and connections into two arrays respectively, and perform array subscript calculation;

[0017] S1.4. Read the data in the array, serialize the data, and store it in the medium. Then, according to different array subscripts, place the pins and wires in different paths of the medium to complete the segmentation of the circuit diagram.

[0018] Preferably, in S1.3, the array size of the pins is set to m , for a given set of pins , let the hash function be ,in, is a mapping of the hash operation of the pin id, and Z is the integer value after the hash operation of the pin. All are mapped to the pin array, the pin ID is hashed and modulo, and the array subscript is calculated as follows: ; The array subscript is calculated as follows: ,in, l Indicates connection, A hash value representing the port ID of the connection driver.

[0019] Preferably, the specific steps of constructing a corresponding time sequence subgraph for each process in S2 and analyzing the time sequence subgraph include:

[0020] S2.1. Start the distributed system. Each process in the distributed system has a corresponding ID, which is numbered from 0 to m-1, where m is the size of the pin array. Each process reads the corresponding array based on its own ID and obtains the data in the array, thereby forming multiple partitions. Each process ID is used as the corresponding partition ID.

[0021] S2.2. Loading connection data in multiple processes and constructing a timing subgraph within the process , where V represents the pin set and E represents the connection set;

[0022] S2.3. Multiple processes simultaneously generate pin partition information, the partition information is a mapping of pins to partition ids, records each pin in which processes exist, and writes the information to a shared medium;

[0023] S2.4. The multi-process program reads the pin information and the pin partition information according to its own ID, traverses all partition IDs in the pin, and constructs the pin details information. The pin details information includes the basic attributes of the pin and the partition ID. Multiple copies of the pin details information are copied according to the partition ID and placed in the corresponding storage medium according to the partition index.

[0024] Preferably, the specific steps of calculating the timing and the pin flip value in S3 are:

[0025] S3.1. Multiple processes run in parallel, reading the timing constraint file and library mapping file information in the corresponding timing subgraph. Starting from the driver pin node with no dependencies, the calculation is performed in topological order. The pin's flip value is calculated based on the fan-out pin information, design constraints, and information in the library mapping file.

[0026] S3.2. The flip value of the driving pin is passed to all fan-out pins through the graph. For each fan-out pin, find the partition ID where the fan-out pin is located. The partition ID is calculated as follows: ,in, is the hash function of the pin id, m is the size of the pin array, and the flip value of the fan-out pin is propagated to other processes through the shared medium;

[0027] S3.3. Each process synchronously checks the storage medium, reads the flip value of the driver pin propagated to the process, and searches the timing subgraph for the pin corresponding to the flip value of the fan-out pin propagated to the process and the driver pin. If the flip value of the fan-in pin of the driver pin has been calculated, the delay of all timing arcs and the flip value of the driver pin are calculated with the driver pin as the center.

[0028] S3.4. Determine whether the delay calculation of the timing arc is completed. If not, return to S3.2 until each process completes the delay calculation of all timing arcs. If completed, it means that the calculation of the process is completed.

[0029] Preferably, the S4 multi-process output timing information completes the timing report, and the specific steps of reporting the timing violation calculation are:

[0030] S4.1. The master process synchronously collects the delay and rollover values ​​calculated by each process from the shared medium until it receives the end flag returned by all synchronized processes. It also marks the received delay and rollover values ​​in the timing diagram.

[0031] S4.2. The main process traverses all paths in the timing graph and accumulates the delay of each link in each path to calculate the arrival time. The calculation formula for the arrival time is: ,in, is the arrival time, is the delay of the connection in the path;

[0032] S4.3. The main process calculates the required arrival time based on the information of each path terminal pin, timing library information, and design constraints. When performing the establishment time check, the required arrival time is The calculation formula is: ,in, To capture the arrival time of the clock, is the clock period, is the setup time; when performing hold time checks, the arrival time is required The calculation formula is: ,in, To capture the arrival time of the clock, To keep time;

[0033] S4.4. The main process calculates the timing violation based on the arrival time and required arrival time in each timing path and completes the violation report.

[0034] When performing setup time checking, timing violations The calculation formula is:

[0035] ,

[0036] in, Indicates the arrival time calculated when establishing the time check;

[0037] When performing hold time checks, timing violations The calculation formula is:

[0038] ,

[0039] in, Indicates the arrival time calculated during the hold time check;

[0040] If the timing violation is a negative value, it means that there is a timing violation on this path, which is displayed in the violation report.

[0041] Preferably, after S1 divides the circuit diagram, the number of divided data is the same as the number of processes in S2.

[0042] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0043] 1. The distributed multi-process timing violation analysis method disclosed herein divides a circuit diagram into sections, launches multiple process programs, and each program reads data from its own partition or slice, then constructs a subgraph and exchanges data. Each of the multiple processes performs timing calculations, which involve inter-process data dependencies, and completes the overall timing calculation through communication. After the calculations are completed, each process outputs its results, and the stand-alone program loads the timing results to complete the timing analysis report. This method significantly improves analysis efficiency through distributed computing and is suitable for processing large-scale circuits.

[0044] 2. The present invention relates to a distributed multi-process timing violation analysis method that is independent of position coordinate information and the distribution characteristics of the circuit structure through data segmentation, distributed subgraph construction, and distributed timing analysis methods. It has good scalability and can be easily implemented using a distributed system and is applicable to all stages of synthesis. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a flow chart of a distributed multi-process timing violation analysis method;

[0046] Figure 2 It is a flow chart of circuit diagram segmentation;

[0047] Figure 3 It is a flowchart in which each process constructs a corresponding timing subgraph and analyzes the timing subgraph;

[0048] Figure 4 This is a flowchart of timing calculation and pin toggle value calculation. DETAILED DESCRIPTION

[0049] In order to further understand the content of the present invention, the present invention is described in detail with reference to the examples. The following examples are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0050] Refer to the attached Figure 1 As shown, the present invention relates to a distributed multi-process timing violation analysis method comprising the following steps:

[0051] S1. Divide the circuit diagram according to the drive port, refer to the attached Figure 2 As shown, the specific steps are:

[0052] S1.1. Build a thread pool. The threads are divided into two parts: one is the producer thread, which is responsible for traversing the circuit diagram, and the other is the consumer thread, which is responsible for processing the traversed data.

[0053] S1.2. Use a single-threaded approach to sequentially traverse the circuit diagram, read the pin and connection information, and place the obtained pin and connection information into a memory queue, called Queue A.

[0054] S1.3. Synchronously start the thread pool, read the pin information and connection information in the A queue in the memory, extract the properties of the pins and connections, and put the pins and connections into two arrays respectively. The array size of the pins is set to m , for a given set of pins , let the hash function be ,in, is a mapping of the hash operation of the pin id, and Z is the integer value after the hash operation of the pin. All are mapped to the pin array, the pin ID is hashed and modulo, and the array subscript is calculated as follows: ; The array size of the connection is also set to m , the array subscript is calculated as: ,in, l Indicates connection, Indicates the hash value of the line driver port ID. Assume that the unique ID of a pin is 100, that is v = 100. Let the hash function The result of a standard integer hash operation on this integer value is the hash input, that is, h (100) = 100, if the pin array size is m =100, then the subscript of the pin array is: h (100)%10=100%10=0, that is, the pin is stored in the 0th item of the pin array. The calculation method of the connection array subscript is the same as the calculation method of the pin array subscript.

[0055] S1.4. Read the data in the array, serialize the data, and store it in a medium, which can be a network shared disk, a cache database, a document database, etc.; for a cache database, the data in the array can be placed in different key values ​​according to the subscript index. For example, the key of the data with the subscript index of 0 in the pin array can be "q_pin:0", and the value can adopt a queue structure to store pin and connection information, and then place the pins and connections in different paths according to different array subscripts to complete the circuit diagram segmentation. After segmentation, the number of subscript indexes of the segmented data is the same as the number of processes of the distributed system used subsequently.

[0056] The segmented data block includes timing arcs, pin information and connection information, wherein the connection data block includes a start pin and an end pin;

[0057] S2. Start multiple processes, each process loads a segmented data block, builds the corresponding time sequence subgraph, and analyzes the time sequence subgraph. Figure 3 As shown, the specific steps include:

[0058] S2.1. Start the distributed system. Each process in the distributed system has a corresponding ID. The IDs are numbered from 0 to m-1, where m is the size of the pin array. Each process reads the corresponding key to obtain data from the array based on its own ID. For example, if the process ID is 0, the pin to be read is located in the "q_pin:0" queue. This step can form multiple partitions, and each process ID is used as the corresponding partition ID.

[0059] S2.2. Loading connection data in multiple processes and constructing a timing subgraph within the process , where V represents the pin set, E represents the connection set, and the timing subgraph is a graph structure. The dependency relationship between timing subgraphs can be constructed based on the connection information and timing arc information. Let <P i , P o > is a pair of lines or time arcs, where P i , P o For pin id, construct a P i Point to P o In the calculation, P o Dependency P i , P i P o The fan-in pin, P o P i fan-out pins.

[0060] S2.3. Multiple processes simultaneously generate pin partition information, which is a mapping of a pin to a partition id, recording which processes each pin exists in, and writing this information to a shared medium. This information is stored in an array in memory. The array type can be a variable array, and the array size is set to m. The subscript of the corresponding record is the hash value;

[0061] S2.4. The multi-process program reads the pin information and the pin partition information according to its own ID, traverses all partition IDs in the pin, and constructs the pin details information. The pin details information includes the basic attributes of the pin and the partition ID. Multiple copies of the pin details information are copied according to the partition ID and placed into the corresponding storage medium according to the hash value.

[0062] Each process also establishes dependencies between sequential subgraphs through data exchange;

[0063] S3. Each process reads the timing constraint information and process library file of the corresponding timing subgraph, and then performs timing calculation and pin flip value calculation according to the topological order, and completes dependency propagation through inter-process communication; the specific steps of timing calculation and pin flip value calculation are as follows: Figure 4 As shown, the specific steps are:

[0064] S3.1. Multiple processes run in parallel, reading the timing constraint file and library mapping file information in the corresponding timing subgraph. Starting from the driver pin node with no dependencies, the calculation is performed in topological order. The pin's flip value is calculated based on the fan-out pin information, design constraints, and information in the library mapping file.

[0065] S3.2. The flip of the driving pin is propagated to all fan-out pins through the graph. For each fan-out pin, find the partition ID where the fan-out pin is located. The partition ID is calculated as ,in, is the hash function of the pin id, m is the size of the pin array, and the flip value of the fan-out pin is propagated to other processes through the shared medium;

[0066] S3.3. Each process synchronously checks the storage medium, reads the flip value of the driver pin propagated to the process, and searches the timing subgraph for the pin corresponding to the flip value of the fan-out pin propagated to the process and the driver pin. If the flip value of the fan-in pin of the driver pin has been calculated, the delay of all timing arcs and the flip value of the driver pin are calculated with the driver pin as the center.

[0067] S3.4. Determine whether the delay calculation of the timing arc is completed. If not, return to S3.2 until each process completes the delay calculation of all timing arcs. If completed, it means that the calculation of the process is completed.

[0068] S4. Output timing information for multiple processes, complete timing reports, and report timing violations. The specific steps for reporting timing violation calculations are:

[0069] S4.1. The master process synchronously collects the delay and rollover values ​​calculated by each process from the shared medium until it receives the end flag returned by all synchronized processes. It also marks the received delay and rollover values ​​in the timing diagram.

[0070] S4.2. The main process traverses all paths in the timing graph and accumulates the delay of each link in each path to calculate the arrival time. The calculation formula for the arrival time is: ,in, is the arrival time, is the delay of the connection in the path. Assume that there is a timing path that passes through CLK, DFF1:Q, AND:A, AND:Z, and DFF2:D pins. The delay between CLK and DFF1:Q is T 1 is 0.1ns, the delay between DFF1:Q and AND:A T2 The delay between AND:A and AND:Z is 0.2ns. T3 The delay between AND:Z and DFF2:D is 0.1ns. T4 is 0.1ns, then the arrival time is:

[0071] .

[0072] S4.3. The main process calculates the required arrival time based on the information of each path terminal pin, timing library information, and design constraints. When performing the establishment time check, the required arrival time The calculation formula is: ,in, To capture the arrival time of the clock, is the clock period, is the setup time; when performing hold time checks, the arrival time is required The calculation formula is: ,in, To capture the arrival time of the clock, To keep time, for the example in S4.2, assume that the arrival time of the capture clock is , clock cycle , establishment time , keep time , then when establishing time check, the required arrival time is , when performing hold time check, the required arrival time is:

[0073] S4.4. The main process calculates the timing violation based on the arrival time and required arrival time in each timing path and completes the violation report.

[0074] When performing setup time checking, timing violations The calculation formula is:

[0075] ,

[0076] in, Indicates the arrival time calculated when establishing the time check. For the examples of S4.2 and S4.3, ;

[0077] When performing hold time checks, timing violations The calculation formula is:

[0078] ,

[0079] in, Represents the arrival time calculated during the hold time check. For the examples in S4.2 and S4.3, ;

[0080] If the timing violation is a negative value, it means that there is a timing violation on this path, which is displayed in the violation report. In this example, A negative value indicates that the data has not remained stable before the effective clock edge arrives. At this time, the capture trigger collects unstable data, which does not meet the setup time check. This record should be displayed in the timing report. In addition, the timing report not only records the information of this path (start pin information, end pin information, etc.), but also records the delay information from the starting node to all nodes in the path, as well as the calculation results of AT and RAT, and displays Slack in the last line.

[0081] The present invention has been described in detail above with reference to the embodiments. However, the contents described are only preferred embodiments of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A distributed multi-process timing violation analysis method, characterized by: It includes the following steps: S1. Split the circuit diagram according to the driver port. The split data block includes timing arc, pin information and connection information. The connection data block includes the start pin and the end pin. S2. Start multiple processes. Each process loads a segmented data block, constructs a corresponding time series subgraph, and analyzes the time series subgraph. The processes also establish dependencies between the time series subgraphs through data exchange. The specific steps include: S2.

1. Start the distributed system. Each process in the distributed system has a corresponding ID, which is numbered from 0 to m-1, where m is the size of the pin array. Each process reads the corresponding array based on its own ID and obtains the data in the array, thereby forming multiple partitions. Each process ID is used as the corresponding partition ID. S2.

2. Loading connection data in multiple processes and constructing a timing subgraph within the process , where V represents the pin set and E represents the connection set; S2.

3. Multiple processes simultaneously generate pin partition information, the partition information is a mapping of pins to partition ids, records each pin in which processes exist, and writes the information to a shared medium; S2.

4. The multi-process program reads the pin information and the pin partition information according to its own ID, traverses all the partition IDs in the pin, and constructs the pin details information, which includes the basic attributes of the pin and the partition ID. It copies multiple copies of the pin details information according to the partition ID and puts them into the corresponding storage medium according to the partition index; S3. Each process reads the timing constraint information and process library file of the corresponding timing subgraph, then performs timing calculations and pin flip value calculations based on the topological order, completing dependency propagation through inter-process communication. The specific steps for timing calculation and pin toggle value calculation are: S3.

1. Multiple processes run in parallel, reading the timing constraint file and library mapping file information in the corresponding timing subgraph. Starting from the driver pin node with no dependencies, the calculation is performed in topological order. The pin's flip value is calculated based on the fan-out pin information, design constraints, and information in the library mapping file. S3.

2. The flip value of the driving pin is passed to all fan-out pins through the graph. For each fan-out pin, find the partition ID where the fan-out pin is located. The partition ID is calculated as follows: ,in, is the hash function of the pin id, m is the size of the pin array, and the flip value of the fan-out pin is propagated to other processes through the shared medium; S3.

3. Each process synchronously checks the storage medium, reads the flip value of the driver pin propagated to the process, and searches the timing subgraph for the pin corresponding to the flip value of the fan-out pin propagated to the process and the driver pin. If the flip value of the fan-in pin of the driver pin has been calculated, the delay of all timing arcs and the flip value of the driver pin are calculated with the driver pin as the center. S3.

4. Determine whether the delay calculation of the timing arc is completed. If not, return to S3.2 until each process completes the delay calculation of all timing arcs. If it is completed, it means that the calculation of the process is completed; S4. Output timing information for multiple processes, complete timing reports, and report timing violations.

2. The distributed multi-process timing violation analysis method according to claim 1, wherein: The specific steps of S1 dividing the circuit diagram according to the driving port are: S1.

1. Build a thread pool. The threads are divided into two parts: one is the producer thread, which is responsible for traversing the circuit diagram, and the other is the consumer thread, which is responsible for processing the traversed data. S1.

2. Traverse the circuit diagram sequentially using a single thread, read the pin and connection information, and place the obtained pin and connection information into a memory queue; S1.

3. Synchronously start the thread pool, read the pin and connection information in the above memory queue, extract the pin and connection attributes, and place the pins and connections into two arrays respectively, and perform array subscript calculation; S1.

4. Read the data in the array, serialize the data, and store it in the medium. Then, according to different array subscripts, place the pins and wires in different paths of the medium to complete the segmentation of the circuit diagram.

3. The distributed multi-process timing violation analysis method according to claim 2, wherein: In S1.3, the array size of the pins is set to m , for a given set of pins , let the hash function be ,in, is a mapping of the hash operation of the pin id, and Z is the integer value after the hash operation of the pin. All are mapped to the pin array, the pin ID is hashed and modulo, and the array subscript is calculated as follows: ; The array size of the connection is also set to m , the array subscript is calculated as: ,in, l Indicates connection, A hash value representing the port ID of the connection driver.

4. The distributed multi-process timing violation analysis method according to claim 1, wherein: The S4 multi-process output timing information completes the timing report. The specific steps of reporting the timing violation calculation are: S4.

1. The master process synchronously collects the delay and rollover values ​​calculated by each process from the shared medium until it receives the end flag returned by all synchronized processes. It also marks the received delay and rollover values ​​in the timing diagram. S4.

2. The main process traverses all paths in the timing graph and accumulates the delay of each link in each path to calculate the arrival time. The calculation formula for the arrival time is: ,in, is the arrival time, is the delay of the connection in the path; S4.

3. The main process calculates the required arrival time based on the information of each path terminal pin, timing library information, and design constraints. When performing the establishment time check, the required arrival time The calculation formula is: ,in, To capture the arrival time of the clock, is the clock period, is the setup time; when performing hold time checks, the arrival time is required The calculation formula is: ,in, To capture the arrival time of the clock, To keep time; S4.

4. The main process calculates the timing violation based on the arrival time and required arrival time in each timing path and completes the violation report. When performing setup time checking, timing violations The calculation formula is: ， in, Indicates the arrival time calculated when establishing the time check; When performing hold time checks, timing violations The calculation formula is: ， in, Indicates the arrival time calculated during the hold time check; If the timing violation is a negative value, it means that there is a timing violation on this path, which is displayed in the violation report.

5. The distributed multi-process timing violation analysis method according to claim 1, wherein: After S1 divides the circuit diagram, the number of divided data is the same as the number of processes in S2.

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