Integrated circuit verification system, method and equipment and storage medium

Abstract

The invention discloses an integrated circuit verification system, an integrated circuit verification method, integrated circuit verification equipment and a storage medium, and relates to the technical field of integrated circuits. Each verification subsystem comprises a plurality of hardware computing units for realizing direct interconnection of signals, and the communication delay between the hardware computing units is shortened while hardware resource expansion is realized, so that the time consumption for functional verification of the integrated circuit is reduced, and the functional verification efficiency of the integrated circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular, to an integrated circuit verification system, method, device, and storage medium. Background Art

[0002] In the field of integrated circuits, the scale and complexity of integrated circuits such as chips are constantly increasing, and the importance of the preliminary verification work is becoming increasingly prominent. The Field-Programmable Gate Array (FPGA) prototype verification platform has been widely used in the functional verification of integrated circuits because it can provide a hardware operating environment close to that of a real chip.

[0003] However, the hardware resources of the FPGA prototype verification platform in the related art are limited. In the case of complex integrated circuit functions, the verification often takes a long time, reducing the efficiency of the functional verification of integrated circuits. Summary of the Invention

[0004] The present application provides an integrated circuit verification system, method, device, and storage medium to at least solve the problem that the verification takes a long time in the related art, reducing the efficiency of the functional verification of integrated circuits.

[0005] The present application provides an integrated circuit verification system, including: a synthesis device and multiple verification subsystems, and each verification subsystem includes multiple hardware computing units;

[0006] The synthesis device is used to split the functional verification service of the integrated circuit to be verified into multiple sub-services and allocate the multiple sub-services to the multiple verification subsystems;

[0007] The verification subsystem is used to receive and execute the sub-service to verify the integrated circuit sub-function corresponding to the sub-service, and obtain the sub-function verification result corresponding to the integrated circuit sub-function;

[0008] For any verification subsystem, the hardware computing units in the verification subsystem are connected by direct connection signal lines, so that the hardware computing units in the verification subsystem are directly interconnected, and the verification subsystem executes the sub-service based on the directly interconnected multiple hardware computing units.

[0009] The present application also provides an integrated circuit verification method, which is applied to the verification subsystem of any of the above integrated circuit verification systems. The method includes:

[0010] Obtain any sub-service allocated by the synthesis device; wherein, the synthesis device splits the functional verification service of the integrated circuit to be verified into multiple sub-services;

[0011] Split the sub - service into multiple micro - services, and allocate the micro - services to different hardware computing units to execute the micro - services based on the hardware computing units, and obtain the micro - service execution results generated by each hardware computing unit;

[0012] Summarize the micro - service execution results generated by each hardware computing unit to obtain the sub - service execution result, and feedback the sub - service execution result to the integrated device;

[0013] Among them, the integrated device obtains the functional verification result of the integrated circuit to be verified by summarizing the sub - service execution results fed back by each verification subsystem.

[0014] This application also provides an integrated circuit verification device, including: any one of the above - mentioned integrated circuit verification systems.

[0015] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any one of the above - mentioned integrated circuit verification methods when executing the computer program.

[0016] This application also provides a computer - readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above - mentioned integrated circuit verification methods are implemented.

[0017] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any one of the above - mentioned integrated circuit verification methods are implemented.

[0018] Through this application, since the functional verification service of the integrated circuit to be verified is split into multiple sub - services and allocated to different verification subsystems for execution, and each verification subsystem includes multiple hardware computing units that achieve direct signal interconnection, while realizing the expansion of hardware resources, the communication delay between each hardware computing unit is reduced, thereby reducing the time consumed for the functional verification of the integrated circuit, and further improving the efficiency of the functional verification of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic diagram of the interaction process of the integrated circuit verification system provided by the embodiment of this application;

[0021] Figure 2 It is a schematic diagram of the structure of an exemplary integrated circuit verification system provided by the embodiment of this application;

[0022] Figure 3 Schematic diagram of a verification subsystem provided by an embodiment of the present application;

[0023] Figure 4 Schematic diagram of a hardware computing unit provided by an embodiment of the present application;

[0024] Figure 5 Schematic diagram of another verification subsystem provided by an embodiment of the present application;

[0025] Figure 6 Schematic diagram of yet another verification subsystem provided by an embodiment of the present application;

[0026] Figure 7 Schematic diagram of an integrated circuit verification method provided by an embodiment of the present application;

[0027] Figure 8 Schematic diagram of an integrated circuit verification device provided by an embodiment of the present application;

[0028] Figure 9 Schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0030] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0031] With the continuous development of integrated circuits, the device scale has become increasingly large, the functions have become more and more complex, and the production cycle has become longer and longer. Many factors have caused the cost to become more and more expensive, which puts forward more rigorous and comprehensive requirements for the early verification work. Pure software and dynamic simulation cannot compare with the working speed of actual integrated circuits in terms of speed, so some hidden problems will not be discovered. In a System on Chip (SOC), the complexity of software is getting higher and higher. The FPGA prototype verification platform can meet the needs of more software development. Compared with software simulation, it is faster and occupies fewer resources. In addition, the main advantage of the FPGA prototype verification platform is that it provides a reliable hardware platform, enabling software to be developed in the initial stage of the project, greatly shortening the R & D cycle.

[0032] However, the hardware resources of the FPGA prototype verification platform in the related technology are limited. In the case of complex functions of integrated circuits, the verification often takes a long time, reducing the efficiency of the functional verification of integrated circuits.

[0033] The embodiment of the present application provides an integrated circuit verification system, method, device and storage medium to solve the above technical problems. The system includes: a synthesis device and multiple verification subsystems, and each verification subsystem includes multiple hardware computing units; the synthesis device is used to split the functional verification service of the integrated circuit to be verified into multiple sub-services and allocate the multiple sub-services to the multiple verification subsystems; the verification subsystem is used to receive and execute the sub-service to verify the integrated circuit sub-function corresponding to the sub-service and obtain the sub-function verification result corresponding to the integrated circuit sub-function; for any verification subsystem, the hardware computing units in the verification subsystem are connected by direct connection signal lines, so that the hardware computing units in the verification subsystem are directly interconnected, and the verification subsystem executes the sub-service based on the directly interconnected multiple hardware computing units. The system provided by the above solution splits the functional verification service of the integrated circuit to be verified into multiple sub-services and allocates them to different verification subsystems for execution, and each verification subsystem includes multiple hardware computing units that realize direct signal interconnection. While realizing the expansion of hardware resources, the communication delay between the hardware computing units is reduced, thereby reducing the time-consuming of the functional verification of the integrated circuit, and further improving the efficiency of the functional verification of the integrated circuit.

[0034] In order to enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0035] The embodiment of the present application provides an integrated circuit verification system for verifying the software functions of integrated circuits such as chips.

[0036] As Figure 1As shown in the figure, it is a schematic diagram of the interaction process of the integrated circuit verification system provided by the embodiment of the present application. The system includes: a synthesis device and multiple verification subsystems, and each verification subsystem includes multiple hardware computing units.

[0037] Among them, the synthesis device is used to split the functional verification service of the integrated circuit to be verified into multiple sub-services and allocate the multiple sub-services to multiple verification subsystems; the verification subsystem is used to receive and execute the sub-service to verify the integrated circuit sub-function corresponding to the sub-service and obtain the sub-function verification result corresponding to the integrated circuit sub-function; for any verification subsystem, the various hardware computing units in the verification subsystem are connected by direct connection signal lines, so that the various hardware computing units in the verification subsystem can achieve direct interconnection, and the verification subsystem executes the sub-service based on the multiple directly interconnected hardware computing units.

[0038] It should be noted that the integrated circuit to be verified includes a central processing unit to be verified, an image processing chip to be verified, etc., and the functional verification service includes instruction set correctness verification, performance index verification, etc.

[0039] Specifically, due to the complex functions of modern integrated circuits and the high difficulty of overall verification, the synthesis device can break down the complex functional verification service into multiple relatively independent sub-services according to factors such as the functional module division, data flow, and processing flow of the integrated circuit. The synthesis device allocates these sub-services to different verification subsystems according to factors such as the resource status of each verification subsystem (such as the number and performance of hardware computing units), and the verification fields it is good at, to ensure the efficient and orderly development of the verification work. Each sub-service corresponds to a specific sub-function of the integrated circuit, and the verification subsystem designs and executes verification tests for these sub-functions to obtain the corresponding sub-function verification results. These results are used to judge whether each sub-function of the integrated circuit meets the design requirements and whether there are functional defects.

[0040] Specifically, inside each verification subsystem, the various hardware computing units are connected by direct connection signal lines. This direct interconnection method is to improve data transmission efficiency. Compared with the bus connection method, the direct connection signal line can reduce congestion and delay in the data transmission process, enabling the hardware computing units to exchange data more quickly and stably. When executing the sub-service, the various hardware computing units cooperate based on the advantages of this direct interconnection to achieve parallel data processing, or can also process the data sequentially according to a specific processing flow to jointly complete the verification task of the sub-service. Taking the sub-service of verifying a complex digital signal processing algorithm as an example, one hardware computing unit may be responsible for preprocessing the input data, another for executing the core algorithm operation, and another for comprehensively processing the operation result. The data is quickly transmitted through the direct connection signal line to efficiently complete the verification work.

[0041] Exemplarily, such asFigure 2 As shown in the figure, it is a schematic structural diagram of an exemplary integrated circuit verification system provided by an embodiment of the present application. The FPGA prototype verification platform includes multiple verification subsystems. Each verification subsystem can perform FPGA verification of set functions and performance. After each verification subsystem is synthesized, the resources of each synthesized verification subsystem are fed back to the synthesis device to form a complete verification system. Among them, a series of complex processes such as compilation, conversion, scheduling, allocation, and controller synthesis need to be implemented in each FPGA verification subsystem. This series of operations is complex and requires high precision. The system provided by the embodiment of the present application is actually to solve the problems of limited resources and excessive time consumption of the prototype verification system in large-scale integrated circuit design. The embodiment of the present application actually proposes a prototype verification platform with multi-FPGA interconnection. Users can split the entire design into different FPGAs, so the resource occupancy rate of each FPGA is reduced, synthesis and placement and routing are easier, and the time to generate the bit file is also less, thereby reducing the verification time. In addition, each FPGA can be synthesized, placed and routed, and the bit file can be generated independently without affecting each other. Therefore, splitting a large-scale design into small-scale designs on different FPGAs, each FPGA runs simultaneously to generate the bit file, greatly improving the efficiency. Among them, the bit file is a file format that converts the logical function of the chip design into configuration information executable by the FPGA.

[0042] Based on the above embodiment, as Figure 3 It is a schematic structural diagram of a verification subsystem provided by an embodiment of the present application. As an implementable manner, in one embodiment, each hardware computing unit is provided with a time-division multiplexing module; the time-division multiplexing module is used to multiplex the direct connection signal lines between the local hardware computing unit and other hardware computing units in different time slots.

[0043] Among them, the local hardware computing unit and other hardware computing units belong to the same verification subsystem.

[0044] It should be noted that the role of the time-division multiplexing module in the integrated circuit verification system provided by the embodiment of the present application is to realize the efficient utilization of the direct connection signal line resources. The time-division multiplexing module (TDM) can integrate multiple signals and transmit them on one physical line. The time-division multiplexing module can divide time into a series of non-overlapping time slots. For the local hardware computing unit and other hardware computing units within the same verification subsystem, they are connected by direct connection signal lines, and the time-division multiplexing module is responsible for managing and multiplexing these direct connection signal lines.

[0045] Specifically, different hardware computing units use direct connection signal lines for data transmission in different time slots. For example, at a certain moment (the first time slot), the local hardware computing unit can send data to hardware computing unit 1 through the direct connection signal line; and at another moment (the second time slot), hardware computing unit 1 or hardware computing unit 2 can use this direct connection signal line to feedback data to the local hardware computing unit or send new data. In this way, within different time slots, the same direct connection signal line can be used by different hardware computing units for data transmission in different directions, realizing the multiplexing of the signal line.

[0046] Among them, in the verification subsystem of multiple hardware computing units, if the time division multiplexing module is not adopted, separate signal lines may be required for communication between each hardware computing unit, which will result in a large number of signal lines and extremely high demand for hardware resources. By multiplexing the direct connection signal lines through the time division multiplexing module, the number of required signal lines is greatly reduced, the hardware cost is lowered, and at the same time, the wiring space on the circuit board is reduced, making the physical structure of the system more compact.

[0047] Specifically, in one embodiment, as Figure 4 shown, it is a schematic structural diagram of the hardware computing unit provided by the embodiment of the present application. For any hardware computing unit, the number of time division multiplexing modules provided by this hardware computing unit is the same as the number of direct connection signal lines connected to this hardware computing unit; the hardware computing unit is connected to the direct connection signal line through the time division multiplexing module. That is, the more direct connection lines, the more time division multiplexing modules, the faster the data transmission rate, and the higher the frequency of the entire verification system. In practical applications, the time division multiplexing module can be not fixed, and high-speed serial buses such as FSI or PCIE can be adopted.

[0048] Specifically, by making each time division multiplexing module correspond to a direct connection signal line, precise control of data transmission can be achieved. The hardware computing unit can independently perform time slot allocation and data scheduling for each direct connection signal line, avoiding scheduling conflicts and data chaos when multiple signals share the same module.

[0049] Based on the above embodiments, since in the current FPGA prototype verification system, the control steps required by the scheduling unit are timing units corresponding to several clock cycles, and the scheduling purpose is to match the moment when each operation occurs. In order to achieve fast clock regulation in the embodiment of the present application, as Figure 5 shown, it is a schematic structural diagram of another verification subsystem provided by the embodiment of the present application. As an implementable manner, in one embodiment, the verification subsystem includes:

[0050] A clock reset module is used to send clock synchronization signals to each hardware computing unit belonging to the same verification subsystem, so as to keep the hardware computing units in clock synchronization; or, when the verification subsystem meets the preset reset condition, send synchronous reset signals to each hardware computing unit, so that each hardware computing unit synchronously resumes its operating state.

[0051] Among them, the signal transmission distance between the clock reset module in the verification subsystem and each hardware computing unit in the verification subsystem is the same. That is, to ensure the clock reset synchronization of each hardware computing unit, the clock reset module is located at the center of multiple hardware computing units, so that the wiring of the clock synchronization signal and the synchronous reset signal to each hardware computing unit is of equal length. The equal-length distance transmission delay is equal, so it will not cause a situation where some hardware computing units in the system have already started working while some have not, thus avoiding system errors.

[0052] It should be noted that in the verification subsystem, multiple hardware computing units need to cooperate to complete the verification task of the integrated circuit sub-function. Among them, clock synchronization is the key to ensuring that each hardware computing unit can work in a coordinated manner. The clock reset module generates a clock synchronization signal and sends it to all hardware computing units within the same verification subsystem. These hardware computing units adjust their own task execution progress according to the received clock synchronization signal, so that their clock signals are consistent in frequency and phase. For example, in a verification subsystem composed of multiple FPGAs (hardware computing units), each FPGA needs to perform data processing and transmission under the same clock, so as to ensure the accurate interaction of data and the correctness of the processing results. When the verification subsystem meets the preset reset condition (such as a system error or the need to restart the verification process, etc.), the clock reset module sends a synchronous reset signal to all hardware computing units, so that each hardware computing unit returns to the initial state at the same time, and then synchronously resumes operation, ensuring the consistency and accuracy of the verification work.

[0053] It should be further noted that in the verification subsystem, since there will be delays in the signal transmission process, if the transmission distances are different, the time for the signal to reach each hardware computing unit will be different, which may lead to clock asynchronization or inconsistent reset operations between hardware computing units, thus affecting the accuracy of the verification results. In the embodiments of the present application, the transmission distance from the clock reset module to each hardware computing unit is kept the same, ensuring that the clock synchronization signal and the synchronous reset signal can reach each hardware computing unit simultaneously.

[0054] Specifically, in one embodiment, as Figure 6 This is a schematic structural diagram of another verification subsystem provided by the embodiments of the present application. As an implementable manner, in one embodiment, the clock reset module includes:

[0055] A crystal oscillator is used to generate a global clock signal for the verification subsystem and send the global clock signal to the register control module and phase-locked loop of each hardware computing unit.

[0056] A clock integrated circuit is used to receive the target clock signal fed back by the phase-locked loop of any hardware computing unit in response to the global clock signal, generate multiple clock signals according to the target clock signal, and send the multiple clock signals to each hardware computing unit.

[0057] Among them, the hardware computing unit includes a register control module and a phase-locked loop; the register control module is used to drive data transmission and logical calculation between registers according to the received global clock signal; the phase-locked loop is used to adjust the frequency and phase of the received global clock signal according to the clock signal requirements of the hardware computing unit to obtain a target clock signal that meets the clock signal requirements of the hardware computing unit, and feedback the target clock signal to the clock integrated circuit.

[0058] Among them, the register control module is also called the Register Transfer Level (RTL for short), and the phase-locked loop is also called the Phase Locked Loop (PLL for short).

[0059] Specifically, a high-precision and high-stability global clock signal can be generated based on the piezoelectric effect of the crystal. The global clock signal is a unified time reference for each hardware computing unit in the system. The crystal oscillator sends the generated global clock signal to the register control module and phase-locked loop in the hardware computing unit at the same time. The register control module receives the global clock signal transmitted by the crystal oscillator and drives data transmission and logical operations between registers based on this signal. Under the control of the clock signal, the registers perform data read and write operations according to a specific timing sequence to complete various complex logical calculation tasks.

[0060] Among them, different hardware computing units may have different frequency and phase requirements for the clock signal. The function of the phase-locked loop is to adjust the global clock signal transmitted by the crystal oscillator according to the needs of the hardware computing unit itself. Specifically, the feedback mechanism inside the phase-locked loop can compare the input global clock signal with the output clock signal of itself, automatically adjust the frequency and phase of the output signal to make the output signal meet the specific requirements of the hardware computing unit, and use the output signal as the target clock signal.

[0061] Specifically, the clock integrated circuit receives the target clock signals fed back from the phase-locked loops of each hardware computing unit, and then, based on these target clock signals, uses internal circuits and algorithms to generate multiple clock signals with different frequencies and / or different phases. The multiple clock signals can meet the diverse requirements of different hardware computing units or different functional modules within the same hardware computing unit for clock signals. Finally, the clock integrated circuit sends the multiple clock signals to each hardware computing unit to ensure that each hardware computing unit can obtain a suitable clock signal to operate properly.

[0062] Specifically, in one embodiment, the clock integrated circuit is used to perform frequency division processing on the obtained target clock signals to convert the target clock signals into clock signals with different frequencies; and determine multiple clock signals based on the clock signals with different frequencies.

[0063] Among them, the multiple clock signals match multiple functional modules of the hardware computing unit.

[0064] Specifically, after the clock integrated circuit receives the target clock signals fed back from the phase-locked loop of the hardware computing unit, it then performs frequency division processing on them. For example, when the frequency of the target clock signal is 100 MHz, the clock integrated circuit can obtain a 50 MHz clock signal through a frequency division operation by 2, a 25 MHz clock signal through a frequency division operation by 4, etc. It can also perform frequency multiplication processing on the target clock signal, and the specific processing method of the clock integrated circuit can be flexibly set according to actual requirements.

[0065] Specifically, after completing the frequency division processing or frequency multiplication processing, the clock integrated circuit determines multiple clock signals based on these clock signals with different frequencies. Since the frequencies of the multiple clock signals are diverse, they can meet the different requirements of multiple functional modules within the hardware computing unit. Among them, the functional modules within the hardware computing unit include a data processing module, a data storage module, a data transmission module, etc.

[0066] Specifically, in one embodiment, in order to ensure the safe and stable operation of the integrated circuit verification system, a fault handling mechanism can be introduced into each verification subsystem. Specifically, sensor data and corresponding fault records during the long-term operation of the hardware computing unit can be collected to form a historical data set. Using a supervised learning algorithm, the historical data is trained. During the training process, the sensor data is used as input features, and the fault type or the occurrence of a fault is used as a label, so that the model can learn the differences in data features between the normal state and the fault state. At the same time, an unsupervised learning algorithm is used to perform anomaly detection on the current real-time data. When the real-time data deviates from the normal distribution, it is determined as an abnormal situation, which may indicate a potential fault. At this time, a fault warning message for the hardware computing module can be generated.

[0067] Further, after the model generates the fault warning information of any hardware computing module, the task reallocation mechanism of the verification subsystem can be started. For example, the computing tasks (micro-services) originally assigned to the hardware computing module are temporarily transferred to other hardware computing modules with lighter loads, reducing the workload of the faulty hardware computing module to delay the occurrence time of the fault.

[0068] The integrated circuit verification system provided by the embodiments of this application includes: a comprehensive device and multiple verification subsystems, and each verification subsystem includes multiple hardware computing units; the comprehensive device is used to split the function verification service of the integrated circuit to be verified into multiple sub-services and allocate the multiple sub-services to the multiple verification subsystems; the verification subsystem is used to receive and execute the sub-services to verify the integrated circuit sub-functions corresponding to the sub-services and obtain the sub-function verification results corresponding to the integrated circuit sub-functions; for any verification subsystem, direct connection signal lines are used to connect the various hardware computing units in the verification subsystem, so that direct interconnection is achieved between the various hardware computing units in the verification subsystem, and the verification subsystem executes the sub-service based on the multiple directly interconnected hardware computing units. In the system provided by the above solution, by splitting the function verification service of the integrated circuit to be verified into multiple sub-services and allocating them to different verification subsystems for execution, and each verification subsystem includes multiple hardware computing units that achieve direct signal interconnection, while expanding the hardware resources, the communication delay between the hardware computing units is reduced, thereby reducing the time consumed for the function verification of the integrated circuit, and further improving the efficiency of the function verification of the integrated circuit. Moreover, the various FPGAs (hardware computing units) are cross-connected, and each FPGA has a direct connection to other FPGAs. The numerous direct connection lines provide a large amount of data transmission. The data exclusively uses the direct connection lines, avoiding the congestion caused by the bus mode. The numerous direct connection lines enable the entire design to be conveniently split onto different FPGAs, and each FPGA can work independently and simultaneously, improving efficiency and saving the time for generating a bit file once. Since each FPGA is independent, when it is verified that a certain RTL design is incorrect, only the FPGA where the modification is made needs to be recompiled separately after the modification, shortening the iteration time. Each FPGA has multiple time-division multiplexing modules, saving the IO quantity of the FPGA. The numerous time-division multiplexing modules and direct connection lines can evenly distribute the data to be transmitted to each time-division multiplexing unit, so the amount of data transmitted by each time-division multiplexing unit is reduced, the transmission frequency is increased, and then the operating frequency of the entire system is also increased. The clock reset module is located at the center of each FPGA, and the clock line and reset line are of equal length from each FPGA, ensuring the synchronization of the entire prototype verification system. The clock reset module has multiple global clocks and multiple FPGA clocks, and the numerous clock quantities facilitate the verification of the prototype system. Whether it is the cross-connection structure or the equidistant clock reset module in this system, there are no requirements for the FPGA, that is, different models of FPGAs can be used in the system, which is convenient for users to assemble this system.

[0069] From the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0070] An embodiment of the present application also provides an integrated circuit verification method, which is applied to the verification subsystem of the integrated circuit verification system provided in the above embodiment.

[0071] As Figure 7 shown, it is a schematic structural diagram of the integrated circuit verification method provided by an embodiment of the present application. The integrated circuit verification method includes:

[0072] Step 701, obtain any sub-service allocated by the integrated device; wherein, the integrated device splits the function verification service of the integrated circuit to be verified into multiple sub-services;

[0073] Step 702, split the sub-service into multiple micro-services, and allocate the micro-services to different hardware computing units to execute the micro-services based on the hardware computing units, and obtain the micro-service execution results generated by each hardware computing unit;

[0074] Step 703, summarize the micro-service execution results generated by each hardware computing unit to obtain the sub-service execution result, and feedback the sub-service execution result to the integrated device.

[0075] Wherein, the integrated device obtains the function verification result of the integrated circuit to be verified by summarizing the sub-service execution results fed back by each verification subsystem.

[0076] For the description of the features in the corresponding embodiment of the integrated circuit verification method, reference can be made to the relevant description of the corresponding embodiment of the integrated circuit verification system, which will not be elaborated here one by one.

[0077] An embodiment of the present application also provides an integrated circuit verification device, as Figure 8 shown, it is a schematic structural diagram of the integrated circuit verification device provided by an embodiment of the present application. The integrated circuit verification device includes the integrated circuit verification system provided in the above embodiment.

[0078] For the description of the features in the corresponding embodiment of the integrated circuit verification device, reference can be made to the relevant description of the corresponding embodiment of the integrated circuit verification system, which will not be elaborated here one by one.

[0079] An embodiment of the present application also provides an electronic device, as Figure 9As shown in the figure, it is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device includes a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the integrated circuit verification method.

[0080] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned embodiments of the integrated circuit verification method when running.

[0081] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk or optical disc, etc., various media that can store computer programs.

[0082] An embodiment of the present application further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the integrated circuit verification method.

[0083] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the integrated circuit verification method.

[0084] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0085] The above has introduced in detail an integrated circuit verification system, method, device, and storage medium provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An integrated circuit verification system, characterized in that: include: A comprehensive device, a plurality of verification subsystems, each of the verification subsystems comprising a plurality of hardware computing units; The integrated device is used to split the function verification business of the integrated circuit to be verified into multiple sub-businesses, and allocate the multiple sub-businesses to the multiple verification subsystems; The verification subsystem is used to receive and execute the sub-service to verify the integrated circuit sub-function corresponding to the sub-service and obtain a sub-function verification result corresponding to the integrated circuit sub-function; For any of the verification subsystems, the various hardware computing units in the verification subsystem are connected by direct signal lines to enable direct interconnection between the various hardware computing units in the verification subsystem, and the verification subsystem executes the sub-business based on multiple directly interconnected hardware computing units.

2. The integrated circuit verification system according to claim 1, characterized in that: Each of the hardware computing units is provided with a time division multiplexing module; The time division multiplexing module is used to multiplex the direct connection signal lines between the local hardware computing unit and other hardware computing units in different time slots; The local hardware computing unit and the other hardware computing units belong to the same verification subsystem.

3. The integrated circuit verification system according to claim 2, characterized in that: For any of the hardware computing units, the number of time division multiplexing modules provided in the hardware computing unit is the same as the number of direct signal lines connected to the hardware computing unit; The hardware computing unit is connected to the direct signal line through the time division multiplexing module.

4. The integrated circuit verification system according to claim 1, characterized in that: The verification subsystem comprises: The clock reset module is used to send a clock synchronization signal to each hardware computing unit belonging to the same verification subsystem so that the hardware computing units maintain clock synchronization; or, when the verification subsystem meets the preset reset conditions, send a synchronous reset signal to each hardware computing unit so that each hardware computing unit synchronously resumes the operating state.

5. The integrated circuit verification system according to claim 4, characterized in that: The signal transmission distance between the clock reset module in the verification subsystem and each hardware computing unit in the verification subsystem is the same.

6. The integrated circuit verification system according to claim 4, characterized in that: The clock reset module comprises: A crystal oscillator, used to generate a global clock signal of the verification subsystem, and send the global clock signal to the register control module and the phase-locked loop of each of the hardware computing units; A clock integrated circuit, used for receiving a target clock signal fed back by a phase-locked loop of any of the hardware computing units in response to the global clock signal, generating multiple clock signals according to the target clock signal, and sending the multiple clock signals to each of the hardware computing units; The hardware computing unit includes the register control module and a phase-locked loop; The register control module is used to drive data transmission and logic calculation between registers according to the received global clock signal; The phase-locked loop is used to adjust the frequency and phase of the received global clock signal according to the clock signal requirements of the hardware computing unit to obtain a target clock signal that meets the clock signal requirements of the hardware computing unit, and feed the target clock signal back to the clock integrated circuit.

7. The integrated circuit verification system according to claim 6, characterized in that: The clock integrated circuit is used for: Performing frequency division processing on the obtained target clock signal to convert the target clock signal into a clock signal of a different frequency; Determining multiple clock signals according to the clock signals of different frequencies; Wherein, the multiple clock signals match multiple functional modules of the hardware computing unit.

8. An integrated circuit verification method, characterized in that: A verification subsystem applied to an integrated circuit verification system as claimed in any one of claims 1 to 7, the method comprising: Acquire any sub-service assigned by the integrated device; wherein the integrated device splits the function verification service of the integrated circuit to be verified into multiple sub-services; Splitting the sub-business into a plurality of micro-businesses, and allocating the micro-businesses to different hardware computing units, so as to execute the micro-businesses based on the hardware computing units, and obtain micro-business execution results generated by each of the hardware computing units; Summarizing the micro-service execution results generated by each of the hardware computing units to obtain a sub-service execution result, and feeding back the sub-service execution result to the integrated device; The integrated device obtains the functional verification result of the integrated circuit to be verified by summarizing the sub-service execution results fed back by each of the verification subsystems.

9. An integrated circuit verification device, characterized in that: include: An integrated circuit verification system as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the integrated circuit verification method as claimed in claim 7.

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