Physical design method and device, server and storage medium

Abstract

The invention provides a physical design method and device, a server and a storage medium, and is applied to the technical field of computers. According to the method, after a netlist of a first module and a netlist of a second module are combined and a netlist of a universal module is generated, physical design is carried out based on the netlist of the universal module; according to the method, a general module is designed, physical design of the general module is divided into a first module database and a second module database, and finally physical verification and time sequence verification are conducted on the first module database and the second module database. According to the method, the first module and the second module are combined into the universal module, and the universal module is physically designed, so that one physical design process can be reduced, subsequent physical verification and time sequence verification processes can be simplified, and the design efficiency of the integrated circuit can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and particularly to a physical design method, apparatus, server, and storage medium. Background Art

[0002] With the continuous improvement of the complexity of integrated circuit design, the hierarchical design method has become an important means to improve design efficiency. The traditional hierarchical design divides the functions of an integrated circuit into multiple independent functional modules, flattens the design of each functional module, and finally completes the assembly at the top level. The advantage of this method is that it supports parallel development of multiple modules and significantly shortens the overall design cycle.

[0003] However, the existing technology has significant limitations in practical applications. When the logical functions of functional modules are the same but the physical layout requirements are different, such as when the physical layout direction cannot be flipped or there are direction requirements for logical co-packaging, the traditional hierarchical design cannot directly reuse functional modules, and different physical designs need to be carried out on the basis of the same logical design to meet the physical layout requirements. Since the physical design needs to be carried out multiple times to complete, it not only wastes a lot of manpower and material resources, but also leads to an overly long design cycle for integrated circuits. Summary of the Invention

[0004] In view of this, this application is committed to providing a physical design method, apparatus, server, and storage medium to solve the problems of complex design process caused by non-reusable physical design modules and overly long design cycle of integrated circuits.

[0005] In a first aspect, this application provides a physical design method, which is applied to a first module and a second module with the same logical function but different physical layouts. The first module includes a main module and a first sub-module, the second module includes the main module and a second sub-module, and the first sub-module and the second sub-module are obtained by reusing the same sub-module. The method includes: Merging the netlists of the first module and the second module to generate a netlist of a general module, where the netlist of the general module includes the netlists of the main module, the first sub-module, and the second sub-module, as well as the external ports of the first module and the second module; Performing physical design based on the netlist of the general module; Splitting the physical design of the general module into a first module database and a second module database; Performing physical verification and timing verification on the first module database and the second module database respectively.

[0006] In an optional implementation, merging the netlists of the first module and the second module to generate a netlist of a general module includes: Copying the netlist of the first module as the base netlist; Add the external ports of the second module and the netlist of the second sub-module to the basic netlist to obtain the netlist of the general module.

[0007] In an alternative embodiment, adding the external ports connecting the second module and the second sub-module and the netlist of the second sub-module to the basic netlist includes: Extract a first list of external ports, where the first list of external ports includes the external ports connecting the main module in the second module and the second sub-module; Add external ports to the basic netlist according to the first list of external ports and connect the external ports to the netlist of the main module Add the netlist of the second sub-module to the basic netlist and connect the netlist of the second sub-module to the netlist of the main module.

[0008] In an alternative embodiment, performing physical design based on the netlist of the general module includes: Import the timing library and physical feature library of the first sub-module and the second sub-module; Add buffers at target positions in the netlist of the general module to obtain a preprocessed netlist; where the target positions include the positions where the first sub-module is connected to the main module and the positions where the second sub-module is connected to the main module; Perform physical design based on the preprocessed netlist.

[0009] In an alternative embodiment, performing physical design based on the preprocessed netlist includes: Perform physical layout based on the preprocessed netlist to obtain the initial physical layout of the general module; Determine a target area where routing is prohibited in the initial physical layout according to the layout information of the first sub-module and the second sub-module; Perform routing in areas other than the target area in the initial physical layout to complete the physical design of the general module.

[0010] In an alternative embodiment, splitting the physical design of the general module into a first module database and a second module database includes: Extract the netlist of the first module from the netlist of the general module and extract the physical library file of the first module from the physical library file of the general module; Combine the netlist and physical library file of the first module into a first module database; Extract the netlist of the second module from the netlist of the general module, and extract the physical library file of the second module from the physical library file of the general module; Combine the netlist and physical library file of the second module into a second module database.

[0011] In an alternative embodiment, extracting the netlist of the first module from the netlist of the general module includes: Remove the second sub-module and its external ports of the second module from the netlist of the general module to obtain the netlist of the first module; Extract the netlist of the second module from the netlist of the general module, including: Remove the first sub-module and its external ports of the first module from the netlist of the general module to obtain the netlist of the second module.

[0012] In an alternative embodiment, extracting the physical library file of the first module from the physical library file of the general module includes: Delete the second sub-module from the physical library file of the general module according to the physical size and layout coordinates of the second sub-module to obtain the physical library file of the first module; Extract the physical library file of the second module from the physical library file of the general module, including: Delete the first sub-module from the physical library file of the general module according to the physical size and layout coordinates of the first sub-module to obtain the physical library file of the second module.

[0013] In a second aspect, the present application provides a physical design device, which is applied to a first module and a second module with the same logical function but different physical layouts. The first module includes a main module and a first sub-module, the second module includes the main module and a second sub-module, and the first sub-module and the second sub-module are obtained based on the reuse of the same sub-module. The device includes: A merging unit for merging the netlists of the first module and the second module to generate a netlist of a general module. The netlist of the general module includes the netlists of the main module, the first sub-module, and the second sub-module, as well as the external ports of the first module and the second module; A design unit for performing physical design based on the netlist of the general module; A splitting unit for splitting the physical design of the general module into a first module database and a second module database; A verification unit for respectively performing physical verification and timing verification on the first module database and the second module database.

[0014] In a third aspect, the present application provides a server, including a memory, a processor, and a computer program stored on the memory and executed by the processor. When the processor executes the computer program, the steps of the physical design method according to any one of the first aspects of the present application are implemented.

[0015] In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the physical design method according to any one of the first aspects of the present application are implemented.

[0016] Based on the above, for the physical design method provided by the present application, after merging the netlists of the first module and the second module to generate the netlist of the common module, physical design is performed based on the netlist of the common module, and the physical design of the common module is split into the first module database and the second module database. Finally, physical verification and timing verification are respectively performed on the first module database and the second module database. Compared with the physical design method in the prior art that requires separate physical design and verification for the first module and the second module, this method merges the first module and the second module into a common module and performs physical design on the common module, thereby reducing one physical design process. Correspondingly, it can also simplify the subsequent physical verification and timing verification processes, which helps to improve the design efficiency of integrated circuits. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 is a flowchart of a physical design method provided by the present application.

[0019] Figure 2 is a schematic diagram of an integrated circuit module mentioned in the present application.

[0020] Figure 3 is a schematic diagram of a common module provided by the present application.

[0021] Figure 4 is a schematic diagram of another common module provided by the present application.

[0022] Figure 5a is a schematic diagram of the split first module provided by the present application.

[0023] Figure 5b is a schematic diagram of the split second module provided by the present application.

[0024] Figure 6 It is a structural block diagram of a physical design device provided by the present application.

[0025] Figure 7 It is a structural block diagram of a server provided by the present application. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0027] As described above, although the hierarchical design method can divide the integrated circuit functions into multiple independent functional modules and perform flattening design on each functional module to achieve parallel development of multiple modules and significantly shorten the overall design cycle, when the logical functions of the functional modules in the integrated circuit are the same but the physical layout requirements are different, such as the physical layout direction cannot be flipped or there are direction requirements for logical co-packaging, the traditional hierarchical design cannot directly reuse the functional modules and needs to perform different physical designs on the basis of the same logical design to meet the physical layout requirements. Since the physical design needs to be performed multiple times to complete, it not only wastes a lot of manpower and material resources, but also results in too long a design cycle for the integrated circuit.

[0028] To solve the above problems, the present application provides a physical design method, which is applied to the physical design of a first module and a second module with the same logical function and different physical layouts. Compared with the physical design methods in the prior art that need to perform physical design and verification on the first module and the second module respectively, this method combines the first module and the second module into a general module and performs physical design on the general module, thereby reducing the physical design process once. Correspondingly, it can also simplify the subsequent physical verification and timing verification processes, which helps to improve the design efficiency of the integrated circuit.

[0029] The physical design method provided by the present application can be applied to an electronic device, which can be a laptop computer, a personal computer (PC), a tablet computer. Of course, it can also be other electronic devices that can run the application program corresponding to the physical design method provided by the present application, which will not be listed one by one here. Of course, in some cases, it can also be applied to a server on the network side. See Figure 1 As shown, the physical design method provided by the present application includes the following steps.

[0030] S100. Merge the netlists of the first module and the second module to generate the netlist of the general module.

[0031] First, it should be noted that the physical design method provided in this application can be applied to the physical design of two or more functional modules in an integrated circuit. The first module and the second module described in this application can be any two modules in the integrated circuit that can apply the physical design method provided in this application for physical design. The physical design processes of the remaining functional modules can all be completed with reference to the physical design method provided in this application.

[0032] See Figure 2 As shown, assume that the integrated circuit includes three first-level modules, respectively labeled as A-l, M, and A-r. Among them, the second-level sub-module a0 is further included in A-l, and the second-level sub-module a1 is further included in A-r. A-l and A-r are arranged in sequence in the physical layout and cannot be flipped. That is, the right side of A-l is connected to M, and the left side is connected to other modules located on the left side of A-l in the integrated circuit through the second-level sub-module a0. Correspondingly, the left side of A-r is connected to M, and the right side is connected to other modules located on the right side of A-r in the integrated circuit through the second-level sub-module a1. It should be noted that for the convenience of description, the module A-l is used as the first module, and the module A-r is used as the second module. The connection between any first-level module and other first-level modules is indicated by a rectangular port (i.e., the black rectangle in the figure), and the corresponding pin is defined as an external port. The connection between any first-level module and its own second-level sub-module is indicated by a circular port (i.e., the black circle in the figure), and the corresponding pin is defined as an internal port.

[0033] In this application, the first module A-l and the second module A-r have the same logical function, but due to the limitation of the connection relationship with the module M, that is, due to the physical layout, the physical layouts of the first module A-l and the second module A-r are different. Further, the first module A-l includes a main module (not shown in the figure) and a first sub-module a0, and the second module A-r also includes the same main module (not shown in the figure) and a second sub-module a1. The main modules in the first module A-l and the second module A-r are the same and are used to implement their main logical functions. Moreover, the first sub-module a0 and the second sub-module a1 are obtained by reusing the same sub-module, that is, this second-level sub-module is isomorphic and can be reused. In actual applications, the corresponding first sub-module a0 and second sub-module a1 can be configured by instantiating and deploying them in the first module A-l and the second module A-r respectively.

[0034] Based on the above premises, the physical design method provided by this application first merges the netlist of the first module and the netlist of the second module, that is, takes the union of the two, and the merged netlist is used as the netlist of the common module. In order to enable the netlist of the common module to cover all the functions of the first module and the second module and facilitate the subsequent splitting of the module, the obtained netlist of the common module includes the netlist of the main module, the netlist of the first sub-module, and the netlist of the second sub-module, and also includes the external ports of the first module and the second module.

[0035] Combined with Figure 3 As shown, the obtained common module after merging is marked as A. Assuming that the physical width of the first module A-l or the second module A-r is x1, and the physical widths of the first sub-module a0 and the second sub-module a1 are both x0, then the physical width of the obtained common module A is x0 + x1. It can be understood that Figure 3 The illustration shown is only for exemplary purposes, and in fact, the layout operation of the common module has not been carried out yet.

[0036] Assume that the netlist of the first module A-l is A-l.v.gz, and correspondingly, the netlist of the second module A-r is A-r.v.gz. Based on this, as an alternative implementation, first copy the netlist of the first module A-l as the base netlist (of course, the netlist of the second module A-r can also be copied as the base netlist). On the basis of the base netlist, add the external ports of the second module A-r and the netlist of the second sub-module a1 to obtain the netlist of the common module A. Referring to the above descriptions of the first module A-l and the second module A-r, the netlist of the common module A can be expressed as A.v.gz.

[0037] Specifically, based on the netlist of the second module A-r, it can be determined that the main module in the second module A-r is connected to the second sub-module a1 and serves as the external port of the second module A-r. By counting the corresponding external ports, the first external port list A-r-r-port.list can be obtained. In addition, by counting the internal ports of the main module and the second sub-module a1 in the second module A-r, the first internal port list A-r-l-port.list can be obtained. Correspondingly, based on the netlist of the first module A-l, it can be determined that the main module in the first module A-l is connected to the first sub-module a0 and serves as the external port of the first module A-l. By counting the corresponding external ports, the second external port list A-l-l-port.list can be obtained. In addition, by counting the internal ports of the main module and the first sub-module a0 in the first module A-l, the second internal port list A-l-r-port.list can be obtained.

[0038] Based on the above statistical situation, according to the external ports recorded in the first external port list A-r-r-port.list and the arrangement order of each external port, corresponding external ports are added to the basic netlist. At the same time, the newly added external ports are connected to the netlist of the main module. Specifically, it can be implemented with reference to the connection relationship of the external ports between the main module and the second sub-module a1 in the second module A-r.

[0039] Furthermore, the netlist of the second sub-module a1 is added to the basic netlist, that is, the aforementioned reusable sub-module is instantiated to obtain the corresponding second sub-module a1. The netlist of the second sub-module a1 is added to the basic netlist, and the netlist of the second sub-module a1 is connected to the netlist of the main module. Specifically, it can be implemented with reference to the connection relationship of the internal ports between the main module and the second sub-module a1 in the second module A-r.

[0040] After completing the relevant processing of the above netlist and connection relationship, the netlist of the general module A can be obtained.

[0041] S110. Perform physical design based on the netlist of the general module.

[0042] It can be understood that since the general module contains both the first sub-module a0 and the second sub-module a1, therefore, during physical design, the timing library and physical feature library of the first sub-module a0 and the second sub-module a1 need to be imported for corresponding verification of the first sub-module a0 and the second sub-module a1.

[0043] In the physical design process of the related technology, after obtaining the netlists of the first module A-l and the second module A-r, the physical designs of the first module A-l and the second module A-r will be carried out respectively, that is, two physical design processes will be carried out. Compared with the prior art, in this application, the first module A-l and the second module A-r have been merged into a general module and the corresponding netlist has been obtained through the foregoing steps. Therefore, in the physical design process, only one physical design needs to be carried out for the netlist of the general module, reducing one physical design process.

[0044] Furthermore, it can be understood that the ultimate goal of the design is to obtain the first module A-l and the second module A-r. Therefore, after completing the corresponding physical design based on the netlist of the general module A, the obtained general module A also needs to be split. For the convenience of the subsequent splitting process, this application provides a preferred implementation manner.

[0045] Specifically, a buffer is added to the target position in the netlist of the general module A to obtain a preprocessed netlist, and physical design is performed based on the obtained preprocessed netlist. Combining the foregoing content, it can be known that the general module A includes a main module, a first sub-module a0, and a second sub-module a1. The connection relationships between the modules mainly involve the connection relationship between the main module and the first sub-module a0, and the connection relationship between the main module and the second sub-module a1. By splitting out the second sub-module a1 in the general module A, the first module A-l can be obtained. Correspondingly, by splitting out the first sub-module a0 in the general module A, the second module A-r can be obtained. Based on this, combining Figure 4 As shown, the target positions described in this embodiment may include the position where the first sub-module a0 is connected to the main module A-m, that is, the right boundary of the first module A-l, and the position where the second sub-module a1 is connected to the main module A-m, that is, the left boundary of the second module A-r. Of course, in actual applications, other positions where the sub-module is connected to the main module may also be used as the target position, Figure 4 The illustration is only an example and does not limit the selection of the target position.

[0046] Combining Figure 4 As shown, the triangular module represents the buffer. During the actual physical layout process, the logical network directly connected to the ports listed in A-l-l-port.list can be extracted from the netlist A-l.v.gz of the first module A-l, and a buffer can be added at this position as the target position. As Figure 4 shown, compared with the view of the first module A_l of the general module A, a column of buffers is connected to the right side of the first module A-l. It should be noted that when placing the buffers, the metal wires connected to them should be arranged according to the original metal layer arrangement order on the right side of the first module A-l; correspondingly, compared with the view of the second module A-r of the general module A, the network where the left port of the second module A-r is located is used as the target position to connect a column of buffers. Similar to the deployment process of the first module A-l, when placing the buffers, the metal wires connected to them should be arranged according to the original metal layer arrangement order of the left port of the second module A-r, and finally the addition of two columns of buffers is completed.

[0047] After the foregoing steps, the processing process of the preprocessed netlist has been completed. Further, physical layout is performed based on the obtained preprocessed netlist, that is, the physical area of the general module A is preprocessed to obtain the initial physical layout of the general module A. Based on this, the target area where routing is prohibited can be further determined in the initial physical layout according to the layout information of the first sub-module a0 and the second sub-module a1. Combining Figure 4As shown, since the physical height dimensions of the first sub-module a0 and the second sub-module a1 are generally not greater than the physical height dimension of the module to which they belong, it is necessary to set corresponding wire-blocking areas in the initial physical layout during wiring, that is, the target areas described in this embodiment. Figure 4 The slanted area shown in Figure 4 is the target area where wiring is prohibited. Of course, in practical applications, corresponding wire-blocking areas can also be set in combination with the external dimensions of the sub-module and the module to which it belongs and other wiring rules, which will not be listed one by one here. Without exceeding the core idea of this application, it also belongs to the scope protected by this application. It can be understood that the purpose of setting the target area where wiring is prohibited is to ensure that when the sub-module is cut out later, the sub-module can be cut out independently without affecting other logic units.

[0048] After determining the target area where wiring is prohibited, wiring can be carried out in the area outside the target area in the initial physical layout to complete the physical design of the general module A.

[0049] S120. Split the physical design of the general module into a first module database and a second module database.

[0050] As mentioned above, the ultimate goal of the design is to obtain the first module A-l and the second module A-r. After completing the physical design of the general module A, it is necessary to split based on the general module A to obtain the first module A-l and the second module A-r. In the physical design process in practical applications, the functional modules in the integrated circuit are respectively recorded with netlists and physical library files for the corresponding design results. Based on this, the netlist of the first module A-l and the netlist of the second module A-r can be extracted from the netlist of the general module A, and further, the physical library file of the first module A-l and the physical library file of the second module A-r can be extracted from the physical library file of the general module A obtained in S110.

[0051] Specifically, based on the generation process of the general module A, since in the previous operations, the connection relationship between the main module and the second sub-module a1 was added to the general module A, when removing the second sub-module a1, first, the connection relationship between the two needs to be disconnected, and the redundant ports, that is, the ports in the aforementioned A-r-r.port.list, need to be deleted. At the same time, the netlist of the second sub-module a1 is removed from the netlist of the general module. It can be understood that since buffers were added in S110, when performing the operations in this step, the corresponding buffers can be directly disconnected, thus simplifying the splitting process of the netlist of the sub-module.

[0052] Correspondingly, removing the netlist of the first sub-module a0 and the external ports of the first sub-module a0 from the netlist of the general module A yields the netlist of the second module A-r. Similar to the process of splitting to obtain the first module A-l, when removing the first sub-module a0, first, the connection relationship between the two needs to be turned off, and the redundant ports, i.e., the ports in the aforementioned A-l-l.port.list, need to be deleted. Since buffers were also added in S110, when performing this step of operation, the corresponding buffers can be directly disconnected.

[0053] In an alternative embodiment, after splitting the netlist of the general module to obtain the netlist of the first module, the obtained netlist of the first module can be checked for logical equivalence with the original netlist of the first module to ensure that the logical function of the first module is not affected. Correspondingly, after splitting the netlist of the general module to obtain the netlist of the second module, the obtained netlist of the second module is also checked for logical equivalence with the original netlist of the second module.

[0054] Furthermore, adjust the physical library file of the general module A. Delete the physical library file of the second sub-module a1 from the physical library file of the general module A to obtain the physical library file of the first module A-l. Since the physical library file is used to record the physical size and layout coordinates of the functional module, therefore, according to the physical size and layout coordinates of the second sub-module a1 recorded in the physical library file, the second sub-module a1 can be deleted from the physical library file of the general module A to obtain the physical library file of the first module A-l. Taking Figure 4 as an example, delete the content in the physical library file of the general module A where the abscissa is greater than x1, and modify the module size recorded in the physical library file from x1 + x0 to x1 to obtain the physical library file of the first module A-l. For example, this physical library file can be stored as A-l.def. The physical layout of the obtained first module A-l can be seen in Figure 5a as shown.

[0055] Adjust the physical library file of the general module A again. According to the physical size and layout coordinates of the first sub-module a0, delete the first sub-module a0 from the physical library file of the general module A to obtain the physical library file of the second module A-r. Taking Figure 4 as an example, delete the content in the physical library file of the general module A where the abscissa is less than x0, and subtract x0 from the abscissa of all relevant modules recorded in the physical library file to obtain the physical library file of the second module A-r. For example, this physical library file can be stored as A-r.def. The physical layout of the obtained second module A-r can be seen in Figure 5b as shown.

[0056] After the above steps, the netlist and physical library file of the first module A1 have been obtained, and the two are combined into the first module database. In an optional implementation, the netlist Al.v.gz and the physical library file Al.def of the first module A1 can be imported into the layout and routing tool to merge and obtain the first module database. Correspondingly, the netlist and physical library file of the second module can be merged into the second module database in the same way.

[0057] S130 , performing physical verification and timing verification on the first module database and the second module database respectively.

[0058] After the above steps, the first module database and the second module database have been obtained, and further physical verification and timing verification are required for the two. Among them, physical verification at least includes design rule check (DRC) and layout and principle Figure 1 The consistency check (Layout Versus Schematic, LVS), the timing verification at least includes static timing analysis (Static Timing Analysis, STA). The specific verification process can refer to the relevant technical implementation, which will not be described in detail here.

[0059] To sum up, compared with the physical design method in the prior art which requires physical design and verification of the first module and the second module respectively, the present method merges the first module and the second module into a common module, and obtains the databases of the two modules by physically designing the common module, thereby reducing the physical design process once. Accordingly, the subsequent physical verification and timing verification processes can also be simplified, which helps to improve the design efficiency of integrated circuits.

[0060] It should be noted that the physical design method provided in the present application can be applied to the physical design of functional modules within an integrated circuit, and can also be applied to the physical design of molecular systems within an integrated circuit.

[0061] The physical design device provided by the present invention is introduced below. The physical design device provided by the present invention belongs to the same application concept as the physical design method provided by the embodiment of the present application, can execute the physical design method provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of executing the physical design method. For technical details not described in detail in this embodiment, please refer to the physical design method provided by the embodiment of the present application, and will not be repeated here.

[0062] The physical design device provided by this application is applied to a first module and a second module with the same logical function but different physical layouts. The first module includes a main module and a first sub-module, and the second module includes a main module and a second sub-module. The first sub-module and the second sub-module are obtained based on the reuse of the same sub-module.

[0063] See Figure 6 As shown, the physical design device provided by this application includes: A merging unit 10, configured to merge the netlists of the first module and the second module to generate a netlist of a general module. The netlist of the general module includes the netlists of the main module, the first sub-module, and the second sub-module, as well as the external ports of the first module and the second module; A design unit 20, configured to perform physical design based on the netlist of the general module; A splitting unit 30, configured to split the physical design of the general module into a first module database and a second module database; A verification unit 40, configured to perform physical verification and timing verification on the first module database and the second module database respectively.

[0064] In an optional implementation manner, the merging unit 10 is configured to merge the netlists of the first module and the second module to generate a netlist of a general module, specifically including: Copy the netlist of the first module as a base netlist; Add the external ports of the second module and the netlist of the second sub-module to the base netlist to obtain the netlist of the general module.

[0065] In an optional implementation manner, the merging unit 10 is configured to add the external ports connecting the second module and the second sub-module and the netlist of the second sub-module to the base netlist, specifically including: Extract a first external port list, where the first external port list includes the external ports connecting the main module in the second module and the second sub-module; Add external ports to the base netlist according to the first external port list, and connect the external ports to the netlist of the main module Add the netlist of the second sub-module to the base netlist, and connect the netlist of the second sub-module to the netlist of the main module.

[0066] Next, refer to Figure 7 to describe the server provided by the embodiment of the present invention. The server provided by this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400; In an embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 complete communication with each other through the communication bus 400; obviously, Figure 7 The communication connection schematic diagram of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 shown is only optional; Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0067] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0068] Among them, the processor 100 is specifically configured to execute the application programs in the memory to implement the steps of the physical design method described above.

[0069] In some embodiments, the present embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disc, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc. One or more instructions for implementing the above steps are stored in the computer-readable storage medium. When the one or more instructions are executed by one or more processors, the processors execute the physical design method described above. For the relevant specific implementation, please refer to the foregoing description, and details are not described herein again.

[0070] In addition to the above methods and devices, the embodiments of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor executes the steps in the physical design method according to various embodiments of the present application described in the above content of this specification.

[0071] A computer program product may write program code for performing the operations of the embodiments of the present application in any combination of one or more programming languages. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0072] Those skilled in the art can understand that the content disclosed in the present disclosure may have various variations and improvements. For example, the various devices or components described above may be implemented by hardware, or may be implemented by software, firmware, or some or all of the combinations of the three.

[0073] In addition, although the present disclosure makes various references to certain units in the systems according to the embodiments of the present disclosure, however, any number of different units may be used and run on the client and / or server. The units are only illustrative, and different aspects of the systems and methods may use different units.

[0074] Flowcharts are used in the present disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the steps before or after do not necessarily have to be carried out precisely in sequence. On the contrary, they may be carried out in reverse order or various steps may be processed simultaneously. At the same time, other operations may also be added to these processes.

[0075] Those of ordinary skill in the art can understand that all or part of the steps in the above methods can be completed by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium such as a read-only memory, etc. Optionally, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, the various modules / units in the above embodiments can be implemented in the form of hardware or in the form of software function modules. The present disclosure is not limited to any specific form of the combination of hardware and software.

[0076] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0077] The foregoing is a description of the present disclosure and should not be construed as limiting thereof. Although several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily appreciate that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing is a description of the present disclosure and should not be considered limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A physical design method, characterized in that: Applied to a first module and a second module with the same logical function and different physical layout, the first module includes a main module and a first submodule, the second module includes the main module and a second submodule, the first submodule and the second submodule are obtained by multiplexing the same submodule, the method includes: Merging the netlists of the first module and the second module to generate a netlist of a general module, wherein the netlist of the general module includes the netlists of the main module, the first submodule and the second submodule, and the external ports of the first module and the second module; Performing physical design based on the netlist of the common module; Splitting the physical design of the universal module into a first module database and a second module database; Physical verification and timing verification are performed on the first module database and the second module database respectively.

2. The method according to claim 1, characterized in that Merging the netlists of the first module and the second module to generate a netlist of a common module includes: Copying the netlist of the first module as a basic netlist; The external port of the second module and the netlist of the second submodule are added to the basic netlist to obtain the netlist of the general module.

3. The method according to claim 2, characterized in that Adding an external port connecting the second module and the second submodule and a netlist of the second submodule to the basic netlist includes: Extracting a first external port list, wherein the first external port list includes external ports in the second module that are connected to the main module and the second submodule; Add an external port to the basic netlist according to the first external port list, and connect the external port to the netlist of the main module The netlist of the second submodule is added to the basic netlist, and the netlist of the second submodule is connected to the netlist of the main module.

4. The method according to claim 1, characterized in that: Perform physical design based on the netlist of the general module, including: Importing the timing library and the physical feature library of the first submodule and the second submodule; Adding a buffer at a target position in the netlist of the general module to obtain a preprocessed netlist; Wherein, the target position includes a position where the first submodule is connected to the main module, and a position where the second submodule is connected to the main module; Physical design is performed based on the preprocessed netlist.

5. The method according to claim 4, characterized in that Performing physical design based on the preprocessed netlist includes: Performing physical layout based on the preprocessed netlist to obtain an initial physical layout of the general module; Determining a target area where routing is prohibited in the initial physical layout according to the layout information of the first submodule and the second submodule; Wiring is performed in a local area outside the target area in the initial physical layout to complete the physical design of the universal module.

6. The method according to claim 1, characterized in that Splitting the physical design of the universal module into a first module database and a second module database includes: Extracting the netlist of the first module from the netlist of the general module, and extracting the physical library file of the first module from the physical library file of the general module; synthesizing the netlist and physical library file of the first module into a first module database; Extracting the netlist of the second module from the netlist of the general module, and extracting the physical library file of the second module from the physical library file of the general module; The netlist and physical library file of the second module are synthesized into a second module database.

7. The method according to claim 6, characterized in that Extracting the netlist of the first module from the netlist of the general module includes: Removing the second submodule and the external port of the second module from the netlist of the general module to obtain a netlist of the first module; Extracting the netlist of the second module from the netlist of the general module includes: The first submodule and the external port of the first module are removed from the netlist of the general module to obtain a netlist of the second module.

8. The method according to claim 6, characterized in that Extracting the physical library file of the first module from the physical library file of the general module includes: According to the physical size and layout coordinates of the second submodule, the second submodule is deleted from the physical library file of the general module to obtain the physical library file of the first module; Extracting the physical library file of the second module from the physical library file of the general module includes: According to the physical size and layout coordinates of the first submodule, the first submodule is deleted from the physical library file of the general module to obtain the physical library file of the second module.

9. A physical design device, characterized in that: Applicable to a first module and a second module with the same logical function and different physical layout, the first module includes a main module and a first submodule, the second module includes the main module and a second submodule, the first submodule and the second submodule are obtained by multiplexing the same submodule, and the device includes: a merging unit, configured to merge the netlists of the first module and the second module to generate a netlist of a common module, wherein the netlist of the common module includes the netlists of the main module, the first submodule and the second submodule, and the external ports of the first module and the second module; A design unit, configured to perform physical design based on a netlist of the general module; A splitting unit, used for splitting the physical design of the universal module into a first module database and a second module database; A verification unit is used to perform physical verification and timing verification on the first module database and the second module database respectively.

10. A server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that: When the processor executes the computer program, the steps of the physical design method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the physical design method according to any one of claims 1 to 8 are implemented.

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