Storage circuit, control method, control device, storage system, and electronic device

Abstract

The invention discloses a storage circuit, a control method, a control device, a storage system and electronic equipment, and relates to the technical field of semiconductors. The memory circuit includes a memory cell array including a first memory cell sub-array and a second memory cell sub-array. The input ends of the storage units in the first storage unit subarray are connected with the first input line group, and the output ends of the storage units are connected with the first output line group; the input ends of the storage units in the second storage unit subarray are connected with the second input line group, and the output ends of the storage units are connected with the second output line group. The first input line group and the second input line group are independent and are used for alternately providing input signals for the first storage unit subarray and the second storage unit subarray; and the first output line group and the second output line group are independent and are used for respectively outputting calculation results of the first storage unit subarray and the second storage unit subarray. The storage circuit can integrally improve the computing power of a storage and computing system.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a storage circuit, a control method, a control device, a memory-computation system, and an electronic device. Background Art

[0002] In traditional computing models, such as the von Neumann architecture, storage and computing are physically separated. When using this computing model for data processing, data is frequently transferred between storage devices and computing devices, resulting in data transfer latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the amount of data processed has increased rapidly, and the demand for data transfer has also increased rapidly. The resulting transfer latency and energy consumption have become increasingly prominent, restricting the development of data processing capabilities and making it difficult for traditional computing models to meet the requirements of processing capabilities.

[0003] The memory-computation integrated architecture can physically integrate storage and computing. This physical integration includes, for example, integrating the storage and computing parts in close proximity through processes such as packaging; or, integrating a processing circuit with processing capabilities in a memory to achieve the integration of in-memory processing functions; or, implementing computing through storage devices or storing data in computing devices to achieve the tight integration of storage and computing. The memory-computation integrated architecture can reduce the demand for data transfer, lower transfer latency and energy consumption, and greatly improve data processing efficiency. However, the memory-computation integrated architecture still faces challenges. For example, the computing efficiency of the memory-computation integrated architecture still needs to be improved. Summary of the Invention

[0004] This application provides a storage circuit, a control method, a control device, a memory-computation system, and an electronic device to improve the computing efficiency of the memory-computation integrated architecture, thereby achieving an increase in computing power.

[0005] In a first aspect, a storage circuit is provided. The storage circuit includes: a first storage unit sub-array and a second storage unit sub-array. Among them, the input terminals of the storage units in the first storage unit sub-array are connected to a first input line group, and the output terminals of the storage units in the first storage unit sub-array are connected to a first output line group; the input terminals of the storage units in the second storage unit sub-array are connected to a second input line group, and the output terminals of the storage units in the second storage unit sub-array are connected to a second output line group; the first input line group and the second input line group are independent and are used to alternately provide input signals to the first storage unit sub-array and the second storage unit sub-array; the first output line group and the second output line group are independent and are used to respectively output the calculation results of the first storage unit sub-array and the second storage unit sub-array.

[0006] Through the technical solution of the embodiments of the present application, the storage circuit divides the storage cell array into different storage cell sub-arrays by using independent input line groups and output line groups. These different storage cell sub-arrays can support the alternating calculation of the storage cell array, improve the utilization rate of the storage cell array or the peripheral circuit through the alternating calculation, release more computing power of the storage cell array or the peripheral circuit, thereby improving the overall computing efficiency of the memory-computation system and ultimately enhancing the computing power of the chip.

[0007] In some implementation manners of the first aspect, the storage cell array includes the storage cells of the first row or the first column. The storage cells of the first row or the first column include the storage cells of the first storage cell sub-array and the storage cells of the second storage cell sub-array, and are respectively connected to the first input line and the second input line. The first input line belongs to the first input line group, and the second input line belongs to the second input line group; alternatively, the storage cell array includes the storage cells of the first row or the first column, and the storage cells of the second row or the second column. The storage cells of the first row or the first column include the storage cells of the first storage cell sub-array and the storage cells of the third storage cell sub-array, and are respectively connected to the first input line and the third input line. The storage cells of the second row or the second column include the storage cells of the second storage cell sub-array and the storage cells of the fourth storage cell sub-array, and are respectively connected to the second input line and the fourth input line. Among them, the first input line belongs to the first input line group, the second input line belongs to the second input line group, the third input line belongs to the third input line group, and the fourth input line belongs to the fourth input line group. The third input line group is used to input signals to the third storage cell sub-array, and the fourth input line group is used to input signals to the fourth storage cell sub-array. The storage cell array further includes the third storage cell sub-array and the fourth storage cell sub-array.

[0008] Through the technical solution of the embodiments of the present application, the storage cell array can be split into more than one set of ping-pong storage cell sub-arrays, and the storage cells of different sets of storage cell sub-arrays can share the input lines, thus reducing the coupling during the alternating calculation.

[0009] In some implementation manners of the first aspect, the storage circuit includes a first region and a second region. Among them, the first storage cell sub-array and the first output line group are located in the first region, and the second storage cell sub-array and the second output line group are located in the second region.

[0010] Through the technical solution of the embodiments of the present application, the storage circuit is split into two regions, so that the signal establishment of the second storage cell sub-array is not affected when the first storage cell sub-array is calculating. This structure is beneficial to simplifying the layout of the first input line group and the second input line group, and has relatively low requirements for the process improvement of the storage cell array. The alternating (or ping-pong) calculation of the storage circuit can be realized with a low-cost improvement.

[0011] In some implementations of the first aspect, the first input line group and the second input line group extend along a first direction, the first output line group and the second output line group extend along a second direction, and the first direction intersects the second direction; the second region is located on one side of the first region along the first direction.

[0012] In some implementations of the first aspect, the output lines in the first output line group and the output lines in the second output line group are arranged in an interleaved manner.

[0013] In some implementations of the first aspect, the first input line group includes a first input line, the second input line group includes a second input line, and at least one of a third input line and a fourth input line is included between the first input line and the second input line. The third input line belongs to a third input line group for signal input to a third memory cell sub-array, and the fourth input line belongs to a fourth input line group for signal input to a fourth memory cell sub-array.

[0014] In some implementations of the first aspect, the memory circuit includes a first memory and computing array and a second memory and computing array. The first memory and computing array includes the first memory cell sub-array and the second memory cell sub-array, and the second memory and computing array includes a third memory cell sub-array and a fourth memory cell sub-array. The input terminals of the memory cells in the third memory cell sub-array are connected to the third input line group, and the output terminals of the memory cells in the third memory cell sub-array are connected to the third output line group. The input terminals of the memory cells in the fourth memory cell sub-array are connected to the fourth input line group, and the output terminals of the memory cells in the fourth memory cell sub-array are connected to the fourth output line group. The third input line group and the fourth input line group are independent and are used to alternately provide input signals to the third memory cell sub-array and the fourth memory cell sub-array. The third output line group and the fourth output line group are independent and are used to respectively output the calculation results of the third memory cell sub-array and the fourth memory cell sub-array.

[0015] Through the technical solution of the embodiments of the present application, the memory circuit divides the memory cell array into different memory and computing arrays by using independent input line groups and output line groups. Each memory and computing array includes multiple memory cell sub-arrays. The different memory cell sub-arrays can support the alternating calculation of the memory cell array. By means of alternating calculation, the utilization rate of the memory cell array or the peripheral circuit is improved, and more computing power of the memory cell array or the peripheral circuit is released, thereby overall improving the overall calculation efficiency of the memory and computing system and ultimately improving the chip computing power.

[0016] In some implementations of the first aspect, the first output line group and the third output line group are the same output line group; the second output line group and the fourth output line group are the same output line group.

[0017] In certain implementations of the first aspect, the first input line group includes a first input line, the second input line group includes a second input line, the third input line group includes a third input line, and the fourth input line group includes a fourth input line; wherein, the memory cells connected by the first input line and the fourth input line are located in the same row or the same column; or, the memory cells connected by the first input line and the second input line are located in the same row or the same column.

[0018] In this implementation, the same row or the same column of the memory circuit may include memory cells in different memory cell sub-arrays of different memory computing arrays, which can reduce the coupling between different memory cell sub-arrays in the same memory computing unit during alternating calculations.

[0019] In certain implementations of the first aspect, the memory cells connected by the second input line and the third input line are located in the same row or the same column; or the memory cells connected by the second input line and the fifth input line are located in the same row or the same column, wherein the fifth input line belongs to a fifth input line group, and the fifth input line group is used to provide input signals to a fifth memory cell sub-array included in a third memory computing array, and the memory circuit further includes a third memory computing array.

[0020] In this implementation, the same row or the same column of the memory circuit may include memory cells in different memory cell sub-arrays of different memory computing arrays, which can reduce the coupling between different memory cell sub-arrays in the same memory computing unit during alternating calculations.

[0021] In certain implementations of the first aspect, the first input line group includes a first input line, the second input line group includes a second input line, wherein the first input line and the second input line share the same input circuit.

[0022] In this implementation, the input lines in the first input line group and the input lines in the second input line group can share the same input circuit, reducing the requirement for the number of input sub-circuits, saving the complexity of the peripheral circuit, and saving the chip area.

[0023] In a second aspect, a control method is provided for controlling a memory circuit. The control method includes: controlling the memory cell array of the memory circuit to perform multiple rounds of computing tasks, including: controlling the first memory cell sub-array and the second memory cell sub-array to perform calculations alternately, wherein there is an overlap between the time of the first round of calculations corresponding to the first memory cell sub-array and the time of the second round of calculations corresponding to the second memory cell sub-array.

[0024] In certain implementations of the second aspect, controlling the memory cell array of the memory circuit to perform multiple rounds of computing tasks further includes: controlling the third memory cell sub-array and the fourth memory cell sub-array to perform computations alternately, where the time for the third round of computation corresponding to the third memory cell sub-array and the time for the fourth round of computation corresponding to the fourth memory cell sub-array overlap.

[0025] In a third aspect, a control device is provided, including at least one processor and an interface circuit. The interface circuit is used for signal connection with the memory circuit, and the at least one processor is used to execute the control method of any item in the second aspect.

[0026] In a fourth aspect, a memory computing system is provided, including the memory circuit of any item in the first aspect and a control device for controlling the memory circuit.

[0027] In a fifth aspect, an electronic device is provided, including the memory computing system provided in the fourth aspect. Description of the Drawings

[0028] Figure 1 A schematic diagram of a memory computing system according to an exemplary embodiment of the present application is shown.

[0029] Figure 2 A schematic diagram of another memory computing system according to an exemplary embodiment of the present application is shown.

[0030] Figure 3 A schematic diagram of a memory circuit according to an exemplary embodiment of the present application is shown.

[0031] Figure 4 A schematic diagram of the computing timing of a memory computing system according to an exemplary embodiment of the present application is shown.

[0032] Figure 5 A schematic diagram of another memory circuit according to an exemplary embodiment of the present application is shown.

[0033] Figure 6 A schematic diagram of a memory device according to an exemplary embodiment of the present application is shown.

[0034] Figure 7 A schematic diagram of another memory circuit according to an exemplary embodiment of the present application is shown.

[0035] Figure 8 A schematic diagram of another memory circuit according to an exemplary embodiment of the present application is shown.

[0036] Figure 9 A schematic diagram of another memory circuit according to an exemplary embodiment of the present application is shown.

[0037] Figure 10Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0038] Figure 11 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0039] Figure 12 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0040] Figure 13 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0041] Figure 14 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0042] Figure 15 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0043] Figure 16 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0044] Figure 17 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0045] Figure 18 Shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application.

[0046] Figure 19 Shows a schematic diagram of a control method according to an exemplary embodiment of the present application.

[0047] Figure 20 Shows a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0048] Figure 21 Shows a schematic diagram of an electronic device according to an exemplary embodiment of the present application. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings.

[0050] To make the drawings concise, only the parts related to the corresponding embodiments are schematically shown in the drawings of the embodiments of the present application, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, only some structures or components are schematically shown, and there may actually be more or fewer identical or similar structures or components.

[0051] The business scenarios described in the embodiments of this application are used to exemplarily illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As can be known to those of ordinary skill in the art, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0052] In this application, unless otherwise clearly specified and limited, "connection" includes direct or indirect connection between objects: the connected objects can be directly connected through a medium (for example, a wire, a trace, etc.), or can be indirectly connected through other components, or can be internally connected. "Coupling" includes signal connection between objects, which can be directly realized through a medium (for example, a wire, a trace, etc.), or can be realized through other components for signal connection, etc. "Grounding" includes direct grounding or indirect grounding. Indirect grounding, for example, includes grounding through other components.

[0053] In this application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish the described objects, and cannot be understood as indicating or implying the relative importance or order between the described objects. In addition, ordinal numbers do not represent the quantity of the described objects. "Multiple" includes two or more, and other quantifiers are similar. "Or", "and / or" are used to describe the relationship between objects, which means non-exclusive inclusion. For example, "A and / or B", "A or B" can include: "A alone", "B alone", or "A and B". Again, "A, B and / or C", "A, B or C" can include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C". In addition, " / " in this application is used to represent the "or" relationship between the front and rear objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of the above "A and / or B", "A or B". The meaning of "one or more of A, B and C" or "at least one of A, B and C" is the same as the meaning of the above "A, B and / or C", "A, B or C".

[0054] In the in-memory computing technology, storage and computing (or operation) are physically integrated. Such physical integration includes, for example, integrating the storage and computing parts in close proximity through processes such as packaging. Another example is integrating a processing circuit with processing capabilities in a memory to achieve the integration of in-memory processing functions. Yet another example is to implement computing through storage devices or store data in computing devices to achieve the tight integration of storage and computing. According to some embodiments, the in-memory computing system may include a storage circuit and a processing circuit (or a control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computing, or sensing of the computing results of data. For example, the processing circuit may call the data stored in the storage circuit and perform computations based on the called data. Another example is that the processing circuit may control the computing of the storage circuit. Yet another example is that the processing circuit may be used to read or sense the computing results of the storage circuit and process the computing results. The present application does not limit the type of the memory, and the memory may include, for example, but not limited to: non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, for example, but not limited to: static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, for example, but not limited to: flash memory, resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or phase change memory (PCM), etc.

[0055] For ease of understanding, Figure 1 FIG. shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of the present application. This in-memory computing system is described by taking in-memory computing implemented with a memory as a carrier as an example.

[0056] As Figure 1As shown, the memory - in - computing system 100 may include a memory circuit (or memory - in - computing circuit) 110 and a control circuit 120. The memory circuit 110 may be used to store weight data (which may also be referred to as weights); the control circuit 120 may be used to control the working state of the memory circuit 110. The working state of the memory circuit 110 includes, for example, a programming state and a computing state. In the programming state, the weight data is written into the memory circuit 110. In the computing state, the memory circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The memory circuit 110 may store multiple weight data, and the multiple weight data may be equivalent to at least one vector (or matrix). The memory circuit 110 may store the weight data in units of memory cells (cells), and the memory cells may also be referred to as storage units or storage structures. For example, the memory circuit 110 includes a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array.

[0057] The memory cell includes a semiconductor device and can utilize the conduction ability of the semiconductor device, such as conductance or transconductance, to achieve the storage of weight data. For example, the memory cell may include a resistive memory device or a transistor memory device. For example, the storage of weight data can be achieved by controlling the conductance of the resistive memory device, or the storage of weight data can be achieved by controlling the transconductance of the transistor memory device. Alternatively, the memory cell can utilize the energy stored in the energy - storage element to achieve the storage of weight data, such as using the charge stored in a capacitor to achieve the storage of weight data; the energy - storage element can be connected to the semiconductor device, and the stored energy can act on the semiconductor device, causing the semiconductor device to generate an appropriate conduction ability.

[0058] The memory circuit 110 can perform calculations in groups. For example, the memory cell array includes at least one memory cell group, and the memory cell group includes a plurality of memory cells and can store multiple weight data. The multiple weight data can be equivalent to a first data vector (or a first data matrix). In the programming state, the weight data is written into the memory cells, which is equivalent to writing the first data vector (or the first data matrix) into the memory cell group in the memory cell array. In the computing state, the memory circuit 110 receives an input signal, the conduction ability of the memory cell can change the input signal to obtain an output signal, and the cumulative output of the output signals in the memory cell group can achieve an equivalent multiplication operation. The memory cell array may include a one - dimensional array, a two - dimensional array, or a three - dimensional array, etc. The memory cell group includes a plurality of memory cells in the same row or the same column in the memory cell array, or a plurality of memory cells in multiple rows or multiple columns, etc., and the plurality of memory cells can output collinearly.

[0059] In some possible embodiments, the memory - computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 may convert the input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on the weight data; the output circuit 140 may convert the output signal Sout into output data D2 for output. The at least one input signal may be equivalent to a second data vector (or a second data matrix), and the output data D2 may be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0060] As an example, Figure 2 FIG. shows a schematic diagram of another memory - computing system according to an exemplary embodiment of the present application.

[0061] As Figure 2 shown, the memory - computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes a plurality of memory cells S ij , where i ∈ [1, m], j ∈ [1, n], m is the number of rows of the memory cell array, and n is the number of columns of the memory cell array. The memory cell S ij can store weight data W ij . When the memory cell array 210 is in the programming state, the conduction ability of the memory cell S ij can be controlled based on the weight data to reach a target state, thereby achieving the storage of the weight data. When the memory cell array 210 is in the computing state, an input signal, such as an input voltage V ij , can be provided to the memory cell S ij through the input terminal IN of the memory cell S i ; the memory cell S ij outputs its output signal at the output terminal OUT, such as an output current. The output terminals of multiple memory cells (such as S 1j - S mj ) can output collinearly. According to Kirchhoff's law, the output signals of multiple memory cells accumulate, and the obtained output signal I j satisfies the following formula:

[0062]

[0063] In some possible embodiments, the input data includes digital input signals, and the input signal V iIt may include analog signals. The input circuit 230 may include, for example, a digital to analog converter (DAC) that converts digital signals into analog signals and provides them to the memory cell array 210. In some possible embodiments, the input signals of the memory cell array 210 may include digital signals, which are represented by the waveform characteristics of the signals, such as the pulse width, amplitude, or area of the signals. The input circuit 230 may adjust the waveform of the signals based on the input data to obtain input signals and provide them to the memory cell array 210.

[0064] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signals of the memory cell array 210 and then outputting them to the subsequent circuit. Such conversion may include one or more of signal type conversion, signal magnitude conversion, etc., such as one or more of current-voltage conversion, analog-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signals of the memory cell array 210. For example, if the output signals of the memory cell array 210 include current signals, the first conversion circuit 241 may convert the current signals into voltage signals. Again, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signals of the memory cell array 210. The second conversion may be implemented by a sampling circuit, for example. Optionally, the signals obtained by the conversion of the first conversion circuit 241 may be further provided to the second conversion circuit 242 for the second conversion. By way of example, the first conversion circuit 241 includes, for example, a transimpedance amplifier (TIA) to convert current signals into voltage signals; the second conversion circuit 242 includes, for example, an analog to digital converter (ADC) to convert analog signals into digital signals and provide them to the subsequent circuit. Again, the output circuit may include a sense amplifier (SA), and the SA may sense and amplify the signals obtained from the memory cell array 210 or the first conversion circuit 241. Additionally, in Figure 2 the example, the memory and computing system 200 may further include a control circuit 220, and the control circuit 220 may be used to control the operating states of the memory cells S ij in the memory cell array 210, such as the programming state and the computing state described above.

[0065] Figure 2 Only by way of example, a connection manner of the memory cells in a memory cell array 210 is shown. In addition to Figure 2In addition to the connection methods shown, other connection methods can also be used. For example, the input ends of the storage unit are connected in columns, and the output ends of the storage unit are connected in rows. For another example, the input end of the storage unit may include the gate of a transistor storage device, or the input end of the storage unit may include the source or drain of a transistor storage device, which is not limited in the embodiments of the present application. The present application also does not limit the type of storage unit. For example, the storage unit may include but is not limited to: a transistor, a memristor, a magnetic tunnel junction (MTJ) or a phase change structure. The present application also does not limit the type of transistor, for example, including a metal oxide semiconductor field effect transistor (MOSFET), a floating gate transistor (FGT), a ferroelectric field effect transistor (FeFET), or a thin film transistor (thin film transistor). For another example, the storage unit may include a plurality of transistors; for example, the storage unit may include a first transistor and a second transistor, wherein the gate of the first transistor is connected to the source or drain of the second transistor, and the charge stored at the gate of the first transistor can be used to characterize the weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of stored charge.

[0066] When the storage and computing system performs calculations, a round of computing tasks may include the process of establishing internal signals and the computing process. The internal signal establishment process, for example, includes the process of establishing the input signal of the input circuit to the storage circuit, or includes the process of establishing the output signal of the storage circuit, or includes the process of establishing the output signal of the conversion circuit; the computing process, for example, may include the conversion process of the storage circuit, or includes the conversion process of the first conversion circuit, or includes the conversion process of the second conversion circuit. The storage and computing system can perform multiple rounds of computing tasks. At present, for the same storage cell array, it is necessary to wait for the completion of the previous round of computing tasks before the next round of computing tasks can be performed, and peripheral circuits such as input circuits and output circuits also need to wait. In this way, the computing power of the storage circuit and peripheral circuits of the storage and computing system is not fully utilized, which limits the computing power of the storage circuit, as well as the computing power of peripheral circuits such as input circuits and output circuits, thereby limiting the computing power of the storage and computing system. Based on this, an embodiment of the present application provides a storage circuit, which can better utilize the computing power of peripheral circuits such as storage circuits, input circuits or output circuits of the storage and computing system, and improve the computing power of the storage and computing system as a whole, so that the computing efficiency of the storage and computing system can be improved.

[0067] Figure 3 A schematic diagram of a storage circuit according to an exemplary embodiment of the present application is shown. As Figure 3 shown, the storage circuit 300 includes a storage cell array 310; wherein, the storage cell array 310 includes a first storage cell sub-array 311 and a second storage cell sub-array 312. The storage circuit 300 further includes a first input line group 321, a second input line group 322, a first output line group 331, and a second output line group 332.

[0068] The input ends of the storage cells in the first storage cell sub-array 311 are connected to the first input line group 321, and the output ends of the storage cells in the first storage cell sub-array 311 are connected to the first output line group 331. The input ends of the storage cells in the second storage cell sub-array 312 are connected to the second input line group 322, and the output ends of the storage cells in the second storage cell sub-array 312 are connected to the second output line group 332.

[0069] The first input line group 321 and the second input line group 322 are independent and are used to alternately provide input signals Sin1 and Sin2 to the first storage cell sub-array 311 and the second storage cell sub-array 312. The first output line group 331 and the second output line group 332 are independent and are used to output the calculation results Sout1 and Sout2 of the first storage cell sub-array 311 and the second storage cell sub-array 312 respectively.

[0070] The above storage circuit divides the storage cell array into different storage cell sub-arrays by using independent input line groups and output line groups. The different storage cell sub-arrays can support the alternating calculation of the storage cell array, and improve the utilization rate of the storage cell array or the peripheral circuit through the alternating calculation, release more computing power of the storage cell array or the peripheral circuit, thereby overall improving the overall calculation efficiency of the memory-computation system and ultimately improving the chip computing power.

[0071] For ease of understanding, Figure 4 a schematic diagram of the calculation timing of a memory-computation system according to an exemplary embodiment of the present application is shown. In Figure 4 it, D1 and D2 are used to represent the preparation time before calculation. For example, it includes the signal establishment time. C1 and C2 are used to represent the calculation time. D1 and C1 are related to the first storage cell sub-array, and D2 and C2 are related to the second storage cell sub-array. For example, D1 can represent the establishment time of the input signal Sin1 input to the first storage cell sub-array. After this time, the input signal Sin1 reaches stability. C1 can represent the calculation time of the first storage cell sub-array; D2 can represent the establishment time of the input signal Sin2 input to the second storage cell sub-array. After this time, the input signal Sin2 reaches stability. C2 can represent the calculation time of the second storage cell sub-array. FromFigure 4 As can be seen, the computing task for the second memory cell sub-array (e.g., the second-round computing) can be started within the computing time of the first memory cell sub-array. Utilizing this computing time, preparations can be made for the computing of the second memory cell sub-array without waiting for the end of the first-round computing task, that is, the second-round computing task can be started; similarly, the computing task for the first memory cell sub-array (e.g., the third-round computing) can be started within the computing time of the second memory cell sub-array without waiting for the end of the second-round computing task, that is, the third-round computing task can be started. For another example, D1 can represent the setup time of the output signal Sout1 of the first memory cell sub-array. After this time, the output signal Sout1 reaches stability. C1 can represent the computing time of the conversion circuit connected to the first memory cell sub-array; D2 can represent the setup time of the output signal Sout2 of the second memory cell sub-array. After this time, the output signal Sout2 reaches stability. C2 represents the computing time of the conversion circuit connected to the second memory cell sub-array. From Figure 4 As can be seen, during the time when the conversion circuit connected to the first memory cell sub-array performs computing, the setup of the output signal of the second memory cell sub-array can be carried out without waiting for the end of the first-round computing task, that is, part of the computing or signal setup in the second-round computing task can be carried out. The meanings represented by D1 and D2 can be the same or different. Similarly, the meanings represented by C1 and C2 can be the same or different.

[0072] For example, during the first-round computing, an input signal is provided to the first memory cell sub-array. After the establishment process of the input signal, the input signal reaches stability. The first memory cell sub-array performs computing and establishes an output signal representing the computing result; after the output signal stabilizes, the conversion circuit can perform computing and output the output signal after conversion. The second-round computing can include a process similar to the first-round computing. Based on the above memory cell array, part of the process of the second-round computing can overlap with the cycle of the first-round computing. For example, part or all of the input signal establishment process, the computing process of the second memory cell sub-array (or the establishment process of the output signal corresponding to the computing result), the computing process of the conversion circuit connected to the second memory cell sub-array, etc. can overlap with the cycle of the first-round computing.

[0073] The input signal Sin1 input to the first memory cell sub-array 311 and the input signal Sin2 input to the second memory cell sub-array 312 can be the same or different, and the present application does not impose any restrictions, and the input signals Sin1 and Sin2 are different according to the different services executed by the storage circuit.

[0074] In some possible embodiments, splitting is performed in the first direction (e.g., row direction) and the second direction (e.g., column direction) of the array, such that the calculation of the first storage cell sub-array does not affect the signal establishment of the second storage cell sub-array. This structure is beneficial for simplifying the layout of the first input line group and the second input line group, and has relatively low requirements for the process improvement of the storage cell array. It can achieve the alternate (or ping-pong) calculation of the storage circuit with low-cost improvements.

[0075] The following is a description with reference to the accompanying drawings. Please refer to Figure 5 , which shows a schematic diagram of another storage circuit provided by an exemplary embodiment of the present application. As Figure 5 shown, the storage circuit 500 includes a storage cell array 510, and the storage cell array 510 includes a first storage cell sub-array 511 and a second storage cell sub-array 512. The first storage cell sub-array 511 includes a plurality of first storage cells S i1 , S i3 , ……, S i(n-1) , and the first input line group includes a first input line IN1i. A plurality of first storage cells S i1 , S i3 , ……, S i(n-1) share the first input line IN1i. The second storage cell sub-array 512 includes a plurality of second storage cells S i2 , S i4 , ……, S in , and the second input line group includes a second input line IN2i. A plurality of second storage cells S i2 , S i4 , ……, S in share the second input line IN2i; and a plurality of first storage cells S i1 , S i3 , ……, S i(n-1) and a plurality of second storage cells S i2 , S i4 , ……, S in are located in the same row. Figure 5 The illustrated embodiment describes the case of splitting the storage cells by column, and the present application is not limited thereto. The storage cells can also be split by row. For example, a plurality of first storage cells and a plurality of second storage cells are located in the same column. Wherein, i ∈ [1, m], m is the number of rows of the storage cell array, and n is the number of columns of the storage cell array.

[0076] In addition, Figure 5The illustrated embodiments are split in an alternating manner. In other embodiments, the split may not be in an alternating manner. For example, the memory cell array 510 may be divided into two regions in the first direction or the second direction, respectively for the first memory cell sub-array or the second memory cell sub-array; or, it may be split alternately by X rows or Y columns, where X may be a positive integer greater than or equal to 1, and Y may be a positive integer greater than or equal to 1. Another example is that the memory cell array may be split evenly or unevenly. For example, the number of memory cells included in the first memory cell sub-array and the second memory cell sub-array may be the same or different. That is, the present application does not limit the distribution manner of the first output line group and the second output line group. For example, the output lines OUT1-OUTn may be split into the first input line group and the second output line group, where the first output line group and the second output line group may adopt an alternating layout or a centralized layout, etc.

[0077] In the above embodiments, multiple first memory cells and multiple second memory cells are located in the same row or the same column. In some other possible embodiments, the multiple first memory cells and the multiple second memory cells are located in adjacent rows or adjacent columns.

[0078] In some embodiments of the present application, the memory cell array may be split into more than one pair of ping-pong memory cell sub-arrays, and the memory cells of different groups of memory cell sub-arrays may share the same row or the same column, thus reducing the coupling during alternating calculations. For example, the memory cell array further includes a third memory cell sub-array and a fourth memory cell sub-array. The memory cell array includes the memory cells of the first row or the first column, and the memory cells of the second row or the second column. The memory cells of the first row or the first column include the memory cells of the first memory cell sub-array and the memory cells of the third memory cell sub-array, which are respectively connected to the first input line and the third input line; the memory cells of the second row or the second column include the memory cells of the second memory cell sub-array and the memory cells of the fourth memory cell sub-array, which are respectively connected to the second input line and the fourth input line; the first input line belongs to the first input line group, the second input line belongs to the second input line group, the third input line belongs to the third input line group, the fourth input line belongs to the fourth input line group, the third input line group is used to input signals to the third memory cell sub-array, and the fourth input line group is used to input signals to the fourth memory cell sub-array.

[0079] The number of input lines of the first input line group and the second input line group may be the same or different; the number of output lines of the first output line group and the second output line group may be the same or different. The number of input lines of the third input line group and the fourth input line group may be the same or different. The number of output lines of the third output line group and the fourth output line group may be the same or different.

[0080] In some possible embodiments, the first input line group 321 includes at least one first input line, and the second input line group 322 includes at least one second input line. Among them, the at least one first input line and the at least one second input line share the same input sub-circuit. For example, they share the same DAC. In this way, the input sub-circuit can provide input signals to different input lines at different times, so as to support the alternating calculation of the storage circuit with a reduced area of the peripheral circuit.

[0081] Similarly, the output circuit can be shared to support the alternating calculation of the storage circuit and reduce the area of the peripheral circuit. For example, in some possible embodiments, the first output line group 331 includes at least one first output line, and the second output line group 332 includes at least one second output line. Among them, the at least one first output line and the at least one second output line share the same output sub-circuit, and the output sub-circuit includes, for example, one or more of a first conversion circuit and a second conversion circuit.

[0082] In the above storage circuit, the storage cell array can be divided into a first storage cell sub-array and a second storage cell sub-array. The first storage cell sub-array and the second storage cell sub-array can alternately and independently receive and process input signals, and can independently output calculation results. Thus, the calculation of one storage cell sub-array does not affect the signal establishment process (including input signal establishment or output signal establishment) of the other storage cell sub-array. Therefore, the signal establishment process of the other storage cell sub-array can be realized by using the calculation time of one storage cell sub-array, which improves the utilization rate of the computing power of the storage cell array and the peripheral circuit, and thus improves the overall computing efficiency and computing power of the memory computing system. In addition, the input line groups and output line groups between the storage cell sub-arrays are independent of each other, which can reduce the interference received by the input and output of the storage cell sub-array and further improve the accuracy of the calculation results.

[0083] The embodiment of the present application further provides a storage device. The storage device may include any one of the above storage circuits, and may further include a selection circuit. The selection circuit is used to select a target input line and provide the input signal output by the input sub-circuit to the target input line, and the target input line is an input line among at least one first input line and at least one second input line sharing the input sub-circuit. According to some embodiments, the selection circuit is used to alternately select the first input line and the second input line.

[0084] The following is a description with reference to the drawings. Figure 6 shows a schematic diagram of a storage device according to an exemplary embodiment of the present application. As Figure 6As shown, the storage device 600 includes a storage circuit 610 and a selection circuit 620. The storage circuit 610 includes a storage cell array 611, a first input line group 612, a second input line group 613, a first output line group 614, and a second output line group 615. The storage cell array 611 includes a first storage cell sub-array 611-1 and a second storage cell sub-array 611-2. The first input line group 612 is used to connect the input ends of the storage cells in the first storage cell sub-array 611-1. The second input line group 613 is used to connect the input ends of the storage cells in the second storage cell sub-array 611-2. The first output line group 614 is used to connect the output ends of the storage cells in the first storage cell sub-array 611-1. The second output line group 615 is used to connect the output ends of the storage cells in the second storage cell sub-array 611-2.

[0085] The selection circuit 620 is connected to the first input line group 612 and the second input line group 613, and is used to select a target input line and provide the input signal output by the input sub-circuit to the target input line. The target input line is an input line among at least one first input line and at least one second input line of the shared input sub-circuit.

[0086] The first storage cell sub-array 611-1 and the second storage cell sub-array 611-2 can respectively input the calculation results into the output circuit through the first output line group 614 and the second output line group 615. Exemplarily, the output circuit may include at least one conversion circuit.

[0087] In some possible embodiments, the selection circuit 620 may include a multiplexer (MUX). The input end of the multiplexer is coupled to the output end of the input sub-circuit, and the multiplexer includes a plurality of output ends for coupling to at least one first input line and at least one second input line. The control end of the multiplexer receives a control signal and selects a target input line based on the control signal. The control signal may come from a control circuit. The control signal can control the multiplexer to alternately select the first input line and the second input line to receive the input signal.

[0088] In some other embodiments, an input sub-circuit may also be connected to each input line, and the control circuit controls the input sub-circuits connected to the first input line and the second input line to work alternately, so as to alternately provide input signals to the first input line and the second input line.

[0089] During multiple rounds of calculations in the memory - computing system, the selection circuit 620 can alternately input the input signal into the first memory cell sub - array 611 - 1 and the second memory cell sub - array 611 - 2. The first memory cell sub - array 611 - 1 and the second memory cell sub - array 611 - 2 can alternately and independently process the input signal and output the calculation result. Therefore, during multiple rounds of calculations, the first memory cell sub - array 611 - 1 and the second memory cell sub - array 611 - 2 can alternately reuse the peripheral circuit, and the peripheral circuit can work more efficiently in terms of timing, reduce the waiting time, or even work continuously, thereby improving the utilization rate of the peripheral circuit. In addition, the memory cell sub - array can also reduce the waiting time for the previous round of calculation or even work continuously, thereby improving the utilization rate of the memory cell sub - array, and overall improving the computing power of the memory - computing system.

[0090] In addition, by setting the selection circuit 620, multiple first memory cells and multiple second memory cells in the first memory cell sub - array and the second memory cell sub - array share the same input sub - circuit, reducing the requirement for the number of input sub - circuits, saving the complexity of the peripheral circuit, and saving the chip area.

[0091] One round of calculation task in the embodiment of the present application may include the establishment of the input signal of the memory cell sub - array, the establishment of the output signal of the memory cell sub - array, and at least one conversion and output process of the output signal. The calculation of the memory cell sub - array may include the calculation process of the memory cell sub - array in this round of calculation task, or it can be understood as the establishment process of the output signal of the memory cell sub - array.

[0092] The above text is introduced with the storage circuit including two memory cell sub - arrays, but the embodiment of the present application is not limited thereto. In some other embodiments of the present application, the storage circuit may include more memory cell sub - arrays, which will be described below in conjunction with Figure 7 for introduction.

[0093] Figure 7 shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. As Figure 7 shown, the storage circuit 700 includes N memory - computing arrays, where N≥2 and is an integer. The N memory - computing arrays include a first memory - computing array 711 and a second memory - computing array 712. The first memory - computing array 711 includes a first memory cell sub - array 711 - 1 and a second memory cell sub - array 711 - 2. The second memory - computing array 712 includes a third memory cell sub - array 712 - 1 and a fourth memory cell sub - array 712 - 2. The storage circuit 700 further includes a first input line group 721, a second input line group 722, a third input line group 723, a fourth input line group 724, a first output line group 731, a second output line group 732, a third output line group 733, and a fourth output line group 734.

[0094] The input terminals of the memory cells in the first memory cell sub-array 711-1 are connected to the first input line group 721, and the output terminals of the memory cells in the first memory cell sub-array 711-1 are connected to the first output line group 731. The input terminals of the memory cells in the second memory cell sub-array 711-2 are connected to the second input line group 722, and the output terminals of the memory cells in the second memory cell sub-array 711-2 are connected to the second output line group 732. The input terminals of the memory cells in the third memory cell sub-array 712-1 are connected to the third input line group 723, and the output terminals of the memory cells in the third memory cell sub-array 712-1 are connected to the third output line group 733. The input terminals of the memory cells in the fourth memory cell sub-array 712-2 are connected to the fourth input line group 724, and the output terminals of the memory cells in the fourth memory cell sub-array 712-2 are connected to the fourth output line group 734.

[0095] The third input line group 723 and the fourth input line group 724 are independent and are used to alternately provide input signals Sin3 and Sin4 to the third memory cell sub-array 712-1 and the fourth memory cell sub-array 712-2.

[0096] The third output line group 733 and the fourth output line group 734 are independent and are used to output the calculation results Sout3 and Sout4 of the third memory cell sub-array 712-1 and the fourth memory cell sub-array 712-2 respectively.

[0097] The above memory circuit divides the memory cell array into different memory cell sub-arrays by using independent input line groups and output line groups. The different memory cell sub-arrays can support the alternating calculation of the memory cell array. By alternating calculation, the utilization rate of the memory cell array or the peripheral circuit can be improved, more computing power of the memory cell array or the peripheral circuit can be released, thereby overall improving the overall calculation efficiency of the memory-computation system and ultimately improving the chip computing power.

[0098] According to some embodiments of the present application, the first output line group and the third output line group are the same output line group; the second output line group and the fourth output line group are the same output line group, that is, the memory cell sub-arrays that do not perform calculations simultaneously can share the same output line group. For example, the first memory cell sub-array that performs alternating calculations is called the Ping1 array, the second memory cell sub-array is called the Pong1 array, and the third memory cell sub-array that performs alternating calculations is called the Ping2 array, and the fourth memory cell sub-array is called the Pong2 array. Then the Ping1 array and the Ping2 array can share the same output line group, and the Pong1 array and the Pong2 array can share the same output line group, so that the complexity of the wiring can be reduced.

[0099] In some possible embodiments, the storage circuit 700 may perform multiple rounds of calculations. Among them, the first storage unit sub-array 711-1 is used for the first round of calculation, the second storage unit sub-array 711-2 is used for the second round of calculation, the third storage unit sub-array 712-1 is used for the third round of calculation, and the fourth storage unit sub-array 712-2 is used for the fourth round of calculation. Among them, the time of at least two rounds of calculations overlaps. For example, the time of the first round of calculation corresponding to the first storage unit sub-array 711-1 and the time of the second round of calculation corresponding to the second storage unit sub-array 711-2 overlap; the time of the third round of calculation corresponding to the third storage unit sub-array 712-1 and the time of the fourth round of calculation corresponding to the fourth storage unit sub-array 712-2 overlap.

[0100] In some possible embodiments, the first input line group 721 includes a first input line, the second input line group 722 includes a second input line, the third input line group 723 includes a third input line, and the fourth input line group 724 includes a fourth input line. Among them, the storage units connected by the first input line and the storage units connected by the third input line are in the same row or the same column of the storage circuit 700; the storage units connected by the second input line and the storage units connected by the fourth input line are in the same row or the same column of the storage circuit 700; or the storage units connected by the first input line and the storage units connected by the second input line are in the same row or the same column; the storage units connected by the third input line and the storage units connected by the fourth input line are in the same row or the same column; or the storage units connected by the first input line and the storage units connected by the fourth input line are in the same row or the same column, and the storage units connected by the second input line and the storage units connected by the third input line are in the same row or the same column.

[0101] In the embodiments of the present application, the same row or the same column of the storage circuit may include storage units in different storage unit sub-arrays of different memory computing arrays, which can reduce the coupling between different storage unit sub-arrays in the same memory computing unit during alternating calculations.

[0102] In some possible embodiments, the N memory computing arrays include a third memory computing array. The third memory computing array includes a fifth storage unit sub-array and a sixth storage unit sub-array. The input ends of the storage units in the fifth storage unit sub-array are connected to the fifth input line group, and the output ends of the storage units in the fifth storage unit sub-array are connected to the fifth output line group. The input ends of the storage units in the sixth storage unit sub-array are connected to the sixth input line group, and the output ends of the storage units in the sixth storage unit sub-array are connected to the sixth output line group. The fifth input line group and the sixth input line group are independent and are used to alternately provide input signals to the fifth storage unit sub-array and the sixth storage unit sub-array. The fifth output line group and the sixth output line group are independent and are used to output the calculation results of the fifth storage unit sub-array and the sixth storage unit sub-array respectively.

[0103] In some possible embodiments, the fifth input line group includes a fifth input line, and the memory cells connected to the second input line and the memory cells connected to the third input line are in the same row or the same column, or the memory cells connected to the second input line and the memory cells connected to the fifth input line are in the same row or the same column.

[0104] In the above storage circuit, the storage circuit can be split into multiple groups of ping-pong memory cell sub-arrays. When the memory cells of different groups of memory cell sub-arrays are in the same row or the same column, the coupling during alternating calculations can be reduced.

[0105] The above introduced the storage circuit and the storage device including the storage circuit provided by the embodiments of the present application. Below, several implementation manners of the memory cell sub-arrays of the storage circuit will be exemplarily introduced.

[0106] Figure 8 shows a schematic diagram of a storage circuit according to an exemplary embodiment of the present application. In Figure 8 where Hx represents a memory and computing array, where x represents the ordinal number of the memory and computing array and can be any positive integer; Hx-Ping represents a memory cell sub-array in the memory and computing array, and Hx-Pong represents another memory cell sub-array in the memory and computing array; Hx-Ping-y identifies the input line in the input line group connected to the memory cell sub-array Hx-Ping, and Hx-Pong-y identifies the input line in the input line group connected to the memory cell sub-array Hx-Pong. And for the sake of distinction, different icons (such as rectangles and triangles) are used to represent the memory cells of the memory cell sub-array Hx-Ping and the memory cells of the memory cell sub-array Hx-Pong, but it does not represent the difference of the memory cells. The memory cells of different memory cell sub-arrays can be the same or different, and the same memory cells have a simpler process implementation and better circuit performance.

[0107] As Figure 8 shown, the memory cell array may include a first region and a second region. Among them, the memory cell sub-array Hx-Ping and the corresponding output line group are located in the first region, and the memory cell sub-array Hx-Pong and the corresponding output line group are located in the second region. In this memory cell array structure, the output lines can be divided into two groups, arranged in regions in terms of physical addresses, and are respectively used for the output of the memory cell sub-array Hx-Ping and the memory cell sub-array Hx-Pong.

[0108] According to some embodiments of the present application, the input lines can extend along a first direction, the output lines can extend along a second direction, and the first direction and the second direction intersect. Optionally, the second region can be located on one side of the first region along the first direction. Exemplarily, Figure 8Taking the row direction as the first direction and the column direction as the second direction as an example. In some other embodiments, the first direction may be the column direction and the second direction may be the row direction.

[0109] According to some embodiments of the present application, the first region and the second region are located on the same side of the selection circuit. In this way, the wiring layout of the storage device can be simplified, and it is convenient for the selection circuit to be connected to the input circuit and the storage circuit.

[0110] According to some embodiments of the present application, the selection circuit may include multiple selection sub-circuits. The input lines of different storage unit sub-arrays can multiplex the input sub-circuit through the selection sub-circuit, and the present application does not limit the number of input lines of the multiplexed input sub-circuit. For ease of understanding, Figure 8 two selection sub-circuits are taken as an example for description. However, the present application is not limited thereto, and actually more selection sub-circuits may be included; and the 8 input lines of the memory and computing arrays H1-H4 multiplex the input sub-circuit, and the input sub-circuit includes a DAC as an example for description; however, the present application is not limited thereto, and actually more or fewer input lines may multiplex the same input sub-circuit, for example, more or fewer input lines of the memory and computing arrays multiplex the same input sub-circuit, or more input lines of a memory and computing array multiplex the same input sub-circuit.

[0111] Exemplarily, continue to refer to Figure 8, the input lines H1-Ping-0, H2-Ping-0, H3-Ping-0, H4-Ping-0, H1-Pong-0, H2-Pong-0, H3-Pong-0, and H4-Pong-0 share the same input sub-circuit. In the figure, taking the DAC as an example, for instance, DAC-0 is shared. The selection circuit includes a selection sub-circuit-0, which is connected to the input lines H1-Ping-0, H2-Ping-0, H3-Ping-0, H4-Ping-0, H1-Pong-0, H2-Pong-0, H3-Pong-0, and H4-Pong-0. The input lines H1-Ping-1, H2-Ping-1, H3-Ping-1, H4-Ping-1, H1-Pong-1, H2-Pong-1, H3-Pong-1, and H4-Pong-1 share the same input sub-circuit, for example, DAC-1 is shared. The selection circuit includes a selection sub-circuit-1, which is connected to the input lines H1-Ping-1, H2-Ping-1, H3-Ping-1, H4-Ping-1, H1-Pong-1, H2-Pong-1, H3-Pong-1, and H4-Pong-1. The selection sub-circuit-y can alternately select the input lines Hx-Ping-y and Hx-Pong-y corresponding to the memory cell sub-arrays Hx-Ping and Hx-Pong to couple the input signals, so that the input lines of the memory cell sub-arrays alternately receive the input signals, realizing alternate calculation.

[0112] Continue to refer to Figure 8 , in some possible embodiments, the same row of the memory circuit may include memory cells in the memory cell sub-array Hx-Ping and memory cells in the memory cell sub-array Hx-Pong; in some other possible embodiments, the same column of the memory circuit includes memory cells in the memory cell sub-array Hx-Ping and memory cells in the memory cell sub-array Hx-Pong.

[0113] In some embodiments of the present application, the first input line group and the second input line group may be arranged in an interleaved manner, and the interleaved arrangement may include uniform interleaving or non-uniform interleaving.

[0114] In some embodiments of the present application, the same row or the same column of the memory circuit includes memory cells of memory cell sub-arrays of different memory and computing arrays.

[0115] For example, in some possible embodiments, the same row or the same column of the storage circuit includes storage cells in the storage cell sub-array Hx-Ping and storage cells in the storage cell sub-array Hx’-Pong, where x’ is different from x. The input lines in the input line group corresponding to the storage cell sub-array Hx-Ping and the input lines in the input line group corresponding to the storage cell sub-array Hx-Pong are arranged in an interleaved manner, that is, there is at least one input line between the input line corresponding to the storage cell sub-array Hx-Ping and the input line corresponding to the storage cell sub-array Hx-Pong, and this input line is the input line corresponding to the storage cell sub-array of other memory computing arrays. For example, the storage cells connected to the input line H1-Ping-0 and the input line H1-Pong-0 are located in different rows of the storage circuit, and there are also other input lines between the input line H1-Ping-0 and the input line H1-Pong-0, such as the input line Hx’-Ping / Pong-y.

[0116] For example, Figure 9 FIG. shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. Figure 9 The meanings of the various identifiers in Figure 8 are referred to

[0117] As Figure 9 shown, the difference from the embodiment shown in Figure 8 is that the same row of the storage circuit includes storage cells in the storage cell sub-array Hx-Ping and storage cells in the storage cell sub-array Hx’-Pong, where x’ is different from x. For example, the input line H1-ping-0 and H3-pong-0 are connected to storage cells in the same row, the input line H2-ping-0 and H4-pong-0 are connected to storage cells in the same row, the input line H3-ping-0 and H1-pong-0 are connected to storage cells in the same row, the input line H4-ping-0 and H2-pong-0 are connected to storage cells in the same row; again, for example, the input line H1-ping-1 and H3-pong-1 are connected to storage cells in the same row, the input line H2-ping-1 and H4-pong-1 are connected to storage cells in the same row, the input line H3-ping-1 and H1-pong-1 are connected to storage cells in the same row, the input line H4-ping-1 and H2-pong-1 are connected to storage cells in the same row. In this way, the coupling during alternating calculations can be reduced, and the computing performance of the storage circuit can be improved. Figure 9 In, for each selection sub-circuit, the physical arrangement of the input lines is the same. In other embodiments, the physical arrangements of the input lines of different selection sub-circuits may also be different. The same physical arrangement can reduce the control logic requirements for the selection circuit and reduce the complexity of the storage device.

[0118] Figure 10 shows a schematic diagram of a storage circuit according to an exemplary embodiment of the present application. In Figure 10 the meanings of Hx, Hx-Ping, Hx-Pong, Hx-Ping-y, and Hx-Pong-y refer to Figure 8 the description of Figure 10 OUT-Ping-k in identifies the output line in the output line group connected to the storage cell sub-array Hx-Ping, and OUT-Pong-k identifies the output line in the output line group connected to the storage cell sub-array Hx-Pong. k is an integer used to identify the output line.

[0119] As Figure 10 shown, the output lines in the output line group corresponding to the storage cell sub-array Hx-Ping and the output lines in the output line group corresponding to Hx-Pong are arranged in an interleaved manner. This interleaved arrangement may include uniform interleaving or non-uniform interleaving.

[0120] According to some embodiments of the present application, the input lines may extend in a first direction, and the output lines may extend in a second direction, and the first direction and the second direction intersect. Exemplarily, Figure 10 the row direction is taken as the first direction and the column direction is taken as the second direction for description. In some other embodiments, the first direction may be the column direction and the second direction may be the row direction.

[0121] According to some embodiments of the present application, the selection circuit may include multiple selection sub-circuits, and the input lines of different storage cell sub-arrays may multiplex the input sub-circuit through the selection sub-circuit. For specific description, refer to Figure 8 the description in , and details will not be elaborated here.

[0122] Continuing to refer to Figure 10 , in some possible embodiments, the same row of the storage circuit includes the storage cells in the storage cell sub-array Hx-Ping and the storage cells in the storage cell sub-array Hx-Pong; in some other possible embodiments, the same column of the storage circuit includes the storage cells in the storage cell sub-array Hx-Ping and the storage cells in the storage cell sub-array Hx-Pong.

[0123] In some embodiments of the present application, the first input line group and the second input line group may be arranged in an interleaved manner, and this interleaved arrangement may include uniform interleaving or non-uniform interleaving.

[0124] In some embodiments of the present application, the same row or the same column of the storage circuit includes the storage cells of the storage cell sub-arrays of different memory and computing arrays.

[0125] For example, in some possible embodiments, the same row or the same column of the storage circuit includes storage units in the storage unit sub-array Hx-Ping and storage units in the storage unit sub-array Hx'-Pong, where x' is different from x. The input lines in the input line group corresponding to the storage unit sub-array Hx-Ping and the input lines in the input line group corresponding to the storage unit sub-array Hx'-Pong are arranged in an interleaved manner, that is, there is at least one input line between the input lines corresponding to the storage unit sub-array Hx-Ping and the input lines corresponding to the storage unit sub-array Hx'-Pong, and this input line is the input line corresponding to the storage unit sub-array of other memory computing arrays. For example, the storage units connected to the input line H1-Ping-0 and the input line H1-Pong-0 are located in different rows of the storage circuit, and there are also other input lines between the input line H1-Ping-0 and the input line H1-Pong-0, such as the input line Hx'-Ping / Pong-y.

[0126] For example, Figure 11 FIG. shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. Figure 11 The meanings of the various identifiers in Figure 8 are referred to

[0127] As Figure 11 shown, the difference from the embodiment shown in Figure 10 is that the same row of the storage circuit includes storage units in the storage unit sub-array Hx-Ping and storage units in the storage unit sub-array Hx'-Pong, where x' is different from x. For example, the storage units connected by the input lines H1-Ping-0 and H3-Pong-0 are in the same row, the storage units connected by the input lines H2-Ping-0 and H1-Pong-0 are in the same row, and the storage units connected by the input lines H3-Ping-0 and H2-Pong-0 are in the same row; again, the storage units connected by the input lines H1-Ping-1 and H3-Pong-1 are in the same row, the storage units connected by the input lines H2-Ping-1 and H1-Pong-1 are in the same row, and the storage units connected by the input lines H3-Ping-1 and H2-Pong-1 are in the same row. In this way, the coupling during alternating calculations can be reduced, and the computing performance of the storage circuit can be improved.

[0128] According to some embodiments of the present application, the storage cell sub-arrays Hx-Ping of different memory and computing arrays can share the same output line; similarly, the storage cell sub-arrays Hx-Pong of different memory and computing arrays can share the same output line. For example, the storage cell sub-arrays H1-Ping, H2-Ping, and H3-Ping of the memory and computing arrays H1-H3 share the same output line OUT-Ping-k. For example, the storage cell sub-arrays H1-Pong, H2-Pong, and H3-Pong of the memory and computing arrays H1-H3 share the same output line OUT-Pong-k. In this way, the complexity of the wiring can be reduced.

[0129] For example, Figure 12 FIG. shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. Figure 12 The meanings of Hx-Ping, Hx-Ping, Hx-Ping-y, and Hx-Pong-y in Figure 8 are referred to Figure 12 In it, OUTx-Ping-k identifies the output line in the output line group connected to the storage cell sub-array Hx-Ping, and OUTx-Pong-k identifies the output line in the output line group connected to the storage cell sub-array Hx-Pong.

[0130] As Figure 12 shown, the difference from the embodiments shown in Figure 10 and Figure 11 is that different storage cell sub-arrays are connected to the output lines in different output line groups. For example, the output lines OUT1-Ping-0, OUT1-Ping-1, and OUT1-Ping-2 are connected to the storage cells in the storage cell sub-array H1-Ping. For another example, the output lines OUT1-Pong-0, OUT1-Pong-1, and OUT1-Pong-2 are connected to the storage cells in the storage cell sub-array H1-Pong. For another example, the output lines OUT2-Ping-0, OUT2-Ping-1, and OUT2-Ping-2 are connected to the storage cells in the storage cell sub-array H2-Ping. For another example, the output lines OUT2-Pong-0, OUT2-Pong-1, and OUT2-Pong-2 are connected to the storage cells in the storage cell sub-array H2-Pong. For another example, the output lines OUT3-Ping-0, OUT3-Ping-1, and OUT3-Ping-2 are connected to the storage cells in the storage cell sub-array H3-Ping. For another example, the output lines OUT3-Pong-0, OUT3-Pong-1, and OUT3-Pong-2 are connected to the storage cells in the storage cell sub-array H3-Pong.

[0131] The present application does not limit the type of storage unit. For example, the storage unit may include a two-terminal storage unit included in a memory such as RRAM, conductive bridge random access memory (CBRAM), phase change random access memory (PCRAM), FeRAM, MRAM, MTJ, or selector only memory (SOM). For example, it may include a three-terminal storage unit included in a memory such as FLASH, DRAM, FeFET, etc.

[0132] The above describes a storage circuit and a storage device including the storage circuit. The following describes several exemplary connection methods between storage units and input lines and output lines.

[0133] Figures 13 - 18 Schematic diagrams showing other storage circuits according to exemplary embodiments of the present application.

[0134] Figures 13 - 16 shows that in taking a similar Figures 10 - 12 A schematic diagram of the connection between the storage unit and the input line and the output line in the case of the arrangement shown, Figures 13 - 16 The meanings of the input line group and output line group identifiers used in the description of similar identifiers can be referred to above and will not be repeated here.

[0135] like Figure 13 As shown, the storage unit is a two-terminal storage unit, including an input terminal and an output terminal, and the input terminal and the output terminal are respectively connected between corresponding input lines and output lines.

[0136] like Figures 14 - 16 As shown, the memory cell is a multi-terminal memory cell, including an input terminal, an output terminal and a selection terminal. The selection terminal is used to turn on the corresponding memory cell. The selection terminal can be connected and led out in a first direction, or can be connected and led out in a second direction. Optionally, the selection terminal can be led out independently in rows or columns, or can be led out in multiple rows / columns. The input terminal can include a gate, the output terminal can include a source or a drain, and the selection terminal can include a drain or a source; or the input terminal can include a source or a drain, the output terminal can include a drain or a source, and the selection terminal can include a gate. For example, Figure 14 As shown, taking a FLASH or FeFET implementation as an example, the input end may include a gate, the output end may include a source or a drain, and the selection end may include a drain or a source; the selection end is connected and led out in a first direction. Figure 15 As shown, the selection end is connected and led out in the second direction. Figure 16 As shown in the figure, the selection terminals are connected in multiple columns. Figures 14 - 16In [the figure], the selection line SL-o can be used to connect and lead out the selection terminal.

[0137] Figure 17 and Figure 18 shows a schematic diagram of the connection mode of the storage unit with the input line and the output line in the case of adopting an arrangement similar to that Figure 8 and Figure 9 shown. The identifiers of the input line group and the output line group adopted in [the figure] are the same as those above, and will not be elaborated here. Figure 17 and Figure 18 The identifiers of the input line group and the output line group adopted in [the figure] are the same as those above, and will not be elaborated here.

[0138] As Figure 17 shown, the storage unit is a two-terminal storage unit, including an input terminal and an output terminal, and the input terminal and the output terminal are respectively connected between the corresponding input line and output line.

[0139] As Figure 18 shown, the storage unit is a multi-terminal storage unit, including an input terminal, an output terminal and a selection terminal. The selection terminal is used to turn on the corresponding storage unit. The selection terminal can be connected and led out in the first direction, or can be connected and led out in the second direction. Optionally, the selection terminal can be independently led out row by row or column by column, or can be led out jointly by multiple rows / multiple columns. The input terminal can include a gate, the output terminal can include a source or a drain, and the selection terminal can include a drain or a source; or, the input terminal can include a source or a drain, the output terminal can include a drain or a source, and the selection terminal can include a gate. Exemplarily, as Figure 18 shown, taking the implementation of FLASH or FeFET as an example, the input terminal can include a gate, the output terminal can include a source or a drain, and the selection terminal can include a drain or a source; the selection terminal is connected and led out in the first direction. In Figure 18 In [the figure], the selection line SL-o can be used to connect and lead out the selection terminal.

[0140] The embodiment of the present application also provides a control method, which is executed by a control device and is used to control any one of the storage circuits provided in the above embodiments. For example, Figure 19 shows a schematic diagram of a control method according to an exemplary embodiment of the present application. The control method 1900 can be used to control a storage circuit, and the storage circuit can include the structure of the storage circuit provided in any of the above embodiments.

[0141] As Figure 19 shown, the control method 1900 can include the following steps:

[0142] S1910, controlling the storage unit array of the storage circuit to perform multiple rounds of calculations.

[0143] S1920, control the first storage cell sub-array and the second storage cell sub-array to perform alternating calculations, where the time of the first round of calculations corresponding to the first storage cell sub-array and the time of the second round of calculations corresponding to the second storage cell sub-array overlap.

[0144] In the embodiments of the present application, by controlling the first storage cell sub-array and the second storage cell sub-array to perform alternating calculations, the utilization rate of the storage cell array or the peripheral circuit is improved, and more computing power of the storage cell array or the peripheral circuit is released, thereby overall improving the overall computing efficiency of the memory-computation system and ultimately improving the chip computing power.

[0145] In some possible embodiments, controlling the storage cell array of the storage circuit to perform multiple rounds of calculation tasks further includes: controlling the third storage cell sub-array and the fourth storage cell sub-array to perform alternating calculations, where the time of the third round of calculations corresponding to the third storage cell sub-array and the time of the fourth round of calculations corresponding to the fourth storage cell sub-array overlap. Optionally, the time of the first round of calculations or the time of the second round of calculations may also overlap with the time of the third round of calculations; optionally, the time of the first round of calculations or the time of the second round of calculations may also overlap with the time of the fourth round of calculations.

[0146] The embodiments of the present application also provide a control device, which is used to execute any one of the control methods provided in the above embodiments. For example, it includes units or means for executing each step of any one of the above control methods.

[0147] The present application does not limit the way of dividing the logical functions in the control device. In actual implementation, different logical functions of the control device can be fully or partially integrated into one physical entity, or physically separated. In addition, for example, the control method can be implemented in the form of a processor calling software; for example, the control device can include a processor, the processor is connected to a memory, instructions are stored in the memory, and the processor calls the instructions stored in the memory to implement any one of the above control methods, and the memory is a memory inside or outside the control device. Or, the above units can be implemented in the form of a hardware circuit, and the functions of part or all of the control device can be realized by designing the hardware circuit, and the hardware circuit can be understood as one or more processing circuits; for example, in some embodiments, the hardware circuit can include an application specific integrated circuit (ASIC), and the functions of part or all of the above control device are realized by designing the logical relationship of the devices in the circuit; for another example, in some embodiments, the hardware circuit can be realized by a programmable logic device (PLD) circuit, which can include a large number of logic devices, and the logical relationship between the logic devices is configured through a configuration file, so as to realize the functions of part or all of the above control device. The above control device can be implemented in the form of a processor calling a program; or in the form of a hardware circuit; or part in the form of a processor calling a program and part in the form of a hardware circuit.

[0148] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor can be a circuit with the ability to read and execute instructions. In other possible embodiments, the processor can implement its functions through the logical relationship of a hardware circuit, and the logical relationship of this hardware circuit is fixed or can be reconfigured. For example, the processor is a hardware circuit implemented by an ASIC or a PLD, such as a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the configuration of the hardware circuit can be understood as the process of the processor loading instructions to implement some or all of the functions of the above control device. The present application does not limit the type of the processor, for example, it includes a central processing unit (CPU), a microcontroller unit (MCU), a graphics processing unit (GPU), or a digital signal processor, etc. Or it can be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc.

[0149] In some possible embodiments, the above control device can be implemented in the form of a system on chip (SOC).

[0150] The embodiments of the present application also provide a control device, which can be located in or include the above control circuit, and this control device can be located Figure 1 or Figure 2 in the control circuit 120 / 220 shown, or independent of the control circuit 120 / 220. This control device can be used to execute any one of the above control methods.

[0151] The embodiments of the present application also provide a control device, which can be referred to Figure 20 . Figure 20 The figure shows a schematic diagram of a control device according to an exemplary embodiment of the present application. As Figure 20 shown, the control device 2000 includes: at least one processing circuit 2010 and an interface circuit 2020. The interface circuit 2020 is used for signal connection with the storage circuit, and at least one processing circuit 2010 is used to execute any one of the control methods provided in the above embodiments.

[0152] An embodiment of the present application further provides a memory-computation system, which includes a storage circuit and a control device. The storage circuit includes the structure of any one of the storage circuits provided in the above embodiments. The control device is used to control the working state of the storage circuit.

[0153] An embodiment of the present application further provides a computer program product, which includes instructions that, when executed by a processor, cause any one of the control methods in the above embodiments to be executed.

[0154] An embodiment of the present application further provides a computer-readable medium, which stores instructions that, when executed by a processor, cause any one of the control methods in the above embodiments to be executed.

[0155] An embodiment of the present application further provides an electronic device, which can be referred to Figure 21 . Figure 21 FIG. shows a schematic diagram of an electronic device according to an exemplary embodiment of the present application. As Figure 21 shown, the electronic device 2100 may include any one of the above memory-computation systems 2110 for processing data of the electronic device. The electronic device may further include an input / output device 2120 for receiving user input or outputting processing results. The present application does not limit the input type and output type. For example, the input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may further include a processor 2130, which may process the data provided to the memory-computation system 2110 or may process the output data of the memory-computation system 2110. The output of the above input / output device 2120 may be based on the output of the processor 2130 or the output of the memory-computation system 2110.

[0156] The present application does not limit the type of the electronic device. For example, according to some embodiments, the electronic device may include a wearable device. Wearable devices include, for example, but are not limited to: head-mounted devices (such as helmets or hats, etc.), devices that can be worn on the ears (such as headphones), devices that can be worn on the wrists (such as watches), devices that can be worn on other parts (such as, electronic necklaces, medical monitoring devices, or glasses, etc.). According to some embodiments, the electronic device may include a portable terminal. For example, the electronic device may include, but is not limited to, mobile phones, general computing devices (such as laptop computers, or tablet computers, etc.), personal digital assistants, and so on. According to some embodiments, the electronic device may include other types of end-side devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may further include devices such as servers.

[0157] In the above embodiments, the descriptions of different embodiments have their own focuses. For parts that are not described or recorded in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. And the above different embodiments can be freely combined as needed. Moreover, with the evolution of technology, the elements described in this application can be replaced by equivalent elements that appear after this application.

Claims

1. A storage circuit, characterized in that: The storage circuit comprises a storage cell array, wherein the storage cell array comprises a first storage cell sub-array and a second storage cell sub-array, wherein: The input ends of the memory cells in the first memory cell subarray are connected to the first input line group, and the output ends of the memory cells in the first memory cell subarray are connected to the first output line group; The input ends of the memory cells in the second memory cell sub-array are connected to the second input line group, and the output ends of the memory cells in the second memory cell sub-array are connected to the second output line group; The first input line group and the second input line group are independent and used to alternately provide input signals to the first storage cell subarray and the second storage cell subarray; the first output line group and the second output line group are independent and used to output calculation results of the first storage cell subarray and the second storage cell subarray respectively.

2. The storage circuit according to claim 1, wherein: The memory cell array comprises a first row or a first column of memory cells, wherein the first row or the first column of memory cells comprises memory cells of the first memory cell subarray and memory cells of the second memory cell subarray, and are respectively connected to a first input line and a second input line, wherein the first input line belongs to the first input line group, and the second input line belongs to the second input line group; or, The memory cell array includes a first row or a first column of memory cells, and a second row or a second column of memory cells, wherein the first row or the first column of memory cells includes memory cells of the first memory cell subarray and memory cells of the third memory cell subarray, which are respectively connected to a first input line and a third input line, and the second row or the second column of memory cells includes memory cells of the second memory cell subarray and memory cells of a fourth memory cell subarray, which are respectively connected to a second input line and a fourth input line, wherein the first input line belongs to the first input line group, the second input line belongs to the second input line group, the third input line belongs to the third input line group, and the fourth input line belongs to the fourth input line group, the third input line group is used to input signals to the third memory cell subarray, and the fourth input line group is used to input signals to the fourth memory cell subarray, and the memory cell array also includes the third memory cell subarray and the fourth memory cell subarray.

3. The storage circuit according to claim 1 or 2, characterized in that: The memory cell array includes a first region and a second region, wherein the first memory cell sub-array and the first output line group are located in the first region, and the second memory cell sub-array and the second output line group are located in the second region.

4. The storage circuit according to claim 3, characterized in that: The first input line group and the second input line group extend along a first direction, the first output line group and the second output line group extend along a second direction, and the first direction and the second direction intersect; The second area is located at one side of the first area along the first direction.

5. The storage circuit according to claim 1 or 2, characterized in that: The output lines in the first output line group are arranged alternately with the output lines in the second output line group.

6. The storage circuit according to any one of claims 1 to 5, characterized in that: The first input line group includes a first input line, the second input line group includes a second input line, at least one of a third input line and a fourth input line is included between the first input line and the second input line, the third input line belongs to a third input line group, the third input line group is used for signal input of a third storage unit subarray, the fourth input line belongs to a fourth input line group, and the fourth input line group is used for signal input of a fourth storage unit subarray.

7. The memory circuit according to any one of claims 1 to 6, characterized in that: The storage circuit includes a first storage and calculation array and a second storage and calculation array, wherein the first storage and calculation array includes the first storage cell sub-array and the second storage cell sub-array, and the second storage and calculation array includes a third storage cell sub-array and a fourth storage cell sub-array; The input ends of the memory cells in the third memory cell sub-array are connected to the third input line group, and the output ends of the memory cells in the third memory cell sub-array are connected to the third output line group; The input ends of the memory cells in the fourth memory cell subarray are connected to the fourth input line group, and the output ends of the memory cells in the fourth memory cell subarray are connected to the fourth output line group; The third input line group and the fourth input line group are independent and are used to alternately provide input signals to the third storage cell subarray and the fourth storage cell subarray; the third output line group and the fourth output line group are independent and are used to output calculation results of the third storage cell subarray and the fourth storage cell subarray respectively.

8. The storage circuit according to claim 7, characterized in that: The first output line group and the third output line group are the same output line group; the second output line group and the fourth output line group are the same output line group.

9. The storage circuit according to claim 7 or 8, characterized in that: The first input line group includes a first input line, the second input line group includes a second input line, the third input line group includes a third input line, and the fourth input line group includes a fourth input line; wherein, The storage units connected to the first input line and the fourth input line are located in the same row or the same column; or, The storage units connected to the first input line and the second input line are located in the same row or the same column.

10. The storage circuit according to claim 9, characterized in that: The storage units connected to the second input line and the third input line are located in the same row or the same column; or The storage units connected to the second input line and the fifth input line are located in the same row or column, wherein the fifth input line group belongs to a five-input line group, and the fifth input line group is used to provide input signals to the fifth storage unit sub-array included in the third storage and computing array, and the storage circuit also includes the third storage and computing array.

11. The memory circuit according to any one of claims 1 to 10, characterized in that: The first input line group includes a first input line, and the second input line group includes a second input line, wherein the first input line and the second input line multiplex a same input subcircuit.

12. A control method, characterized in that: Used to control the storage circuit according to any one of claims 1 to 11, the control method comprising: Controlling the storage cell array of the storage circuit to perform multiple rounds of computing tasks, including: The first storage unit subarray and the second storage unit subarray are controlled to perform calculations alternately, wherein a first round of calculation time corresponding to the first storage unit subarray and a second round of calculation time corresponding to the second storage unit subarray overlap.

13. The control method according to claim 12, characterized in that: Controlling the storage unit array of the storage circuit to perform multiple rounds of computing tasks also includes: The third storage unit subarray and the fourth storage unit subarray are controlled to perform calculations alternately, wherein a third round of calculation time corresponding to the third storage unit subarray and a fourth round of calculation time corresponding to the fourth storage unit subarray overlap.

14. A control device, characterized in that: The device comprises at least one processor and an interface circuit, wherein the interface circuit is used for signal connection with the storage circuit, and the at least one processor is used for executing the control method according to claim 12 or 13.

15. A storage and calculation system, characterized in that: It comprises a storage circuit as described in any one of claims 1 to 11 and a control device, wherein the control device is used to control the storage circuit.

16. An electronic device, characterized in that: Including the storage and calculation system as described in claim 15.

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