Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first substrate and a first bonding layer arranged on the first substrate, wherein the first bonding layer comprises a first dielectric layer and a first bonding welding pad arranged in the first dielectric layer; the second bonding layer is arranged on the second substrate, and the second bonding layer comprises a second dielectric layer and a second bonding welding pad arranged in the second dielectric layer; wherein the size of the second bonding pad in the direction parallel to the second substrate is smaller than the size of the first bonding pad in the direction parallel to the first substrate; the number of the second bonding pads is greater than that of the first bonding pads; the first bonding layer is connected with the second bonding layer, and each first bonding pad is connected with at least one second bonding pad.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In order to improve the integration density per unit area in a chip, the memory array (Array) and the peripheral circuit (CMOS) of the chip can be processed on two wafers respectively, and then wafer-to-wafer bonding is performed to form a three-dimensional chip.

[0003] Currently, there are still many problems to be solved in the three-dimensional chip formed by bonding. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.

[0005] To achieve the above object, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, embodiments of the present disclosure provide a semiconductor structure, which includes:

[0007] A first substrate, a first bonding layer disposed on the first substrate, the first bonding layer including a first dielectric layer and a first bonding pad disposed in the first dielectric layer;

[0008] A second substrate, a second bonding layer disposed on the second substrate, the second bonding layer including a second dielectric layer and a second bonding pad disposed in the second dielectric layer; wherein, the size of the second bonding pad along the direction parallel to the second substrate is smaller than the size of the first bonding pad along the direction parallel to the first substrate; the number of the second bonding pads is greater than the number of the first bonding pads;

[0009] The first bonding layer and the second bonding layer are bonded, and each first bonding pad is bonded to at least one second bonding pad.

[0010] In some embodiments, the size of the first bonding pad along the direction parallel to the first substrate is greater than or equal to the sum of the size of the second bonding pad along the direction parallel to the second substrate and the pitch between any two adjacent second bonding pads.

[0011] In some embodiments, the total contact area between the first bonding pad and the second bonding pad is greater than or equal to the product of the number of the first bonding pads and the orthographic projection area of the second bonding pad on the second substrate.

[0012] In some embodiments, the first bonding layer further includes a first barrier layer, and the first dielectric layer is located between the first substrate and the first barrier layer; wherein, the materials of the first barrier layer and the first dielectric layer are different; and / or,

[0013] The second bonding layer further includes a second barrier layer, and the second dielectric layer is located between the second substrate and the second barrier layer; wherein, the materials of the second barrier layer and the second dielectric layer are different.

[0014] In some embodiments, the first bonding layer further includes a first adhesion layer, the first adhesion layer is located between the first substrate and the first dielectric layer, and the first bonding pad sequentially penetrates through the first barrier layer, the first dielectric layer, and the first adhesion layer; wherein, the materials of the first adhesion layer and the first dielectric layer are different; and / or,

[0015] The second bonding layer further includes a second adhesion layer, the second adhesion layer is located between the second substrate and the second dielectric layer, and the second bonding pad sequentially penetrates through the second barrier layer, the second dielectric layer, and the second adhesion layer; wherein, the materials of the second adhesion layer and the second dielectric layer are different.

[0016] In some embodiments, the semiconductor structure further includes:

[0017] A first dummy pad disposed in the first dielectric layer, wherein each of the first bonding pads is connected to a first metal wire through a first conductive pillar for transmitting an electrical signal; the first dummy pad is not connected to the first metal wire;

[0018] A second dummy pad disposed in the second dielectric layer, wherein each of the second bonding pads is connected to a second metal wire through a second conductive pillar for transmitting an electrical signal; at least some of the second dummy pads are not connected to the second metal wire;

[0019] The first dummy pad and the second dummy pad are bonded.

[0020] In some embodiments, the spacing between any two adjacent first bonding pads, the spacing between any two adjacent first dummy pads, and the spacing between any adjacent first bonding pad and the first dummy pad are all the same; and / or,

[0021] The spacing between any two adjacent second bonding pads, the spacing between any two adjacent second dummy pads, and the spacing between any adjacent second bonding pad and the second dummy pad are all the same.

[0022] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:

[0023] Provide a first substrate;

[0024] Form a first bonding layer on the first substrate; wherein, the first bonding layer includes a first dielectric layer and a first bonding pad disposed in the first dielectric layer;

[0025] Provide a second substrate;

[0026] Form a second bonding layer on the second substrate; wherein, the second bonding layer includes a second dielectric layer and a second bonding pad disposed in the second dielectric layer; wherein, the size of the second bonding pad in the direction parallel to the second substrate is smaller than the size of the first bonding pad in the direction parallel to the first substrate; the number of the second bonding pads is greater than the number of the first bonding pads;

[0027] Bond the first bonding layer and the second bonding layer, and bond each first bonding pad and at least one second bonding pad.

[0028] In some embodiments, forming the first bonding layer on the first substrate includes:

[0029] Form a first dielectric layer and a first barrier layer on the first substrate in sequence;

[0030] Etch the first barrier layer and part of the first dielectric layer in sequence to form an initial groove;

[0031] Fill a dielectric material in the initial groove to form a first protective layer; the first protective layer also covers the first barrier layer;

[0032] Etch the first protective layer and use the etched first barrier layer as a mask to etch the first dielectric layer to form a first groove;

[0033] Etch the first protective layer, the first barrier layer and the first dielectric layer in sequence to form a second groove; at least part of the second groove communicates with the first groove;

[0034] Fill a conductive material in the first groove and the second groove to form a first conductive material layer;

[0035] Perform a planarization process on the first conductive material layer and the first protective layer to form a first conductive pillar in the first groove and a first bonding pad in the second groove and expose the first barrier layer; wherein, the materials of the first barrier layer and the first dielectric layer are different.

[0036] In some embodiments, forming the first bonding layer on the first substrate includes:

[0037] Form a first adhesion layer, a first dielectric layer, a first barrier layer, and a first protective layer on the first substrate;

[0038] Etch the first protective layer, the first barrier layer, the first dielectric layer, and the first adhesion layer in sequence to form a second groove;

[0039] Fill the second groove with a conductive material to form a first conductive material layer;

[0040] Perform a planarization process on the first conductive material layer and the first protective layer to form a first bonding pad in the second groove and expose the first barrier layer; wherein, the materials of the first adhesion layer and the first dielectric layer are different.

[0041] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. In the embodiments of the present disclosure, since the size of the second bonding pad is smaller than that of the first bonding pad, and the number of the second bonding pads is greater than that of the first bonding pads, after the first bonding layer and the second bonding layer are bonded, each first bonding pad is bonded to at least one second bonding pad. In this way, even if there is an alignment offset during the bonding process, the contact area between the first bonding pad and the second bonding pad will not be reduced, resulting in an increase in contact resistance. Furthermore, it is beneficial to increase the process window of the bonding alignment process. Description of the Drawings

[0042] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided for some examples;

[0043] Figure 2 A schematic flow diagram of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figures 3A to 3L A schematic cross-sectional structure diagram of a semiconductor structure during manufacturing provided for some embodiments;

[0045] Figures 4A to 4G A schematic cross-sectional structure diagram of a semiconductor structure during manufacturing provided for some other embodiments. Detailed Embodiments

[0046] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present disclosure.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0048] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout the drawings, like reference numerals denote like elements.

[0049] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply the existence of a first element, component, region, layer, or section in the present disclosure.

[0050] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0053] With the development of semiconductor technology, in the wafer bonding process, a hybrid bonding (HB) process is usually adopted, that is, metal layer to metal layer bonding and dielectric layer to dielectric layer bonding. At the bonding interface, there are both intermolecular bonding of dielectric layer to dielectric layer and electrical connection of metal layer to metal layer. Therefore, high requirements are imposed on the bonding interface.

[0054] Currently, with the further miniaturization of device dimensions according to Moore's law, misalignment is likely to occur in the bonding between metal layers of wafers, which will lead to a reduction in the contact area and thus an increase in the contact resistance. In addition, there will be direct contact between the metal layer and the dielectric layer at the bonding interface, and metal diffusion (such as copper diffusion) problems may occur during the subsequent heat treatment process. Therefore, it is urgent to improve the bonding process.

[0055] Before introducing the embodiments of the present disclosure, three directions for describing semiconductor structures that may be used in the embodiments of the present disclosure are defined first. The three directions may include the X direction, the Y direction, and the Z direction. Both the X direction and the Y direction are parallel to the substrate and the X direction intersects the Y direction, and the Z direction is perpendicular to the substrate.

[0056] Reference Figure 1 , Figure 1 is a schematic cross-sectional structure diagram of a semiconductor structure provided for some examples. As Figure 1 shown, the first bonding pads 102 and the second bonding pads 104 are connected in one-to-one correspondence. Among them, the dimension of the first bonding pad in the X direction is L 102 , and the dimension of the second bonding pad 104 in the X direction is L 104 . The pitch between two adjacent first bonding pads 102 is b, that is, the dimension of the dielectric layer between two adjacent first bonding pads 102 in the X direction is b. Figure 1Schematically shows the size L of the first bonding pad 102 and the size L of the second bonding pad 104 to be the same.

[0057] If there is no alignment offset during the bonding process, the contact area between the first bonding pad 102 and the second bonding pad 104 is the positive projection area of the first bonding pad 102 (or the second bonding pad 104) in the XY plane. The size of the contact portion between the first bonding pad 102 and the second bonding pad 104 in the X direction is L 102 (or L 104 ).

[0058] Due to the alignment offset in the actual bonding process, the size of the contact portion between the first bonding pad 102 and the second bonding pad 104 in the X direction is (L 102 -a), that is, the alignment offset in the actual bonding process causes the contact area between the first bonding pad 102 and the second bonding pad 104 to decrease, thereby increasing the contact resistance.

[0059] In addition, due to the alignment offset in the actual bonding process, at the bonding interface (as shown by the dashed line in Figure 1 ), the first bonding pad 102 (or the second bonding pad 104) will be in direct contact with the dielectric layer, and problems such as metal diffusion (such as copper diffusion) may occur during the subsequent heat treatment process.

[0060] Referring to Figure 2 , Figure 2 is a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 2 , an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:

[0061] Step S201: Provide a first substrate;

[0062] Step S202: Form a first bonding layer on the first substrate; wherein, the first bonding layer includes a first dielectric layer and a first bonding pad disposed in the first dielectric layer;

[0063] Step S203: Provide a second substrate;

[0064] Step S204: Form a second bonding layer on the second substrate; wherein, the second bonding layer includes a second dielectric layer and a second bonding pad disposed in the second dielectric layer; wherein, the size of the second bonding pad in the direction parallel to the second substrate is smaller than the size of the first bonding pad in the direction parallel to the first substrate; the number of the second bonding pads is greater than the number of the first bonding pads;

[0065] Step S205: Bond the first bonding layer and the second bonding layer, and bond each first bonding pad and at least one second bonding pad.

[0066] Reference Figures 3A to 3L , Figures 3A to 3L FIG. is a schematic cross-sectional structure diagram of a semiconductor structure provided for some embodiments during the manufacturing process. The following will be combined with Figure 2 and Figures 3A to 3L to describe in detail the manufacturing process of the semiconductor structure.

[0067] In an embodiment of the present disclosure, in step S201, a first substrate 302 is provided.

[0068] In an embodiment of the present disclosure, in step S202, a first bonding layer 320 is formed on the first substrate 302; wherein, the first bonding layer 320 includes a first dielectric layer 316 and first bonding pads 328 disposed in the first dielectric layer 316.

[0069] Exemplarily, a third dielectric layer 304 is further disposed between the first substrate 302 and the first bonding layer 320, and a first metal wire 306 and a first conductive pillar 312 are further disposed in the third dielectric layer 304, and the first metal wire 306 and the first conductive pillar 312 are electrically connected.

[0070] As Figure 3A shown, a third dielectric layer 304 is formed on the first substrate 302, and a first metal wire 306 is disposed in the third dielectric layer 304; a first mask layer 308 is formed on the third dielectric layer 304. Wherein, the first mask layer 308 has at least one opening, and the first mask layer 308 can be used to define the position of the first groove.

[0071] Here, the first substrate 302 may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc. The present disclosure places no special limitation on the material of the first substrate 302.

[0072] Here, a memory array may be formed on the first substrate 302; alternatively, peripheral circuits may be formed on the first substrate 302. Exemplarily, the memory array may be a Dynamic Random Access Memory (DRAM) memory array. A first metal wire 306 is provided in the third dielectric layer 304, and the first metal wire 306 can lead out the electrical signals of the memory array or the peripheral circuits on the first substrate 302.

[0073] Here, the process of forming the third dielectric layer 304 may include, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

[0074] In some embodiments, the material of the third dielectric layer 304 may be, for example, silicon dioxide.

[0075] In some embodiments, the material of the first mask layer 308 may be, for example, Photoresist (PR).

[0076] As Figure 3B shown, along the Z direction, the third dielectric layer 304 is etched using the first mask layer 308 to form a first groove 310; wherein, the bottom of the first groove 310 exposes the first metal wire 306; the first mask layer 308 is removed.

[0077] Here, the process of forming the first groove 310 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0078] Here, in the cross-sectional structure schematic diagram of the first groove 310 in the XZ plane, it presents an inverted trapezoid, and the top size of the first groove 310 is larger than the bottom size of the first groove 310. The positive projection of the first groove 310 on the XY plane may be a quadrilateral, a circle, an ellipse, etc. The present disclosure has no special limitation on the shape of the positive projection of the first groove 310 on the XY plane and the XZ plane.

[0079] As Figure 3C shown, a conductive material is filled in the first groove 310, and the conductive material also covers the third dielectric layer 304; the conductive material is planarized to form a first conductive column 312 in the first groove 310 and expose the third dielectric layer 304.

[0080] Here, the conductive material may include, but is not limited to, gold, copper, aluminum, etc. In a specific embodiment, copper is filled in the first groove 310.

[0081] Here, the planarization process may include, but is not limited to, chemical mechanical polishing (CMP).

[0082] As Figure 3C shown, in some embodiments, a first adhesion layer 314 is formed on the first substrate 302, including: forming the first adhesion layer 314 on the third dielectric layer 304 and the first conductive pillar 312.

[0083] As Figure 3D shown, in some embodiments, step S202 includes: sequentially forming a first dielectric layer 316, a first barrier layer 318, a first protection layer 322, and a second mask layer 324 on the first adhesion layer 314; wherein, the first adhesion layer 314, the first dielectric layer 316, and the first barrier layer 318 together form a first bonding layer 320; along the Z direction, the first protection layer 322, the first barrier layer 318, the first dielectric layer 316, and the first adhesion layer 314 are sequentially etched using the second mask layer 324 to form a second groove 326; the second mask layer 324 is removed. Wherein, the second mask layer 324 has at least one opening, and the second mask layer 324 can be used to define the position of the second groove 326.

[0084] In some embodiments, the size of the second groove 326 in the X direction is greater than the size of the first groove 310 in the X direction.

[0085] Here, the processes for forming the first adhesion layer 314, the first dielectric layer 316, the first barrier layer 318, and the first protection layer 322 may include, but are not limited to, CVD, PVD, ALD, or any combination thereof.

[0086] In some embodiments, the materials of the first adhesion layer 314 and the first dielectric layer 316 are different; and / or, the materials of the first barrier layer 318 and the first dielectric layer 316 are different. Here, the materials of the first adhesion layer 314 and the first barrier layer 318 may be, for example, silicon carbonitride. The materials of the first dielectric layer 316 and the first protection layer 322 may be, for example, silicon dioxide.

[0087] In some embodiments, the material of the second mask layer 324 may be, for example, photoresist.

[0088] Here, the process for forming the second groove 326 may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0089] Here, the cross-sectional structure of the second groove 326 in the XZ plane is shown as a quadrilateral. The positive projection of the second groove 326 in the XY plane may be a quadrilateral, a circle, an ellipse, etc. The present disclosure does not have any special limitations on the shape of the positive projection of the second groove 326 in the XY plane and the XZ plane.

[0090] Figure 3D A plurality of second grooves 326 are shown, and the bottom of some of the plurality of second grooves 326 exposes the third dielectric layer 304. After filling the conductive material into this part of the second grooves 326, a first dummy pad is formed; the bottom of some of the plurality of second grooves 326 exposes the first conductive pillar 312. After filling the conductive material into this part of the second grooves 326, a first bonding pad is formed.

[0091] As Figure 3E shown, in some embodiments, step S202 includes: filling a conductive material into the second groove 326 to form a first conductive material layer; planarizing the first conductive material layer and the first protective layer 322 to form a first bonding pad 328 in some of the second grooves 326, forming a first dummy pad 330 in some of the second grooves 326, and exposing the first barrier layer 318.

[0092] Here, the first bonding layer 320 includes a first adhesion layer 314, a first dielectric layer 316, and a first barrier layer 318 that are stacked in sequence. The first bonding layer 320 is provided with a first bonding pad 328 and a first dummy pad 330. Both the first bonding pad 328 and the first dummy pad 330 penetrate through the first barrier layer 318, the first dielectric layer 316, and the first adhesion layer 314 in sequence.

[0093] In some embodiments, the first bonding pad 328 and the first dummy pad 330 have the same size.

[0094] In some embodiments, the first pad includes a first bonding pad 328 and a first dummy pad 330, and the spacing between any two adjacent first pads is the same, that is, the spacing between any two adjacent first bonding pads 328, the spacing between any two adjacent first dummy pads 330, and the spacing between any adjacent first bonding pad 328 and first dummy pad 330 are all the same.

[0095] In this way, it is more beneficial to simplify the process of etching to form the second groove, and it is more beneficial to control the dishing on the surface of the first bonding pad and the first dummy pad.

[0096] In the embodiments of the present disclosure, the difference between the first bonding pad 328 and the first dummy pad 330 is that: the first bonding pad 328 is connected to the first metal wire 306 through the first conductive pillar 312, and the first bonding pad 328 is used to transmit electrical signals; the first dummy pad 330 is not connected to the first metal wire 306, and the first dummy pad 330 cannot be used to transmit electrical signals.

[0097] Here, the material of the first conductive material layer may include, but is not limited to, gold, copper, aluminum, etc. In a specific embodiment, copper is filled in the second groove 326.

[0098] Here, the planarization process may include, but is not limited to, CMP.

[0099] In the embodiment of the present disclosure, in step S203, a second substrate 332 is provided.

[0100] In the embodiment of the present disclosure, in step S204, a second bonding layer 350 is formed on the second substrate 332; wherein, the second bonding layer 350 includes a second dielectric layer 346 and second bonding pads 358 disposed in the second dielectric layer 346; wherein, the size of the second bonding pads 358 in the direction parallel to the second substrate 332 is smaller than the size of the first bonding pads 328 in the direction parallel to the first substrate 302; the number of the second bonding pads 358 is greater than the number of the first bonding pads 328.

[0101] Exemplarily, a fourth dielectric layer 334 is further provided between the second substrate 332 and the second bonding layer 350. Second metal lines 336 and second conductive posts 342 are further provided in the fourth dielectric layer 334, and the second metal lines 336 and the second conductive posts 342 are electrically connected.

[0102] As Figure 3F shown, a fourth dielectric layer 334 is formed on the second substrate 332, and second metal lines 336 are provided in the fourth dielectric layer 334; a third mask layer 338 is formed on the fourth dielectric layer 334. Among them, the third mask layer 338 has at least one opening, and the third mask layer 338 can be used to define the position of the third groove.

[0103] Here, a memory array may be formed on the first substrate 302, and a peripheral circuit may be formed on the second substrate 332; or, a peripheral circuit may be formed on the first substrate 302, and a memory array may be formed on the second substrate 332.

[0104] Here, the materials and formation processes of the second substrate 332, the fourth dielectric layer 334, the second metal lines 336, and the third mask layer 338 may respectively refer to the relevant descriptions of the first substrate 302, the third dielectric layer 304, the first metal lines 306, and the first mask layer 308 described above, and will not be elaborated here.

[0105] As Figure 3G shown, along the Z direction, the fourth dielectric layer 334 is etched using the third mask layer 338 to form a third groove 340; wherein, the second metal lines 336 are exposed at the bottom of the third groove 340; the third mask layer 338 is removed.

[0106] Here, the process of forming the third groove 340 and the shape of the third groove 340 can refer to the relevant descriptions of the aforementioned first groove 310, which will not be elaborated here.

[0107] As Figure 3H shown, a conductive material is filled in the third groove 340, and the conductive material also covers the fourth dielectric layer 334; the conductive material is planarized to form a second conductive column 342 in the third groove 340 and expose the fourth dielectric layer 334.

[0108] Here, the process of filling the conductive material in the third groove 340 and the planarization process can refer to the relevant descriptions of the process of filling the conductive material in the first groove 310 and the planarization process, which will not be elaborated here.

[0109] As Figure 3H shown, in some embodiments, a second adhesion layer 344 is formed on the second substrate 332, including: forming the second adhesion layer 344 on the fourth dielectric layer 334 and the second conductive column 342.

[0110] As Figure 3I shown, in some embodiments, step S204 includes: forming a second dielectric layer 346, a second barrier layer 348, a second protective layer 352, and a fourth mask layer 354 on the second adhesion layer 344; wherein, the second adhesion layer 344, the second dielectric layer 346, and the second barrier layer 348 together form a second bonding layer 350; along the Z direction, the second protective layer 352, the second barrier layer 348, the second dielectric layer 346, and the second adhesion layer 344 are sequentially etched using the fourth mask layer 354 to form a fourth groove 356; the fourth mask layer 354 is removed. Among them, the fourth mask layer 354 has at least one opening, and the fourth mask layer 354 can be used to define the position of the fourth groove 356.

[0111] Here, the materials and formation processes of the second adhesion layer 344, the second dielectric layer 346, the second barrier layer 348, the second protective layer 352, and the fourth mask layer 354 can refer to the materials and formation processes of the aforementioned first adhesion layer 314, the first dielectric layer 316, the first barrier layer 318, the first protective layer 322, and the second mask layer 324. The process of forming the fourth groove 356 and the shape of the fourth groove 356 can refer to the relevant descriptions of the aforementioned second groove 326, which will not be elaborated here.

[0112] In some embodiments, the dimension of the fourth groove 356 in the X direction is greater than the dimension of the third groove 340 in the X direction.

[0113] In some embodiments, the materials of the second adhesion layer 344 and the second dielectric layer 346 are different; and / or, the materials of the second barrier layer 348 and the second dielectric layer 346 are different. Here, the materials of the second adhesion layer 344 and the second barrier layer 348 can be, for example, silicon carbonitride. The materials of the second dielectric layer 346 and the second protective layer 352 can be, for example, silicon dioxide.

[0114] Figure 3I A plurality of fourth grooves 356 are illustrated, and the bottoms of some of the plurality of fourth grooves 356 expose the fourth dielectric layer 334. After filling conductive material in this part of the fourth grooves 356, a second dummy pad is formed; the bottoms of some of the plurality of fourth grooves 356 expose the second conductive posts 342. After filling conductive material in this part of the fourth grooves 356, a second bonding pad or a second dummy pad is formed.

[0115] As Figure 3J shown, in some embodiments, step S204 includes: filling conductive material in the fourth grooves 356; planarizing the conductive material and the second protective layer 352 to form a second bonding pad 358 in some of the fourth grooves 356, forming a second dummy pad 360 in some of the fourth grooves 356, and exposing the second barrier layer 348.

[0116] Here, the second bonding layer 350 includes a second adhesion layer 344, a second dielectric layer 346, and a second barrier layer 348 that are stacked in sequence. The second bonding layer 350 is provided with a second bonding pad 358 and a second dummy pad 360. Both the second bonding pad 358 and the second dummy pad 360 penetrate through the second barrier layer 348, the second dielectric layer 346, and the second adhesion layer 344 in sequence.

[0117] In some embodiments, the second bonding pad 358 and the second dummy pad 360 have the same size.

[0118] In some embodiments, the second pad includes a second bonding pad 358 and a second dummy pad 360, and the spacing between any two adjacent second pads is the same, that is, the spacing between any two adjacent second bonding pads 358, the spacing between any two adjacent second dummy pads 360, and the spacing between any adjacent second bonding pad 358 and second dummy pad 360 are all the same.

[0119] In this way, it is more beneficial to simplify the process of etching to form the fourth grooves, and it is more beneficial to control the depression on the surfaces of the second bonding pad and the second dummy pad.

[0120] In the embodiments of the present disclosure, the difference between the second bonding pad 358 and the second dummy pad 360 is as follows: the second bonding pad 358 is connected to the second metal wire 336 through the second conductive pillar 342, and the second bonding pad 358 is used to transmit electrical signals; the second dummy pad 360 is not connected to the second metal wire 336, and the second dummy pad 360 cannot be used to transmit electrical signals, or the second dummy pad 360 is connected to the second metal wire 336 through the second conductive pillar 342, but the second dummy pad 360 is not bonded to the first bonding pad 328, and the second dummy pad 360 cannot be used to transmit electrical signals.

[0121] As Figure 3K shown, step S205 includes: bonding (i.e., joining) the first bonding layer 320 and the second bonding layer 350 to form a semiconductor structure 300; wherein, at the bonding interface (as Figure 3K shown by the dashed line), the first bonding pad 328 and the second bonding pad 358 can form a metal bond for transmitting electrical signals; the first barrier layer 318 and the second barrier layer 348 can form an intermolecular bond. Here, the dimension of the first bonding pad 328 in the X direction is larger than the dimension of the second bonding pad 358 in the X direction; the number of the first bonding pads 328 is less than the number of the second bonding pads 358; each first bonding pad 328 can be bonded to at least one second bonding pad 358.

[0122] In this way, each first bonding pad can be bonded to at least one second bonding pad. Even if there is an alignment offset during the actual bonding process, the contact area between the first bonding pad and the second bonding pad will not be reduced, that is, the contact resistance will not increase, which is conducive to increasing the process window of the bonding alignment process.

[0123] In the embodiments of the present disclosure, a part of the first bonding pad (or the first dummy pad) contacts the second barrier layer, a part of the second bonding pad contacts the first barrier layer, and the second dummy pad contacts the first barrier layer. The first barrier layer and the second barrier layer can prevent the metal materials of the second bonding pad (or the second dummy pad) and the first bonding pad (or the first dummy pad) from diffusing to the bonding interface, thereby improving the performance of the semiconductor structure.

[0124] In some embodiments, the dimension of the first bonding pad 328 in the direction parallel to the first substrate 302 is greater than or equal to the sum of the dimension of the second bonding pad 358 in the direction parallel to the second substrate 332 and the pitch between any two adjacent second bonding pads 358.

[0125] Here, compared with the first bonding pad, the second bonding pad has a smaller size and a larger number. The maximum effective contact area between each first bonding pad and a second bonding pad is the area of the second bonding pad. By defining that the size of the first bonding pad is larger than the size of the second bonding pad and the pitch between two adjacent second bonding pads, each first bonding pad can be bonded to at least one second bonding pad, ensuring that the contact area between the first bonding pad and the second bonding pad is the maximum effective contact area. This can increase the process window of the bonding alignment process and avoid an increase in contact resistance due to a decrease in the contact area between the first bonding pad and the second bonding pad.

[0126] In addition, the first dummy pad and the second dummy pad can form a metal bond. Although the bonding between the first dummy pad and the second dummy pad cannot transmit electrical signals, it can still improve the bonding effect at the bonding interface.

[0127] As Figure 3K shown, three first bonding pads 328 are arranged continuously, and two first dummy pads 330 are located at both ends. Among them, the sizes of the first bonding pad 328 and the first dummy pad 330 in the X direction are both d1, and the pitch between any two adjacent first pads (i.e., the first bonding pad 328 and the first dummy pad 330 or any two adjacent first bonding pads 328) is s1. Still as Figure 3K shown, the second bonding pads 358 and the second dummy pads 360 are arranged alternately. Among them, the size of the second bonding pad 358 in the X direction is d2, and the pitch between any two adjacent second pads (i.e., the second bonding pad 358 and the second dummy pad 360) is s2.

[0128] By defining d2 + s2 = 1 / 2 * (d1 + s1) = d1, that is, there is a second dummy pad 360 between any two adjacent second bonding pads 358, that is, the second bonding pads 358 and the second dummy pads 360 are arranged alternately. The total contact area between the first bonding pad 328 and the second bonding pad 358 is equal to the product of the number of the first bonding pads 328 and the area of the second bonding pad 358.

[0129] As Figure 3L shown, three first bonding pads 328 are arranged continuously, and two first dummy pads 330 are located at both ends. Among them, the sizes of the first bonding pad 328 and the first dummy pad 330 in the X direction are both d3, and the pitch between any two adjacent first pads (i.e., the first bonding pad 328 and the first dummy pad 330 or any two adjacent first bonding pads 328) is s3. Still as Figure 3LAs shown, two second dummy pads 360 are provided between any two adjacent second bonding pads 358. Among them, the size of the second bonding pad 358 in the X direction is d4, and the distance between any two adjacent second pads (i.e., the second bonding pad 358 and the second dummy pad 360 or any two adjacent second dummy pads 360) is s4.

[0130] By defining d4 + s4 = 1 / 3*(d3 + s3) = d3, that is, two second dummy pads 360 are provided between any two adjacent second bonding pads 358. The total contact area between the first bonding pad 328 and the second bonding pad 358 is equal to the product of the number of the first bonding pads 328 and the area of the second bonding pad 358.

[0131] Reference Figures 4A to 4G , Figures 4A to 4G FIG. is a schematic cross-sectional structure diagram of a semiconductor structure provided for other embodiments during the manufacturing process. The following will be combined with Figure 2 and Figures 4A to 4G to describe in detail the manufacturing process of another semiconductor structure.

[0132] In the embodiment of the present disclosure, in step S201, a first substrate 402 is provided.

[0133] In the embodiment of the present disclosure, in step S202, a first bonding layer 410 is formed on the first substrate 402; among them, the first bonding layer 410 includes a first dielectric layer 404 and a first bonding pad 426 provided in the first dielectric layer 404.

[0134] As Figure 4A shown, in some embodiments, step S202 includes: sequentially forming a first dielectric layer 404 and a first barrier layer 408 on the first substrate 402; among them, a first metal wire 406 is provided in the first dielectric layer 404, and the first dielectric layer 404 and the first barrier layer 408 together form a first bonding layer 410; a first mask layer 412 is formed on the first barrier layer 408. Among them, the first mask layer 412 has at least one opening, and the first mask layer 412 can be used to define the positions of the initial groove and the first groove.

[0135] Here, the processes for forming the first dielectric layer 404 and the first barrier layer 408 may include but are not limited to CVD, PVD, ALD, or any combination thereof.

[0136] In some embodiments, the materials of the first dielectric layer 404 and the first barrier layer 408 are different. Compared with the first dielectric layer 404, the first barrier layer 408 has a stronger ability to block the diffusion of metal materials during the heat treatment process. Here, the material of the first dielectric layer 404 may be, for example, silicon dioxide, and the material of the first barrier layer 408 may be, for example, silicon carbonitride.

[0137] As shown Figure 4B in FIG. 1, along the Z direction, the first barrier layer 408 and a part of the first dielectric layer 404 are sequentially etched using the first mask layer 412 to form an initial groove 414. Among them, the etched first barrier layer 408 can be used to define the position of the first groove.

[0138] Here, the process of forming the initial groove 414 may include but is not limited to wet etching, dry etching, or a combination thereof.

[0139] As shown Figure 4C in FIG. 2, the first mask layer 412 is removed; a dielectric material is filled in the initial groove 414 to form a first protective layer 416; the first protective layer 416 also covers the first barrier layer 408.

[0140] In some embodiments, the materials of the first dielectric layer 404 and the first protective layer 416 may be the same.

[0141] As shown Figure 4D in FIG. 3, a second mask layer 418 is formed on the first protective layer 416. The second mask layer 418 has at least one opening, and the second mask layer 418 can be used to define the position of the second groove.

[0142] Here, the materials of the first mask layer 412 and the second mask layer 418 may be the same, for example, photoresist.

[0143] As shown Figure 4E in FIG. 4, along the Z direction, the first protective layer 416 is etched using the etched first barrier layer 408 as a mask, and the first dielectric layer 404 is etched to form a first groove 420; the bottom of the first groove 420 exposes the first metal line 406; along the Z direction, the first protective layer 416, the first barrier layer 408, and the first dielectric layer 404 are sequentially etched to form a second groove 422, and at least a part of the second groove 422 communicates with the first groove 420. The second groove 422 communicating with the first groove 420 can form a first bonding pad after being filled with a conductive material, and the second groove 422 not communicating with the first groove 420 can form a first dummy pad after being filled with a conductive material.

[0144] In some embodiments, the dimension of the second groove 422 in the X direction is larger than the dimension of the first groove 420 in the X direction.

[0145] Figure 4EA plurality of second grooves 422 are shown, and the bottoms of some of the plurality of second grooves 422 expose the first dielectric layer 404. After filling conductive material into these some second grooves 422 subsequently, a first dummy pad is formed; some of the plurality of second grooves 422 communicate with the first groove 420 to expose the first metal line 406. After filling conductive material into these some second grooves 422 subsequently, a first bonding pad is formed.

[0146] As Figure 4F shown, the second mask layer 418 is removed.

[0147] As Figure 4G shown, conductive material is filled into the first groove 420 and the second grooves 422 to form a first conductive material layer; the first conductive material layer and the first protective layer 416 are planarized to form a first conductive pillar 424 in the first groove 420, a first bonding pad 426 in the second grooves 422, and expose the first barrier layer 408; wherein, the materials of the first barrier layer 408 and the first dielectric layer 404 are different.

[0148] Here, the first bonding layer 410 includes the first dielectric layer 404 and the first barrier layer 408 which are stacked, and the first bonding layer 410 is provided with a first bonding pad 426 and a first dummy pad 428.

[0149] In the embodiment of the present disclosure, step S204 includes: sequentially forming a second dielectric layer and a second barrier layer on a second substrate; sequentially etching the second barrier layer and a part of the second dielectric layer to form an initial groove; filling a dielectric material into the initial groove to form a second protective layer; the second protective layer also covers the second barrier layer; etching the second protective layer and using the etched second barrier layer as a mask to etch the second dielectric layer to form a third groove; sequentially etching the second protective layer, the second barrier layer, and the second dielectric layer to form a fourth groove; at least part of the fourth groove communicates with the third groove; filling conductive material into the third groove and the fourth groove to form a second conductive material layer; planarizing the second conductive material layer and the second protective layer to form a second conductive pillar in the third groove, a second bonding pad in the fourth groove, and expose the second barrier layer; wherein, the materials of the second barrier layer and the second dielectric layer are different.

[0150] Figures 3A to 3E and Figures 4A to 4G The difference from the semiconductor structure shown is that: Figures 3A to 3E In the semiconductor structure shown, the first bonding layer 320 includes a first adhesion layer 314, a first dielectric layer 316, and a first barrier layer 318 which are sequentially stacked, and both the first bonding pad 328 and the first dummy pad 330 penetrate through the first barrier layer 318, the first dielectric layer 316, and the first adhesion layer 314 in sequence.Figures 4A to 4G In the illustrated semiconductor structure, the first bonding layer 410 includes a first dielectric layer 404 and a first barrier layer 408. The first bonding pad 426 and the first dummy pad 428 both penetrate through the first barrier layer 408 and extend into the first dielectric layer 404.

[0151] As Figure 3K and Figure 3L shown, an embodiment of the present disclosure provides a semiconductor structure 300, which includes:

[0152] A first substrate 302, a first bonding layer 320 disposed on the first substrate 302, and the first bonding layer 320 includes a first dielectric layer 316 and a first bonding pad 328 disposed in the first dielectric layer 316;

[0153] A second substrate 332, a second bonding layer 350 disposed on the second substrate 332, and the second bonding layer 350 includes a second dielectric layer 346 and a second bonding pad 358 disposed in the second dielectric layer 346; wherein, the dimension of the second bonding pad 358 in the direction parallel to the second substrate 332 is smaller than the dimension of the first bonding pad 328 in the direction parallel to the first substrate 302; the number of the second bonding pads 358 is greater than the number of the first bonding pads 328;

[0154] The first bonding layer 320 and the second bonding layer 350 are bonded, and each first bonding pad 328 is bonded to at least one second bonding pad 358.

[0155] In some embodiments, the dimension of the first bonding pad 328 in the direction parallel to the first substrate 302 is greater than or equal to the sum of the dimension of the second bonding pad 358 in the direction parallel to the second substrate 332 and the pitch between any two adjacent second bonding pads 358.

[0156] In some embodiments, the total contact area between the first bonding pad 328 and the second bonding pad 358 is greater than or equal to the product of the number of the first bonding pads 328 and the orthographic projection area of the second bonding pad 358 on the second substrate 332.

[0157] As Figure 4G shown, in some embodiments, the first bonding layer 410 further includes a first barrier layer 408, and the first dielectric layer 404 is located between the first substrate 402 and the first barrier layer 408; wherein, the materials of the first barrier layer 408 and the first dielectric layer 404 are different; and / or,

[0158] The second bonding layer further includes a second barrier layer, and the second dielectric layer is located between the second substrate and the second barrier layer; wherein, the materials of the second barrier layer and the second dielectric layer are different.

[0159] In some embodiments, the first bonding layer 320 further includes a first adhesion layer 314, the first adhesion layer 314 is located between the first substrate 302 and the first dielectric layer 316, and the first bonding pad 328 sequentially penetrates through the first barrier layer 318, the first dielectric layer 316, and the first adhesion layer 314; wherein, the materials of the first adhesion layer 314 and the first dielectric layer 316 are different; and / or,

[0160] The second bonding layer 350 further includes a second adhesion layer 344, the second adhesion layer 344 is located between the second substrate 332 and the second dielectric layer 346, and the second bonding pad 358 sequentially penetrates through the second barrier layer 348, the second dielectric layer 346, and the second adhesion layer 344; wherein, the materials of the second adhesion layer 344 and the second dielectric layer 346 are different.

[0161] In some embodiments, the semiconductor structure 300 further includes:

[0162] A first dummy pad 330 disposed in the first dielectric layer 316, wherein each first bonding pad 328 is connected to the first metal wire 306 through a first conductive pillar 312 for transmitting electrical signals; the first dummy pad 330 is not connected to the first metal wire 306;

[0163] A second dummy pad 360 disposed in the second dielectric layer 346, wherein each second bonding pad 358 is connected to the second metal wire 336 through a second conductive pillar 342 for transmitting electrical signals; at least part of the second dummy pads 360 are not connected to the second metal wire 336;

[0164] The first dummy pad 330 and the second dummy pad 360 are bonded.

[0165] In some embodiments, the spacing between any two adjacent first bonding pads 328, the spacing between any two adjacent first dummy pads 330, and the spacing between any adjacent first bonding pad 328 and first dummy pad 330 are all the same; and / or,

[0166] The spacing between any two adjacent second bonding pads 358, the spacing between any two adjacent second dummy pads 360, and the spacing between any adjacent second bonding pad 358 and second dummy pad 360 are all the same.

[0167] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. In the embodiments of the present disclosure, since the size of the second bonding pad is smaller than the size of the first bonding pad, and the number of the second bonding pads is greater than the number of the first bonding pads, after the first bonding layer and the second bonding layer are bonded, each first bonding pad is bonded to at least one second bonding pad. In this way, even if there is an alignment offset during the bonding process, the contact area between the first bonding pad and the second bonding pad will not be reduced, resulting in an increase in the contact resistance. Therefore, it is beneficial to increase the process window of the bonding alignment process.

[0168] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0169] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A first substrate, a first bonding layer disposed on the first substrate, the first bonding layer including a first dielectric layer and a first bonding pad disposed in the first dielectric layer; A second substrate, a second bonding layer disposed on the second substrate, the second bonding layer including a second dielectric layer and a second bonding pad disposed in the second dielectric layer; wherein, a dimension of the second bonding pad in a direction parallel to the second substrate is smaller than a dimension of the first bonding pad in a direction parallel to the first substrate; a number of the second bonding pads is greater than a number of the first bonding pads; The first bonding layer and the second bonding layer are bonded, and each of the first bonding pads is bonded to at least one of the second bonding pads.

2. The semiconductor structure according to claim 1, characterized in that, The dimension of the first bonding pad in a direction parallel to the first substrate is greater than or equal to a sum of a dimension of the second bonding pad in a direction parallel to the second substrate and a pitch between any two adjacent second bonding pads.

3. The semiconductor structure according to claim 1, characterized in that, A total contact area between the first bonding pad and the second bonding pad is greater than or equal to a product of a number of the first bonding pads and a projected area of the second bonding pad on the second substrate.

4. The semiconductor structure according to claim 1, characterized in that, The first bonding layer further includes a first barrier layer, and the first dielectric layer is located between the first substrate and the first barrier layer; wherein, materials of the first barrier layer and the first dielectric layer are different; and / or, The second bonding layer further includes a second barrier layer, and the second dielectric layer is located between the second substrate and the second barrier layer; wherein, materials of the second barrier layer and the second dielectric layer are different.

5. The semiconductor structure according to claim 4, characterized in that, The first bonding layer further includes a first adhesion layer, the first adhesion layer is located between the first substrate and the first dielectric layer, and the first bonding pad sequentially penetrates through the first barrier layer, the first dielectric layer, and the first adhesion layer; wherein, materials of the first adhesion layer and the first dielectric layer are different; and / or, The second bonding layer further includes a second adhesion layer, the second adhesion layer is located between the second substrate and the second dielectric layer, and the second bonding pad sequentially penetrates through the second barrier layer, the second dielectric layer, and the second adhesion layer; wherein, materials of the second adhesion layer and the second dielectric layer are different.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: A first dummy pad disposed in the first dielectric layer, wherein each of the first bonding pads is connected to a first metal wire through a first conductive pillar for transmitting an electrical signal; the first dummy pad is not connected to the first metal wire; A second dummy pad disposed in the second dielectric layer, wherein each of the second bonding pads is connected to a second metal wire through a second conductive pillar for transmitting an electrical signal; at least some of the second dummy pads are not connected to the second metal wire; The first dummy pad and the second dummy pad are bonded.

7. The semiconductor structure according to claim 6, characterized in that, A pitch between any two adjacent first bonding pads, a pitch between any two adjacent first dummy pads, and a pitch between any adjacent first bonding pad and first dummy pad are all the same; and / or, The pitch between any two adjacent second bonding pads, between any two adjacent second dummy pads, and between any adjacent second bonding pad and second dummy pad is the same.

8. A method for manufacturing a semiconductor structure, characterized in that, The method includes: providing a first substrate; forming a first bonding layer on the first substrate; wherein, the first bonding layer includes a first dielectric layer and first bonding pads disposed in the first dielectric layer; providing a second substrate; forming a second bonding layer on the second substrate; wherein, the second bonding layer includes a second dielectric layer and second bonding pads disposed in the second dielectric layer; wherein, the dimension of the second bonding pad in the direction parallel to the second substrate is smaller than the dimension of the first bonding pad in the direction parallel to the first substrate; the number of the second bonding pads is greater than the number of the first bonding pads; bonding the first bonding layer and the second bonding layer, and bonding each first bonding pad and at least one second bonding pad.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The forming of the first bonding layer on the first substrate includes: successively forming a first dielectric layer and a first barrier layer on the first substrate; successively etching the first barrier layer and a part of the first dielectric layer to form an initial groove; filling a dielectric material in the initial groove to form a first protective layer; the first protective layer also covers the first barrier layer; etching the first protective layer and using the etched first barrier layer as a mask to etch the first dielectric layer to form a first groove; successively etching the first protective layer, the first barrier layer, and the first dielectric layer to form a second groove; at least a part of the second groove communicates with the first groove; filling a conductive material in the first groove and the second groove to form a first conductive material layer; performing a planarization process on the first conductive material layer and the first protective layer to form a first conductive pillar in the first groove and a first bonding pad in the second groove and expose the first barrier layer; wherein, the materials of the first barrier layer and the first dielectric layer are different.

10. The manufacturing method of the semiconductor structure according to claim 8, characterized in that, The forming of the first bonding layer on the first substrate includes: forming a first adhesion layer, a first dielectric layer, a first barrier layer, and a first protective layer on the first substrate; successively etching the first protective layer, the first barrier layer, the first dielectric layer, and the first adhesion layer to form a second groove; filling a conductive material in the second groove to form a first conductive material layer; performing a planarization process on the first conductive material layer and the first protective layer to form a first bonding pad in the second groove and expose the first barrier layer; wherein, the materials of the first adhesion layer and the first dielectric layer are different.

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