Semiconductor device and manufacturing method thereof
By designing semiconductor devices containing chip carriers, the problem of the lack of protective layers in the chip embedding process in the prior art is solved, and higher power density, energy efficiency and reliability are achieved.
Patent Information
- Application Number
- CN202411856377.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-19
- Filing Date
- 2024-12-17
- Publication Date
- 2025-06-20
AI Technical Summary
In the prior art, semiconductor devices used to embed printed circuit boards lack a protective layer during chip embedding, resulting in complex manipulation and difficulty in meeting the improvement of power density, energy efficiency and reliability.
A semiconductor device including a chip carrier is designed, the chip carrier comprising a first cavity and a second cavity, the semiconductor die is mounted in the first cavity, the patterned top metallization layer includes an electrical contact pad, the insulating layer is arranged inside the second cavity, the electrical conductor is electrically coupled with the semiconductor die, and is encapsulated by an encapsulation material.
Through this design, the robustness and handling of semiconductor devices during chip embedding are improved, and the need for improved power density, energy efficiency and reliability is met.
Smart Images
Figure CN120184129A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices for embedding in a printed circuit board (PCB). Background Art
[0002] Modern power electronics technologies for inverter control, DC-DC converters, and battery management are one of the key technologies for electrified drives. The requirements for applications in terms of power density, energy efficiency, reliability, and system cost reduction are constantly increasing. One way to meet these requirements is to embed power semiconductors in power circuit boards. Instead of being soldered to the printed circuit board as discrete packaged components, power semiconductors are embedded in so-called system printed circuit boards (power and logic) using chip embedding technology. For chip embedding, semiconductor devices typically do not have any protective layer or encapsulation at the contact pads, and the chip carrier complicates the manipulation of the semiconductor device during chip embedding.
[0003] Therefore, there is a need for more robust power semiconductors for embedding chips in PCBs. Summary of the Invention
[0004] A semiconductor device including a chip carrier is disclosed. The chip carrier includes a first cavity and a second cavity. A semiconductor die is mounted in the first cavity, wherein the semiconductor die includes a patterned top metallization layer, and the patterned top metallization layer includes a first electrical contact pad. An insulating layer is disposed inside the second cavity. A first electrical conductor includes a first end and a second end, wherein the first end of the first electrical conductor is disposed above the insulating layer, and the second end of the first electrical conductor is electrically coupled to the first electrical contact pad of the semiconductor die. An encapsulation material encapsulates both ends of the first electrical conductor, a portion of the chip carrier, and the semiconductor die.
[0005] A semiconductor device including a chip carrier is disclosed. The chip carrier includes a first cavity. A semiconductor die is mounted inside the first cavity, wherein the semiconductor die includes a patterned top metallization layer, and the patterned top metallization layer includes a first electrical contact pad and a contact pad. A first electrical conductor, wherein the first end of the first electrical conductor is fixed to a floating contact portion of the semiconductor die, and the second end of the first electrical conductor is electrically coupled to the first electrical contact pad of the semiconductor die. An encapsulation material encapsulates both ends of the first electrical conductor and the semiconductor die, and wherein the first electrical conductor is partially exposed from the top surface of the encapsulation material.
[0006] A method for manufacturing a semiconductor device is disclosed, the method comprising:
[0007] - providing a chip carrier,
[0008] - forming a first cavity and a second cavity on a surface of the chip carrier;
[0009] - Mount the semiconductor die in the first cavity, wherein the semiconductor die includes a patterned top metallization layer, and the patterned top metallization layer includes a first electrical contact pad;
[0010] - Dispose an insulating layer inside the second cavity;
[0011] - Mount a first electrical conductor including a first end and a second end, wherein the first end of the first electrical conductor is mounted on the insulating layer, and the second end of the first electrical conductor is mounted on the first electrical contact pad of the semiconductor die;
[0012] - Encapsulate both ends of the first electrical conductor and the semiconductor die with an encapsulating material.
[0013] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the drawings. Description of the Drawings
[0014] The present disclosure is illustrated in the drawings by way of example and not limitation, wherein like or identical reference numerals refer to like or identical elements. The elements in the drawings are not necessarily drawn to scale relative to each other. The features of the various illustrated examples may be combined unless they are mutually exclusive.
[0015] Figure 1 A top view of a semiconductor device having a chip carrier is shown, and the chip carrier provides separate cavities for a semiconductor die and contact pads.
[0016] Figure 2 A cross-sectional view of the semiconductor device taken along line AA’ is shown. Figure 1 of line AA’
[0017] Figure 3 A top view of an alternative example of a semiconductor device is shown, and the semiconductor device has multiple electrical conductors over one of the cavities.
[0018] Figure 4 An example of another semiconductor device is shown, and the semiconductor device has two cavities for mounting electrical conductors.
[0019] Figure 5 An example of a top view of another semiconductor device is shown, and the semiconductor device has additional cavities on the chip carrier.
[0020] Figure 6 An example of a top view of another semiconductor device is shown, and the semiconductor device has contact pads on the semiconductor die.
[0021] Figure 7A - Figure 7F A method of forming a semiconductor device with exposed electrical conductors is shown. Detailed implementation manners
[0022] The semiconductor device described herein includes a chip carrier having a surface and a cavity formed on the surface of the chip carrier. A semiconductor die is mounted inside one of the cavities, and contact pads are formed inside the other cavity. The contact pads are electrically isolated from the chip carrier. The semiconductor die and the contact pads are electrically coupled via an electrical conductor. In particular, one end of the electrical conductor is electrically coupled to the semiconductor die, and the other end of the electrical conductor is fixed on the contact pad. A portion of the chip carrier, both ends of the electrical conductor, and the semiconductor die are encapsulated by an encapsulating material. The electrical conductor is exposed from the encapsulating material in a direction perpendicular to the surface of the chip carrier, and the exposed section of the electrical conductor serves as an external contact portion of the semiconductor device.
[0023] In Figure 1 and Figure 2 a top view and a cross-sectional view of an exemplary semiconductor device 100 are shown, respectively. Figure 2 The cross-sectional view of the semiconductor device 100 in Figure 1 shows a cross-section along the line AA'. The semiconductor device 100 has a chip carrier 102 and a semiconductor die 104. The chip carrier 102 can be a single piece, i.e., including a continuous metal piece, such as a lead frame made of a metal (e.g., copper, copper alloy, or an iron-nickel alloy such as Alloy 42). At least two cavities 106, 108 are formed on the surface 110 of the chip carrier 102, for example, by stamping, embossing, or any other suitable technique. The bottom of the cavity 106 forms a die pad 112. The semiconductor die 104 is mounted inside the cavity 106 and on the die pad 112, wherein the lower side 114 (e.g., the back side) of the semiconductor die 104 faces the die pad 112. A conductive joint 116 is arranged between the lower side 114 of the semiconductor die 104 and the die pad 112, and the conductive joint 116 electrically couples and mechanically couples the semiconductor die 104 to the chip carrier 102.
[0024] The semiconductor die 104 has a control pad 124 and load pads 126, 128 that are coupled to a control electrode and load electrodes of the semiconductor die 104, respectively. The load electrodes can be source and drain or emitter and collector. Each electrode (control electrode and load electrode) is formed via a respective stack of patterned metallization layers in the semiconductor die. The stack of patterned metallization layers can include a titanium layer disposed on the semiconductor material of the semiconductor die 104 and a NiV layer disposed on the titanium layer. The outermost patterned metallization layer of the respective stack of patterned metallization layers forms the respective electrical contact pads 124, 126, 128. The control pad 124 and load pad 128 can be formed on the upper side 120 (e.g., front side) of the semiconductor die 104 opposite the lower side 114, while the load pad 126 can be formed on the lower side 114 of the semiconductor die 104. In Figure 1 and Figure 2 shown, the load pads 126, 128 are shown on opposite sides 114, 120 of the semiconductor die 104 because the load pads 126, 128 are typically implemented for vertical semiconductor devices.
[0025] However, in some examples, both load pads 126, 128 can be formed on the upper side 120 of the semiconductor die 104, and the semiconductor die 104 experiences current flow in a direction transverse to the upper side 120 or lower side 114 of the semiconductor die 104, i.e., the semiconductor die 104 can be a planar semiconductor die.
[0026] The semiconductor die 104 includes sidewalls 132 that connect the upper side 120 and lower side 114 of the semiconductor die 104. The semiconductor die 104 is disposed inside a cavity 106 such that there is a gap between the sidewalls 134 of the cavity 106 and the sidewalls 132 of the semiconductor die 104, thereby electrically isolating the upper side 120 of the semiconductor die 104 from the chip carrier 102.
[0027] The semiconductor device 100 has electrical conductors 136, 138, 140, which are implemented as connection rings in the Figure 1 and Figure 2 illustrated example. Specifically, both ends of the electrical conductor 138 are electrically coupled to the surface 110 of the chip carrier 102 and are thus electrically coupled to the load pad 126 of the semiconductor die 104, while both ends of the electrical conductor 140 are electrically coupled to the load pad 128 of the semiconductor die 104. Any suitable number of electrical conductors 138, 140 can be present in the semiconductor device 100. The electrical conductors 138, 140 can also be connection straps or small clips.
[0028] Considering thermal performance, the control pad 124 is typically kept as small as possible to provide more space for the load pad 128. Thus, the control pad 124 is too small to form a closed connection loop on the control pad 124. To overcome this problem, one end of the electrical conductor 136 is disposed above the cavity 108, and the other end of the electrical conductor 136 is electrically coupled to the control pad 124 of the semiconductor die 104. In particular, one end of the electrical conductor 136 is electrically coupled to the contact pad 142 inside the cavity 108, where the contact pad 142 is electrically isolated from the chip carrier 102.
[0029] The contact pad 142 has an insulating layer 144 and a conductive structure 146. The insulating layer 144 is disposed between the substrate 146b of the conductive structure 146 and the bottom 108b of the cavity 108. The insulating layer 144 completely covers the substrate 146b of the conductive structure 146 and a part of the bottom 108b of the cavity 108 facing the substrate 146b of the conductive structure 146. In some examples, the insulating layer may completely cover the bottom 108b of the cavity 108 and partially cover the sidewall 108s of the cavity 108. The insulating layer 144 may include a laminate, or ceramic, or any suitable electrical insulating material. The substrate 146b of the conductive structure 146 is fixed in the middle of the top surface 144t of the insulating layer 144 such that the sidewall 108s of the cavity 108 is electrically isolated from the conductive structure 146. The top surface 144t of the insulating layer faces away from the bottom 108b of the cavity 108. The middle of the top surface 144t of the insulating layer 144 is defined as the section of the insulating layer 144 away from the side edges of the insulating layer 144. In particular, one end of the electrical conductor 136 is fixed to the top 146t of the conductive structure 146 opposite to the substrate 146b. The conductive structure 146 may be a metal block or a metal foil.
[0030] The ends of the electrical conductors 136, 138, 140 are electrically coupled to or fixed in their respective positions by, for example, ball bonding technology or wedge bonding or soldering or sintering or welding.
[0031] The encapsulation material 150 encapsulates the semiconductor die 104, both ends of the conductors 136, 138, 140, and at least a portion of the chip carrier 102. The encapsulation material 150 also fills the gap between the sidewall 132 of the semiconductor die 104 and the sidewall 134 of the cavity 106. Similarly, the encapsulation material 150 may fill at least a portion of the gap between the sidewall 108s of the cavity 108 and the conductive structure 146. The intermediate sections 136t, 138t, 140t of the conductors 136, 138, 140 protrude from the upper surface 204 of the encapsulation material 150 and can thus be contacted (explained later) after the semiconductor die 104 is embedded in, for example, a PCB. The intermediate sections 136t, 138t, 140t of the conductors 136, 138, 140 are located between the ends of the respective conductors 136, 138, 140, and the upper surface 204 of the encapsulation material 150 faces the surface 110 of the chip carrier 102. The cavity 108 may be partially exposed from the encapsulation material 150. In particular, the top 146t of the conductive structure 146 is partially exposed, and the exposed portion of the conductive structure 146 can be used to test the semiconductor die 104.
[0032] As described above, the semiconductor device 100 can be embedded in a PCB, where vias or holes are drilled above the intermediate sections 136t, 138t, 140t of the conductors 136, 138, 140, and a metallization layer is arranged on the surface of the PCB. By extending the metallization layer into the holes or vias of the PCB, the metallization layer is electrically coupled to the respective intermediate sections 136t, 138t, 140t of the conductors 136, 138, 140.
[0033] The semiconductor device 100 can be embedded in a PCB that includes a plurality of insulating layers alternating with metal layers for current rerouting. The insulating layer covering the surface of the semiconductor device includes vias or holes drilled above the intermediate sections 136t, 138t, 140t of the conductors 136, 138, 140 and is filled with a conductive material to contact the semiconductor device and integrate the device into the desired application circuit.
[0034] The encapsulation material 150 does not have filler particles and can thus have a thickness t in the range of 70 μm to 100 μm, where the thickness t of the encapsulation material 150 is measured between the first control pad 124 of the semiconductor die 104 and the upper surface 204 of the encapsulation material 150 along a direction perpendicular to the control pad 124 of the semiconductor die 104. The encapsulation material 150 may include any suitable dielectric material, particularly a molding material with high-temperature stability and / or good dielectric properties. The thickness t of the encapsulation material 150 being in the above range results in a smaller coverage area of the semiconductor device 100.
[0035] In some examples, the encapsulation material 150 may also completely encapsulate the surface 110 of the chip carrier 102 that includes the cavities 106, 108 and other surfaces of the chip carrier 102.
[0036] In some examples, the contact pad 142 may be formed of a stack of an upper metal layer, a dielectric, and a lower metal layer (e.g., a direct copper bond chip carrier or an active metal brazed chip carrier (not shown)). The dielectric is sandwiched between the upper metal layer and the lower metal layer in the stack, thus electrically isolating the upper layer and the lower layer from each other. The lower metal layer is fixed inside the cavity 108. This can be done during processing and thus simultaneously with mounting the semiconductor die 104 inside the cavity 106. The first end of the electrical conductor 136 is fixed to the upper metal layer of the stack, e.g., connected to the upper metal layer of the stack.
[0037] In some examples, the cavity 108 may also be filled with a potting material and the first end of the electrical conductor 136 is fixed inside the potting material. The potting material may include, for example but not limited to, epoxy resin, resin, etc.
[0038] Now referring Figure 3 , a top view of an exemplary semiconductor device 300 with and without the encapsulation material 150 is shown. The semiconductor device 300 may include Figure 1 - Figure 2 some or all of the features of the semiconductor device 100 of
[0039] Figure 4 and will only be discussed with respect to the differences. The semiconductor device 300 has a plurality of electrical conductors 302 mounted above the cavity 108. The plurality of electrical conductors 302 may be arranged in an array. Both ends of each electrical conductor in the plurality of electrical conductors 302 are fixed on the top 146t of the conductive structure 146 and encapsulated by the encapsulation material 150. Similar to the electrical conductors 136, 138, 140, the intermediate section of each electrical conductor in the plurality of electrical conductors 302 protrudes from the encapsulation material 150. Since one end of the electrical conductor 136 and both ends of each electrical conductor in the plurality of electrical conductors 302 are fixed to the conductive structure 146, the control pad 124 of the semiconductor die 104 can be accessed through the intermediate sections of the plurality of electrical conductors 302. In other words, compared with the single electrical conductor 136, the intermediate sections of the plurality of electrical conductors 302 increase the electrical contact area for electrically coupling the control pad 124. Figure 3some or all of the features of semiconductor device 300 and will discuss only the differences. Semiconductor device 400 is characterized in that semiconductor device 400 has an additional cavity 402 on surface 110 of chip carrier 102. Similar to cavity 108, cavity 402 has an insulating layer 444 and a conductive structure 446 disposed inside cavity 402. In this example, one end of each of a plurality of conductors 404 is fixed on top 446t of conductive structure 446, while the other end of each of the plurality of conductors 404 is fixed on top 146t of conductive structure 146.
[0040] Figure 5 A top view of an exemplary semiconductor device 500 is shown, which may include Figure 1 some or all of the features of semiconductor device 100 and will discuss only the differences. Chip carrier 102 has another cavity 502 on surface 110 of chip carrier 102, similar to cavity 108, and the other cavity 502 has an insulating layer 544 and a conductive structure 546. Conductor 140 further extends between load pad 128 of semiconductor die 104 and cavity 502. In particular, one end of conductor 140 is fixed on load pad 128 of semiconductor die 104, while the other end of conductor 140 is fixed to top 546t of conductive structure 546. Both ends of conductor 140 are encapsulated by encapsulant 150, while conductive structure 546 may be partially exposed from encapsulant 150. In particular, top 546t of conductive structure 546 may be partially exposed, and the exposed portion of top 546t of conductive structure 546 may be used to test semiconductor die 104. There may be any number of suitable conductors 140.
[0041] Figure 6 A semiconductor device 600 is shown, which may include Figure 1 some or all of the features of semiconductor device 100 and will discuss only the differences. Chip carrier 602 has only one cavity 106 on surface 610 of chip carrier 602, and semiconductor die 604 is mounted inside cavity 106. In addition to control pad 124 and load pads 126, 128, semiconductor die 604 further includes a contact pad 642 located on upper side 120 of semiconductor die 604, which is electrically isolated from control pad 124 and load pads 126, 128. One end of conductor 636 is fixed on floating contact pad 642 of semiconductor die 604, and the other end of conductor 636 is fixed on control pad 124 of semiconductor die 604. The top section of conductor 636 is exposed from encapsulant 150 and is used to electrically couple control pad 124 of semiconductor die 604 when embedded in a laminated application structure (e.g., a PCB).
[0042] Figure 7A - Figure 7F illustrates different steps of a method 700 for manufacturing a semiconductor device, the method 700 having the following steps:
[0043] - Providing a chip carrier 702 having a surface 710,
[0044] - Forming a first cavity 706 and a second cavity 708 on the surface 710 of the chip carrier 702 by stamping, imprinting or any other suitable technique,
[0045] - Mounting a semiconductor die 704 in the first cavity 706, wherein the semiconductor die 704 includes a patterned top metallization layer, and the patterned top metallization layer includes a first electrical contact pad 724,
[0046] - Disposing an insulating layer 744 inside the second cavity 708 and mounting a conductive structure 746 inside the second cavity 708 and on the insulating layer 744, wherein the conductive structure 746 is electrically isolated from the chip carrier 702,
[0047] - Mounting a first electrical conductor 736 including a first end and a second end, wherein the first end of the first electrical conductor 736 is mounted on the top 746t of the conductive structure 746, and the second end of the first electrical conductor 736 is mounted on the first electrical contact pad 724 of the semiconductor die 704,
[0048] - Encapsulating both ends of the first electrical conductor 736, a part of the chip carrier 702, and the semiconductor die 704 with an encapsulation material 712, and an intermediate section 736t of the first electrical conductor 736 is exposed from an upper surface 714 of the encapsulation material opposite to the surface 710 of the chip carrier 702.
[0049] The semiconductor die can be configured, for example, as a power MISFET (Metal Insulator Semiconductor Field Effect Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Gate Field Effect Transistor), a HEMT (High Electron Mobility Transistor), a power bipolar transistor, or a power diode such as a PIN diode or a Schottky diode.
[0050] The semiconductor die can be made of specific semiconductor materials such as Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc. In addition, the semiconductor die can contain inorganic and / or organic materials that are not semiconductors. The semiconductor die can have different types and can be manufactured by different techniques.
[0051] The encapsulation material can include any filler-free plastic or non-conductive material and can at least partially define the shape of the semiconductor device. The encapsulation material can be and can include or be a thermosetting material or a thermoplastic material or a polymer or a molding compound without filler particles. Various techniques such as compression molding, injection molding, powder molding, liquid molding, transfer molding, or film-assisted molding (FAM) can be used to form the encapsulation material.
[0052] The following examples relate to other aspects of the present disclosure:
[0053] Example 1 discloses a semiconductor device including:
[0054] - A chip carrier including a first cavity and a second cavity;
[0055] - A semiconductor die mounted in the first cavity, wherein the semiconductor die includes a patterned top metallization layer including a first electrical contact pad;
[0056] - An insulating layer disposed inside the second cavity;
[0057] - A first electrical conductor including a first end and a second end, wherein the first end of the first electrical conductor is disposed above the insulating layer and the second end of the first electrical conductor is electrically coupled to the first electrical contact pad of the semiconductor die;
[0058] - An encapsulation material encapsulating both ends of the first electrical conductor, a portion of the chip carrier, and the semiconductor die.
[0059] Example 2 discloses the semiconductor device according to Example 1, wherein an intermediate section of the first electrical conductor between the first end and the second end protrudes from the encapsulation material.
[0060] Example 3 discloses the semiconductor device according to Example 2, wherein the encapsulation material is a filler-free encapsulation material and has a thickness in the range of 70 μm - 100 μm, wherein the thickness of the encapsulation material is measured between the first electrical contact pad of the semiconductor die and the top surface of the encapsulation material along a direction perpendicular to the first electrical contact pad of the semiconductor die.
[0061] Example 4 discloses the semiconductor device according to Example 3, wherein a conductive structure is disposed inside the second cavity and on top of the insulating layer such that the conductive structure inside the second cavity is electrically isolated from the second cavity, and wherein the first end of the first electrical conductor is fixed to the conductive structure.
[0062] Example 5 discloses a semiconductor device according to Example 4, the semiconductor device further comprising a second electrical conductor including a first end and a second end, and wherein an intermediate section of the second electrical conductor located between the first end and the second end of the second electrical conductor protrudes from the encapsulating material, and wherein the first end of the second electrical conductor is fixed to the conductive structure.
[0063] Example 6 discloses a semiconductor device according to Example 5, wherein the second end of the second electrical conductor is fixed to the conductive structure, and wherein both ends of the second electrical conductor are encapsulated by the encapsulating material.
[0064] Example 7 discloses a semiconductor device according to Example 5, wherein the chip carrier further comprises a third cavity, wherein an insulating layer is disposed inside the third cavity, the conductive structure is fixed inside the third cavity and on top of the insulating layer, wherein the second end of the second electrical conductor is fixed to the conductive structure, and wherein both ends of the second electrical conductor are encapsulated by the encapsulating material.
[0065] Example 8 discloses a semiconductor device according to any one of the foregoing examples, the semiconductor device further comprising:
[0066] - an additional cavity and an additional electrical conductor, the additional cavity being located on the chip carrier, wherein the additional cavity includes an insulating layer disposed inside the additional cavity, the conductive structure is fixed inside the additional cavity and on top of the insulating layer, wherein the semiconductor die includes an additional patterned top metallization layer, the patterned top metallization layer including a second electrical contact pad,
[0067] - wherein a first end of the additional electrical conductor is electrically coupled to the second electrical contact pad of the semiconductor die, and a second end of the additional electrical conductor is fixed to the conductive structure,
[0068] - wherein both ends of the additional electrical conductor are encapsulated by the encapsulating material.
[0069] Example 9 discloses a semiconductor device, the semiconductor device comprising:
[0070] - a chip carrier including a first cavity;
[0071] - a semiconductor die mounted inside the first cavity, wherein the semiconductor die includes a patterned top metallization layer, the patterned top metallization layer including a first electrical contact pad and a contact pad;
[0072] - a first electrical conductor, wherein a first end of the first electrical conductor is fixed to a floating contact pad of the semiconductor die, and a second end of the first electrical conductor is electrically coupled to the first electrical contact pad of the semiconductor die;
[0073] - An encapsulation material that encapsulates both ends of a first electrical conductor and a semiconductor die, and wherein the first electrical conductor is partially exposed from the top surface of the encapsulation material.
[0074] Example 10 discloses a method for manufacturing a semiconductor device, the method comprising:
[0075] - Providing a chip carrier,
[0076] - Forming a first cavity and a second cavity on the surface of the chip carrier;
[0077] - Mounting a semiconductor die in the first cavity, wherein the semiconductor die includes a patterned top metallization layer, and the patterned top metallization layer includes a first electrical contact pad;
[0078] - Disposing an insulating layer inside the second cavity;
[0079] - Mounting a first electrical conductor including a first end and a second end, wherein the first end of the first electrical conductor is mounted above the insulating layer, and the second end of the first electrical conductor is mounted on the first electrical contact pad of the semiconductor die;
[0080] - Encapsulating both ends of the first electrical conductor and the semiconductor die with an encapsulation material.
[0081] Example 11 discloses the method according to Example 10, wherein mounting the first end of the first electrical conductor above the insulating layer includes mounting the first end of the first electrical conductor on a conductive structure inside the second cavity, wherein the conductive structure is electrically isolated from the second cavity.
[0082] Example 12 discloses the method according to Example 10, wherein a film-assisted molding is used to partially expose the first electrical conductor from the top surface of the encapsulation material.
[0083] Example 13 discloses the method according to Example 11, wherein the encapsulation includes compression molding or transfer molding on the semiconductor chip in a molding cavity, wherein the molding cavity is configured such that the first electrical conductor is partially exposed from the encapsulation material.
[0084] Although specific examples have been shown and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be used in place of the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.
[0085] It should be noted that the specification and the drawings only illustrate the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements, although these arrangements are not explicitly described or illustrated herein, but they embody the principles of the present invention and are included within the spirit and scope of the present invention. In addition, all examples and embodiments outlined herein are mainly explicitly for explanatory purposes only, to assist the reader in understanding the principles of the proposed method and system. Further, all statements providing the principles, aspects and embodiments of the present invention and their specific examples are intended to cover their equivalents.
Claims
1. A semiconductor device (100, 300, 400, 500), comprising: - a chip carrier (102) comprising a first cavity (106) and a second cavity (108); - a semiconductor die (104) mounted in the first cavity (106), the semiconductor die (104) comprising a patterned top metallization layer, the patterned top metallization layer comprising a first electrical contact pad (124); - an insulating layer (144) arranged inside the second cavity (108); a first electrical conductor (136) comprising a first end and a second end, wherein the first end of the first electrical conductor (136) is disposed above the insulating layer (144) and the second end of the first electrical conductor (136) is electrically coupled to a first electrical contact pad (124) of the semiconductor die (104); - an encapsulation material (150) encapsulating both ends of the first electrical conductor (136), a portion of the chip carrier (102), and the semiconductor die (104).
2. The semiconductor device (300, 400, 500) according to claim 1, wherein: A middle section (136t) of the first electrical conductor (136) between the first end and the second end protrudes from the encapsulation material (150).
3. The semiconductor device (300, 400, 500) according to claim 2, wherein: The encapsulation material (150) is a filler-free encapsulation material and has a thickness in the range of 70 μm-100 μm, the thickness of the encapsulation material (150) being measured between the first electrical contact pad (124) of the semiconductor die (104) and the top surface (204) of the encapsulation material (150) along a direction vertical to the first electrical contact pad (124) of the semiconductor die (104).
4. The semiconductor device (100, 300, 400, 500) according to claim 3, wherein: The conductive structure (146) is arranged inside the second cavity (108) and is located on top of the insulating layer (144), so that the conductive structure (146) inside the second cavity (108) is electrically isolated from the second cavity (108), and the first end of the first electrical conductor (136) is fixed on the conductive structure (146).
5. The semiconductor device (300, 400) of claim 4, further comprising a second electrical conductor (302, 404), the second electrical conductor (302, 404) comprising a first end and a second end, wherein: An intermediate section (302t, 404t) of the second electrical conductor (302, 404) between a first end and a second end of the second electrical conductor (302, 404) protrudes from the encapsulation material (150), and the first end of the second electrical conductor (302, 404) is fixed to the conductive structure (146).
6. The semiconductor device (300) according to claim 5, wherein: The second end of the second electrical conductor (302) is fixed on the conductive structure (146), and both ends of the second electrical conductor (302) are encapsulated by an encapsulation material (150).
7. The semiconductor device (400) according to claim 5, wherein: The chip carrier (102) also includes a third cavity (402), an insulating layer (444) is arranged inside the third cavity (402), a conductive structure (446) is fixed inside the third cavity (402) and located on top of the insulating layer (444), a second end of the second electrical conductor (404) is fixed on the conductive structure (446), and both ends of the second electrical conductor (404) are encapsulated by an encapsulation material (150).
8. The semiconductor device (500) according to any one of the preceding claims, further comprising: an additional cavity (502) and an additional electrical conductor (504), the additional cavity (502) being located on the chip carrier (102), the additional cavity (502) comprising an insulating layer (544) arranged inside the additional cavity (502), a conductive structure (546) being fixed inside the additional cavity (502) and on top of the insulating layer (544), the semiconductor die (104) comprising an additional patterned top metallization layer, the additional patterned top metallization layer comprising a second electrical contact pad (128), - wherein a first end of the additional electrical conductor (504) is electrically coupled to a second electrical contact pad (128) of the semiconductor die (104), and a second end of the additional electrical conductor (504) is fixed to the conductive structure (546), - wherein both ends of the additional electrical conductor (504) are encapsulated by the encapsulation material (150).
9. A semiconductor device (600), comprising: - a chip carrier (602) comprising a first cavity (106); - a semiconductor die (604) mounted inside the first cavity (106), the semiconductor die (604) comprising a patterned top metallization layer, the patterned top metallization layer comprising a first electrical contact pad (124) and a floating contact pad (642); a first electrical conductor (636), wherein a first end of the first electrical conductor (636) is fixed to a floating contact pad (642) of the semiconductor die (604), and a second end of the first electrical conductor (636) is electrically coupled to a first electrical contact pad (124) of the semiconductor die (604); - an encapsulation material (150) encapsulating both ends of the first electrical conductor (636) and the semiconductor die (604), the first electrical conductor (636) being partially exposed from a top surface of the encapsulation material (150).
10. A method (700) for manufacturing a semiconductor device, the method (700) comprising: - providing a chip carrier (702), - forming a first cavity (706) and a second cavity (708) on a surface (710) of the chip carrier (702); - mounting a semiconductor die (704) in the first cavity (706), the semiconductor die (704) comprising a patterned top metallization layer, the patterned top metallization layer comprising a first electrical contact pad (724); - arranging an insulating layer (744) inside the second cavity (708); - mounting a first electrical conductor (736) comprising a first end and a second end, wherein the first end of the first electrical conductor (736) is mounted on the insulating layer (744) and the second end of the first electrical conductor (736) is mounted on the first electrical contact pad (724) of the semiconductor die (704); - encapsulating both ends of the first electrical conductor (736) and the semiconductor die (704) with an encapsulation material (712).
11. The method (700) of claim 10, wherein: Mounting the first end of the first electrical conductor (736) over the insulating layer (744) includes mounting the first end of the first electrical conductor (736) on a conductive structure (746) within the second cavity (708), the conductive structure (746) being electrically isolated from the second cavity (708).
12. The method (700) of claim 10, wherein: Film assisted molding is used to partially expose the first electrical conductor (736) from the top surface of the encapsulation material (712).
13. The method (700) of claim 11, wherein: Encapsulation includes compression molding or transfer molding on the semiconductor die (704) in a molding cavity configured such that the first electrical conductor (736) is partially exposed from the encapsulation material (712).