Semiconductor structure, preparation method and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method and electronic equipment. The semiconductor structure comprises a substrate, a first connection structure and a second connection structure, the first connection structure comprises a first conduction part located between a first active region and a second active region, and a first connection part located on the top surfaces of the first active region and the second active region; the second connection structure comprises a second conduction part located between the first active region and the second active region, and a second connection part located on the top surfaces of the first active region and the second active region. By adjusting the contact area between the first connecting part and the first active region and the contact area between the second connecting part and the second active region, the contact resistance between the connecting structure and the first active region and the contact resistance between the connecting structure and the second active region can be reduced, and the parasitic capacitance can be further reduced by adjusting the sizes of the first conduction part and the second conduction part; therefore, the parasitic capacitance of the semiconductor device can be reduced while the contact resistance is reduced, and the electrical property and the reliability of the semiconductor device are further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure, a preparation method, and an electronic device. Background Art

[0002] In the manufacturing process of integrated circuits, as the size of basic semiconductor devices continues to shrink, the impact of resistance-capacitance delay on device performance becomes increasingly significant. For example, resistance-capacitance delay can cause problems such as signal transmission delay, reduced device operating speed, affected timing performance, increased power consumption, and affected signal integrity, thereby leading to a decline in the reliability and electrical properties of semiconductor devices. Summary of the Invention

[0003] The objective of this application is to provide a semiconductor structure, a preparation method, and an electronic device, which solve problems such as signal transmission delay, reduced device operating speed, affected timing performance, increased power consumption, and affected signal integrity caused by resistance-capacitance delay in the semiconductor structure, and improve the reliability and electrical properties of the semiconductor structure. To achieve the objective of this application, the following technical solutions are provided:

[0004] In a first aspect, this application provides a semiconductor structure, including:

[0005] A substrate, in which a first active region and a second active region are arranged at intervals along a first direction parallel to the top surface of the substrate;

[0006] A first connection structure, located on the top surface of the substrate, the first connection structure connecting the first active region and the second active region, the first connection structure including a first conduction part located between the first active region and the second active region, and a first connection part located on the top surfaces of the first active region and the second active region;

[0007] A second connection structure, located on the top surface of the substrate, the second connection structure connecting the first active region and the second active region, the second connection structure including a second conduction part located between the first active region and the second active region, and a second connection part located on the top surfaces of the first active region and the second active region;

[0008] Wherein, the first connection structure and the second connection structure are arranged at intervals along a second direction, and the first direction and the second direction are perpendicular.

[0009] The semiconductor structure of the present application connects the first active region and the second active region through the first connection structure, enabling signal conduction between the first active region and the second active region. Moreover, through the first connection portion and the second connection portion, signal extraction from the first active region and the second active region can be achieved. Additionally, by adjusting the contact areas between the first connection portion and the second connection portion and the first active region and the second active region, the contact resistance between the connection structure and the first active region and the second active region can be reduced. Consequently, the power consumption of the device can be decreased, the current transmission efficiency can be improved, the speed and frequency response can be enhanced, the thermal effect can be reduced, and the anti-interference ability can be strengthened, thereby improving the reliability of the device. Further, through the first conduction portion, the first connection portion on the top surface of the first active region and the first connection portion on the top surface of the second active region can be connected to conduct the signals extracted by the first connection portion and the second connection portion, thereby realizing the signal connection between the first active region and the second active region. And by adjusting the sizes of the first conduction portion and the second conduction portion, the parasitic capacitance can be reduced. Consequently, while reducing the contact resistance, the parasitic capacitance of the semiconductor device can be decreased, thereby improving the electrical properties and reliability of the semiconductor device.

[0010] In some embodiments, the semiconductor structure further includes:

[0011] A gate structure, which is located between the first connection structure and the second connection structure, spans across the first active region and the second active region, and is arranged at intervals with the first connection structure and the second connection structure in a first direction.

[0012] In some embodiments, the distance between the first conduction portion and the gate structure is greater than the distance between the first connection portion and the gate structure;

[0013] The distance between the second conduction portion and the gate structure is greater than the distance between the second connection portion and the gate structure.

[0014] In some embodiments, the size of the first conduction portion in the first direction is equal to or less than the distance between the first active region and the second active region;

[0015] The size of the second conduction portion in the first direction is equal to or less than the distance between the first active region and the second active region.

[0016] In some embodiments, the size of the first conduction portion in the second direction is less than the size of the first connection portion in the second direction;

[0017] The size of the second conduction portion in the second direction is less than the size of the second connection portion in the second direction.

[0018] In a second aspect, the present application also provides a method for manufacturing a semiconductor structure, including:

[0019] Providing a substrate, wherein the substrate includes a first active region and a second active region arranged at intervals in a first direction parallel to the top surface of the substrate;

[0020] Forming a first connection structure and a second connection structure on the top surface of the substrate, the first connection structure connecting the first active region and the second active region, and the second connection structure connecting the first active region and the second active region. Wherein, the first connection structure includes a first conduction part located between the first active region and the second active region, and a first connection part located on the top surfaces of the first active region and the second active region. The second connection structure includes a second conduction part located between the first active region and the second active region, and a second connection part located on the top surfaces of the first active region and the second active region. The first connection structure and the second connection structure are arranged at intervals in a second direction, and the first direction and the second direction are perpendicular.

[0021] In the method for manufacturing a semiconductor structure according to the embodiments of the present application, first, a substrate is provided, and then a first connection structure and a second connection structure are formed on the top surface of the substrate. The first active region and the second active region can be connected through the first connection structure, signal conduction between the first active region and the second active region can be achieved, and signal extraction from the first active region and the second active region can be realized through the first connection part and the second connection part. Moreover, by adjusting the contact areas between the first connection part and the second connection part and the first active region and the second active region, the contact resistance between the connection structure and the first active region and the second active region can be reduced, thereby reducing the power consumption of the device, improving the current transmission efficiency, enhancing the speed and frequency response, reducing the thermal effect, and enhancing the anti-interference ability, and further improving the reliability of the device. Further, through the first conduction part, the first connection part on the top surface of the first active region and the first connection part on the top surface of the second active region can be connected to conduct the signals extracted by the first connection part and the second connection part, thereby realizing the connection of signals between the first active region and the second active region. And by adjusting the sizes of the first conduction part and the second conduction part, the parasitic capacitance can be reduced, thereby ensuring that while reducing the contact resistance, the parasitic capacitance of the semiconductor device is reduced, and further improving the electrical properties and reliability of the semiconductor device.

[0022] In some embodiments, the forming of the first connection structure and the second connection structure on the top surface of the substrate includes:

[0023] Form a first connection via hole and a second connection via hole arranged at intervals in a second direction on the top surface of the substrate, where the first connection via hole connects the first active region and the second active region, and the second connection via hole connects the first active region and the second active region;

[0024] Etch the first connection via hole on the top surfaces of the first active region and the second active region to form a first connection trench, and etch the second connection via hole on the top surfaces of the first active region and the second active region to form a second connection trench;

[0025] Form a connection conductive layer in the first connection via hole, the second connection via hole, the first connection trench, and the second connection trench. The connection conductive layer in the first connection via hole and the first connection trench constitutes the first connection structure, and the connection conductive layer in the second connection via hole and the second connection trench constitutes the second connection structure.

[0026] In some embodiments, after providing the substrate and before forming the first connection structure and the second connection structure on the top surface of the substrate, it further includes:

[0027] Form a gate structure on the top surface of the substrate. The gate structure is located between the first connection structure and the second connection structure, straddles the first active region and the second active region, and is arranged at intervals in a first direction from the first connection structure and the second connection structure.

[0028] In some embodiments, the distance between the first conduction portion and the gate structure is greater than the distance between the first connection portion and the gate structure;

[0029] The distance between the second conduction portion and the gate structure is greater than the distance between the second connection portion and the gate structure.

[0030] In a third aspect, the present application further provides an electronic device, including:

[0031] The semiconductor structure described in the first aspect; or

[0032] Prepared by using the preparation method of the semiconductor structure described in any item of the second aspect.

[0033] The electronic device of the present application can achieve signal conduction between the first active region and the second active region through the first connection structure, and can export the signals of the first active region and the second active region through the first connection portion and the second connection portion. Moreover, by adjusting the contact areas between the first connection portion and the second connection portion and the first active region and the second active region, the contact resistance between the connection structure and the first active region and the second active region can be reduced. As a result, the power consumption of the device can be decreased, the current transmission efficiency can be improved, the speed and frequency response can be enhanced, the thermal effect can be reduced, and the anti-interference ability can be strengthened, thereby improving the reliability of the device. Further, through the first conduction portion, the first connection portion on the top surface of the first active region and the first connection portion on the top surface of the second active region can be connected to conduct the signals exported by the first connection portion and the second connection portion, thereby realizing the signal connection between the first active region and the second active region. And by adjusting the sizes of the first conduction portion and the second conduction portion, the parasitic capacitance can be reduced, thereby ensuring that while reducing the contact resistance, the parasitic capacitance of the semiconductor device is reduced, and further improving the electrical properties and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 is a top view structural schematic diagram of a semiconductor structure provided in an embodiment;

[0036] Figure 2 is a cross-sectional structural schematic diagram of a semiconductor structure provided in an embodiment;

[0037] Figure 3 is a flowchart of a preparation method of a semiconductor structure provided in an embodiment;

[0038] Figure 4 is a flowchart of steps S121 to S123 in a preparation method of a semiconductor structure provided in an embodiment;

[0039] Figure 5 is a cross-sectional structural schematic diagram of the structure obtained in step S121 in a preparation method of a semiconductor structure provided in an embodiment;

[0040] Figure 6 is a cross-sectional structural schematic diagram of the structure obtained in step S122 in a preparation method of a semiconductor structure provided in an embodiment.

[0041] Description of Reference Numerals

[0042] 10. Substrate; 101. First active region; 102. Second active region; 20. First connection structure; 201. First conduction part; 202. First connection part; 30. Second connection structure; 301. Second conduction part; 302. Second connection part; 40. Gate structure; 50. First connection via hole; 60. Second connection via hole; 70. First connection trench; 80. Second connection trench. Detailed Description of the Embodiment

[0043] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0045] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0046] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawings is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also have additional orientations (such as, for example, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0047] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. It is to be expected that variations in the shapes as illustrated may occur, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be construed as limited to the particular shapes of regions shown herein, but include shape deviations resulting, for example, from manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0049] In the process of manufacturing an integrated circuit, as the size of semiconductor basic devices continues to shrink, the impact of resistance-capacitance delay on device performance becomes increasingly significant. The wider the connecting wires, the smaller the distance between the wires and the gate, and the larger the parasitic capacitance between the gate and the source / drain. The smaller the connecting wires, the larger the contact resistance between the source and the drain. For example, resistance-capacitance delay can cause many problems such as signal transmission delay, reduction in the operating speed of the device, impact on timing performance, increase in power consumption, and impact on signal integrity, etc., thereby leading to a decline in the reliability and electrical properties of semiconductor devices.

[0050] An embodiment of the present application provides a semiconductor structure. Please refer to Figure 1 and Figure 2 . The semiconductor structure includes: a substrate, a first connection structure 20, and a second connection structure 30. The substrate includes a first active region 101 and a second active region 102 arranged at intervals in a first direction parallel to the top surface of the substrate; the first connection structure 20 is located on the top surface of the substrate, and the first connection structure 20 connects the first active region 101 and the second active region 102. The first connection structure 20 includes a first conduction part 201 located between the first active region 101 and the second active region 102, and a first connection part 202 located on the top surfaces of the first active region 101 and the second active region 102; the second connection structure 30 is located on the top surface of the substrate, and the second connection structure 30 connects the first active region 101 and the second active region 102. The second connection structure 30 includes a second conduction part 301 located between the first active region 101 and the second active region 102, and a second connection part 302 located on the top surfaces of the first active region 101 and the second active region 102; wherein, the first connection structure 20 and the second connection structure 30 are arranged at intervals in a second direction, and the first direction and the second direction are perpendicular.

[0051] Exemplarily, please refer to Figure 2 . Figure 2 is a schematic cross-sectional structure diagram of the semiconductor structure provided in the embodiment of the present application. The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. In this embodiment, the substrate 10 is a silicon substrate.

[0052] Exemplarily, the first direction is the OY direction as shown in Figure 1 , and the second direction is the OX direction as shown in Figure 1 .

[0053] Exemplarily, the doping type of the first active region 101 may include but is not limited to P-type or N-type; the doping type of the second active region 102 may include but is not limited to P-type or N-type.

[0054] Exemplarily, the materials of the first conduction part 201 and the second conduction part 301 may include but are not limited to metal materials, for example, copper metal. It should be noted that the materials of the first conduction part 201 and the second conduction part 301 may be the same or different. The first conduction part 201 and the second conduction part 301 can lead out the electrical signals of the first active region 101 and the second active region 102 to be respectively transmitted to the first connection part 202 and the second connection part 302.

[0055] Exemplarily, the materials of the first connection portion 202 and the second connection portion 302 may include but are not limited to metal materials, such as tungsten metal and cobalt metal. It should be noted that the materials of the first connection portion 202 and the second connection portion 302 may be the same or different. The first connection portion 202 and the second connection portion 302 can respectively transmit the electrical signals generated by the transistors to the first conduction portion 201 and the second conduction portion 301.

[0056] It should be noted that the greater the distance between the first conduction portion 201 and the gate structure 40, and between the second conduction portion 301 and the gate structure 40, the smaller the parasitic capacitance between the gate structure 40 and the conductive structure. The smaller the contact area between the first connection portion 202 and the first active region 101 and the second active region 102, and between the second connection portion 302 and the first active region 101 and the second active region 102, the greater the parasitic resistance of the device.

[0057] The semiconductor structure of the present application can connect the first active region 101 and the second active region 102 through the first connection structure 20, realize signal conduction between the first active region 101 and the second active region 102, and through the first connection portion 202 and the second connection portion 302, realize signal derivation of the first active region 101 and the second active region 102. And by adjusting the contact area between the first connection portion 202 and the second connection portion 302 and the first active region 101 and the second active region 102, the contact resistance between the connection structure and the first active region 101 and the second active region 102 can be reduced, thereby reducing the power consumption of the device, improving the current transmission efficiency, enhancing the speed and frequency response, reducing the thermal effect, and enhancing the anti-interference ability, and further improving the reliability of the device. Further, through the first conduction portion 201, the first connection portion 202 on the top surface of the first active region 101 and the first connection portion 202 on the top surface of the second active region 102 can be connected to conduct the signals derived from the first connection portion 202 and the second connection portion 302, thereby realizing signal connection between the first active region 101 and the second active region 102. And by adjusting the sizes of the first conduction portion 201 and the second conduction portion 301, the parasitic capacitance can be reduced, thereby ensuring that while reducing the contact resistance, the parasitic capacitance of the semiconductor device is reduced, and further improving the electrical properties and reliability of the semiconductor device.

[0058] In some embodiments, please refer to Figure 1 and Figure 2 , the semiconductor structure further includes: a gate structure 40, the gate structure 40 is located between the first connection structure 20 and the second connection structure 30, the gate structure 40 straddles the first active region 101 and the second active region 102, and is arranged at intervals with the first connection structure 20 and the second connection structure 30 in the first direction.

[0059] Exemplarily, the gate structure 40 may include a gate dielectric layer and a gate conductive layer. The gate dielectric layer may include, but is not limited to, a silicon oxide layer. The gate conductive layer may include, but is not limited to, a polysilicon layer. The gate structure 40 spans across the first active region 101 and the second active region 102, and can control the formation and switching state of a conductive channel through an electric field, as well as control the magnitude of the current in the first active region 101 and the second active region 102 through a gate voltage.

[0060] In the semiconductor structure provided by the embodiments of the present application, since the gate structure 40 spans across the first active region 101 and the second active region 102, it can control the formation and switching state of a conductive channel through an electric field, as well as control the magnitude of the current in the first active region 101 and the second active region 102 through a gate voltage. Moreover, through the gate structure 40, the formation and closing of the channel can be controlled through an electric field, enabling a high on-current to be achieved at an extremely low leakage current, thereby achieving an extremely high switching ratio and improving the electrical properties of the semiconductor device.

[0061] In some embodiments, referring to Figure 1 , the distance between the first conducting portion 201 and the gate structure 40 is greater than the distance between the first connecting portion 202 and the gate structure 40; the distance between the second conducting portion 301 and the gate structure 40 is greater than the distance between the second connecting portion 302 and the gate structure 40.

[0062] Exemplarily, the larger the distance d1 between the first conducting portion 201 and the gate structure 40, the smaller the parasitic capacitance (such as the coupling capacitance between the gate and the connecting structure), and thus the signal delay and power consumption can be reduced. The larger the distance d1 between the second conducting portion 301 and the gate structure 40, the smaller the parasitic capacitance, and thus the signal delay and power consumption can be reduced.

[0063] In the semiconductor structure provided in the embodiments of the present application, by setting the distance between the first conduction portion 201 and the gate structure 40 to be greater than the distance d2 between the first connection portion 202 and the gate structure 40, the contact area between the first connection portion 202 and the first active region 101 and the second active region 102 can be increased. Furthermore, while reducing the on-resistance between the first active region 101 and the second active region 102 and the connection structure, by increasing the distance between the first conduction portion 201 and the gate structure 40, the parasitic capacitance between the gate and the connection structure can be reduced. And by setting the distance between the second conduction portion 301 and the gate structure 40 to be greater than the distance d2 between the second connection portion 302 and the gate structure 40, the contact area between the second connection portion 302 and the first active region 101 and the second active region 102 can be increased. Furthermore, while reducing the on-resistance between the first active region 101 and the second active region 102 and the connection structure, by increasing the distance between the second conduction portion 301 and the gate structure 40, the parasitic capacitance between the gate and the connection structure can be reduced, improving the electrical properties and reliability of the semiconductor structure.

[0064] In some embodiments, referring to Figure 1 , the dimension of the first conduction portion 201 in the first direction is equal to or less than the distance between the first active region 101 and the second active region 102; the dimension of the second conduction portion 301 in the first direction is equal to or less than the distance between the first active region 101 and the second active region 102.

[0065] Exemplarily, when the dimension of the first conduction portion 201 in the first direction is equal to the distance between the first active region 101 and the second active region 102, it can ensure that the first conduction portion 201 always maintains a relatively large distance from the gate structure 40 in the first direction. Therefore, the parasitic capacitance between the gate structure 40 and the connection structure can be minimized to the greatest extent.

[0066] Exemplarily, when the dimension of the first conduction portion 201 in the first direction is less than the distance between the first active region 101 and the second active region 102, it can ensure that there is a sufficiently large contact area between the first connection portion 202 and the first active region 101 and the second active region 102. Furthermore, the contact resistance on the surfaces of the first active region 101 and the second active region 102 can be reduced.

[0067] Exemplarily, when the dimension of the second conduction portion 301 in the first direction is equal to the distance between the first active region 101 and the second active region 102, it can ensure that the second conduction portion 301 always maintains a relatively large distance from the gate structure 40 in the first direction. Therefore, the parasitic capacitance between the gate structure 40 and the connection structure can be minimized to the greatest extent.

[0068] Exemplarily, the size of the second conduction part 301 in the first direction is smaller than the distance between the first active region 101 and the second active region 102, which can ensure that there is a sufficiently large contact area between the second connection part 302 and the first active region 101 and the second active region 102, and thus the contact resistance on the surfaces of the first active region 101 and the second active region 102 can be reduced.

[0069] In the semiconductor structure provided in the embodiment of the present application, by setting the size of the first conduction part 201 in the first direction to be equal to the distance between the first active region 101 and the second active region 102, the parasitic capacitance between the gate structure 40 and the connection structure can be minimized to the greatest extent. By setting the size of the first conduction part 201 in the first direction to be smaller than the distance between the first active region 101 and the second active region 102, the contact resistance on the surfaces of the first active region 101 and the second active region 102 can be reduced. By setting the size of the second conduction part 301 in the first direction to be equal to the distance between the first active region 101 and the second active region 102, the parasitic capacitance between the gate structure 40 and the connection structure can be minimized to the greatest extent. By setting the size of the second conduction part 301 in the first direction to be smaller than the distance between the first active region 101 and the second active region 102, the contact resistance on the surfaces of the first active region 101 and the second active region 102 can be reduced. Therefore, in the semiconductor structure provided in the embodiment of the present application, the sizes of the first conduction part 201 and the second conduction part 301 in the first direction can be set according to the actual situation of the semiconductor device, so as to reduce the on-resistance of the device while reducing the parasitic capacitance of the device, and further improve the reliability and applicability of the semiconductor device.

[0070] In some embodiments, please refer to Figure 1 , the size of the first conduction part 201 in the second direction is smaller than the size of the first connection part 202 in the second direction; the size of the second conduction part 301 in the second direction is smaller than the size of the second connection part 302 in the second direction.

[0071] Exemplarily, the size of the first conduction part 201 in the second direction is smaller than the size of the first connection part 202 in the second direction, which can increase the distance between the first conduction part 201 and the gate structure 40, and ensure that the first connection part 202 has a sufficiently large contact area with the first active region 101 and the second active region 102. The size of the second conduction part 301 in the second direction is smaller than the size of the second connection part 302 in the second direction, which can increase the distance between the second conduction part 301 and the gate structure 40, and ensure that the second connection part 302 has a sufficiently large contact area with the first active region 101 and the second active region 102.

[0072] In the semiconductor structure provided in the embodiments of the present application, by setting the size of the first conduction part 201 in the second direction to be smaller than the size of the first connection part 202 in the second direction, the parasitic capacitance can be reduced by increasing the distance between the first conduction part 201 and the gate structure 40. At the same time, the parasitic resistance can be reduced by increasing the contact area between the first connection part 202 and the first active region 101 and the second active region 102, thereby improving the reliability and electrical properties of the semiconductor structure.

[0073] An embodiment of the present application provides a method for manufacturing a semiconductor structure. Please refer to Figure 3 , including:

[0074] S11: Provide a substrate, which includes a first active region and a second active region arranged at intervals in a first direction parallel to the top surface of the substrate.

[0075] Exemplarily, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium-silicon wafer. In this embodiment, the substrate 10 is a silicon substrate.

[0076] Exemplarily, the first direction is the OY direction as shown in Figure 1 , and the second direction is the OX direction as shown in Figure 1 .

[0077] Exemplarily, the first active region 101 and the second active region 102 may be formed by, but are not limited to, ion doping. The doping type of the first active region 101 may include but is not limited to P-type or N-type; the doping type of the second active region 102 may include but is not limited to P-type or N-type.

[0078] S12: Form a first connection structure and a second connection structure on the top surface of the substrate. The first connection structure connects the first active region and the second active region, and the second connection structure connects the first active region and the second active region. Among them, the first connection structure includes a first conduction part located between the first active region and the second active region, and a first connection part located on the top surfaces of the first active region and the second active region. The second connection structure includes a second conduction part located between the first active region and the second active region, and a second connection part located on the top surfaces of the first active region and the second active region. The first connection structure and the second connection structure are arranged at intervals in the second direction, and the first direction and the second direction are perpendicular.

[0079] Exemplarily, a connection structure can be formed by, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), or high-density plasma chemical vapor deposition (HDP-CVD). The materials of the first conduction part 201 and the second conduction part 301 can include, but not limited to, metal materials, such as copper metal. It should be noted that the materials of the first conduction part 201 and the second conduction part 301 can be the same or different. The first conduction part 201 and the second conduction part 301 can lead out the electrical signals of the first active region 101 and the second active region 102 and transfer them to the first connection part 202 and the second connection part 302 respectively.

[0080] Exemplarily, the materials of the first connection part 202 and the second connection part 302 can include, but not limited to, metal materials, such as tungsten metal and cobalt metal. It should be noted that the materials of the first connection part 202 and the second connection part 302 can be the same or different. The first connection part 202 and the second connection part 302 can transfer the electrical signals generated by the transistor to the first conduction part 201 and the second conduction part 301 respectively.

[0081] It should be noted that the greater the distance d1 between the first conduction part 201 and the gate structure 40 and the distance d1 between the second conduction part 301 and the gate structure 40, the smaller the parasitic capacitance between the gate structure 40 and the conductive structure. The smaller the contact areas between the first connection part 202 and the first active region 101 and the second active region 102, and between the second connection part 302 and the first active region 101 and the second active region 102, the greater the parasitic resistance of the device.

[0082] A method for manufacturing a semiconductor structure according to an embodiment of the present application first provides a substrate, and then forms a first connection structure and a second connection structure on the top surface of the substrate. The first active region and the second active region can be connected through the first connection structure, signal conduction between the first active region and the second active region can be achieved, and signal derivation between the first active region and the second active region can be realized through the first connection portion and the second connection portion. Moreover, by adjusting the contact areas between the first connection portion and the second connection portion and the first active region and the second active region, the contact resistance between the connection structure and the first active region and the second active region can be reduced, thereby reducing the power consumption of the device, improving the current transmission efficiency, enhancing the speed and frequency response, reducing the thermal effect, and enhancing the anti-interference ability, and further improving the reliability of the device. Further, through the first conduction portion, the first connection portion on the top surface of the first active region and the first connection portion on the top surface of the second active region can be connected to conduct the signals derived from the first connection portion and the second connection portion, thereby realizing the connection of signals between the first active region and the second active region. And by adjusting the sizes of the first conduction portion and the second conduction portion, the parasitic capacitance can be reduced, thereby ensuring that while reducing the contact resistance, the parasitic capacitance of the semiconductor device is reduced, and further improving the electrical properties and reliability of the semiconductor device.

[0083] In some embodiments, referring to Figure 4 , forming a first connection structure and a second connection structure on the top surface of the substrate includes:

[0084] S121: Form a first connection through-hole and a second connection through-hole arranged at intervals in a second direction on the top surface of the substrate. The first connection through-hole connects the first active region and the second active region, and the second connection through-hole connects the first active region and the second active region.

[0085] Exemplarily, referring to Figure 5 , a first connection through-hole 50 and a second connection through-hole 60 arranged at intervals in a second direction can be formed on the top surface of the substrate by using, but not limited to, wet etching or dry etching processes.

[0086] S122: Etch the first connection through-hole on the top surfaces of the first active region and the second active region to form a first connection trench, and etch the second connection through-hole on the top surfaces of the first active region and the second active region to form a second connection trench.

[0087] Exemplarily, referring to Figure 6 , the first connection through-hole 50 on the top surfaces of the first active region 101 and the second active region 102 can be etched by using, but not limited to, wet etching or dry etching processes to form a first connection trench 70. The second connection through-hole 60 on the top surfaces of the first active region 101 and the second active region 102 can be etched by using, but not limited to, wet etching or dry etching processes to form a second connection trench 80.

[0088] S123: Form a connecting conductive layer in the first connection through-hole, the second connection through-hole, the first connection trench, and the second connection trench. The connecting conductive layer in the first connection through-hole and the first connection trench constitutes a first connection structure, and the connecting conductive layer in the second connection through-hole and the second connection trench constitutes a second connection structure.

[0089] Exemplarily, the connecting conductive layer can be formed by, but not limited to, chemical vapor deposition process, atomic layer deposition process, and high-density plasma chemical vapor deposition process.

[0090] In the manufacturing method of the semiconductor structure provided in the embodiments of the present application, first, a first connection through-hole and a second connection through-hole arranged at intervals along the second direction are formed on the top surface of the substrate, which can connect the first active region and the second active region. Further etching the first connection through-hole and the second connection through-hole on the top surface of the first active region can form a first connection trench and a second connection trench, and the first connection trench and the second connection trench can expand the exposed top surface of the first active region. Finally, a connecting conductive layer is formed in the first connection through-hole, the second connection through-hole, the first connection trench, and the second connection trench. Therefore, there is a sufficient distance between the first conduction part formed in the first connection through-hole and the second conduction part formed in the second connection through-hole and the gate structure. The first connection part and the second connection part formed in the first connection trench and the second connection trench have a sufficient contact area with the first active region and the second active region. Furthermore, while reducing the on-resistance of the device, the parasitic resistance of the device can be reduced, and thus the electrical performance of the semiconductor device can be improved.

[0091] In some embodiments, please refer to Figure 1 , after providing the substrate and before forming the first connection structure and the second connection structure on the top surface of the substrate, it further includes: forming a gate structure 40 on the top surface of the substrate. The gate structure 40 is located between the first connection structure 20 and the second connection structure 30, the gate structure 40 straddles the first active region 101 and the second active region 102, and is arranged at intervals with the first connection structure 20 and the second connection structure 30 along the first direction.

[0092] It should be noted that the larger the distance between the first conduction part 201 and the gate structure 40, and between the second conduction part 301 and the gate structure 40, the smaller the parasitic capacitance between the gate structure 40 and the conductive structure. The smaller the contact area between the first connection part 202 and the first active region 101 and the second active region 102, and between the second connection part 302 and the first active region 101 and the second active region 102, the larger the parasitic resistance of the device.

[0093] Exemplarily, the gate structure 40 may include a gate dielectric layer and a gate conductive layer. The gate dielectric layer may include, but is not limited to, a silicon oxide layer. The gate conductive layer may include, but is not limited to, a polysilicon layer. The gate structure 40 straddles the first active region 101 and the second active region 102, and can control the formation and switching state of the conductive channel through an electric field, and control the current magnitude of the first active region 101 and the second active region 102 through the gate voltage.

[0094] In the manufacturing method of the semiconductor structure provided in the embodiments of the present application, since the gate structure 40 straddles the first active region 101 and the second active region 102, it can control the formation and switching state of the conductive channel through an electric field, and control the current magnitude of the first active region 101 and the second active region 102 through the gate voltage. Moreover, through the gate structure 40, it can control the formation and closing of the channel, and can achieve a high on-current at an extremely low leakage current, thereby achieving an extremely high switching ratio and improving the electrical properties of the semiconductor device.

[0095] In some embodiments, refer to Figure 1 , the distance between the first conduction part 201 and the gate structure 40 is greater than the distance between the first connection part 202 and the gate structure 40; the distance between the second conduction part 301 and the gate structure 40 is greater than the distance between the second connection part 302 and the gate structure 40.

[0096] Exemplarily, the greater the distance between the first conduction part 201 and the gate structure 40, the smaller the parasitic capacitance (such as the coupling capacitance between the gate and the connection structure), and thus the signal delay and power consumption can be reduced. The greater the distance between the second conduction part 301 and the gate structure 40, the smaller the parasitic capacitance (will be reduced, and thus the signal delay and power consumption can be reduced.

[0097] In the semiconductor structure provided in the embodiment of the present application, by setting the distance between the first conduction part 201 and the gate structure 40 to be greater than the distance between the first connection part 202 and the gate structure 40, the contact area between the first connection part 202 and the first active region 101 and the second active region 102 can be increased. Furthermore, while reducing the conduction resistance between the first active region 101 and the second active region 102 and the connection structure, by increasing the distance between the first conduction part 201 and the gate structure 40, the parasitic capacitance between the gate and the connection structure can be reduced. And by setting the distance between the second conduction part 301 and the gate structure 40 to be greater than the distance between the second connection part 302 and the gate structure 40, the contact area between the second connection part 302 and the first active region 101 and the second active region 102 can be increased. Furthermore, while reducing the conduction resistance between the first active region 101 and the second active region 102 and the connection structure, by increasing the distance between the second conduction part 301 and the gate structure 40, the parasitic capacitance between the gate and the connection structure can be reduced, improving the electrical properties and reliability of the semiconductor structure.

[0098] The embodiment of the present application provides an electronic device including the semiconductor structure in the above embodiment.

[0099] In the electronic device of the present application, the first active region and the second active region can be connected through the first connection structure to achieve signal conduction between the first active region and the second active region. And the signals of the first active region and the second active region can be led out through the first connection part and the second connection part. By adjusting the contact area between the first connection part and the second connection part and the first active region and the second active region, the contact resistance between the connection structure and the first active region and the second active region can be reduced. Furthermore, the power consumption of the device can be reduced, the current transmission efficiency can be improved, the speed and frequency response can be enhanced, the thermal effect can be reduced, and the anti-interference ability can be enhanced, thereby improving the reliability of the device. Further, the first connection parts on the top surfaces of the first active region and the second active region can be connected through the first conduction part to conduct the signals led out by the first connection part and the second connection part, thereby realizing the connection of the signals between the first active region and the second active region. And by adjusting the sizes of the first conduction part and the second conduction part, the parasitic capacitance can be reduced. Furthermore, while reducing the contact resistance, the parasitic capacitance of the semiconductor device can be reduced, thereby improving the electrical properties and reliability of the semiconductor device.

[0100] The embodiment of the present application provides an electronic device prepared by using the preparation method of the semiconductor structure in any of the above embodiments.

[0101] For the electronic device of the present application, a substrate is first provided, and then a first connection structure and a second connection structure are formed on the top surface of the substrate. The first active region and the second active region can be connected through the first connection structure, enabling signal conduction between the first active region and the second active region. Moreover, through the first connection portion and the second connection portion, signal extraction from the first active region and the second active region can be achieved. By adjusting the contact areas between the first connection portion and the second connection portion and the first active region and the second active region, the contact resistance between the connection structure and the first active region and the second active region can be reduced, thereby reducing the power consumption of the device, improving the current transmission efficiency, enhancing the speed and frequency response, reducing the thermal effect, and strengthening the anti-interference ability, and further improving the reliability of the device. Further, through the first conduction portion, the first connection portion on the top surface of the first active region and the first connection portion on the top surface of the second active region can be connected to conduct the signals extracted by the first connection portion and the second connection portion, thereby achieving signal connection between the first active region and the second active region. By adjusting the dimensions of the first conduction portion and the second conduction portion, the parasitic capacitance can be reduced, thereby ensuring that while reducing the contact resistance, the parasitic capacitance of the semiconductor device is reduced, and further improving the electrical performance and reliability of the semiconductor device.

[0102] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0103] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate includes a first active region and a second active region arranged at intervals along a first direction parallel to a top surface of the substrate; a first connection structure, located on the top surface of the substrate, the first connection structure connecting the first active area and the second active area, the first connection structure comprising a first conductive portion located between the first active area and the second active area, and a first connection portion located on the top surfaces of the first active area and the second active area; a second connection structure, located on the top surface of the substrate, the second connection structure connecting the first active area and the second active area, the second connection structure comprising a second conductive portion located between the first active area and the second active area, and a second connection portion located on the top surfaces of the first active area and the second active area; The first connection structure and the second connection structure are arranged at intervals along a second direction, and the first direction is perpendicular to the second direction.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A gate structure, wherein the gate structure is located between the first connection structure and the second connection structure, the gate structure spans the first active region and the second active region, and is arranged with the first connection structure and the second connection structure at intervals along a first direction.

3. The semiconductor structure according to claim 2, characterized in that: The distance between the first conductive portion and the gate structure is greater than the distance between the first connecting portion and the gate structure; A distance between the second conducting portion and the gate structure is greater than a distance between the second connecting portion and the gate structure.

4. The semiconductor structure according to claim 1, characterized in that: The size of the first conductive portion in the first direction is equal to or smaller than the distance between the first active area and the second active area; A size of the second conductive portion in the first direction is equal to or smaller than a distance between the first active region and the second active region.

5. The semiconductor structure according to claim 1, characterized in that: The size of the first conductive portion in the second direction is smaller than the size of the first connecting portion in the second direction; A size of the second conductive portion in the second direction is smaller than a size of the second connecting portion in the second direction.

6. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate includes a first active region and a second active region arranged at intervals along a first direction parallel to a top surface of the substrate; A first connection structure and a second connection structure are formed on the top surface of the substrate, the first connection structure connects the first active area and the second active area, and the second connection structure connects the first active area and the second active area, wherein the first connection structure includes a first conductive portion located between the first active area and the second active area, and a first connection portion located on the top surfaces of the first active area and the second active area, the second connection structure includes a second conductive portion located between the first active area and the second active area, and a second connection portion located on the top surfaces of the first active area and the second active area, the first connection structure and the second connection structure are arranged at intervals along a second direction, and the first direction is perpendicular to the second direction.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The forming of the first connection structure and the second connection structure on the top surface of the substrate includes: forming a first connecting through hole and a second connecting through hole arranged at intervals along a second direction on the top surface of the substrate, the first connecting through hole connecting the first active area and the second active area, and the second connecting through hole connecting the first active area and the second active area; Etching first connecting through holes on the top surfaces of the first active region and the second active region to form first connecting grooves, and etching second connecting through holes on the top surfaces of the first active region and the second active region to form second connecting grooves; A connecting conductive layer is formed in the first connecting through hole, the second connecting through hole, the first connecting groove and the second connecting groove. The connecting conductive layer in the first connecting through hole and the first connecting groove constitutes the first connecting structure. The connecting conductive layer in the second connecting through hole and the second connecting groove constitutes the second connecting structure.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that: After providing the substrate and before forming the first connection structure and the second connection structure on the top surface of the substrate, the method further includes: A gate structure is formed on the top surface of the substrate. The gate structure is located between the first connection structure and the second connection structure. The gate structure spans the first active area and the second active area and is spaced apart from the first connection structure and the second connection structure along a first direction.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The distance between the first conductive portion and the gate structure is greater than the distance between the first connecting portion and the gate structure; A distance between the second conducting portion and the gate structure is greater than a distance between the second connecting portion and the gate structure.

10. An electronic device, characterized in that: include: The semiconductor structure according to claims 1 to 5; or The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 6 to 9.

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