Device of monolithic integrated circuit

Abstract

Embodiments of the present disclosure may include an apparatus of monolithic integrated circuits that includes an addressable laser array, where the addressable laser array includes a plurality of N light emitting sources. Embodiments may also include a multiplexer including N transistors, where each transistor of the N transistors is associated with a different one of the N light emitting sources that are a plurality. According to various embodiments, each of the N transistors is operable to address an associated light emitting source.

Description

Technical Field

[0001] The present disclosure generally relates to a monolithic integrated circuit laser multiplexer. Background Art

[0002] Aspects of the present disclosure relate to a monolithic integrated circuit laser multiplexer. Conventional technical solutions for monolithic integrated circuit laser multiplexers may have various problems. In this regard, conventional systems and methods for monolithic integrated circuit laser multiplexers may be expensive, bulky, and / or inefficient.

[0003] By comparing conventional systems and methods with some aspects of the methods and systems of the present disclosure set forth in the remainder of the present disclosure in conjunction with the reference drawings, the limitations and disadvantages of such technical means will become apparent to those skilled in the art. Summary of the Invention

[0004] The monolithic integrated circuit laser multiplexer is shown in at least one of the drawings and / or described in conjunction with at least one of the drawings, and is more fully set forth in the claims.

[0005] These and other advantages, aspects, and novel features of the present disclosure, as well as details of the illustrated embodiments of the present disclosure, will be more fully understood from the following description and drawings. Brief Description of the Drawings

[0006] The various features and advantages of the present disclosure can be more readily understood from the following detailed description in conjunction with the accompanying drawings, in which like reference numerals denote like structural elements.

[0007] Figure 1 is a block diagram showing a monolithic integrated circuit laser multiplexer according to some embodiments of the present disclosure.

[0008] Figure 2 Shows an exemplary schematic diagram of a monolithic integrated circuit device 100 according to various embodiments of the present disclosure.

[0009] Figure 3 Shows another exemplary schematic diagram of a monolithic integrated circuit device 100 according to various embodiments of the present disclosure.

[0010] Figure 4 Shows an exemplary structure of a multiplexer 114 using pHEMT.

[0011] Figure 5 Shows an exemplary structure of a multiplexer 114 using HBT.

[0012] Figure 6 Shows an exemplary monolithic GaAs VCSEL-pHEMT structure.

[0013] Figure 7 shows an exemplary monolithic GaAs VCSEL-HBT structure.

[0014] Figure 8 is a block diagram further describing a monolithic integrated circuit device.

[0015] Figure 9 is a block diagram further describing a monolithic integrated circuit device.

[0016] Figure 10 is a block diagram further describing a monolithic integrated circuit device. Detailed implementation

[0017] The following discussion provides various examples of methods and systems for a monolithic integrated circuit laser multiplexer. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0018] The accompanying drawings show a general construction manner, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Additionally, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different drawings represent the same elements.

[0019] The term "and / or" means any one or more of the items in the list connected by "and / or". As an example, "x and / or y" represents any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" represents any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z".

[0020] The terms "comprise", "contain", "include" and / or "have" are "open" terms and specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features.

[0021] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of the present disclosure, the first element discussed in the present disclosure may be referred to as the second element.

[0022] Unless otherwise specified, the term "coupled" may be used to describe two elements in direct contact with each other or two elements indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" may be used to describe two elements in direct contact with each other or two elements indirectly connected by one or more other elements.

[0023] Embodiments of the present disclosure may include a monolithic integrated circuit device that includes an addressable laser array including N light sources that are plural. Embodiments may also include a multiplexer including N transistors, each of the N transistors being associated with a different one of the N light sources that are plural. According to various embodiments, each of the N transistors is operable to address an associated one of the light sources.

[0024] Embodiments may include that each of the N light sources that are plural may be an LED, an EEL, a VCSEL, or a PCSEL. According to various embodiments, the monolithic integrated circuit may include a substrate / waf er made of GaN, GaAs, InP, SiC, or GaSb. Embodiments may also include that each of the N transistors that are plural may be a MESFET, a pHEMT, a HFET, or an HBT operable for a 3-terminal analog function.

[0025] According to various embodiments, the monolithic integrated circuit may include plural epitaxial layers operable to form the light sources and the transistors. According to various embodiments, the epitaxial layers for forming the light sources may be isolated from the epitaxial layers for forming the transistors by one or more epitaxial layers of high-resistivity GaAs and / or InGaP.

[0026] According to various embodiments, an InGaP layer is operable to stop etching between one or more epitaxial layers associated with the plural light sources and one or more epitaxial layers associated with the plural transistors. According to various embodiments, the epitaxial layers for forming the light sources may be different from the epitaxial layers for forming the transistors. The etch stop layer may also be made of AlAs or AlGaAs. According to various embodiments, instead of an etch stop layer, a timed etch manufacturing process may be used. The timed etch manufacturing process may refer to controllably removing material from the surface of a semiconductor wafer using a chemical etchant for a specified duration so as to precisely etch away the material. The process may be controlled by a predetermined etch rate (i.e., the volume of material removed per unit time).

[0027] According to various embodiments, an epitaxial layer associated with a transistor may cover an epitaxial layer associated with a light source. Embodiments may also include an epitaxial structure for N light sources, where N is a plurality, and the epitaxial structure may include a smooth buffer layer, an N-type DBR layer, one or more active layers, and a P-type DBR layer.

[0028] According to various embodiments, the smooth buffer layer, the N-type DBR layer, one or more active layers, and the P-type DBR layer may each include a plurality of epitaxial layers. Embodiments may also include an epitaxial structure for N transistors, where N is a plurality, and the epitaxial structure may include one or more single-groove pHEMTs.

[0029] Embodiments may also include an epitaxial structure for N transistors, where N is a plurality, and the epitaxial structure may include one or more double-groove pHEMTs. Embodiments may also include a lower barrier layer. Embodiments may also include a lower δ-doped layer. Embodiments may also include a lower spacer layer. Embodiments may also include a channel layer. Embodiments may also include an upper spacer layer. Embodiments may also include an upper δ-doped layer. Embodiments may also include an upper barrier layer. Embodiments may also include a Schottky layer. Embodiments may also include a groove layer. Embodiments may also include an etch stop layer. Embodiments may also include a cap layer.

[0030] Embodiments may also include an epitaxial structure for N transistors, where N is a plurality, and the epitaxial structure may include an HBT. Embodiments may include a subset electrode layer, a collector layer, a base layer, an emitter layer, and / or an emitter cap layer. According to various embodiments, the transistor may be isolated from the light source by ion implantation and / or mesa etching.

[0031] Traditionally, lasers have typically been driven by an external drive circuit. This approach may not allow for optimal switching speeds. If a chip with individually addressable lasers or sub-arrays is desired, this approach may be expensive and have an inconvenient form factor. The present disclosure monolithically integrates an analog multiplexer function onto the laser chip such that it can be effectively driven by a circuit. According to various embodiments of the present disclosure, a triple-junction laser function may be monolithically integrated onto the chip and may be used in a laser array.

[0032] Figure 1It is a block diagram depicting a monolithic integrated circuit device 100 according to some embodiments of the present disclosure. In some embodiments, the monolithic integrated circuit device 100 may include an addressable laser array 110. The addressable laser array 110 may include N light-emitting sources 112 that are plural in number and a multiplexer 114. The multiplexer 114 may also include N transistors 116, and each of the N transistors 116 is associated with a different one of the N light-emitting sources 112 that are plural in number. Each of the N transistors 116 is operable to address the associated one light-emitting source 112.

[0033] The monolithic integrated circuit device 100 can operate as an electronic circuit integrated onto a single semiconductor substrate and can operate as a component that houses additional elements on the semiconductor. The addressable laser array 110 is operable to selectively activate laser sources, e.g., the light-emitting sources 112. Each light-emitting source 112 in the addressable laser array 110 can be individually controlled. The light-emitting sources 112 are operable to emit light, e.g., using laser light sources. The multiplexer 114 is operable to manage, address, and control the plural light-emitting sources 112. Each light-emitting source 112 may be associated with a transistor 116 that forms part of the multiplexer 114. The transistor 116 may allow for individual control of the light-emitting source 112.

[0034] Figure 2 An exemplary schematic diagram of the monolithic integrated circuit device 100 according to various embodiments of the present disclosure is shown. In addition to Figure 1 the elements shown, Figure 2 it further includes a control interface 120 and a driver 130. The control interface 120 may be coupled between the driver 130 and the multiplexer 114. The driver 130 is operable to supply power to the light-emitting sources 112. The control interface 120 is generally a bandwidth-limited and time-sensitive interface. Therefore, it may be desirable to reduce the number of control interfaces 120. According to various embodiments of the present disclosure, it is preferable to use a single control interface 120 and then use the multiplexer 114 to select the desired light-emitting source 112 instead of addressing each light-emitting source 112 individually with the control interface 120.

[0035] Figure 3 Another exemplary schematic diagram of the monolithic integrated circuit device 100 according to various embodiments of the present disclosure is shown.

[0036] In some embodiments, each of the N light-emitting sources 112 that are plural in number may be an LED, an EEL, a VCSEL, or a PCSEL.

[0037] An LED can be a light-emitting diode. An LED can be a semiconductor light source capable of emitting light when an electric current flows through it. This may occur due to a process called electroluminescence, in which the movement of electrons in a semiconductor material can release energy in the form of photons. LEDs can be efficient, durable, and have a long service life. LEDs can be widely used in various applications, such as displays or indicators. LEDs can have low power consumption and low heat generation.

[0038] An EEL can be an edge-emitting laser. An edge-emitting laser (EEL) can be a semiconductor laser in which light can be emitted from the edge of a semiconductor chip rather than from the surface. EELs are typically used in applications that require higher output power and longer coherence lengths. Since EELs are capable of producing highly collimated or parallel beams, EELs are typically used in telecommunications and high-speed data transmission.

[0039] A VCSEL can be a vertical-cavity surface-emitting laser. A VCSEL can be a semiconductor laser diode that emits light perpendicular to the wafer surface rather than from its edge. A distinguishing feature of a VCSEL can be its vertical-cavity structure, which can be formed by Bragg reflectors. VCSELs can offer low manufacturing costs, high efficiency, and the ability to be easily tested and configured into two-dimensional arrays. VCSELs can be commonly used in optical communications, sensing applications, and consumer electronic devices.

[0040] A PCSEL can be a photonic-crystal surface-emitting laser. A PCSEL can be a laser that utilizes the properties of a photonic crystal to control light emission. A photonic crystal can be an optical material with a periodic structure on the scale of the optical wavelength. This can allow a PCSEL to produce highly directional and coherent beams. The structure of a PCSEL enables better control of the optical properties of the laser, which can make a PCSEL ideal for special applications such as high-density data storage and advanced optical communications.

[0041] In some embodiments, the monolithic integrated circuit may further include a substrate / wafers made of GaN, GaAs, InP, SiC, or GaSb.

[0042] GaN can refer to gallium nitride. Gallium nitride can be a binary III-V direct-bandgap semiconductor material that can have high electron mobility and thermal stability. As a substrate in a monolithic integrated circuit, GaN is particularly useful for high-frequency and high-power applications, such as radio-frequency components and power electronic devices. GaN's wide bandgap, high breakdown electric field, and thermal conductivity make it an ideal choice for devices that may need to operate under extreme conditions, such as high-temperature and high-pressure environments.

[0043] GaAs may refer to gallium arsenide. Gallium arsenide may be another III-V compound semiconductor with a direct bandgap, known for its higher electron mobility than silicon. For example, in the case of monolithic integrated circuits, GaAs may be used in applications that require high-frequency operation and low-noise amplification. This may include microwave and millimeter-wave technology applications. The high electron mobility of GaAs may allow for fast electronic components.

[0044] InP may refer to indium phosphide. Indium phosphide may be a binary semiconductor composed of indium and phosphorus, belonging to the III-V group of semiconductors. InP may have a direct bandgap and possess high electron mobility and a large intrinsic resistivity. InP substrates are often used in optoelectronic devices (e.g., high-speed photodetectors and lasers) as well as high-frequency integrated circuits. InP may offer advantages in terms of low noise and high-frequency capabilities.

[0045] SiC may refer to silicon carbide. Silicon carbide may be a wide-bandgap semiconductor material that is particularly hard, chemically inert, and thermally stable. In the field of monolithic integrated circuits, SiC may be highly valuable for high-power, high-temperature, and high-frequency applications. The wide bandgap and high thermal conductivity of SiC make it an ideal substrate material for power electronic devices, including high-voltage transistors and diodes, especially in environments where high temperatures or high frequencies prevail.

[0046] GaSb may refer to gallium antimonide. Gallium antimonide may be a III-V compound semiconductor with a bandgap narrower than that of GaAs or GaN. As a substrate material in monolithic integrated circuits, GaSb may be ideally used in infrared photodetectors and thermophotovoltaic devices. The bandgap of GaSb may make it advantageous for special applications in optoelectronics and devices operating in the mid-infrared wavelength range.

[0047] In some embodiments, each of the N transistors, which are multiple in number, may be a MESFET, pHEMT, HFET, or HBT capable of operating for a 3-terminal analog function.

[0048] MESFET may refer to a metal-semiconductor field-effect transistor. A MESFET may be a field-effect transistor that uses a metal-semiconductor junction (Schottky barrier) as the gate. This type of transistor is typically fabricated using compound semiconductors (e.g., GaAs or SiC) and is ideally suited for microwave and radio frequency (RF) applications. The high electron mobility and low parasitic capacitance of MESFETs make them particularly advantageous for high-frequency, high-power, and low-noise applications, such as radar systems and satellite communications.

[0049] pHEMT can refer to a pseudomorphic high electron mobility transistor. A pHEMT can be a special type of field effect transistor characterized by a higher concentration of charge carriers. This can allow for increased electron mobility and desirable performance. pHEMTs are mainly used in high-frequency and low-noise applications such as RF amplifiers because pHEMTs have desirable high-frequency characteristics.

[0050] HFET can refer to a heterostructure field effect transistor. An HFET can also be referred to as a HEMT (high electron mobility transistor), although an HFET can include different types of heterostructure transistors. An HFET can employ a heterostructure to create a channel with high electron mobility, making it suitable for high-frequency and high-power applications. For example, HFETs can be used in telecommunications, broadband amplifiers, and other applications that require high-speed operation.

[0051] HBT can refer to a heterojunction bipolar transistor. An HBT can be a bipolar transistor that can use different semiconductor materials for the emitter and base regions, creating a heterojunction. This can allow for improved performance, including higher speed and efficiency compared to traditional bipolar transistors. HBTs are commonly used in high-frequency applications such as RF and microwave circuits. HBTs can also be used in optoelectronics, where their high current density can be beneficial for laser drivers and photodetectors.

[0052] Figure 4 An exemplary structure of a multiplexer 114 using pHEMTs is shown. A plurality of pHEMTs 116 are shown, which can switch an "input" signal to one of four output signals labeled "output 1", "output 2", "output 3", and "output 4". According to various embodiments of the present disclosure, such a multiplexer 114 can be used in a monolithic integrated circuit 100 as Figure 2 shown. A reference switch 140 is also shown.

[0053] The reference switch 140 can be used to provide a consistent voltage or current level against which other inputs can be compared. This can ideally ensure correct switching operation and ensure that crosstalk or interference between channels can be minimized. In some cases, the reference switch 140 can be used as a safety or calibration point. For example, when no other switches are activated, the reference switch 140 can be engaged to ensure that no lasers are inadvertently activated. In other cases, the reference switch 140 can be used to monitor the multiplexer 114.

[0054] Figure 5An exemplary structure of the multiplexer 114 using HBTs is shown. A plurality of HBTs 116 are shown, which can switch an "input" signal to one of four output signals labeled "Output 1", "Output 2", "Output 3", and "Output 4". According to various embodiments of the present disclosure, such a multiplexer 114 can be used in, for example, Figure 3 the monolithic integrated circuit 100 as shown.

[0055] In some embodiments, the monolithic integrated circuit may include a plurality of epitaxial layers that are operable to form the light source 112 and the transistors 116.

[0056] An epitaxial layer may refer to a layer of crystalline semiconductor material that can be grown on a crystalline semiconductor substrate. The ordered growth of the epitaxial layer aligned with the crystal structure of the substrate can ensure that the epitaxial layer inherits the same crystal structure as the underlying substrate.

[0057] Figure 6 An exemplary monolithic GaAs VCSEL-pHEMT structure is shown. A cross-section of a semiconductor layer including the pHEMT 116 and the VCSEL light source 112 is shown. For the VCSEL light source 112, the direction of the emitted light 290, the anode 280, the cathode 201, the smooth buffer layer 220, the N-type DBR (distributed Bragg reflector) layer 230, the active layer 250, and the P-type DBR layer 240 are also shown. For the pHEMT 116, the epitaxial layer 260, the source connector 272, the gate connector 270, and the drain connector 274 are shown.

[0058] The VCSEL light source 112 includes the N-type DBR layer 230 and the P-type DBR layer 240 that can act as mirrors, forming the top and bottom of the laser cavity. The active layer 250 is the location where light generation and amplification occur.

[0059] The pHEMT 116 can be formed from the epitaxial layer 260. The epitaxial layer 260 may include a channel that can be made of InGaAs. This layer may be strained, resulting in enhanced electron mobility. In addition, the epitaxial layer 260 may include a barrier layer, such as a layer of AlGaAs or AlGaInAs, that can form a heterojunction with the channel. In addition, the epitaxial layer 260 may include one or more layers made of, for example, doped GaAs.

[0060] In some embodiments, the epitaxial layer used to form the light source 112 can be isolated from the epitaxial layer used to form the transistors 116 by one or more epitaxial layers of high-resistivity GaAs (gallium arsenide) and / or InGaP (indium gallium phosphide). For example, in Figure 6 , one or more epitaxial layers 260 of high resistivity can be located near the P-type DBR layer 240. For example, inFigure 7 In this case, the high-resistivity InGaP layer can be adjacent to the P-type DBR layer 240. According to various embodiments, such as Figure 7 The etch stop layer of the HBT shown can be conductive or resistive. In some embodiments, the high-resistivity InGaP layer can also stop etching between one or more epitaxial layers of the transistor. The etch stop layer can also be made of AlAs or AlGaAs. According to various embodiments, a timed etch manufacturing process can be used instead of an etch stop layer.

[0061] Figure 7 An exemplary monolithic GaAs VCSEL-HBT structure is shown. A cross-section of a semiconductor layer including the HBT 116 and the VCSEL light-emitting source 112 is shown. For the VCSEL light-emitting source 112, the direction of emitted light 290, the anode 280, the cathode 201, the smoothing buffer layer 220, the N-type DBR (distributed Bragg reflector) layer 230, the active layer 250, and the P-type DBR layer 240 are also shown. For the HBT 116, the epitaxial layer 260, the collector connector 292, the base connector 296, and the emitter connector 294 are shown. In addition, the isolation layer 301, the emitter 302 (e.g., InGaP emitter), and the base 303 (e.g., GaAs base) are shown.

[0062] In some embodiments, the InGaP layer can operate to stop etching between one or more epitaxial layers associated with the plurality of light-emitting sources 112 and one or more epitaxial layers 260 associated with the plurality of transistors. The etch stop layer can also be made of AlAs or AlGaAs. According to various embodiments, a timed etch manufacturing process can be used instead of an etch stop layer.

[0063] In some embodiments, the epitaxial layers used to form the light-emitting source 112 can be different from the epitaxial layers used to form the transistor 116, as Figure 6 and Figure 7 shown. In some embodiments, the epitaxial layers associated with the transistor 116 can cover the epitaxial layers associated with the light-emitting source 112. In some embodiments, the transistor 116 can be isolated from the light-emitting source 112 by ion implantation and / or mesa etching. According to various embodiments of the present disclosure, the light-emitting source 112 can include a smoothing buffer layer 220, an N-type DBR layer 230, one or more active layers 250, and a P-type DBR layer 240.

[0064] Figure 8 is a further description according to some embodiments of the present disclosure from Figure 1 and Figure 6Block diagram of a monolithic integrated circuit device 100. In some embodiments, the epitaxial structure for a plurality of N transistors 116 may include one or more single-groove pHEMTs 312. One or more single-groove pHEMTs 312 may include a lower barrier layer 314, a lower δ-doped layer 316, a lower spacer layer 318, a channel layer 320, an upper spacer layer 322, an upper δ-doped layer 324, an upper barrier layer 326, a Schottky layer 328, an etch stop layer 330, and a cap layer 332.

[0065] The upper δ-doped layer 324 and the lower δ-doped layer 316 may be layers that include heavily doped dopants in a narrow region. The upper δ-doped layer 324 and the lower δ-doped layer 316 may be made of a suitable dopant material, such as silicon. According to various embodiments, the pHEMT 312 may be formed without the upper δ-doped layer 324.

[0066] The Schottky layer 328 may refer to a region near the interface of the Schottky barrier, which may form when a metal contacts a semiconductor, for example, between the metal gate and the underlying semiconductor material in a pHEMT.

[0067] The lower spacer layer 318 and the upper spacer layer 322 are operable to isolate electrons from their donor atoms in the lower δ-doped layer 316 and the upper δ-doped layer 324 in the electron gas channel. This can reduce scattering and improve electron mobility. The spacer layers can also help confine electrons in the quantum well, ensuring that the electrons remain in the high-mobility channel. For example, the lower spacer layer 318 and the upper spacer layer 322 may be made of AlGaAs or InAlAs.

[0068] In the case of the pHEMT 312, a single recess may refer to a manufacturing step in which a portion of the semiconductor layer above the two-dimensional electron gas channel may be etched away ("recessed") to define and optimize the gate region. This recess process may be performed to reduce the thickness of the barrier layer directly under the metal gate contact, which in turn affects the height of the Schottky barrier and may allow for better control of the threshold voltage and transconductance of the device.

[0069] Figure 9 is a further description according to some embodiments of the present disclosure from Figure 1 and Figure 6 Block diagram of a monolithic integrated circuit device 100. In some embodiments, the epitaxial structure for a plurality of N transistors 116 may include one or more double-groove pHEMTs 412. One or more double-recess pHEMTs 412 may include a lower barrier layer 414, a lower δ-doped layer 416, a lower spacer layer 418, a channel layer 420, an upper spacer layer 422, an upper δ-doped layer 424, an upper barrier layer 426, a Schottky layer 428, a groove layer 430, an etch stop layer 432, and a cap layer 434. These layers may be the same asFigure 8 are similar to those described in

[0070] In the case of the pHEMT 412, the dual-groove can be contrasted with Figure 8 the single-groove described, i.e., multiple different groove etching steps can be performed on different layers or regions of the device to achieve specific device characteristics.

[0071] By allowing for more precise control of the electron density in the channel, the groove process can enhance the overall performance of the pHEMT and thus improve the device's RF performance, power handling, and linearity. The groove layer 430 can refer to the layer affected by the recessing step, e.g., the gate groove or the channel groove.

[0072] Figure 10 is a further description according to some embodiments of the present disclosure of the monolithic integrated circuit device 100 from Figure 1 and Figure 7 The epitaxial structure of the transistor 116 can include an HBT 520. The HBT 520 can include a subset electrode layer 521, a collector layer 522, a base layer 523, an emitter layer 524, and one or more emitter capping layers 525.

[0073] The subset electrode layer 521 can include, for example, SI GaAs or InGaP. The collector layer 522 can include, for example, GaAs. The base layer 523 can include, for example, GaAs. The emitter layer 524 can include, for example, InGaP. The emitter capping layer 525 can include, for example, InGaAs.

[0074] In some embodiments, the transistor 116 is isolated from the light source 112 by ion implantation and / or mesa etching.

[0075] This disclosure includes references to specific examples; however, those skilled in the art will understand that various changes can be made and equivalent technical means can be substituted without departing from the scope of this disclosure. In addition, the disclosed examples can be modified without departing from the scope of this disclosure. Therefore, the intention is that this disclosure is not limited to the disclosed examples, but rather this disclosure will include all examples falling within the scope of the appended claims.

Claims

1. A device comprising a monolithic integrated circuit of an addressable laser array, the addressable laser array comprising: There are multiple N light sources; a multiplexer comprising N transistors, each of the N transistors being associated with a different one of the plurality of the N light sources; and Each of the N transistors is operable to address an associated light source.

2. The device according to claim 1, wherein: Each of the plurality of N light emitting sources is an LED, an EEL, a VCSEL or a PCSEL.

3. The device according to claim 1, wherein: The monolithic integrated circuit includes a substrate / wafer made of GaN, GaAs, InP, SiC or GaSb.

4. The device according to claim 1, wherein: Each of the plurality of N transistors is a MESFET, pHEMT, HFET or HBT capable of operating for a 3-terminal analog function.

5. The device according to claim 1, wherein: The monolithic integrated circuit includes a plurality of epitaxial layers operable to form the light emitting source and the transistor.

6. The device according to claim 5, wherein: The epitaxial layers used to form the light emitting sources are isolated from the epitaxial layers used to form the transistors by one or more epitaxial layers of high resistivity GaAs and / or InGaP.

7. The device according to claim 5, wherein: The epitaxial layer used to form the light emitting source is different from the epitaxial layer used to form the transistor.

8. The device according to claim 1, wherein: The epitaxial structure of the plurality of N light sources includes a smooth buffer layer, an N-type DBR layer, one or more active layers and a P-type DBR layer.

9. The device according to claim 8, wherein: The smoothing buffer layer, the N-type DBR layer, the one or more active layers, and the P-type DBR layer each include a plurality of epitaxial layers.

10. The device according to claim 1, wherein: The epitaxial structure of the plurality of N transistors includes one or more single-groove pHEMTs, and the one or more single-groove pHEMTs include a lower barrier layer, a lower δ-doped layer, a lower spacer layer, a channel layer, an upper spacer layer, an upper δ-doped layer, an upper barrier layer, a Schottky layer, an etch stop layer and a cap layer.

11. The device according to claim 1, wherein: The epitaxial structure of the plurality of N transistors includes one or more double-groove pHEMTs, and the one or more double-groove pHEMTs include a lower barrier layer, a lower δ-doped layer, a lower spacer layer, a channel layer, an upper spacer layer, an upper δ-doped layer, an upper barrier layer, a Schottky layer, a groove layer, an etch stop layer and a cap layer.

12. The device according to claim 1, wherein: The epitaxial structure of the plurality of N transistors includes a HBT, and the HBT includes a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer.

13. The device according to claim 6, wherein: The InGaP layer is operable to stop etching between one or more epitaxial layers associated with a plurality of said light emitting sources and one or more epitaxial layers associated with a plurality of said transistors.

14. The device according to claim 5, wherein: The epitaxial layer associated with the transistor overlies the epitaxial layer associated with the light emitting source.

15. The device according to claim 1, wherein: The transistor is isolated from the light emitting source by ionization and / or mesa etching.

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