Adaptive gate voltage adjustment

Abstract

The invention relates to adaptive gate voltage regulation. Systems and methods are described for a method of operating a switching converter. The controller may sense a load current associated with an output voltage of the power stage. The controller may define the gate voltage to one of a default voltage level and a modified voltage level based on the sensed load current. The gate voltage may be used to drive a power stage.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices. More specifically, the present disclosure relates to an adaptive gate voltage adjustment for a power converter. Background Art

[0002] A voltage regulator or a switching converter can convert an input voltage into an output voltage with a desired voltage level. A switching converter (e.g., a three-level buck converter) can include a controller, a pair of gate drivers, and a pair of switches including a high-side switch and a low-side switch. The controller can provide a control signal (e.g., a pulse-width modulation (PWM) or a pulse-frequency modulation (PFM) signal) to the pair of gate drivers. The gate drivers can alternately drive the high-side switch and the low-side switch according to the control signal. The alternating switches can convert the input voltage into the output voltage. Summary of the Invention

[0003] In one embodiment, a semiconductor device is generally described. The semiconductor device can include a circuit and a controller. The circuit can be configured to define a gate voltage for driving a power stage. The controller can be configured to sense a load current output by the power stage. The controller can also be configured to control the circuit based on the sensed load current to define the gate voltage as one of a default voltage level and a modified voltage level.

[0004] In one embodiment, a system is generally described. The system can include a power stage configured to convert an input voltage into an output voltage. The system can also include a driver circuit configured to output a gate voltage to drive the power stage. The system can also include a controller configured to sense a load current associated with the output voltage. The controller can also be configured to define the gate voltage as one of a default voltage level and a modified voltage level based on the sensed load current.

[0005] In one embodiment, a method for operating a switching converter is generally described. The method can include sensing a load current associated with an output voltage of a power stage. The method can also include defining the gate voltage as one of a default voltage level and a modified voltage level based on the sensed load current. The gate voltage can be used to drive the power stage. Brief Description of the Drawings

[0006] Figure 1 is a schematic diagram showing a system in which adaptive gate voltage adjustment can be implemented in one embodiment.

[0007] Figure 2 is a schematic diagram showing an example implementation of adaptive gate voltage adjustment in another embodiment.

[0008] Figure 3 It is a schematic diagram showing another exemplary implementation of adaptive gate voltage adjustment in another embodiment.

[0009] Figure 4 It is a schematic diagram showing exemplary parameters of an implementation that can be used for adaptive gate voltage adjustment in one embodiment.

[0010] Figure 5 It is a flowchart illustrating the process of implementing adaptive gate voltage adjustment in one embodiment. Detailed implementation

[0011] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those of ordinary skill in the art will understand that the various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0012] Figure 1 It is a schematic diagram showing a system in which adaptive gate voltage adjustment can be implemented in one embodiment. Figure 1 The illustrated system 100 can be implemented by one or more semiconductor devices. The system 100 can at least include a controller 102, a driver integrated circuit (IC) 104, a high-side switch labeled HS, and a low-side switch labeled LS. The driver IC 104 can include a driver configured to drive HS and another driver configured to drive LS. The driver IC 104 can be configured to provide a gate voltage Vg to drive the switch HS and the switch LS. The switch HS can be configured to conduct when LS is off, and vice versa. When HS conducts and LS is off, the voltage at the switch node SW between HS and LS can be pulled up to Vin, such that the voltage at the switch node SW is equal to Vin. When HS is off and LS conducts, the voltage at the switch node SW can be pulled down to ground, so that VSW is equal to zero. In one embodiment, the HS switch and the LS switch can be field effect transistors (FETs) (such as metal oxide semiconductor field effect transistors (MOSFETs)). In other embodiments, the HS switch and the LS switch can be diodes or insulated gate bipolar transistors (IGBTs).

[0013] The controller 102 can be, for example, a processor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA), or any other circuit configured to control and operate the battery circuit 101. Although described as a CPU in the illustrative embodiments, the controller 102 is not limited to the CPU in these embodiments and can include any other circuit configured to control and operate the driver IC 104. The controller 102 can be configured to generate control signals (such as pulse width modulation (PWM) or pulse frequency modulation (PFM) signals) for controlling the driver IC 104 to selectively turn on and off the switch HS and the switch LS.

[0014] When performing a switching operation, the efficiency of the power stage including the HS switch and the LS switch can vary depending on multiple characteristics. This can include FET conduction losses and switching losses. The FET conduction loss is related to the gate voltage, so as the gate voltage increases, the drain-source on-state resistance (Rds(on)) decreases. However, as the gate voltage increases, the total gate charge (Qg) increases, which results in switching losses. Switching losses occur during the transition between the on-state and the off-state of the FET. During this transition, the FET is not fully on or fully off, causing periods of high current and high voltage simultaneously. This generates significant power consumption, which leads to the total switching loss. Additionally, the operating mode of most power converters is typically continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM, the inductor current remains non-zero throughout the switching cycle, ensuring continuous energy flow. On the other hand, in DCM, the inductor current drops to zero before the start of the next switching cycle, resulting in discontinuous energy flow.

[0015] For a more detailed description below, the controller 102 can be configured to change the voltage level of the gate voltage Vg at a specified time to improve the efficiency of the system 100. In one embodiment, the controller 102 can include a circuit 103 that can change the gate voltage Vg depending on the load current A. The controller 102 can be configured to monitor the load current Iload received by the load with Vout and enable or disable the circuit 103 based on the load current Iload to change the gate voltage Vg. In one aspect, the relationship between the efficiency of the system 100 and the load current Iload can depend on the gate voltage Vg. By way of example, a lower gate voltage can cause higher efficiency at lower load currents, while a higher gate voltage can result in higher efficiency at higher load currents. The controller 102 can monitor the load current Iload and determine whether operating the switch HS and the switch LS with a higher gate voltage or a lower gate voltage will optimize the efficiency of the system 100.

[0016] Figure 2 FIG. is a schematic diagram showing an exemplary embodiment of adaptive gate voltage adjustment in another embodiment. Figure 2 For the description of Figure 1 the components shown. In Figure 2 the embodiment shown, circuit 103 may include circuit 202 and circuit 204. Driver IC 104 may include driver 208 and driver 210. Driver 208 may be configured to drive the HS switch, and driver 210 may be configured to drive the LS switch. Drivers 208 and 210 may be configured to receive control signal 206 to generate the gate voltage Vg for driving the HS switch and the LS switch. Control signal 206 may be, for example, a PWM or PFM signal generated by Figure 1 controller 102 shown.

[0017] Circuit 202 may be a low dropout (LDO) regulator configured to generate a regulated voltage level even when the input voltage Vsupp varies with the voltage level. In one embodiment, circuit 202 may include a combination of various electronic components that may be arranged into a circuit for generating the regulated voltage. In Figure 2 the embodiment shown, circuit 202 may be implemented by an LDO that may generate a voltage signal 201 having a default voltage level. The voltage signal 201 having the default voltage level may be provided by circuit 202 to circuit 204 (if circuit 204 is enabled, as Figure 2 shown) and other components of system 100. Circuit 204 may be connected to capacitor C and is configured to modify (e.g., increase or decrease) the voltage level of voltage signal 201. In one embodiment, circuit 204 may include a combination of various electronic components that may be arranged into a circuit for modifying the voltage level of voltage signal 201. In Figure 2 the exemplary embodiment shown, circuit 204 may be a voltage multiplier circuit (such as a capacitive charge pump), and the default voltage level of voltage signal 201 is 5 volts (V). When circuit 204 is a voltage multiplier, circuit 204 may increase (such as double) the default voltage level of voltage signal 201 from 5V to 10V. In another embodiment, the default voltage level may be, for example, 10V, and circuit 204 may be configured to reduce or halve the default voltage level of voltage signal 201 to a lower voltage (such as 5V).

[0018] Additionally, circuit 204 can be configured to receive an enable signal or logic input EN from controller 102. Depending on the value of the enable signal EN, circuit 204 can be enabled or disabled. When the enable signal EN indicates ON, circuit 204 can be enabled to modify the voltage signal 201 received from circuit 202. The modified voltage signal can be provided to drivers 208, 210 so that the gate voltage Vg can be set to the modified voltage signal and the modified voltage signal can be used to drive switches HS and LS. In one embodiment, controller 102 can include components configured to monitor the load current Iload and generate the enable signal EN based on the monitoring to enable or disable circuit 204. In Figure 2 the example embodiment shown, controller 102 can include comparator 220, which can receive a voltage derived from the load current Iload through resistor R and a reference voltage Vref. The reference voltage Vref can be a predefined voltage that defines the condition for activating circuit 204. In one embodiment, if the default voltage level is 5V, in response to the voltage derived from the load current Iload being greater than or equal to Vref, comparator 220 can output the enable signal EN to enable circuit 204 for modifying the voltage signal 201 (or doubling it from 5V to 10V).

[0019] Figure 3 is a schematic diagram showing another example implementation of adaptive gate voltage adjustment in another embodiment. Figure 3 The description can refer to Figures 1 to 2 the components shown. In Figure 3 the embodiment shown, the enable signal EN indicates OFF, which causes circuit 204 to be disabled. When circuit 204 is disabled, the voltage signal 201 generated by circuit 202 can bypass circuit 204, and the default voltage level (e.g., 5V) can be provided to drivers 208, 210 so that the gate voltage Vg can be set to the default voltage signal, and switches HS and LS can be driven using the default voltage level. In Figure 3 the embodiment shown, if the default voltage level is 5V, in response to the voltage derived from the load current Iload being less than Vref, comparator 220 can output the enable signal EN to disable circuit 204, thereby preventing modification of the voltage signal 201 and keeping Vg at the default voltage signal.

[0020] Figure 4 is a schematic diagram showing an example implementation of adaptive gate voltage adjustment. Figure 4 The description can refer to Figures 1 to 3 the components shown. Figure 4The schematic diagram therein depicts the relationship between the estimated efficiency (expressed as a percentage) and the load current Iload (measured in amperes). Curve 401 illustrates the relationship between the estimated efficiency and the load current Iload when a 5V gate voltage is applied to the driver IC 104. Curve 402 illustrates the relationship between the estimated efficiency and the load current when a 10V gate voltage is applied to the driver IC 104. Curve 401 corresponding to the 5V gate voltage shows higher efficiency in the low ampere range, indicating optimal performance at lower load currents. In contrast, curve 402 associated with the 10V gate voltage exhibits higher efficiency in the high ampere range, indicating optimal performance at higher load currents. Therefore, the controller 102 is configured to change the gate voltage Vg from 5V to 10V when the load current reaches a higher range to reduce FET conduction losses and switching losses, which improves efficiency. When the load current is in a lower range, the controller 102 can also change the gate voltage Vg from 10V to 5V to reduce FET conduction losses and switching losses, which improves efficiency.

[0021] In one embodiment, to maximize the efficiency of the power stage (i.e., the HS switch and the LS switch and / or the entire system 100), the controller 102 can be configured to enable or disable the circuit 204 to modify the gate voltage Vg at the optimal time. The optimal time can depend on various conditions, such as circuit parameters or the type of MOSFET used. The controller 102 can be programmed to enable the circuit 204 to modify Vg based on specific conditions or by manual input at a specific time. Additionally, the controller 102 can be configured to enable or disable the circuit 204 multiple times for multiple load current ranges. In one example embodiment, the controller 102 can use a predefined load current 406 to set the reference voltage Vref, as Figure 2 and Figure 3 shown. The predefined load current 406 can be the load current at which curve 401 intersects curve 402, or at which the efficiency of the default gate voltage (e.g., curve 401 corresponding to 5V) starts to drop below the efficiency of the modified gate voltage (e.g., curve 401 corresponding to 10V). If the default voltage level is 5V, the controller 102 can monitor Iload and, in response to Iload being greater than or equal to the predefined load current 406, generate an enable signal EN to enable the circuit 204 to increase Vg from the default voltage level of 5V to 10V. If the default voltage level is 10V, the controller 102 can monitor Iload and, in response to Iload being less than the predefined load current 406, generate an enable signal EN to enable the circuit 204 to decrease Vg from the default voltage level of 10V to 5V.

[0022] In another example embodiment, the controller 102 may set the reference voltage Vref using another predefined load current 408. The predefined load current 408 may depend on the CCM-DCM boundary. The CCM-DCM boundary may be the condition under which the controller 102 transitions from continuous operation (i.e., CCM) to discontinuous operation (i.e., DCM). In one aspect, the controller 102 may be configured to switch the operating mode based on the detection of the CCM-DCM boundary. Thus, using the predefined load current 408 corresponding to the CCM-DCM boundary may utilize the existing functionality and hardware of the controller 102.

[0023] In one aspect, the controller 102 may be configured to sense the load current at the voltage output Vout of the power stage (i.e., the HS switch and the LS switch). In the low load current range, the controller 102 may be configured to operate in DCM. When in DCM, the controller 102 may deactivate the voltage doubler circuit 204 by sending a turn-off signal at EN. The gate drivers 208 and 210 generate Vg using a default voltage level (e.g., 5V) gate driver to drive the HS switch and the LS switch. When the load current reaches a higher range and the controller 102 transitions the operating mode to CCM, the controller 102 may enable the voltage doubler circuit 204. The voltage doubler circuit 204 may receive 5V from the circuit 202 and double the voltage to 10V. The 10V may be received by the gate drivers 208 and the gate driver 210, and the gate voltage Vg of 10V may drive the HS switch and the LS switch.

[0024] Figure 5 A flowchart illustrating the process of impregnating a gate driver in one embodiment is shown. Process 500 may include one or more operations, actions, or functions, as shown in one or more of blocks 501 and / or 503. Although illustrated as discrete blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel.

[0025] Process 500 may be performed by a controller (such as the controller 102 described in the present disclosure). Process 500 may start at block 501. In block 501, the controller may sense the load current associated with the output voltage of the power stage. Process 500 may continue from block 501 to block 503. In block 503, the controller may define the gate voltage as one of a default voltage level and a modified voltage level based on the sensed load current. The gate voltage may be used to drive the power stage.

[0026] In one embodiment, the default voltage level may be lower than the modified voltage level. The controller may determine that the sensed load current is greater than a predefined load current. In response to determining that the sensed load current is greater than the predefined load current, the controller may increase the default voltage level to the modified voltage level.

[0027] In one embodiment, the controller may determine that the sensed load current is less than a predefined load current. In response to determining that the sensed load current is less than the predefined load current, the controller may maintain the default voltage level.

[0028] In one embodiment, the controller may compare the sensed load current with a predefined load current corresponding to the transition between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) of the power stage. The controller may define the gate voltage based on the result of the comparison between the sensed load current and the predefined load current.

[0029] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a particular logical function. In certain alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0030] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will also be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] All corresponding structures, materials, acts, and equivalents of the methods or steps and functional elements (if any) in the following claims are intended to include any structures, materials, or acts for performing the functions in combination with other claimed elements as specifically claimed. The description of the invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed form of the invention. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The selection and description of the embodiments were chosen to best explain the principles of the invention and its practical application, and to enable others of ordinary skill in the art to understand the invention with various modifications suitable for the particular purposes contemplated.

Claims

1. A semiconductor device, comprising: circuitry configured to define a gate voltage for driving a power stage; as well as The controller is configured as: sensing a load current output by the power stage; as well as Based on the sensed load current, the circuit is controlled to define the gate voltage to one of a default voltage level and a modified voltage level. 2 . The semiconductor device according to claim 1 , wherein the default voltage level is lower than the modified voltage level. 3 . The semiconductor device according to claim 1 , wherein the default voltage level is higher than the modified voltage level.

4. The semiconductor device according to claim 1, wherein the default voltage level is lower than the modified voltage level, and the controller is configured to: determining that the sensed load current is greater than a predefined load current; and In response to determining that the sensed load current is greater than the predefined load current, the circuit is enabled to increase the default voltage level to the modified voltage level.

5. The semiconductor device according to claim 4, wherein the controller is configured to: determining that the load current sensed when the circuit is enabled is less than the predefined load current; and In response to determining that the load current sensed when the circuit is enabled is less than the predefined load current, the circuit is disabled to prevent modification of the default voltage level.

6. The semiconductor device according to claim 1, wherein the default voltage level is lower than the modified voltage level, and the circuit comprises: a low dropout (LDO) regulator configured to generate a signal having the default voltage level; as well as A voltage doubler is configured to modify the voltage signal by multiplying the default voltage level.

7. The semiconductor device according to claim 1, wherein: The controller is configured to: comparing the sensed load current with a predefined load current, wherein the predefined load current corresponds to an overlap between a first efficiency of the power stage and a second efficiency of the power stage, the first efficiency being associated with the default voltage level and the second efficiency being associated with the modified voltage level; and controlling the circuit to define the gate voltage based on a result of the comparison between the sensed load current and the predefined load current.

8. The semiconductor device according to claim 1, wherein: The controller is configured to: comparing the sensed load current with a predefined load current, wherein the predefined load current corresponds to a transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM) of the power stage; and controlling the circuit to define the gate voltage based on a result of the comparison between the sensed load current and the predefined load current.

9. A system comprising: a power stage configured to convert an input voltage into an output voltage; a driver circuit configured to output a gate voltage to drive the power stage; as well as The controller is configured as: sensing a load current associated with the output voltage; as well as The gate voltage is defined to be one of a default voltage level and a modified voltage level based on the sensed load current.

10. The system of claim 9, wherein the default voltage level is lower than the modified voltage level.

11. The system of claim 9, wherein the default voltage level is higher than the modified voltage level.

12. The system of claim 9, wherein the default voltage level is lower than the modified voltage level, and the controller is configured to: determining that the sensed load current is greater than a predefined load current; and In response to determining that the sensed load current is greater than the predefined load current, the default voltage level is increased to the modified voltage level.

13. The system of claim 12, wherein the controller is configured to: determining that the load current sensed when the circuit is enabled is less than the predefined load current; and In response to determining that the load current sensed when the circuit is enabled is less than the predefined load current, the circuit is disabled to prevent modification of the default voltage level.

14. The system of claim 9, wherein the default voltage level is lower than the modified voltage level, and the controller further comprises: a low dropout (LDO) regulator configured to generate a signal having the default voltage level; as well as A voltage doubler is configured to modify the voltage signal by multiplying the default voltage level.

15. The system of claim 9, wherein: The controller is configured to: comparing the sensed load current with a predefined load current, wherein the predefined load current corresponds to an overlap between a first efficiency of the power stage and a second efficiency of the power stage, the first efficiency being associated with the default voltage level and the second efficiency being associated with the modified voltage level; as well as The gate voltage is defined based on a result of the comparison between the sensed load current and the predefined load current.

16. The system of claim 9, wherein: The controller is configured to: comparing the sensed load current with a predefined load current, wherein the predefined load current corresponds to a transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM) of the power stage; and the gate voltage is defined based on a result of the comparison between the sensed load current and the predefined load current.

17. A method of operating a switching converter, the method comprising: sensing a load current associated with an output voltage of the power stage; as well as Based on the sensed load current, a gate voltage is defined to be one of a default voltage level and a modified voltage level, wherein the gate voltage is used to drive the power stage.

18. The method of claim 17, wherein the default voltage level is lower than the modified voltage level, and the method further comprises: determining that the sensed load current is greater than a predefined load current; as well as In response to determining that the sensed load current is greater than the predefined load current, the default voltage level is increased to the modified voltage level.

19. The method according to claim 17, further comprising: determining that the sensed load current is less than a predefined load current; as well as In response to determining that the sensed load current is less than the predefined load current, maintaining the default voltage level.

20. The method of claim 17, further comprising: comparing the sensed load current with a predefined load current corresponding to a transition between a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM) of the power stage; as well as The gate voltage is defined based on a result of the comparison between the sensed load current and the predefined load current.

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