Double-loop bootstrap low-voltage starting circuit applied to Boost converter

Abstract

The invention discloses a double-loop bootstrap low-voltage starting circuit applied to a Boost converter. The double-loop bootstrap low-voltage starting circuit comprises a voltage judgment module, an open-loop low-voltage starting module and a closed-loop low-voltage starting module, open-loop bootstrap and closed-loop bootstrap are combined, through the design scheme that the open-loop bootstrap is connected with the closed-loop bootstrap, by combining the characteristics that the lowest starting voltage of the open-loop bootstrap can be lower in detection and the closed-loop bootstrap is high in speed and good in stability, on the premise that the starting stability is guaranteed, the lowest starting voltage of the circuit is detected as much as possible; furthermore, a quadruple voltage charge pump in the open-loop low-voltage starting module has no threshold voltage loss and is high in driving capability, so that the starting circuit can work under extremely low input voltage.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and particularly relates to a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter. Background Art

[0002] With the booming development of communication technology and Internet of Things technology, the application of wireless sensor networks has been quite extensive, and it can be foreseen that related applications will emerge in more industries in the near future. Since the energy provided by the wireless sensor node network to the power management chip is unstable and has a wide range of variations, it is of great value to study how to start at a low input voltage.

[0003] The Boost converter uses the alternating switching of power switching tubes to control the inductor current to achieve step-up. Under normal conventional input voltages, it can work normally without a special startup circuit. However, the power supply voltage of wireless sensor node networks is often limited. For example, a single solar cell can provide a voltage of 500 - 600 mV outdoors, but can only provide a voltage of 100 - 200 mV in a dark environment; a direct methanol fuel cell can only provide a voltage of 300 - 500 mV. Therefore, a special startup circuit is required to work normally. Moreover, MOS transistors with a breakdown voltage of 5V generally have a threshold voltage greater than the power supply voltage of the above-mentioned wireless sensor node networks due to their specially processed gate oxide layers, which greatly limits the reduction of the startup voltage of the Boost converter.

[0004] Existing methods for low-voltage cold startup of Boost converters, such as using an LC oscillator to drive a charge pump or a transformer to achieve step-up at a lower voltage, require the use of many off-chip passive devices and have a complex actual manufacturing process, which cannot be achieved and is not conducive to the miniaturized application of the device. It is also possible to use an on-chip integrated oscillator and charge pump, but it is difficult to reduce the startup voltage due to factors such as threshold voltage and process deviation, has weak driving ability, and has poor reliability due to its open-loop structure. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0006] The present invention provides a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter, including:

[0007] A voltage discrimination module, an open-loop low-voltage startup module, and a closed-loop low-voltage startup module; wherein,

[0008] The voltage discrimination module is used to discriminate the input voltage V INOr the output voltage V of the Boost converter ST Make a judgment and output the first enable signal ENN1 or the second enable signal ENN2;

[0009] The open-loop low-voltage startup module is used to output a first boost signal according to the first enable signal ENN1, enter the open-loop bootstrap boost mode, and use the first boost signal to boost the output voltage V of the Boost converter ST Perform open-loop boost;

[0010] The closed-loop low-voltage startup module is used to output a second boost signal according to the first enable signal ENN1, the second enable signal ENN2, and the inductor voltage V of the inductor in the Boost converter SW Output the second boost signal, enter the closed-loop bootstrap boost mode, and use the second boost signal to boost the output voltage V of the Boost converter ST Perform closed-loop boost so that the output voltage V of the Boost converter ST Rises to the target voltage to complete the startup.

[0011] In an embodiment of the present invention, the voltage discrimination module makes a judgment on the input voltage V IN Or the output voltage V of the Boost converter ST Make a judgment and output the first enable signal ENN1 or the second enable signal ENN2, including:

[0012] Make a judgment on the input voltage V IN Or the output voltage V of the Boost converter ST Make a judgment. When V IN Or V ST Is less than the preset threshold, output the first enable signal ENN1. When V ST Is greater than or equal to the preset threshold and less than the target voltage, output the second enable signal ENN2.

[0013] In an embodiment of the present invention, the lifting speed of the closed-loop bootstrap boost mode is faster than that of the open-loop bootstrap boost mode.

[0014] In an embodiment of the present invention, the open-loop low-voltage startup module includes:

[0015] Ring oscillator, frequency divider, level shifter, gate driver circuit, quadruple voltage charge pump and capacitor C CP ; Among them,

[0016] The input end of the ring oscillator serves as the input end of the open-loop low-voltage startup module, the power supply end serves as the power supply end of the open-loop low-voltage startup module, and the output end is connected to the input end of the frequency divider;

[0017] The output end of the frequency divider is connected to the input end of the level shifter;

[0018] The power input terminal of the level shift circuit is connected to the output terminal of the quadruple voltage charge pump, and the output terminal is connected to the input terminal of the gate drive circuit;

[0019] The power input terminal of the gate drive circuit is connected to the output terminal of the quadruple voltage charge pump, and the output terminal serves as the output terminal of the open-loop low-voltage startup module;

[0020] The power terminal of the quadruple voltage charge pump is connected to the power terminal of the ring oscillator, and the output terminal is connected to the first terminal of capacitor C CP ;

[0021] The second terminal of capacitor C CP is grounded.

[0022] In an embodiment of the present invention, the quadruple voltage charge pump includes:

[0023] a clock multiplier circuit and a voltage bootstrap circuit; wherein,

[0024] The input terminal of the clock multiplier circuit serves as the input terminal of the quadruple voltage charge pump, the first output terminal is connected to the first input terminal of the voltage bootstrap circuit, and the second output terminal is connected to the second input terminal of the voltage bootstrap circuit;

[0025] The power terminal of the voltage bootstrap circuit serves as the power terminal of the quadruple voltage charge pump, and the output terminal serves as the output terminal of the quadruple voltage charge pump.

[0026] In an embodiment of the present invention, the clock multiplier circuit includes: an inverter, a first clock multiplier sub-circuit and a second clock multiplier sub-circuit with the same structure, and the inverter is arranged at the input terminal of the first clock multiplier sub-circuit; either the first clock multiplier sub-circuit or the second clock multiplier sub-circuit includes:

[0027] NMOS transistor M N1 , NMOS transistor M N2 , NMOS transistor M N3 , NMOS transistor M N4 , PMOS transistor M P1 , PMOS transistor M P2 , PMOS transistor M P3 , PMOS transistor M P4 , PMOS transistor M P5 , PMOS transistor M P6 , PMOS transistor M P7 , capacitor C1, capacitor C2 and capacitor C3; wherein,

[0028] The source terminal of the NMOS transistor M N1 is grounded, the gate terminal serves as the input terminal of the corresponding clock multiplier sub-circuit, and the drain terminal is connected to the PMOS transistor MP1 The drain terminal of

[0029] The NMOS transistor M N2 has its source terminal connected to the source terminal of the NMOS transistor M N1 , its gate terminal connected to the gate terminal of the NMOS transistor M N1 , and its drain terminal connected to the drain terminal of the PMOS transistor M P3 at node C;

[0030] The NMOS transistor M N3 has its source terminal connected to the source terminal of the NMOS transistor M N2 , its gate terminal connected to the gate terminal of the NMOS transistor M N2 , and its drain terminal connected to the drain terminal of the PMOS transistor M P5 at node E;

[0031] The NMOS transistor M N4 has its source terminal connected to the source terminal of the NMOS transistor M N3 , its gate terminal connected to the gate terminal of the NMOS transistor M N3 , and its drain terminal connected to the drain terminal of the PMOS transistor M P7 at node G;

[0032] The PMOS transistor M P1 has its source terminal connected to the power supply terminal of the quadruple - voltage charge pump, and its gate terminal connected to the gate terminal of the NMOS transistor M N1 ;

[0033] The PMOS transistor M P2 has its source terminal connected to the source terminal of the PMOS transistor M P3 at node B, its gate terminal connected to node C, and its drain terminal connected to the source terminal of the PMOS transistor M P1 ;

[0034] The PMOS transistor M P3 has its gate terminal connected to the gate terminal of the NMOS transistor M N1 ;

[0035] The PMOS transistor M P4 has its source terminal connected to the source terminal of the PMOS transistor M P5 at node D, its gate terminal connected to node E, and its drain terminal connected to the drain terminal of the PMOS transistor M P2 ;

[0036] The PMOS transistor M P5 has its gate terminal connected to the gate terminal of the NMOS transistor M N1 ;

[0037] The PMOS transistor M P6 has its source terminal connected to the source terminal of the PMOS transistor M P7The source terminal of [device] is connected to node F, the gate terminal is connected to node G, and the drain terminal is connected to the drain terminal of PMOS transistor M P4 ;

[0038] The gate terminal of the PMOS transistor M P7 is connected to the gate terminal of NMOS transistor M N4 , and node G serves as the output terminal of the corresponding clock multiplier circuit;

[0039] The first terminal of the capacitor C1 is connected to node B, and the second terminal is connected to node A;

[0040] The first terminal of the capacitor C2 is connected to node D, and the second terminal is connected to node C;

[0041] The first terminal of the capacitor C3 is connected to node F, and the second terminal is connected to node E.

[0042] In an embodiment of the present invention, a voltage bootstrap circuit includes:

[0043] NMOS transistor M N5 , NMOS transistor M N6 , NMOS transistor M N7 , NMOS transistor M N8 , NMOS transistor M N9 , NMOS transistor M N10 , NMOS transistor M N11 , PMOS transistor M P8 , PMOS transistor M P9 , PMOS transistor M P10 , capacitor C4, capacitor C5 and capacitor C6; wherein,

[0044] The source terminal of the NMOS transistor M N5 is connected to the drain terminal of the NMOS transistor M N9 at node H, the gate terminal is connected to the output terminal of the first clock multiplier circuit, and the drain terminal serves as the power supply terminal of the voltage bootstrap circuit;

[0045] The source terminal of the NMOS transistor M N6 is connected to the source terminal of the NMOS transistor M P8 at node I, the gate terminal is connected to the gate terminal of the NMOS transistor M N9 , and the drain terminal is connected to the drain terminal of the NMOS transistor M N5 ;

[0046] The source terminal of the NMOS transistor M N7 is connected to the source terminal of the PMOS transistor M P9 at node K, the gate terminal is connected to the gate terminal of the NMOS transistor M N6 , and the drain terminal is connected to the drain terminal of the NMOS transistor M N6 ;

[0047] The source terminal of the NMOS transistor M N8 is connected to the source terminal of the PMOS transistor M P10 at node M. The gate terminal is connected to the gate terminal of the NMOS transistor M N7 and the drain terminal is connected to the drain terminal of the NMOS transistor M N7 .

[0048] The source terminal of the NMOS transistor M N9 is grounded and the gate terminal is connected to the output terminal of the second clock doubler circuit;

[0049] The source terminal of the NMOS transistor M N10 is connected to the source terminal of the NMOS transistor M N9 . The gate terminal is connected to the gate terminal of the NMOS transistor M N7 and the drain terminal is connected to the drain terminal of the PMOS transistor M P8 at node J;

[0050] The source terminal of the NMOS transistor M N11 is connected to the source terminal of the NMOS transistor M N10 . The gate terminal is connected to the gate terminal of the NMOS transistor M N8 and the drain terminal is connected to the drain terminal of the PMOS transistor M P9 at node L;

[0051] The gate terminal of the PMOS transistor M P8 is connected to the gate terminal of the NMOS transistor M N9 ;

[0052] The gate terminal of the PMOS transistor M P9 is connected to the gate terminal of the PMOS transistor M P8 ;

[0053] The gate terminal of the PMOS transistor M P10 is connected to the gate terminal of the PMOS transistor M P9 . The drain terminal is node N, serving as the output terminal of the voltage bootstrap circuit;

[0054] The first terminal of the capacitor C4 is connected to node I and the second terminal is connected to node H;

[0055] The first terminal of the capacitor C5 is connected to node K and the second terminal is connected to node J;

[0056] The first terminal of the capacitor C6 is connected to node M and the second terminal is connected to node L.

[0057] In an embodiment of the present invention, the closed-loop low-voltage startup module includes:

[0058] NMOS transistor M N12 , NMOS transistor M N13 , PMOS transistor MP11 and PMOS transistor M P12 and PMOS transistor M P13 , a digital logic controller, and a current detection comparator; wherein,

[0059] The source terminal of the NMOS transistor M N12 is grounded, the gate terminal is connected to the second output terminal of the digital logic controller, and the drain terminal is connected to the drain terminal of the PMOS transistor M P11 ;

[0060] The source terminal of the NMOS transistor M N13 is grounded, the gate terminal is connected to the fifth output terminal of the digital logic controller, and the drain terminal is connected to the drain terminal of the NMOS transistor M P13 ;

[0061] The source terminal of the PMOS transistor M P11 serves as the power supply terminal of the closed-loop low-voltage startup module, and the gate terminal is connected to the first output terminal of the digital logic controller;

[0062] The source terminal of the PMOS transistor M P12 is connected to the power supply terminal of the closed-loop low-voltage startup module, the gate terminal is connected to the third output terminal of the digital logic controller, and the drain terminal is connected to the source terminal of the NMOS transistor M P13 ;

[0063] The gate terminal of the NMOS transistor M P13 is connected to the fourth output terminal of the digital logic controller, and the drain terminal serves as the output terminal of the closed-loop low-voltage startup module;

[0064] The first enable input terminal of the digital logic controller receives a first enable signal ENN1, the second enable input terminal receives a second enable signal ENN2, the first voltage input terminal of the digital logic controller is connected to the drain terminal of the NMOS transistor M P13 , and the second voltage input terminal is connected to the output terminal of the current detection comparator;

[0065] The inverting input terminal of the current detection comparator is connected to the inductor voltage V SW of the inductor in the Boost converter, and the non-inverting input terminal receives a reference current I RH .

[0066] In an embodiment of the present invention, the Boost converter includes:

[0067] an inductor, a diode, a startup power transistor M N0 and a startup capacitor C ST ; wherein,

[0068] The first end of the inductor is connected to an input voltage V IN , and the second end is connected to the drain terminal of the startup power transistor M N0 ;

[0069] The input terminal of the diode is connected to the second terminal of the inductor, and the output terminal is connected to the first terminal of the starting capacitor C ST .

[0070] The source terminal of the starting power transistor M N0 is grounded, and the gate terminal serves as the input terminal of the Boost converter;

[0071] The first terminal of the starting capacitor C ST serves as the output terminal of the Boost converter, and the second terminal is grounded.

[0072] Advantages of the present invention:

[0073] In the solution provided by the present invention, open-loop bootstrap is combined with closed-loop bootstrap. Through the design scheme of connecting closed-loop bootstrap by open-loop bootstrap, and combining the characteristics that the lowest starting voltage of open-loop bootstrap can be lower and the closed-loop bootstrap has fast speed and good stability, the lowest starting voltage of the circuit is explored as low as possible on the premise of ensuring starting stability; further, the quadruple voltage charge pump in the open-loop low-voltage starting module has no threshold voltage loss and strong driving ability, ensuring that the starting circuit can work at extremely low input voltages. Description of the drawings

[0074] Figure 1 is a schematic diagram of the principle of a dual-loop bootstrap low-voltage starting circuit applied to a Boost converter provided by an embodiment of the present invention;

[0075] Figure 2 is a starting flow chart of a dual-loop bootstrap low-voltage starting circuit applied to a Boost converter provided by an embodiment of the present invention;

[0076] Figure 3 is a schematic diagram of the structure of an open-loop low-voltage starting module in a dual-loop bootstrap low-voltage starting circuit applied to a Boost converter provided by an embodiment of the present invention;

[0077] Figure 4 is a schematic diagram of the structure of a clock multiplier sub-circuit in an open-loop low-voltage starting module provided by an embodiment of the present invention;

[0078] Figure 5 is a waveform diagram of a clock multiplier circuit in an open-loop low-voltage starting module provided by an embodiment of the present invention;

[0079] Figure 6 is a schematic diagram of the structure of a voltage bootstrap circuit in an open-loop low-voltage starting module provided by an embodiment of the present invention;

[0080] Figure 7Waveform schematic diagram of the voltage bootstrap circuit in an open-loop low-voltage startup module provided by an embodiment of the present invention;

[0081] Figure 8 Structural schematic diagram of the closed-loop low-voltage startup module in a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter provided by an embodiment of the present invention;

[0082] Figure 9 Waveform diagram of the closed-loop low-voltage startup module in a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter provided by an embodiment of the present invention;

[0083] Figure 10 Simulation waveform diagram of the operation of the open-loop low-voltage startup module in a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter provided by an embodiment of the present invention;

[0084] Figure 11 Simulation waveform diagram of the entire startup process of a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter provided by an embodiment of the present invention. Detailed implementation manners

[0085] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0086] There are two traditional solutions for realizing the low-voltage startup of a Boost converter. First is the solution for realizing low-voltage startup by closed-loop bootstrap. Through the way of loop control, the voltage multiplication is realized by periodically charging and discharging the bootstrap capacitor to drive the power tube to realize the startup of the converter. Under the closed-loop bootstrap solution, when the voltage of the input power supply is low, the circuit involving loop control cannot work properly, then the circuit function fails and the closed-loop bootstrap circuit cannot work.

[0087] Secondly is the startup solution realized by open-loop bootstrap. By generating a control waveform with a fixed duty cycle and multiplying the voltage of this control waveform through a charge pump or other circuits to obtain the driving signal for starting the power tube, thereby realizing the boost process of the converter. The working voltage of this solution can reach a relatively low level, but due to the lack of participation of negative feedback, when the PVT conditions change, parameters such as the working period of the circuit will change greatly, which will make the system more affected by external conditions, with poor robustness and low reliability in practical applications.

[0088] In view of the above problems, an embodiment of the present invention provides a dual-loop bootstrap low-voltage startup circuit applied to a Boost converter, as Figure 1 shown, which may include:

[0089] A voltage discrimination module, an open-loop low-voltage startup module, and a closed-loop low-voltage startup module; wherein,

[0090] A voltage discrimination module is configured to determine the input voltage V IN or the output voltage V of the Boost converter ST and output a first enable signal ENN1 or a second enable signal ENN2;

[0091] An open-loop low-voltage startup module is configured to output a first boost signal according to the first enable signal ENN1, enter an open-loop bootstrap boost mode, and use the first boost signal to boost the output voltage V of the Boost converter ST in an open-loop manner;

[0092] A closed-loop low-voltage startup module is configured to output a second boost signal according to the first enable signal ENN1, the second enable signal ENN2, and the inductor voltage V of the inductor in the Boost converter SW and enter a closed-loop bootstrap boost mode, and use the second boost signal to boost the output voltage V of the Boost converter ST in a closed-loop manner, so that the output voltage V of the Boost converter ST rises to the target voltage to complete startup.

[0093] Specifically, the voltage discrimination module determines the input voltage V IN or the output voltage V of the Boost converter ST and outputs a first enable signal ENN1 or a second enable signal ENN2, which may include:

[0094] Determine the input voltage V IN or the output voltage V of the Boost converter ST and when V IN or V ST is less than a preset threshold, output the first enable signal ENN1, and when V ST is greater than or equal to the preset threshold and less than the target voltage, output the second enable signal ENN2.

[0095] For the startup flowchart of the dual-loop bootstrap low-voltage startup circuit provided by the embodiments of the present invention, please refer to Figure 2 as shown. It can be seen from Figure 2 that the output of the voltage discrimination module determines the startup process of the dual-loop bootstrap low-voltage startup circuit. The input end of the voltage discrimination module is connected to the input voltage V IN and the output voltage V of the Boost converter ST , and outputs the comparison result ENN1 of V IN or V ST with the preset threshold, and the comparison result of V STThe comparison result ENN2 with the target voltage is used to determine the working order of each module, thereby controlling the entire startup process of the dual-loop bootstrap low-voltage startup circuit. Optionally, the preset threshold can be set to 550 mV, and the target voltage can be set to 1.8 V.

[0096] At the beginning of the startup circuit operation. When the input voltage V IN is relatively low and does not meet the implementation conditions for closed-loop bootstrap, the output voltage V of the Boost converter is lifted above the preset threshold through the open-loop bootstrap lift mode. ST At this time, the voltage discrimination module determines whether the startup circuit reaches the closed-loop bootstrap lift mode by detecting the magnitude of the output voltage V ST . If it reaches, the output voltage V ST is accelerated in its rising process through the closed-loop control bootstrap method. When the voltage discrimination module detects that the output voltage V ST reaches the target voltage, it indicates that the startup circuit has reached the voltage level at which the Boost converter operates normally, and the startup is completed. At the same time, the voltage discrimination module will compare the input voltage V IN and the output voltage V ST to select high-voltage operation for other modules.

[0097] It can be understood that the lifting speed of the closed-loop bootstrap lift mode is faster than that of the open-loop bootstrap lift mode.

[0098] The open-loop low-voltage startup module, as Figure 3 shown, may include:

[0099] a ring oscillator, a frequency divider, a level shifter circuit, a gate driver circuit, a quadruple voltage charge pump, and a capacitor C CP ; where

[0100] the input terminal of the ring oscillator serves as the input terminal of the open-loop low-voltage startup module, the power supply terminal serves as the power supply terminal of the open-loop low-voltage startup module, and the output terminal is connected to the input terminal of the frequency divider;

[0101] the output terminal of the frequency divider is connected to the input terminal of the level shifter circuit;

[0102] the power supply input terminal of the level shifter circuit is connected to the output terminal of the quadruple voltage charge pump, and the output terminal is connected to the input terminal of the gate driver circuit;

[0103] the power supply input terminal of the gate driver circuit is connected to the output terminal of the quadruple voltage charge pump, and the output terminal serves as the output terminal of the open-loop low-voltage startup module;

[0104] the power supply terminal of the quadruple voltage charge pump is connected to the power supply terminal of the ring oscillator, and the output terminal is connected to the first terminal of the capacitor C CP ;

[0105] Capacitor CCP The second end is grounded.

[0106] A quadruple voltage charge pump may include:

[0107] A clock multiplier circuit and a voltage bootstrap circuit; wherein,

[0108] The input end of the clock multiplier circuit serves as the input end of the quadruple voltage charge pump, the first output end is connected to the first input end of the voltage bootstrap circuit, and the second output end is connected to the second input end of the voltage bootstrap circuit;

[0109] The power supply end of the voltage bootstrap circuit serves as the power supply end of the quadruple voltage charge pump, and the output end serves as the output end of the quadruple voltage charge pump.

[0110] The clock multiplier circuit may include: an inverter, a first clock multiplier sub-circuit and a second clock multiplier sub-circuit with the same structure. The inverter is arranged at the input end of the first clock multiplier sub-circuit; either the first clock multiplier sub-circuit or the second clock multiplier sub-circuit, as Figure 4 shown, may include:

[0111] NMOS transistor M N1 、NMOS transistor M N2 、NMOS transistor M N3 、NMOS transistor M N4 、PMOS transistor M P1 、PMOS transistor M P2 、PMOS transistor M P3 、PMOS transistor M P4 、PMOS transistor M P5 、PMOS transistor M P6 、PMOS transistor M P7 、capacitor C1, capacitor C2 and capacitor C3; wherein,

[0112] The source end of NMOS transistor M N1 is grounded, the gate end serves as the input end of the corresponding clock multiplier sub-circuit, and the drain end is connected to the drain end of PMOS transistor M P1 at node A;

[0113] The source end of NMOS transistor M N2 is connected to the source end of NMOS transistor M N1 ,the gate end is connected to the gate end of NMOS transistor M N1 ,and the drain end is connected to the drain end of PMOS transistor M P3 at node C;

[0114] The source end of NMOS transistor M N3 is connected to the source end of NMOS transistor M N2 ,the gate end is connected to the gate end of NMOS transistor M N2 ,and the drain end is connected to the drain end of PMOS transistor MP5 The drain terminal of

[0115] NMOS transistor M N4 is connected to the source terminal of NMOS transistor M N3 , the gate terminal is connected to the gate terminal of NMOS transistor M N3 , and the drain terminal is connected to the drain terminal of PMOS transistor M P7 at node E;

[0116] PMOS transistor M P1 has its source terminal connected to the power supply terminal of the quadruple voltage charge pump, and its gate terminal connected to the gate terminal of NMOS transistor M N1 ;

[0117] PMOS transistor M P2 has its source terminal connected to the source terminal of PMOS transistor M P3 at node B, its gate terminal connected to node C, and its drain terminal connected to the source terminal of PMOS transistor M P1 ;

[0118] PMOS transistor M P3 has its gate terminal connected to the gate terminal of NMOS transistor M N1 ;

[0119] PMOS transistor M P4 has its source terminal connected to the source terminal of PMOS transistor M P5 at node D, its gate terminal connected to node E, and its drain terminal connected to the drain terminal of PMOS transistor M P2 ;

[0120] PMOS transistor M P5 has its gate terminal connected to the gate terminal of NMOS transistor M N1 ;

[0121] PMOS transistor M P6 has its source terminal connected to the source terminal of PMOS transistor M P7 at node F, its gate terminal connected to node G, and its drain terminal connected to the drain terminal of PMOS transistor M P4 ;

[0122] PMOS transistor M P7 has its gate terminal connected to the gate terminal of NMOS transistor M N4 , and node G serves as the output terminal of the corresponding clock multiplier circuit;

[0123] The first terminal of capacitor C1 is connected to node B, and the second terminal is connected to node A;

[0124] The first terminal of capacitor C2 is connected to node D, and the second terminal is connected to node C;

[0125] The first terminal of capacitor C3 is connected to node F, and the second terminal is connected to node E.

[0126] For the waveform schematic diagram of the clock doubling circuit, please refer to Figure 5 As shown, NodeB, NodeE, and NodeG respectively represent Node B, Node E, and Node G. represents the inverted signal output after the CLK signal passes through the inverter. It can be seen from the working waveform of the clock doubling circuit that when the clock doubling circuit starts to work, CLK = 1, and the NMOS transistors M N1 , NMOS transistor M N2 , NMOS transistor M N3 and NMOS transistor M N4 are turned on, while the PMOS transistors M P1 , PMOS transistor M P2 , PMOS transistor M P3 , PMOS transistor M P4 , PMOS transistor M P5 and PMOS transistor M P6 are turned off. At this time, the potentials of Node A, Node C, Node E, and Node G are 0 volts, while the voltages of Node B, Node D, and Node F are VCC. The voltages across the capacitors C1, C2, and C3 are all charged to VCC. Subsequently, the CLK signal jumps to 0, and the NMOS transistors M N1 , NMOS transistor M N2 , NMOS transistor M N3 and NMOS transistor M N4 are disconnected, while the PMOS transistors M P1 , PMOS transistor M P2 , PMOS transistor M P3 , PMOS transistor M P4 , PMOS transistor M P5 and PMOS transistor M P6 are turned on. Node A is connected to VCC through the PMOS transistor M P1 , so the voltage of Node A is VCC; the voltage of Node C is the sum of the voltage of Node A and the voltage drop across capacitor C1, so the voltage of Node B is 2VCC; and so on: the voltage of Node E is the sum of the voltage of Node C and the voltage drop across capacitor C2, so the voltage of Node E is 3VCC; the voltage of Node G is the sum of the voltage of Node E and the voltage drop across capacitor C3, so the voltage of Node G is 4VCC.

[0127] The voltage bootstrap circuit, as Figure 6 shown, may include:

[0128] NMOS transistor M N5 , NMOS transistor M N6 , NMOS transistor M N7 , NMOS transistor M N8 , NMOS transistor M N9, NMOS transistor M N10 , NMOS transistor M N11 , PMOS transistor M P8 , PMOS transistor M P9 , PMOS transistor M P10 , capacitor C4, capacitor C5, and capacitor C6; among them,

[0129] The source terminal of NMOS transistor M N5 is connected to the drain terminal of NMOS transistor M N9 at node H, the gate terminal is connected to the output terminal of the first clock multiplier circuit, and the drain terminal serves as the power supply terminal of the voltage bootstrap circuit;

[0130] The source terminal of NMOS transistor M N6 is connected to the source terminal of NMOS transistor M P8 at node I, the gate terminal is connected to the gate terminal of NMOS transistor M N9 , and the drain terminal is connected to the drain terminal of NMOS transistor M N5 ;

[0131] The source terminal of NMOS transistor M N7 is connected to the source terminal of PMOS transistor M P9 at node K, the gate terminal is connected to the gate terminal of NMOS transistor M N6 , and the drain terminal is connected to the drain terminal of NMOS transistor M N6 ;

[0132] The source terminal of NMOS transistor M N8 is connected to the source terminal of PMOS transistor M P10 at node M, the gate terminal is connected to the gate terminal of NMOS transistor M N7 , and the drain terminal is connected to the drain terminal of NMOS transistor M N7 ;

[0133] The source terminal of NMOS transistor M N9 is grounded, and the gate terminal is connected to the output terminal of the second clock multiplier circuit;

[0134] The source terminal of NMOS transistor M N10 is connected to the source terminal of NMOS transistor M N9 , the gate terminal is connected to the gate terminal of NMOS transistor M N7 , and the drain terminal is connected to the drain terminal of PMOS transistor M P8 at node J;

[0135] The source terminal of NMOS transistor M N11 is connected to the source terminal of NMOS transistor M N10 , the gate terminal is connected to the gate terminal of NMOS transistor M N8 , and the drain terminal is connected to the drain terminal of PMOS transistor M P9 at node L;

[0136] PMOS transistor M P8 has its gate terminal connected to the gate terminal of NMOS transistor M N9 ;

[0137] The gate terminal of PMOS transistor M P9 is connected to the gate terminal of PMOS transistor M P8 ;

[0138] The gate terminal of PMOS transistor M P10 is connected to the gate terminal of PMOS transistor M P9 , and its drain terminal is node N, serving as the output terminal of the voltage bootstrap circuit;

[0139] The first terminal of capacitor C4 is connected to node I, and the second terminal is connected to node H;

[0140] The first terminal of capacitor C5 is connected to node K, and the second terminal is connected to node J;

[0141] The first terminal of capacitor C6 is connected to node M, and the second terminal is connected to node L.

[0142] For the waveform schematic diagram of the voltage bootstrap circuit, please refer to Figure 7 as shown. NodeH, NodeI, NodeK, NodeM, and NodeN respectively represent node H, node I, node K, node M, and node N. It can be seen from the working waveform of the voltage bootstrap circuit that when the voltage bootstrap circuit starts to work, the CLK signal is at a high level. At this time, NMOS transistors M N6 , NMOS transistors M N7 , NMOS transistors M N8 , NMOS transistors M N9 , NMOS transistors M N10 , and NMOS transistors M N11 are all turned on, while NMOS transistor M N5 , PMOS transistor M P8 , PMOS transistor M P9 , and PMOS transistor M P10 are turned off; Node H, node J, and node L are grounded, while node I, node K, and node M are connected to VCC. Therefore, the voltages across capacitors C4, C5, and C6 are charged to VCC. After half a CLK cycle, the CLK signal jumps to a low level. At this time, NMOS transistors M N6 , NMOS transistors M N7 , NMOS transistors M N8 , NMOS transistors M N9 , NMOS transistors M N10 , and NMOS transistors M N11 are turned off, while NMOS transistor M N5 , PMOS transistor M P8 , PMOS transistor M P9 and PMOS transistor MP10 is turned on, and an electrical path formed by the series connection of capacitor C4, capacitor C5, and capacitor C6 is formed between the node N of the voltage bootstrap circuit and VCC. Due to the charge sharing effect, the series connection of capacitor C4, capacitor C5, and capacitor C6 starts to charge capacitor C in the open-loop low-voltage startup module. CP After several cycles, the voltage across capacitor C CP will be charged to the sum of the voltages across VCC and the three bootstrap capacitors C4, C5, and C6, that is, 4 times VCC.

[0143] The closed-loop low-voltage startup module, as Figure 8 shown, may include:

[0144] NMOS transistor M N12 , NMOS transistor M N13 , PMOS transistor M P11 , PMOS transistor M P12 , PMOS transistor M P13 , a digital logic controller, and a current detection comparator; where

[0145] the source terminal of NMOS transistor M N12 is grounded, the gate terminal is connected to the second output terminal of the digital logic controller, and the drain terminal is connected to the drain terminal of PMOS transistor M P11 ;

[0146] the source terminal of NMOS transistor M N13 is grounded, the gate terminal is connected to the fifth output terminal of the digital logic controller, and the drain terminal is connected to the drain terminal of NMOS transistor M P13 ;

[0147] the source terminal of PMOS transistor M P11 serves as the power supply terminal of the closed-loop low-voltage startup module, and the gate terminal is connected to the first output terminal of the digital logic controller;

[0148] the source terminal of PMOS transistor M P12 is connected to the power supply terminal of the closed-loop low-voltage startup module, the gate terminal is connected to the third output terminal of the digital logic controller, and the drain terminal is connected to the source terminal of NMOS transistor M P13 ;

[0149] the gate terminal of NMOS transistor M P13 is connected to the fourth output terminal of the digital logic controller, and the drain terminal serves as the output terminal of the closed-loop low-voltage startup module;

[0150] the first enable input terminal of the digital logic controller receives the first enable signal ENN1, the second enable input terminal receives the second enable signal ENN2, the first voltage input terminal of the digital logic controller is connected to the drain terminal of NMOS transistor M P13 , and the second voltage input terminal is connected to the output terminal of the current detection comparator;

[0151] The inverting input terminal of the current detection comparator is connected to the inductor voltage V of the inductor in the Boost converter SW and the non-inverting input terminal is connected to the reference current I RH .

[0152] The Boost converter, as Figure 1 shown, may include:

[0153] an inductor, a diode, a startup power transistor M N0 and a startup capacitor C ST ; where

[0154] the first end of the inductor is connected to the input voltage V IN , and the second end is connected to the drain terminal of the startup power transistor M N0 ;

[0155] the input terminal of the diode is connected to the second end of the inductor, and the output terminal is connected to the first end of the startup capacitor C ST ;

[0156] the source terminal of the startup power transistor M N0 is grounded, and the gate terminal serves as the input terminal of the Boost converter;

[0157] the first end of the startup capacitor C ST serves as the output terminal of the Boost converter, and the second end is grounded.

[0158] It can be understood that the inductor voltage V of the inductor in the Boost converter SW is the voltage of the second end of the inductor. As can be seen from Figure 8 , the signal output from the first output terminal of the digital logic controller is Φ1, the signal output from the second output terminal is Φ2, the signal output from the third output terminal is Φ3, the signal output from the fourth output terminal is Φ4, and the signal output from the fifth output terminal is Φ5.

[0159] For the waveform diagram of the closed-loop low-voltage startup module in the double-loop bootstrap low-voltage startup circuit, please refer to Figure 9 shown. It can be seen that the working waveform of the closed-loop low-voltage startup module. At the beginning of the bootstrap cycle, the closed-loop low-voltage startup module first enters the pre-charge state. Since VCC charges the gate terminal of the startup power transistor M N0 in the Boost converter, the voltage V GST at the output terminal of the closed-loop low-voltage startup module rises to about one VCC, and then controls the PMOS transistor M P11 and the PMOS transistor M P13 to conduct, while the NMOS transistor M N12 , the NMOS transistor M N13 , and the PMOS transistor M P12Turn off, and the closed-loop low-voltage startup module enters the bootstrap state. In the bootstrap state, the inductor current I of the inductor in the Boost converter L gradually rises. When it reaches the reference current I RH , the output of the current detection comparator jumps to low. At this time, the closed-loop low-voltage startup module enters the inductor discharge stage, controlling the PMOS transistor M P11 and the PMOS transistor M P13 to turn off, while the NMOS transistor M N12 , the NMOS transistor M N13 , and the PMOS transistor M P12 conduct. After the delay ends, control the NMOS transistor M N12 , the MOS transistor M P12 and the PMOS transistor M P13 to conduct, while the NMOS transistor M N13 and the PMOS transistor M P11 turn off. The closed-loop low-voltage startup module changes to the pre-charge state and enters the closed-loop control bootstrap process of the next cycle.

[0160] For the simulation waveform diagram of the double-loop bootstrap low-voltage startup circuit during the operation of the open-loop low-voltage startup module, please refer to Figure 10 as shown. It can be seen that when the startup circuit has an input voltage of 180 mV, I L represents the inductance value of the inductor in the Boost converter, CLK represents the clock signal output by the ring oscillator, and V GST represents the output terminal voltage of the closed-loop low-voltage startup module. The waveform shows that through the quadruple voltage charge pump, the voltage V GST at the output terminal of the closed-loop low-voltage startup module rises to about four times the input voltage level.

[0161] For the simulation waveform diagram of the entire startup process of the double-loop bootstrap low-voltage startup circuit, as Figure 11 shown. It can be seen that V ST represents the output voltage of the Boost converter. When the double-loop bootstrap low-voltage startup circuit has an input voltage of 180 mV, it first enters the open-loop bootstrap boost mode. When the voltage V GST rises above 180 mV (i.e., at time t1), the power supply in the double-loop bootstrap low-voltage startup circuit switches to V ST , and the startup accelerates; when V ST rises above the preset threshold, it switches to the closed-loop low-voltage startup to continue boosting.

[0162] The dual-loop bootstrap low-voltage startup circuit proposed by the embodiment of the present invention combines open-loop bootstrap and closed-loop bootstrap. Through the design scheme of connecting the closed-loop bootstrap by the open-loop bootstrap, and combining the characteristics that the lowest startup voltage of the open-loop bootstrap can reach a lower level and the closed-loop bootstrap has fast speed and good stability, the lowest startup voltage of the circuit is explored as low as possible on the premise of ensuring startup stability; further, the quadruple voltage charge pump in the open-loop low-voltage startup module has no threshold voltage loss and strong driving ability, ensuring that the startup circuit can work at an extremely low input voltage.

[0163] It should be noted that in the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0164] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A dual-loop bootstrap low-voltage start-up circuit for a Boost converter, characterized in that: include: Voltage discrimination module, open-loop low-voltage starting module and closed-loop low-voltage starting module; wherein, The voltage discrimination module is used to determine the input voltage V IN or the output voltage of the Boost converter V ST Make a judgment and output a first enable signal ENN1 or a second enable signal ENN2; The open-loop low-voltage startup module is used to output a first boost signal according to the first enable signal ENN1, enter the open-loop bootstrap mode, and use the first boost signal to boost the output voltage V ST Perform open loop lifting; The closed-loop low-voltage startup module is used to generate an inductor voltage V of the inductor in the Boost converter according to the first enable signal ENN1, the second enable signal ENN2 and the inductor voltage V SW Output the second boost signal, enter the closed-loop bootstrap mode, and use the second boost signal to boost the output voltage V ST Perform closed-loop boosting to make the output voltage V ST Rise to the target voltage and start-up is completed.

2. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 1, characterized in that: The voltage discrimination module detects the input voltage V IN or the output voltage of the Boost converter V ST Making a judgment and outputting a first enable signal ENN1 or a second enable signal ENN2 includes: For input voltage V IN or the output voltage of the Boost converter V ST Make a judgment, at V IN or V ST When V ST When the voltage is greater than or equal to the preset threshold and less than the target voltage, the second enable signal ENN2 is output.

3. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 1, characterized in that: The lifting speed of the closed-loop self-bootstrap lifting mode is faster than the lifting speed of the open-loop self-bootstrap lifting mode.

4. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 1, characterized in that: The open-loop low-voltage starting module comprises: Ring oscillator, frequency divider, level shift circuit, gate drive circuit, quadruple voltage charge pump and capacitor C CP ;in, The input end of the ring oscillator is used as the input end of the open-loop low-voltage startup module, the power supply end is used as the power supply end of the open-loop low-voltage startup module, and the output end is connected to the input end of the frequency divider; The output end of the frequency divider is connected to the input end of the level shift circuit; The power input end of the level shift circuit is connected to the output end of the quadruple voltage charge pump, and the output end is connected to the input end of the gate drive circuit; The power input end of the gate drive circuit is connected to the output end of the quadruple voltage charge pump, and the output end serves as the output end of the open-loop low-voltage startup module; The power supply end of the quadruple voltage charge pump is connected to the power supply end of the ring oscillator, and the output end is connected to the capacitor C CP A first end is connected; The capacitor C CP The second end is grounded.

5. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 4, characterized in that: The quadruple voltage charge pump comprises: A clock multiplication circuit and a voltage bootstrap circuit; wherein, The input end of the clock multiplication circuit serves as the input end of the quadruple voltage charge pump, the first output end is connected to the first input end of the voltage bootstrap circuit, and the second output end is connected to the second input end of the voltage bootstrap circuit; The power supply end of the voltage bootstrap circuit serves as the power supply end of the quadruple voltage charge pump, and the output end serves as the output end of the quadruple voltage charge pump.

6. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 5, characterized in that: The clock multiplication circuit comprises: an inverter, a first clock multiplication subcircuit and a second clock multiplication subcircuit having the same structure, wherein the inverter is arranged at the input end of the first clock multiplication subcircuit; either the first clock multiplication subcircuit or the second clock multiplication subcircuit comprises: NMOS tube M N1 、NMOS tube M N2 、NMOS tube M N3 、NMOS tube M N4 、PMOS tube M P1 、PMOS tube M P2 、PMOS tube M P3 、PMOS tube M P4 、PMOS tube M P5 、PMOS tube M P6 、PMOS tube M P7 , capacitor C1, capacitor C2 and capacitor C3; wherein, The NMOS tube M N1 The source end of the PMOS tube M is connected to the ground, the gate end is used as the input end of the corresponding clock multiplication sub-circuit, and the drain end is connected to the PMOS tube M P1 The drain end is connected to node A; The NMOS tube M N2 The source end of the NMOS tube M N1 The source end is connected to the gate end of the NMOS tube M N1 The gate end is connected to the PMOS tube M P3 The drain end is connected to the node C; The NMOS tube M N3 The source end of the NMOS tube M N2 The source end is connected to the gate end of the NMOS tube M N2 The gate end is connected to the PMOS tube M P5 The drain end is connected to the node E; The NMOS tube M N4 The source end of the NMOS tube M N3 The source end is connected to the gate end of the NMOS tube M N3 The gate end is connected to the PMOS tube M P7 The drain end of is connected to the node G; The PMOS tube M P1 The source end is connected to the power supply end of the quadruple voltage charge pump, and the gate end is connected to the NMOS tube M N1 The gate terminal connection; The PMOS tube M P2 The source end of the PMOS tube M P3 The source end is connected to node B, the gate end is connected to node C, and the drain end is connected to PMOS tube M P1 The source connection of The PMOS tube M P3 The gate terminal of the NMOS tube M N1 The gate terminal connection; The PMOS tube M P4 The source end of the PMOS tube M P5 The source end is connected to node D, the gate end is connected to node E, and the drain end is connected to PMOS tube M P2 The drain connection of The PMOS tube M P5 The gate terminal of the NMOS tube M N1 The gate terminal connection; The PMOS tube M P6 The source end of the PMOS tube M P7 The source end is connected to node F, the gate end is connected to node G, and the drain end is connected to PMOS tube M P4 The drain connection of The PMOS tube M P7 The gate terminal of the NMOS tube M N4 The gate terminal of the clock multiplication sub-circuit is connected, and the node G serves as the output terminal of the corresponding clock multiplication sub-circuit; The first end of the capacitor C1 is connected to the node B, and the second end is connected to the node A; The first end of the capacitor C2 is connected to the node D, and the second end is connected to the node C; The first end of the capacitor C3 is connected to the node F, and the second end is connected to the node E.

7. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 6, characterized in that: The voltage bootstrap circuit comprises: NMOS tube M N5 、NMOS tube M N6 、NMOS tube M N7 、NMOS tube M N8 、NMOS tube M N9 、NMOS tube M N10 、NMOS tube M N11 、PMOS tube M P8 、PMOS tube M P9 、PMOS tube M P10 , capacitor C4, capacitor C5 and capacitor C6; wherein, The NMOS tube M N5 The source end of the NMOS tube M N9 The drain terminal is connected to the node H, the gate terminal is connected to the output terminal of the first clock multiplication sub-circuit, and the drain terminal serves as the power supply terminal of the voltage bootstrap circuit; The NMOS tube M N6 The source end of the NMOS tube M P8 The source end is connected to node I, and the gate end is connected to NMOS tube M N9 The gate end is connected to the drain end of the NMOS tube M N5 The drain connection of The NMOS tube M N7 The source end of the PMOS tube M P9 The source end is connected to node K, and the gate end is connected to NMOS tube M N6 The gate end is connected to the drain end of the NMOS tube M N6 The drain connection of The NMOS tube M N8 The source end of the PMOS tube M P10 The source end is connected to node M, and the gate end is connected to NMOS tube M N7 The gate end is connected to the drain end of the NMOS tube M N7 The drain connection of The NMOS tube M N9 The source end is grounded, and the gate end is connected to the output end of the second clock multiplication sub-circuit; The NMOS tube M N10 The source end of the NMOS tube M N9 The source end is connected to the gate end of the NMOS tube M N7 The gate end is connected to the PMOS tube M P8 The drain end of is connected to the node J; The NMOS tube M N11 The source end of the NMOS tube M N10 The source end is connected to the gate end of the NMOS tube M N8 The gate end is connected to the PMOS tube M P9 The drain end is connected to the node L; The PMOS tube M P8 The gate terminal of the NMOS tube M N9 The gate terminal connection; The PMOS tube M P9 The gate terminal of the PMOS tube M P8 The gate terminal connection; The PMOS tube M P10 The gate terminal of the PMOS tube M P9 The gate terminal is connected to the drain terminal of the voltage bootstrap circuit, and the drain terminal is the node N, which serves as the output terminal of the voltage bootstrap circuit; The first end of the capacitor C4 is connected to the node I, and the second end is connected to the node H; The first end of the capacitor C5 is connected to the node K, and the second end is connected to the node J; The first end of the capacitor C6 is connected to the node M, and the second end is connected to the node L.

8. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 5, characterized in that: The closed-loop low-voltage starting module comprises: NMOS tube M N12 、NMOS tube M N13 、PMOS tube M P11 、PMOS tube M P12 、PMOS tube M P13 , digital logic controller and current detection comparator; wherein, The NMOS tube M N12 The source end is grounded, the gate end is connected to the second output end of the digital logic controller, and the drain end is connected to the PMOS tube M P11 The drain connection of The NMOS tube M N13 The source end is grounded, the gate end is connected to the fifth output end of the digital logic controller, and the drain end is connected to the NMOS tube M P13 The drain connection of The PMOS tube M P11 The source end is used as the power supply end of the closed-loop low-voltage starting module, and the gate end is connected to the first output end of the digital logic controller; The PMOS tube M P12 The source end is connected to the power supply end of the closed-loop low-voltage startup module, the gate end is connected to the third output end of the digital logic controller, and the drain end is connected to the NMOS tube M P13 The source connection of The NMOS tube M P13 The gate end is connected to the fourth output end of the digital logic controller, and the drain end serves as the output end of the closed-loop low-voltage startup module; The first enable input terminal of the digital logic controller is connected to the first enable signal ENN1, the second enable input terminal is connected to the second enable signal ENN2, and the first voltage input terminal of the digital logic controller is connected to the NMOS transistor M. P13 The drain terminal is connected to the second voltage input terminal and the output terminal of the current detection comparator is connected; The inverting input terminal of the current detection comparator is connected to the inductor voltage V of the inductor in the Boost converter. SW The positive input terminal is connected to the reference current I RH .

9. A dual-loop bootstrap low-voltage starting circuit for a Boost converter according to claim 1, characterized in that: The Boost converter comprises: Inductor, diode, start-up power tube M N0 and starting capacitor C ST ;in, The first end of the inductor is connected to the input voltage V IN The second end is connected to the start power tube M N0 The drain connection of The input end of the diode is connected to the second end of the inductor, and the output end is connected to the starting capacitor C ST A first end is connected; The starting power tube M N0 The source end is grounded, and the gate end serves as the input end of the Boost converter; The starting capacitor C ST The first end of is used as the output end of the Boost converter, and the second end is grounded.

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