Low noise amplifier and wireless electronic equipment

Abstract

The embodiment of the invention provides a low noise amplifier. Comprising an input end, a first output end, a second output end, a first branch circuit connected between the input end and the first output end, a second branch circuit connected between the input end and the second output end, and a third branch circuit connected between an intermediate node in the second branch circuit and the first output end. Wherein the input end is used for receiving a single-end voltage signal, the first output end and the second output end are used for outputting a pair of differential current signals, and the third branch is used for balancing the transconductance gain of the first output end and the transconductance gain of the second output end. The low-noise amplifier has the advantages of low noise, high linearity and low energy consumption in a broadband, realizes balance of differential output current signals, is easy to realize and occupies a small space.

Description

Technical Field

[0001] The present invention relates to wireless communication technologies, and particularly to a low-noise amplifier and a wireless electronic device. Background Art

[0002] With the increasing demand for wireless communication products and services, the demand for low-cost, miniaturized, and highly energy-efficient radio frequency integrated circuit (RFIC) transceivers has also increased. To meet these requirements, the printed circuit board (PCB) area can be reduced, system complexity and power consumption can be lowered. At the same time, RFIC transceivers need to support multiple communication standards, such as Global System for Mobile Communications (GSM), Wideband Code Division Multiple Access (WCDMA), Bluetooth, Long-term Evolution (LTE), 5G New Radio (NR), and 5G Reduced Capability (RedCap), etc. In addition, RFICs also need to operate in multiple frequency bands. Multiple standards and multiple frequency bands determine the number of RFIC input terminals. Currently, RFICs may need to support more than 20 RX input terminals.

[0003] To reduce the number of pins to save area, reduce complexity, and avoid incompatibility with filters (e.g., surface acoustic wave filters), RFICs usually adopt single-ended inputs. The single-ended input design can also reduce the number of radio frequency traces between the RFIC and the front-end module (FEM), thereby simplifying PCB wiring and reducing the layout area. On the other hand, differential signal processing can reduce the sensitivity to substrate noise, reduce coupling and leakage, and has stronger anti-interference ability against common-mode interference, while providing a better second-order intercept point (IP2). To take advantage of the above advantages, RFIC chips usually use a single-ended to differential (S2D) low-noise amplifier (LNA) at the front end to convert single-ended signals into differential signals suitable for subsequent processing.

[0004] In the prior art, the following two methods are mainly used to implement S2D: using a single-ended I / O amplifier combined with a balanced-unbalanced converter (Balun) to provide a differential output; or implementing S2D conversion by using a transformer-type Balun combined with a differential amplifier. However, the single-ended I / O amplifier in the former method is very sensitive to power supply parasitic parameters and / or ground parasitic parameters, resulting in the gain, noise factor (NF), stability, and matching performance being easily affected adversely. The latter method will lead to an increase in loss and deterioration of the noise factor due to problems such as the large chip area and limited quality factor of the transformer-type Balun.

[0005] To overcome the above problems, an amplifier with an active Balun can be used to achieve a balance among noise, linearity, and power consumption. This solution can use a negative feedback amplifier, or use a common gate (CG) amplifier and a common source (CS) amplifier to eliminate feedforward noise. However, the negative feedback amplifier has stability problems, and although the structure of the CG-CS amplifier has good stability, different load impedances need to be used to implement S2D, resulting in more complex control of the output load in the current output mode.

[0006] Therefore, how to solve the above defects of the active Balun amplifier, balance noise, linearity, and power consumption with a simple and stable structure, and achieve a high-quality differential output current signal is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0007] In view of this, embodiments of the present invention provide a low-noise amplifier and a wireless electronic device, which can balance noise, linearity, and power consumption and achieve a high-quality differential output current signal by using a simple and stable structure.

[0008] A first aspect of an embodiment of the present application provides a low-noise amplifier, including an input terminal, a first output terminal, and a second output terminal. The low-noise amplifier further includes: a first branch circuit connected between the input terminal and the first output terminal; a second branch circuit connected between the input terminal and the second output terminal; and a third branch circuit connected between an intermediate node in the second branch circuit and the first output terminal; wherein, the input terminal is used to receive a single-ended voltage signal, the first output terminal and the second output terminal are used to output a pair of differential current signals, and the third branch is used to equalize the transconductance gain of the first output terminal and the transconductance gain of the second output terminal.

[0009] In some embodiments, the intermediate node divides the second branch circuit into a first sub-circuit and a second sub-circuit; the first branch circuit is configured to provide a first transconductance gain between the input terminal and the first output terminal; the second branch circuit is configured to provide a second transconductance gain between the input terminal and the second output terminal, wherein the first sub-circuit is configured to provide a first sub-transconductance gain between the input terminal and the intermediate node, the second sub-circuit is configured to provide a second sub-transconductance gain between the intermediate node and the second output terminal, and the second transconductance gain is the sum of the first sub-transconductance gain and the second sub-transconductance gain; the third branch circuit is configured to provide a third transconductance gain between the intermediate node and the first input terminal; the first sub-transconductance gain is equal to the second sub-transconductance gain, and the third transconductance gain is equal to the difference between the first sub-transconductance gain and the first transconductance gain.

[0010] In some embodiments, the first branch circuit includes a first transistor and a second transistor. The first non-gate of the first transistor is connected to the input terminal, the second non-gate of the first transistor is connected to the first non-gate of the second transistor, and the second non-gate of the second transistor is connected to the first output terminal; the second branch circuit includes a third transistor and a fourth transistor.

[0011] In some embodiments, the gate of the third transistor is connected to the input terminal through a first AC coupling capacitor, the first non-gate of the fourth transistor is connected to the second output terminal, and the second non-gate of the fourth transistor and the first non-gate of the third transistor are connected to the intermediate node.

[0012] In some embodiments, the third branch circuit includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to the intermediate node through a second AC coupling capacitor, the first non-gate of the eighth transistor is connected to the first output terminal, and the second non-gate of the eighth transistor is connected to the first non-gate of the seventh transistor.

[0013] In some embodiments, the noise amplifier further includes: a first resistor connected between the first output terminal and the power supply; and a second resistor connected between the second output terminal and the power supply, wherein the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0014] In some embodiments, the noise amplifier further includes a fifth transistor, a sixth transistor, a first resistor, and a second resistor, wherein: the first poles of the fifth transistor and the sixth transistor are connected to the power supply; the second pole of the fifth transistor is connected to the first output terminal and is connected to the gate of the fifth transistor through the first resistor; and the second pole of the sixth transistor is connected to the second output terminal and is connected to the gate of the sixth transistor through the second resistor.

[0015] In some embodiments, the noise amplifier further includes: a fourth branch circuit connected between the second output terminal and the gate of the third transistor.

[0016] In some embodiments, the noise amplifier further includes: a fourth branch circuit connected between the first non-gate of the second transistor and the gate of the sixth transistor.

[0017] In some embodiments, the third branch circuit includes a third AC coupling capacitor.

[0018] In some embodiments, the fourth branch circuit includes a fourth AC coupling capacitor.

[0019] In some embodiments, the input terminal is grounded through a first bias resistor, and the second non-gate of the third transistor is grounded. In some embodiments, the second non-gate of the seventh transistor is grounded.

[0020] In some embodiments, the gates of the first transistor, the second transistor, and the fourth transistor are all connected to their respective bias voltages, and the gate of the third transistor is connected to its corresponding DC bias voltage through a second bias resistor. In some embodiments, the gate of the eighth transistor is connected to its bias voltage, and the gate of the seventh transistor is connected to its corresponding DC bias voltage through a third bias resistor.

[0021] A second aspect of the embodiments of the present application provides a wireless electronic device, including the low-noise amplifier in any of the foregoing embodiments.

[0022] In summary, the embodiments of the present application provide a low-noise amplifier and a wireless electronic device having the low-noise amplifier. The low-noise amplifier achieves the balance of differential output current signals while having low noise, high linearity, and low power consumption in a wide frequency band, and has the advantages of being easy to implement and occupying a small space. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings without creative efforts based on these drawings.

[0024] Figure 1 Shows a block diagram of a low-noise amplifier (LNA) according to an embodiment of the present application;

[0025] Figure 2 Shows a schematic diagram of the working principle of the LNA according to an embodiment of the present application;

[0026] Figure 3 The circuit schematic diagram of an LNA according to an embodiment of the present application is shown;

[0027] Figure 4 The circuit schematic diagram of an LNA according to another embodiment of the present application is shown;

[0028] Figure 5 The circuit schematic diagram of an LNA according to still another embodiment of the present application is shown;

[0029] Figure 6 The circuit schematic diagram of an LNA according to still another embodiment of the present application is shown; and

[0030] Figures 7A to 7F The simulation results of an LNA according to an embodiment of the present application are shown. Detailed implementation manners

[0031] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] As mentioned in the background art, currently, there is no effective method to balance noise, linearity, and power consumption with a simple and stable structure for an amplifier having an active balun. Although the common-gate common-source (CG-CS) amplifier structure has certain prospects, while increasing the amplifier gain and / or reducing the amplifier noise, the voltage detection circuit needs to provide more gain, and the matching circuit cannot change synchronously with the detection circuit due to the need to maintain input impedance matching, that is, there is a mismatch between the two branch circuits (i.e., the CG branch and the CS branch), ultimately resulting in problems such as common mode and nonlinearity in the output signal.

[0033] For this reason, the embodiments of the present invention provide a low-noise amplifier (LNA) that provides a balanced differential output signal for subsequent processing downstream of the amplifier without increasing system complexity and without affecting other performance requirements of the receiver.

[0034] Please refer to Figure 1 . Figure 1A structural block diagram of an LNA according to an embodiment of the present application is shown. In this embodiment, the LNA includes an input terminal IN, a first output terminal OUT1, and a second output terminal OUT2. In the embodiment of the present application, the input terminal IN is used to receive a single-ended voltage signal. The single-ended voltage signal may come from an element upstream of the LNA in a receive chain (i.e., an Rx chain, which can also be understood as a receive device including the LNA), such as an antenna or a preselection filter, etc. The first output terminal OUT1 and the second output terminal OUT2 are used to output a pair of differential current signals to complete the single-ended-to-differential (S2D) function of the LNA in the current output mode. The differential current signal can be processed by an element downstream of the LNA in the Rx chain, such as a channel selection filter or a mixer, etc. It can be understood that one of the first output terminal OUT1 and the second output terminal OUT2 is used to output a positive-polarity output signal, and the other is used to output a negative-polarity output signal. The embodiment of the present application does not specifically limit which of the two outputs the positive-polarity output signal and which outputs the negative-polarity output signal. The specific output manner can be determined by the specific elements used in the circuit.

[0035] Continue to refer to Figure 1 In the embodiment of the present application, the LNA further includes a first branch circuit 10, a second branch circuit 20, and a third branch circuit 30. Among them, the first branch circuit 10 is connected between the input terminal IN and the first output terminal OUT1, and the second branch circuit 20 is connected between the input terminal and the second output terminal OUT2. The second branch circuit 20 has an intermediate node N, and the third branch circuit 30 is connected between the intermediate node N and the first output terminal OUT1. It can be understood that the intermediate node N divides the second branch circuit 20 into a first sub-circuit 21 and a second sub-circuit 22, that is, the first sub-circuit 21 is connected between the input terminal IN and the intermediate node N, and the second sub-circuit 22 is connected between the intermediate node N and the second output terminal OUT2. In the embodiment of the present application, the form of the intermediate node N is not specifically limited. It can be any terminal, metal wire, interconnect layer, etc., as long as it can achieve electrical interconnection between the first sub-circuit 21, the second sub-circuit 22, and the third branch circuit 30. At the same time, the specific elements and circuit structures of the first branch circuit 10, the second branch circuit 20, and the third branch circuit 30 are not specifically limited in the embodiment of the present application, as long as they can achieve the functions corresponding to the respective branch circuits described below.

[0036] Please refer to Figure 1 on the basis of Figure 2 . Figure 2The schematic diagram of the working principle of the LNA according to an embodiment of the present application is shown. In the embodiment of the present application, the first branch circuit 10 is used to provide a first transconductance gain Gm1 between the input terminal IN and the output terminal OUT1, and the second branch circuit 20 is used to provide a second transconductance gain Gm2 between the input terminal IN and the output terminal OUT2. Among them, for the first sub-circuit 21 and the second sub-circuit 22, taking the intermediate node N as the dividing point, the second transconductance gain Gm2 can be divided into two parts: the first sub-transconductance gain Gm21 and the second sub-transconductance gain Gm22. In addition, the third branch circuit 30 is used to provide a third transconductance gain Gm3.

[0037] Since the third branch circuit 30 is connected between the intermediate node N and the first output terminal OUT1, a part of the transconductance gain of the second branch circuit 20 can be added to the first branch circuit 10 through the third branch circuit 30, so as to provide additional gain for the path between the input terminal IN and the first output terminal OUT1. Specifically, the transconductance gain of the first output terminal can be written as:

[0038] Gm out1 = Gm1 + (Gm21 / Gm22) × Gm3 (1)

[0039] The transconductance gain of the second output terminal is:

[0040] Gm out2 = Gm21 (2)

[0041] Therefore, when Gm1 is less than Gm21, by selecting appropriate components for the second sub-circuit 22 and the third branch circuit 30, the gain balance between the first output terminal OUT1 and the second output terminal OUT2 can be achieved, that is, Gm out1 = Gm out2 . By combining the above formulas (1) and (2), this balance can be derived as:

[0042] Gm3 = (Gm22 / Gm21) × (Gm21 - Gm1) (3)

[0043] In some embodiments, the first sub-transconductance gain Gm21 and the second sub-transconductance gain Gm22 can be made equal or approximate. For example, similar components can be provided for the first sub-circuit 21 and the second sub-circuit 22. In this application, no specific limitation is imposed on "similar" or "approximate" in terms of numerical values, and it can be adjusted according to actual requirements. For example, it can mean that one numerical value is within the range of ±3%, ±5%, ±10%, etc. of another numerical value. At the same time, those skilled in the art can also understand that "equal" or "equals" in this application does not limit to a strict mathematical equality relationship, and in actual technologies, it also covers an approximately equal or substantially equal relationship within a certain technical error or measurement tolerance range. Under the above conditions, the above formulas (1) and (3) are transformed into:

[0044] Gm out1 ≈Gm1 + Gm3 (4)

[0045] Gm3 = Gm21 - Gm1 (5)

[0046] That is, Gm22 similar to Gm21 can be selected, and Gm3 can be set as the difference between G21 and Gm1, so as to achieve gain balance between the first output terminal OUT1 and the second output terminal OUT2.

[0047] It is not difficult to see that in the embodiments of this application, the third branch circuit 30 is used to balance the transconductance gain of the first output terminal OUT1 and the transconductance gain of the second output terminal OUT2. At the same time, this balancing method does not require additional restrictions on the load at the output terminal, greatly improving the applicable range of the LNA.

[0048] It can be understood that, for the sake of clearly and concisely explaining the gist of the embodiments of this application, the specific structures of each branch circuit are not shown in detail in Figure 1 and Figure 2 , nor is the load condition at the output terminal shown, but these omitted contents do not affect those skilled in the art to understand the specific implementation manners of the foregoing embodiments based on the common general knowledge in the art. The details of the above embodiments will be further described below in conjunction with specific implementation manners.

[0049] Please refer to Figure 3 . Figure 3The circuit schematic diagram of an LNA according to an embodiment of the present application is shown. In some embodiments, the first branch circuit 10 includes a first transistor T1 and a second transistor T2, and the second branch circuit 20 includes a third transistor T3 and a fourth transistor T4. Among them, the first transistor T1 and the second transistor T2 are connected in series, that is, the first non-gate of the first transistor T1 is connected to the input terminal IN, the second non-gate of the first transistor T1 is linked to the first non-gate of the second transistor T2, and the second non-gate of the second transistor is connected to the first output terminal OUT1. The third transistor T3 and the fourth transistor T4 are connected in a cascode manner, that is, the gate of the third transistor T3 is connected to the input terminal IN through a first AC coupling capacitor C1, the first non-gate of the fourth transistor T4 is connected to the second output terminal OUT2, and the second non-gate of the fourth transistor T4 and the first non-gate of the third transistor T3 are connected to the intermediate node N. In this structure, the third transistor T3 and the first AC coupling capacitor C1 can be regarded as the first sub-circuit 21, and at the same time, the fourth transistor T4 can be regarded as the second sub-circuit 22.

[0050] In the present application, "non-gate" means one of the source or drain of a transistor, but is not limited to a specific one of the source or drain, as long as the first non-gate and the second non-gate refer to two different non-gates. Taking Figure 3 the structure shown as an example, the first non-gates of the first transistor T1 and the second transistor T2 can be the source, the second non-gates can be the drain, and at the same time, the first non-gates of the third transistor T3 and the fourth transistor T4 can be the drain, and the second non-gates can be the source.

[0051] In the present application, the transistor can be any type of transistor, including but not limited to bipolar junction transistor (BJT), junction field effect transistor (JFET), metal oxide semiconductor field effect transistor (MOSFET), fin field effect transistor (FinFET), gate-all-around field effect transistor (GAA-FET), nanowire field effect transistor, etc.

[0052] It can be understood that the first branch circuit 10 is not limited to the above-mentioned discrete dual-transistor structure (that is, T1 and T2). By selecting appropriate transistors, a single transistor can be used to replace the first transistor T1 and the second transistor T2, or more transistors can be used to replace the first transistor T1 and / or the second transistor T2. For example, the transconductance gain of the selected transistor is equivalent to the total transconductance gain of the first transistor T1 and the second transistor T2 connected in series.

[0053] In the foregoing structure, the gates of the first transistor T1 and the second transistor T2 in the first branch circuit 10 can be connected to corresponding bias voltages. This common-gate connection method can ensure the matching of the input impedance of the LNA. At the same time, the gate of the third transistor T3 in the second branch circuit 20 is directly connected to the input node IN through the first AC coupling capacitor C1, so that the second output terminal OUT2 can have an inverting gain (relative to the gain at the first output OUT1). Such a first branch circuit 10 and a second branch circuit 20 form an active Balun topology. Moreover, due to the presence of the second transistor T2 and the fourth transistor T4, the isolation between the two branch circuits is enhanced, and at the same time, their respective output impedances are also improved. Generally speaking, this structure can achieve the balance of differential output current signals while realizing low noise, high linearity, and low power consumption in a wide frequency band, and has the advantages of being easy to implement and occupying a small space, providing the possibility for a high-performance LNA.

[0054] Please continue to refer to Figure 3 。In some embodiments, the third branch circuit 30 includes a seventh transistor T7 and an eighth transistor T8. Similar to the second branch circuit, the seventh transistor T7 and the eighth transistor T8 are connected in a cascode manner, that is, the gate of the seventh transistor T7 is connected to the intermediate node N through the second AC coupling capacitor C2, the first non-gate of the eighth transistor T8 is connected to the first output terminal OUT1, and the second non-gate of the eighth transistor T8 is connected to the first non-gate of the seventh transistor T7. This structure causes a part of the current flowing through the second branch circuit 20 to be directed to the first output terminal OUT1 through the second AC coupling capacitor C2, the seventh transistor T7, and the eighth transistor T8, thereby achieving the balance of the transconductance gain at the two output terminals.

[0055] Specifically, in the foregoing active topology Balun, in order to increase the corresponding transconductance gain and obtain a small noise factor (NF), the second branch circuit 20 often selects components with a large transconductance. In contrast, the selection of components in the first branch circuit 10 can be determined according to specific circuit requirements. This difference will introduce a mismatch in phase and / or amplitude between the first output terminal OUT1 and the second output terminal OUT2. To solve this mismatch, we can start from the perspective of the load, that is, different load resistors can be provided for the first output terminal OUT1 and the second output terminal OUT2 to achieve the same output voltage. However, in practical applications, it is difficult to adopt the above design for an LNA operating in the current mode. For example, when the LNA needs to provide signals for a mixer downstream in the Rx chain, at this time, the first output terminal OUT1 and the second output terminal OUT2 need to provide balanced output currents for the relatively low impedance of the mixer, which will make the design of the output terminal load extremely complicated.

[0056] Therefore, by attaching a part of the transconductance of the second branch circuit 20 to the first branch circuit 10 through the seventh transistor T7 and the eighth transistor T8, the transconductance of the two output terminals can be balanced without affecting the load, while compensating for the amplitude and phase of the output current. At the same time, since this solution can keep the load resistances of the first output terminal OUT1 and the second output terminal OUT2 the same, the balanced output current signal can improve the overall linear characteristics of the Rx chain while still maintaining the advantages of the active Balun topology in terms of high gain and low noise.

[0057] Continue to refer to Figure 3 。In some embodiments, the LNA further includes a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the first output terminal OUT1 and the power supply VDD, and the second resistor R2 is connected between the second output terminal OUT2 and the power supply VDD. To provide sufficient current to drive the downstream components of the LNA in the Rx chain, the resistance values of the first resistor R1 and the second resistor R2 are relatively small here. In some embodiments, the resistance values of the first resistor R1 and the second resistor R2 are equal.

[0058] Please refer to Figure 4 。 Figure 4 FIG. shows a circuit schematic diagram of an LNA according to another embodiment of the present application. Compared with the structure in Figure 3 ,the main difference in the structure in Figure 4 lies in the design of the output terminal load. Different from directly using the first resistor R1 and the second resistor R2 as the loads between the two output terminals and the power supply as described above, in some embodiments, the load of the first output terminal OUT1 includes a fifth transistor T5 and a first resistor R1, and the load of the second output terminal OUT2 includes a sixth transistor T6. The first pole of the fifth transistor T5 is connected to the power supply VDD, the second pole is connected to the first output terminal OUT1, and the gate is connected to its second pole through the first resistor R1. Similarly, the first pole of the sixth transistor T6 is connected to the power supply VDD, the second pole is connected to the second output terminal OUT2, and the gate is connected to its second pole through the second resistor R2. It can be understood that for both the fifth transistor T5 and the sixth transistor T6, their first and second poles are non-gate poles.

[0059] The above transistor-based load structure can stabilize the power supply at the output terminal at a level that is different from the power supply by a gate-source voltage threshold, and the output impedance will depend on the source-drain impedance of the transistor. Compared with Figure 3Compared with the structure in the load structure, this load structure can provide a higher output impedance for driving the downstream components of the Rx chain, and can also provide a wider output voltage swing. At the same time, due to the increase in impedance, the noise in the current output signal is smaller, the driving ability of the LNA to the downstream components is improved, and it also prevents part of the output current signal from flowing into the signal ground through the parasitic effect on the ground. Overall, this structure improves the gain of the entire Rx chain and reduces the NF.

[0060] Please refer to Figure 5 . Figure 5 FIG. 4 shows a circuit diagram of an LNA according to another embodiment of the present application. Figure 4 Compared with the structure in Figure 5 One difference between the structures in FIG. 1 and FIG. 2 is the structure of the third branch circuit 30. In some embodiments, the third branch circuit includes a third AC coupling capacitor C3. That is, Figure 4 The second AC coupling capacitor C2, the fifth transistor T5 and the sixth transistor T6 in the LNA circuit can be simplified to the third AC coupling capacitor C3. At this time, the third branch circuit 30 directly uses the fifth transistor 50 to achieve the purpose of guiding part of the transconductance gain of the second branch circuit 20 to the first output terminal OUT1, thereby simplifying the LNA circuit structure and providing similar functions.

[0061] In addition, Figure 4 Compared with the structure in Figure 5 Another difference of the structure is that an additional fourth branch circuit is provided. In some embodiments, the LNA further includes a fourth branch circuit, which is connected between the second output terminal OUT2 and the gate of the third transistor T3. This structure can also increase the transconductance of the sixth transistor T6 to the second output terminal OUT2, thereby providing a higher gain.

[0062] The above two differences can be respectively applied to the LNA provided in the embodiment of the present application. Figure 4 Based on the structure shown in FIG. 1 , the third branch circuit 30 can be simplified to the third AC coupling capacitor C3 without adding the fourth branch circuit. Figure 4 The same third branch circuit 30 is added with a fourth branch circuit at the same time, and the third branch circuit 30 can also be simplified into a third AC coupling capacitor C3 and a fourth branch circuit. In any of the above cases, the transistor as the output load also plays the role of increasing the output transconductance. This structure can reduce the noise introduced by the transistor itself, and partially compensate for the impact of replacing the pure resistive load with a transistor. At the same time, since the transistor in the load has the same bias current as the transistor in the corresponding branch circuit (for example, the fifth transistor T5 and the first transistor T1 and the second transistor T2 in the first branch circuit 10), this solution can also reduce the energy consumption of the LNA.

[0063] In the above solution, by selecting appropriate fifth transistor T5 and sixth transistor T6, the amplitude and phase difference between the first output terminal OUT1 and the second output terminal OUT2 can be minimized. When the parameters of the fifth transistor T5 and the sixth transistor T6 are similar, the scheme of simplifying the third branch circuit 30 into the third AC coupling capacitor C3 and adding the fourth branch circuit at the same time maximally balances the differential output currents at the first output terminal OUT1 and the second output terminal OUT2, so a relatively more ideal LNA can be obtained.

[0064] Please refer to Figure 6 . Figure 6 Fig. shows a circuit schematic diagram of an LNA according to another embodiment of the present application. Compared with the structure in Figure 5 , Figure 6 the difference in the structure in

[0065] lies in the connection manner of the fourth branch circuit. In some embodiments, the fourth branch circuit is connected between the first non-gate of the second transistor T2 and the gate of the sixth transistor T6. That is to say, the fourth branch circuit can be connected between the common node M between the first transistor T1 and the second transistor T2 and the gate of the sixth transistor T6. Figure 5 In Figure 6 the connection manner of the fourth branch circuit and the third branch circuit 30 in this solution is symmetrically arranged. Compared with the structure in

[0066] It can be understood that Figure 5 and Figure 6 provide two mutually replaceable connection manners of the fourth branch circuit. Therefore, Figure 6 the fourth branch circuit in Figure 4 can also be freely combined with the structures of the two third branch circuits 30 shown in Figure 5 . In some embodiments, the aforementioned fourth branch circuit may include a fourth AC coupling capacitor C4. Therefore, the fourth branch circuit only needs simple AC-DC isolation to be realized.

[0067] In the embodiments of the present application, since the differential output signals of the first output terminal OUT1 and the second output terminal OUT2 have good balance characteristics in terms of phase and amplitude, the linear characteristics of the entire Rx chain will also be improved. At this time, by means of techniques such as noise reduction, distortion removal, current reuse, and adaptive adjustment of the output signal, the noise in the output signal and the power consumption of the LNA can be minimized. In addition, whether it is Figure 5 or Figure 6 For the structures shown in, the fourth branch circuit can enable the LNA of the embodiments of the present application to break the problem that the traditional structure must make a trade-off among noise, linearity, and power consumption, and obtain good output performance while achieving the balance of the differential output signal.

[0068] The balance characteristics of the differential output signals of the first output terminal OUT1 and the second output terminal OUT2 can be achieved by conditioning the output terminal load and the components in each branch circuit. Taking Figure 6 the structure shown in as an example, the gains of the first output terminal OUT1 and the second output terminal OUT2 can be obtained by the following formula:

[0069] Gm out1 = Gm T1 + (Gm T3 / Gm T4 ) × Gm T5 (6)

[0070] Gm out2 = Gm 13 + (Gm T1 / Gm T2 ) × Gm T6 (7)

[0071] Where Gm out1 and Gm out2 respectively represent the transconductance gains at the first output terminal OUT1 and the second output terminal OUT2, and Gm T1 to Gm T6 respectively represent the transconductance gains of the first transistor T1 to the sixth transistor T6. In some embodiments, the first transistor T1 and the second transistor T2 may have the same or similar parameters, and the third transistor T3 and the fourth transistor T4 may have the same or similar parameters. At this time, the above formulas (6) and (7) can be simplified as:

[0072] Gm out1 ≈ Gm T1 + Gm T5 (8)

[0073] Gm out2 ≈ Gm T3 + Gm T6 (9)

[0074] That is, for the first branch circuit 10 and the second branch circuit 20, at this time, by keeping the sum of the gains of their respective front-end transistors and corresponding load transistors equal, the balance of the differential output signal can be achieved.

[0075] It can be understood that the embodiments of the present application do not specifically limit the types of each transistor, as long as it can achieve the above functions. Taking the above Figures 3 to 6 corresponding embodiments as examples, in some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 can be set as N-type transistors (for example, n-channel MOSFETs), and the fifth transistor T5 and the sixth transistor T6 can be set as P-type transistors (for example, p-channel MOSFETs). At this time, the first output terminal OUT1 can output a positive-phase signal, and correspondingly, the second output terminal OUT2 outputs an inverted-phase signal. In other embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 can be set as P-type transistors (for example, p-channel MOSFETs), and the fifth transistor T5 and the sixth transistor T6 can be set as N-type transistors (for example, n-channel MOSFETs). At this time, the second output terminal OUT2 can output a positive-phase signal, and correspondingly, the first output terminal OUT1 outputs an inverted-phase signal.

[0076] The biasing and grounding conditions of each element in the embodiments of the present application are briefly described below to enhance the understanding of the above various embodiments. Those skilled in the art can also adjust the grounding and biasing settings according to actual needs.

[0077] In some embodiments, the input terminal OUT1 is grounded through the first bias resistor R1 bias and the second non-gate of the third transistor T3 is grounded. If there is a seventh transistor T7, its second non-gate is grounded. It can be understood that in the embodiments of the present application, grounding means that the corresponding terminal is connected to a wire, terminal, or other conductor with a reference potential of zero.

[0078] In some embodiments, the gate of the first transistor T1 is connected to the first bias voltage Bias1, the gate of the second transistor T2 is connected to the second bias voltage Bias2, and the gate of the fourth transistor T4 is connected to the third bias voltage Bias4. If there is an eighth transistor T8, its gate is connected to the fourth bias voltage Bias8. In the embodiments of the present application, the bias voltage of each transistor is determined by the type of the corresponding transistor. It can be understood that the above bias voltages can adopt the same voltage or different voltages.

[0079] In some embodiments, the gate of the third transistor is connected to the first DC bias voltage DC Bias1 through the second bias resistor R2 bias If there is a seventh transistor T7, its gate is connected to the second DC bias voltage DC Bias2 through the third bias resistor R3 bias Similar to the foregoing embodiments, grounding means that the corresponding terminal is connected to a wire, terminal, or other conductor with a reference potential of zero, and the bias resistors and DC biases of each transistor are determined by the type of the corresponding transistor. In some embodiments, the foregoing DC bias voltages may be the same or different, and at the same time, the foregoing bias resistors may be the same or different.

[0080] In the embodiments of the present application, the functional elements in the LNA may not include inductive elements, thereby greatly reducing the space occupied by the LNA. In addition, the LNA structure in the embodiments of the present application can be easily integrated with the existing structure and adapted to a variety of existing processes. For example, the LNA in the embodiments of the present application can be combined with bulk CMOS, Silicon-on-insulator (SOI), BJT, FinFET and other processes.

[0081] Please refer to Figures 7A to 7F .. Figures 7A to 7F shows the simulation results of the LNA according to an embodiment of the present application, where Figure 7A shows the third-order input intercept point (IIP3) of the LNA, Figure 7B shows the NF of the LNA, Figure 7C shows the transconductance gain of the differential output of the two output terminals of the LNA, Figure 7D shows the gain error of the differential output of the LNA, Figure 7E shows the phase error of the differential output of the LNA, Figure 7F shows the return loss (S11) of the LNA. In this embodiment, the structure of the LNA can be referred to Figure 6 as shown. The simulation frequency range is for the frequency band from 0.7 GHz to 2.7 GHz, and this frequency band corresponds to the low frequency band (LB) to the medium high frequency band (MHB), where Gm1 and Gm2 respectively represent the transconductance gains at the first output terminal OUT1 and the second output terminal OUT2. In addition, for the test of the linear characteristic (IIP3), a two-tone signal with a 1 MHz difference from the carrier frequency is used, and the simulation input impedance of the LNA is set to 50 Ω.

[0082] As can be seen from the simulation results, the IIP3 of the LNA remains above 13 dBm throughout the frequency band, and has a very flat NF value (between 5.4 dB and 5.6 dB). At the same time, the transconductance gains of the two differential output terminals are almost the same, the gain error does not exceed 0.35 dB, and the phase error does not exceed 1.7 degrees. The return loss of the LNA is controlled below -10 dB. It is not difficult to see that this structure has very ideal performance in terms of noise, linearity, and differential output signal balance.

[0083] Another aspect of the embodiments of the present application further provides a wireless electronic device. The wireless electronic device includes the LNA in any of the foregoing embodiments. Therefore, the wireless electronic device can also achieve the corresponding technical effects of the foregoing embodiments. It can be understood that the wireless electronic device includes an Rx chain, and the LNA is a part of the Rx chain, which amplifies the signaler and is used to implement the S2D function. In some embodiments, the wireless electronic device may include a receiver or a transceiver, or may include an integrated circuit having a receiver circuit or a transceiver circuit, and the LNA may be a part of the receiver, transceiver, receiver circuit, or transceiver circuit. The embodiments of the present application do not limit the specific form of the wireless electronic device, as long as it can implement the function of receiving wireless signals.

[0084] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the electronic device disclosed in the embodiments, since it corresponds to the LNA disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description of the LNA-related parts.

[0085] It should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0086] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low noise amplifier, comprising an input terminal, a first output terminal and a second output terminal, characterized in that: Also includes: a first branch circuit connected between the input terminal and the first output terminal; a second branch circuit connected between the input terminal and the second output terminal; as well as a third branch circuit connected between an intermediate node in the second branch circuit and the first output terminal; The input end is used to receive a single-ended voltage signal, the first output end and the second output end are used to output a pair of differential current signals, and the third branch circuit is used to balance the transconductance gain of the first output end and the transconductance gain of the second output end.

2. The low noise amplifier according to claim 1, characterized in that: The intermediate node divides the second branch circuit into a first sub-circuit and a second sub-circuit; The first branch circuit is used to provide a first transconductance gain between the input terminal and the first output terminal; The second branch circuit is used to provide a second transconductance gain between the input terminal and the second output terminal, wherein the first sub-circuit is used to provide a first sub-transconductance gain between the input terminal and the intermediate node, the second sub-circuit is used to provide a second sub-transconductance gain between the intermediate node and the second output terminal, and the second transconductance gain is the sum of the first sub-transconductance gain and the second sub-transconductance gain; The third branch circuit is used to provide a third transconductance gain between the intermediate node and the first input terminal; and The first sub-transconductance gain is equal to the second sub-transconductance gain, and the third transconductance gain is equal to a difference between the first sub-transconductance gain and the first transconductance gain.

3. The low noise amplifier according to claim 1 or 2, characterized in that: The first branch circuit includes a first transistor and a second transistor, wherein a first non-gate of the first transistor is connected to the input terminal, a second non-gate of the first transistor is connected to a first non-gate of the second transistor, and a second non-gate of the second transistor is connected to the first output terminal.

4. The low noise amplifier according to claim 3, characterized in that: The second branch circuit includes a third transistor and a fourth transistor, the gate of the third transistor is connected to the input terminal through a first AC coupling capacitor, the first non-gate of the fourth transistor is connected to the second output terminal, and the second non-gate of the fourth transistor and the first non-gate of the third transistor are connected to the intermediate node.

5. The low noise amplifier according to claim 4, characterized in that: The third branch circuit includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected to the intermediate node through a second AC coupling capacitor, the first non-gate of the eighth transistor is connected to the first output terminal, and the second non-gate of the eighth transistor is connected to the first non-gate of the seventh transistor.

6. The low noise amplifier according to claim 5, characterized in that: Also includes a fifth transistor, a sixth transistor, a first resistor and a second resistor, wherein: The first electrode of the fifth transistor and the first electrode of the sixth transistor are connected to a power supply; The second electrode of the fifth transistor is connected to the first output terminal and is connected to the gate of the fifth transistor through the first resistor; and, The second electrode of the sixth transistor is connected to the second output terminal, and is connected to the gate of the sixth transistor through the second resistor.

7. The low noise amplifier according to claim 6, characterized in that: Also includes: a fourth branch circuit connected between the second output terminal and the gate of the third transistor, or A fourth branch circuit is connected between the first non-gate of the second transistor and the gate of the sixth transistor.

8. The low noise amplifier according to any one of claim 7, characterized in that: The third branch circuit includes a third AC coupling capacitor, and / or The fourth branch circuit includes a fourth AC coupling capacitor.

9. The low noise amplifier according to claim 4, characterized in that: The input terminal is grounded via a first bias resistor, and the second non-gate of the third transistor is grounded; and / or The gate of the first transistor, the gate of the second transistor and the gate of the fourth transistor are all connected to respective bias voltages, and the gate of the third transistor is connected to a direct current bias voltage through a second bias resistor.

10. A wireless electronic device, characterized in that: Comprising a low noise amplifier according to any one of claims 1 to 9.

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