Clock signal delay control circuit
By designing a clock signal delay control circuit including operational amplifiers, MOS tubes and other components, the offset detection and pulse width detection units are used to solve the problems of edge alignment and pulse width differences between clock signals at different load receiving ends, and the stability and consistency of clock signals are achieved.
Patent Information
- Application Number
- CN202510653132.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-21
- Publication Date
- 2025-06-20
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The existing clock signal delay control circuit cannot effectively align the clock signal edges at different load receiving ends, and the pulse width difference caused by path or impedance differences is difficult to eliminate.
A clock signal delay control circuit including an operational amplifier, MOS tube, capacitor, resistor, connector, diode and flip-flop is designed to detect and adjust the clock signal to align the edges of the receiving ends of different loads and eliminate pulse width differences caused by path or impedance differences.
Effective alignment of the edges of clock signals at different load receiving ends is achieved, and pulse width differences caused by path or impedance differences are prevented, ensuring the stability and consistency of clock signals.
Smart Images
Figure CN120185586A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of signal control, and particularly relates to a control circuit for clock signal delay. Background Art
[0002] Patent CN118900118A discloses a control circuit for clock signal delay. This circuit aligns the clock signal edges at the two receiving ends of a single load by setting two groups of variable delay lines and a calibration circuit. However, different physical path lengths or impedance differences will not only cause edge offsets, but also affect the slopes of the rising edge / falling edge, ultimately resulting in pulse width differences of the clock signal obtained by different load receiving ends. Therefore, a control circuit for clock signal delay is proposed, which can align the clock signal edges at different load receiving ends and prevent pulse width differences of the clock signal obtained by different load receiving ends due to path or impedance differences. Summary of the Invention
[0003] In view of the above technical problems, the object of the present invention is to provide a control circuit for clock signal delay, including a plurality of operational amplifiers, a plurality of MOS transistors, a plurality of capacitors, a plurality of resistors, a plurality of connectors, a plurality of diodes, and a flip-flop. The non-inverting input terminal of operational amplifier U1 among the plurality of operational amplifiers is connected to one end of capacitor C1 and the cathode of diode D2, and the inverting input terminal is connected to one end of resistor R1 and one end of resistor R2; the non-inverting input terminal of operational amplifier U6 is connected to the fifth pin of flip-flop U5, the inverting input terminal is connected to one end of resistor R20 and one end of resistor R21, and the output terminal is connected to the other end of resistor R20 and the gate of MOS transistor Q1; the drain of MOS transistor Q1 is connected to terminal P1 of the connector, and the source is connected to one end of resistor R4 and one end of resistor R5; the first pin and the fourth pin of flip-flop U5 are connected, the second pin and the sixth pin are connected, the third pin is connected to one end of resistor R14 and terminal P3 of the connector, and the fourteenth pin, the other end of resistor R2 and the power supply are connected; the anode of diode D2 is connected to the other end of resistor R4; the other end of capacitor C1, the other end of resistor R1, the other end of resistor R5, the other end of resistor R14, the other end of resistor R21, the seventh pin of flip-flop U5 and the ground terminal are connected.
[0004] Further, the non-inverting input terminal of operational amplifier U2 among the plurality of operational amplifiers is connected to terminal P2 of the connector, and the inverting input terminal is connected to the cathode of diode D1 and one end of capacitor C2; the gate of MOS transistor Q2 is connected to the output terminal of operational amplifier U1, the drain is connected to terminal P1 of the connector, and the source is connected to one end of resistor R3 and one end of resistor R6; the anode of diode D1 is connected to the other end of resistor R3; the other end of capacitor C2 and the other end of resistor R6 are connected to the ground terminal.
[0005] Further, the gate of MOS transistor Q3 among the several MOS transistors is connected to the gate of MOS transistor Q2, the drain is connected to one end of resistor R7 and one end of resistor R8, and the source is connected to one end of resistor R15 and the terminal of connector P4; the other end of resistor R7 is connected to the output terminal of operational amplifier U2; the other ends of resistor R8 and resistor R15 are connected to the ground terminal.
[0006] Further, the non-inverting terminal of operational amplifier U3 among the several operational amplifiers is connected to the terminal of connector P4, the inverting terminal is connected to one end of resistor R9 and one end of resistor R16, and the output terminal is connected to the gate of MOS transistor Q4 and the other end of resistor R16; the source of MOS transistor Q4 is connected to one end of resistor R12 and one end of capacitor C3, and the drain is connected to one end of resistor R10; the other end of resistor R10 is connected to the power supply; the other end of capacitor C3, the other end of resistor R9, and the other end of resistor R12 are connected to the ground terminal.
[0007] Further, the non-inverting terminal of operational amplifier U4 among the several operational amplifiers is connected to one end of resistor R11 and the drain of MOS transistor Q5, and the inverting terminal is connected to one end of resistor R18 and one end of resistor R19; the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source is connected to one end of capacitor C3; the other end of resistor R19 is connected to the power supply; the other ends of resistor R11 and resistor R18 are connected to the ground terminal.
[0008] Further, the cathode of diode D3 among the several diodes is connected to the terminal of connector P3, and the anode is connected to the output terminal of operational amplifier U4, the gate of MOS transistor Q6, and the gate of MOS transistor Q7; the drain of MOS transistor Q6 is connected to one end of capacitor C1; the drain of MOS transistor Q7 is connected to one end of capacitor C2; the sources of MOS transistor Q6 and MOS transistor Q7 are connected to the ground terminal.
[0009] Further, one end of resistor R17 among the several resistors is connected to the gate of MOS transistor Q2, and the other end is connected to the ground terminal.
[0010] Further, one end of resistor R13 among the several resistors is connected to the gate of MOS transistor Q1, and the other end is connected to the ground terminal.
[0011] The beneficial effects of the present invention compared with the prior art are as follows: The present invention can align the clock signal edges of different load receivers, and at the same time can prevent the pulse width difference when different load receivers obtain the clock signal due to path or impedance differences. Description of the Drawings
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required in the prior art and the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0013] Figure 1 The circuit structure diagram provided by the present invention. Specific embodiments
[0014] In order to make the purpose and advantages of the present invention more clear, the following specifically describes the present invention in combination with embodiments. It should be understood that the following text is only used to describe one or several specific implementation manners of the present invention, and does not strictly limit the scope of protection of the specific claims of the present invention.
[0015] The present invention discloses a control circuit for clock signal delay, including a plurality of operational amplifiers, a plurality of MOS transistors, a plurality of capacitors, a plurality of resistors, a plurality of connectors, a plurality of diodes, and flip-flops; the plurality of operational amplifiers include operational amplifier U1 and operational amplifier U6; the plurality of MOS transistors include MOS transistor Q1; the plurality of capacitors include capacitor C1; the plurality of resistors include resistor R1, resistor R2, resistor R4, resistor R5, resistor R14, resistor R20, resistor R21; the plurality of connectors include connector P1 and connector P3; the plurality of diodes include diode D2; Specifically, the non-inverting terminal of operational amplifier U1 in the plurality of operational amplifiers is connected to one end of capacitor C1 and the cathode of diode D2, and the inverting terminal is connected to one end of resistor R1 and one end of resistor R2; the non-inverting terminal of operational amplifier U6 is connected to the fifth pin of flip-flop U5, the inverting terminal is connected to one end of resistor R20 and one end of resistor R21, and the output terminal is connected to the other end of resistor R20 and the gate of MOS transistor Q1; the drain of MOS transistor Q1 is connected to the terminal of connector P1, and the source is connected to one end of resistor R4 and one end of resistor R5; the first pin and the fourth pin of flip-flop U5 are connected, the second pin and the sixth pin are connected, the third pin is connected to one end of resistor R14 and the terminal of connector P3, the fourteenth pin, the other end of resistor R2 and the power supply are connected; the anode of diode D2 is connected to the other end of resistor R4; the other end of capacitor C1, the other end of resistor R1, the other end of resistor R5, the other end of resistor R14, the other end of resistor R21, the seventh pin of flip-flop U5 and the ground terminal are connected.
[0016] Specifically, the several resistors further include resistor R3 and resistor R6; the non-inverting input terminal of operational amplifier U2 among the several operational amplifiers is connected to terminal P2 of the several connectors, and the inverting input terminal is connected to the cathode of diode D1 among the several diodes and one end of capacitor C2 among the several capacitors; the gate of MOS transistor Q2 among the several MOS transistors is connected to the output terminal of operational amplifier U1, the drain is connected to terminal P1 of the connector, and the source is connected to one end of resistor R3 and one end of resistor R6; the anode of diode D1 is connected to the other end of resistor R3; the other end of capacitor C2 and the other end of resistor R6 are connected to the ground terminal.
[0017] Specifically, the several resistors further include resistor R7, resistor R8, and resistor R15; the gate of MOS transistor Q3 among the several MOS transistors is connected to the gate of MOS transistor Q2, the drain is connected to one end of resistor R7 and one end of resistor R8, and the source is connected to one end of resistor R15 and terminal P4 of the several connectors; the other end of resistor R7 is connected to the output terminal of operational amplifier U2; the other ends of resistor R8 and resistor R15 are connected to the ground terminal.
[0018] Specifically, the several resistors further include resistor R9, resistor R10, resistor R12, and resistor R16; the non-inverting input terminal of operational amplifier U3 among the several operational amplifiers is connected to terminal P4 of the connector, the inverting input terminal is connected to one end of resistor R9 and one end of resistor R16, and the output terminal is connected to the gate of MOS transistor Q4 among the several MOS transistors and the other end of resistor R16; the source of MOS transistor Q4 is connected to one end of resistor R12 and one end of capacitor C3 among the several capacitors, and the drain is connected to one end of resistor R10; the other end of resistor R10 is connected to the power supply; the other end of capacitor C3, the other end of resistor R9, and the other end of resistor R12 are connected to the ground terminal.
[0019] Specifically, the several resistors further include resistor R11, resistor R18, and resistor R19; the non-inverting input terminal of operational amplifier U4 among the several operational amplifiers is connected to the other end of resistor R11 and the drain of MOS transistor Q5 among the several MOS transistors, and the inverting input terminal is connected to one end of resistor R18 and one end of resistor R19; the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source is connected to one end of capacitor C3; the other end of resistor R19 is connected to the power supply; the other ends of resistor R11 and resistor R18 are connected to the ground terminal.
[0020] Specifically, the cathode of diode D3 among the several diodes is connected to terminal P3 of the connector, and the anode is connected to the output terminal of operational amplifier U4, the gate of MOS transistor Q6 among the several MOS transistors, and the gate of MOS transistor Q7 among the several MOS transistors; the drain of MOS transistor Q6 is connected to one end of capacitor C1; the drain of MOS transistor Q7 is connected to one end of capacitor C2; the sources of MOS transistor Q6 and MOS transistor Q7 are connected to the ground terminal.
[0021] Specifically, one end of resistor R17 among the several resistors is connected to the gate of MOS transistor Q2, and the other end is connected to the ground terminal.
[0022] Specifically, one end of resistor R13 among the several resistors is connected to the gate of MOS transistor Q1, and the other end is connected to the ground terminal.
[0023] Refer to the appendix Figure 1 In the control circuit, an offset detection unit is provided. The offset detection unit is used to detect the offset amount when the two load receiving ends obtain the clock signal. The clock signal source synchronously feeds back the clock signal to the two load receiving ends. This signal reaches the load receiving ends through their respective physical paths. At this time, the receiving end signal is at the rising edge. The offset detection unit detects and records the rising edges of the clock signals obtained by the two load receiving ends. The receiving end that is the first to be at the rising edge is the calibration end, and the other is the matching end. After the detection is completed, the offset detection unit restricts the clock signal source from feeding back the clock signal to the calibration end. Then, the clock signal source synchronously feeds back the clock signal to the matching end and the connector P3 in the control circuit. The signal at the connector P3 end is fed back to pin 3 of flip-flop U5. In the initial state, pin 5 of flip-flop U5 is at a low level and pin 6 is at a high level. When the clock signal is at the rising edge, the levels of pins 5 and 6 of flip-flop U5 are swapped. The output end of operational amplifier U6, resistor R20, and resistor R21 form a signal loop. The signal at the resistor R21 end is fed back to the inverting end of operational amplifier U6. Operational amplifier U6 outputs saturated. The signal at the output end of operational amplifier U6 is fed back to the gate of MOS transistor Q1. Resistor R13 is used to discharge the parasitic capacitance of the gate of MOS transistor Q1. The voltage difference between the gate and the source of MOS transistor Q1 is higher than the conduction threshold, and MOS transistor Q1 conducts. Connector P1 is used to obtain the power signal of the pulse width detection unit. When MOS transistor Q1 conducts, the signal at connector P1 passes through the drain of MOS transistor Q1, the source of MOS transistor Q1, and resistor R5 to the ground terminal. The signal at the resistor R5 end makes the potential of the capacitor C1 start to rise after passing through resistor R4 and diode D2. The power signal passes through resistor R2 and resistor R1 to the ground terminal. The signal at the resistor R1 end is the delay reference signal of the clock signal and can be changed by adjusting the resistance value of resistor R1. When the potential of the capacitor C1 rises to slightly higher than the potential of the resistor R1 end, operational amplifier U1 outputs. The signal at the output end of operational amplifier U1 is fed back to the calibration end through the physical path. The offset detection unit repeatedly adjusts the resistance value of resistor R1 to make operational amplifier U1 output with a delay to align the edges of the two load receiving ends, thereby eliminating the edge offset caused by the path difference.
[0024] The signal at the output terminal of the operational amplifier U1 is fed back to the gate of the MOS transistor Q2. When the operational amplifier U1 outputs a signal, the voltage difference between the gate and the source of the MOS transistor Q2 is higher than the conduction threshold, and the MOS transistor Q2 conducts. The signal of the connector P1 passes through the drain, source of the MOS transistor Q2, and the resistor R6 to the ground terminal. The signal at the resistor R6 terminal causes the potential of the capacitor C2 to rise after passing through the resistor R3 and the diode D1. There is a pulse width detection unit in the control circuit, which is used to detect the pulse width of the clock signal obtained at the matching terminal. There is a detection capacitor in the pulse width detection unit, and the power supply signal for charging the capacitor is provided by the pulse width detection unit. This power supply signal is synchronously fed back to the control circuit. When the clock signal fed back by the clock signal source is at the rising edge, the detection capacitor charges; when the clock signal is at the falling edge, the detection capacitor stops charging. At this time, the potential amplitude of the detection capacitor is the pulse width amplitude of the clock signal at the calibration terminal. The pulse width detection unit records this signal and feeds it back to the connector P2. By adjusting the resistance values of the resistors R3 and R6 and the capacitance value of the capacitor C2, the charging speed of the capacitor C2 is made consistent with the charging speed of the detection capacitor in the pulse width detection unit. The signal at the capacitor C2 terminal is fed back to the inverting terminal of the operational amplifier U2, and the signal of the connector P2 is fed back to the non-inverting terminal of the operational amplifier U2. When the signal amplitude at the capacitor C2 terminal is slightly higher than the signal amplitude at the connector P2 terminal, the operational amplifier U2 is cut off. The signal at the output terminal of the operational amplifier U2 passes through the resistors R7 and R8 to the ground terminal. The signal at the output terminal of the operational amplifier U1 is fed back to the gate of the MOS transistor Q3. The resistor R17 is used to discharge the parasitic capacitance between the gates of the MOS transistors Q3 and Q2. When the operational amplifier U1 outputs a signal, the voltage difference between the gate and the source of the MOS transistor Q3 is higher than the conduction threshold, and the MOS transistor Q3 conducts. The signal at the resistor R8 terminal passes through the drain, source of the MOS transistor Q3, and the resistor R15 to the ground terminal. The signal at the resistor R15 terminal is fed back to the calibration terminal through the connector P4. By adjusting the resistance value of the resistor R8, the level of the delayed clock signal is made consistent with the pulse width and level of the clock signal obtained in real time at the matching terminal. The signal at the connector P4 terminal is the delayed clock signal. Based on this, a new clock signal is generated based on the pulse width and level of the clock signal obtained in real time at the matching terminal and fed back to prevent the pulse width difference of the clock signal obtained by different load receiving ends due to path or impedance differences (the slope of the rising edge / falling edge).
[0025] The signal at the 15 - end of resistor R1 is synchronously fed back to the non - inverting input terminal of operational amplifier U3. The output terminal of operational amplifier U3, resistor R16, and resistor R9 form a signal loop. The signal at the end of resistor R9 is fed back to the inverting input terminal of operational amplifier U3. When the delayed clock signal is at a high level, operational amplifier U3 saturates and outputs. The signal at the output terminal of operational amplifier U3 is fed back to the gates of MOS transistors Q4 and Q5. When operational amplifier U3 outputs, the voltage difference between the gate and source of MOS transistor Q4 is higher than the conduction threshold, MOS transistor Q4 conducts, and the voltage difference between the gate and source of MOS transistor Q5 is higher than the conduction threshold, MOS transistor Q5 cuts off. The power supply signal passes through resistor R10, the drain of MOS transistor Q4, the source of MOS transistor Q4, and resistor R12 to the ground terminal. At the same time, the potential of capacitor C3 starts to rise. When the delayed clock signal is at a low level, MOS transistor Q4 cuts off, MOS transistor Q5 conducts, the potential of capacitor C3 drops, and the signal at the end of capacitor C3 is fed back to the non - inverting input terminal of operational amplifier U4 through the source and drain of MOS transistor Q5. Resistor R11 is a pull - down resistor for the non - inverting input terminal of operational amplifier U4. Operational amplifier U4 outputs. The signal at the output terminal of operational amplifier U4 is fed back to pin 3 of flip - flop U5 through diode D3. The levels of pins 5 and 6 of flip - flop U5 are replaced again. At the same time, the signal at the output terminal of operational amplifier U4 is synchronously fed back to the gates of MOS transistors Q6 and Q7. The voltage differences between the gates and sources of MOS transistors Q6 and Q7 are higher than the conduction threshold, MOS transistor Q6 conducts, MOS transistor Q7 conducts. The signal at the end of capacitor C1 passes through the drain and source of MOS transistor Q6 to the ground terminal, the potential of the end of capacitor C1 to the ground, the signal at the end of capacitor C2 passes through the drain and source of MOS transistor Q7 to the ground terminal, the signal at the end of capacitor C2 to the ground potential, the power supply signal passes through resistor R19 and resistor R18 to the ground terminal. The signal at the end of resistor R18 is the reference signal. When the signal at the end of capacitor C3 is lower than the reference signal, operational amplifier U4 cuts off.
[0026] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above - mentioned exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non - restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.
Claims
1. A control circuit for clock signal delay, characterized in that: The invention comprises a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of capacitors, a plurality of resistors, a plurality of connectors, a plurality of diodes and triggers. The operational amplifier U1 in the plurality of operational amplifiers has a non-inverting end connected to one end of the capacitor C1 and a cathode of the diode D2, and an inverting end connected to one end of the resistor R1 and one end of the resistor R2; the non-inverting end of the operational amplifier U6 is connected to the fifth pin of the trigger U5, the inverting end is connected to one end of the resistor R20 and one end of the resistor R21, and the output end is connected to the other end of the resistor R20 and the gate of the MOS tube Q1; the drain of the MOS tube Q1 is connected to the end of the connector P1, and the source is connected to one end of the resistor R4 and one end of the resistor R5; the first pin of the trigger U5 is connected to the fourth pin, the second pin is connected to the sixth pin, the third pin is connected to one end of the resistor R14 and the end of the connector P3, and the fourteenth pin and the other end of the resistor R2 are connected to the power supply; the anode of the diode D2 is connected to the other end of the resistor R4; the other end of the capacitor C1, the other end of the resistor R1, the other end of the resistor R5, the other end of the resistor R14, the other end of the resistor R21, and the seventh pin of the trigger U5 are connected to the ground.
2. The clock signal delay control circuit according to claim 1, characterized in that: The operational amplifier U2 among the plurality of operational amplifiers is connected at the same phase end to the connector P2 end, and at the inverting end to the cathode of the diode D1 and one end of the capacitor C2; the gate of the MOS tube Q2 is connected to the output end of the operational amplifier U1, the drain is connected to the connector P1 end, and the source is connected to one end of the resistor R3 and one end of the resistor R6; the anode of the diode D1 is connected to the other end of the resistor R3; and the other end of the capacitor C2, the other end of the resistor R6 and the ground end are connected.
3. The clock signal delay control circuit according to claim 2, characterized in that: The gate of the MOS tube Q3 among the plurality of MOS tubes is connected to the gate of the MOS tube Q2, the drain is connected to one end of the resistor R7 and one end of the resistor R8, the source is connected to one end of the resistor R15 and the end of the connector P4; the other end of the resistor R7 is connected to the output end of the operational amplifier U2; the other end of the resistor R8 and the other end of the resistor R15 are connected to the ground end.
4. The clock signal delay control circuit according to claim 3, characterized in that: The operational amplifier U3 among the plurality of operational amplifiers is connected at its in-phase end to the connector P4 end, its inverting end to one end of the resistor R9 and one end of the resistor R16, and its output end to the gate of the MOS tube Q4 and the other end of the resistor R16; the source of the MOS tube Q4 is connected to one end of the resistor R12 and one end of the capacitor C3, and its drain is connected to one end of the resistor R10; the other end of the resistor R10 is connected to the power supply; the other end of the capacitor C3, the other end of the resistor R9, and the other end of the resistor R12 are connected to the ground end.
5. The clock signal delay control circuit according to claim 4, characterized in that: The operational amplifier U4 among the plurality of operational amplifiers is connected at its in-phase end to one end of the resistor R11 and the drain of the MOS tube Q5, and its inverting end to one end of the resistor R18 and one end of the resistor R19; the gate of the MOS tube Q5 is connected to the gate of the MOS tube Q4, and its source is connected to one end of the capacitor C3; the other end of the resistor R19 is connected to the power supply; the other end of the resistor R11 and the other end of the resistor R18 are connected to the ground.
6. The clock signal delay control circuit according to claim 5, characterized in that: The cathode of the diode D3 among the plurality of diodes is connected to the end of the connector P3, and the anode is connected to the output end of the operational amplifier U4, the gate of the MOS tube Q6, and the gate of the MOS tube Q7; the drain of the MOS tube Q6 is connected to one end of the capacitor C1; the drain of the MOS tube Q7 is connected to one end of the capacitor C2; the source of the MOS tube Q6, the source of the MOS tube Q7, and the grounding end are connected.
7. The clock signal delay control circuit according to claim 2, characterized in that: One end of the resistor R17 among the plurality of resistors is connected to the gate of the MOS transistor Q2, and the other end is connected to the ground.
8. The clock signal delay control circuit according to claim 1, characterized in that: One end of the resistor R13 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is connected to the ground.