GaN integrated chip and device

Abstract

The invention discloses a GaN integrated chip and device, the GaN integrated chip comprises a depletion type power switch tube and a startup circuit, the depletion type power switch tube is provided with a first source electrode, a first drain electrode and a first gate electrode, the startup circuit at least comprises a startup device, a capacitor structure and a diode structure, the startup device is provided with a second source electrode, and the capacitor structure is provided with a second drain electrode. One end of the first source electrode is electrically connected with the positive electrode of the diode structure, the negative electrode of the diode structure is electrically connected with one end of the second source electrode, the negative electrode of the diode structure is further electrically connected with one end of the capacitor structure, the starting device is in an on state during starting, and the starting device is in an off state after starting; the start-up circuit is used for supplying power to the IC during start-up, and the first source electrode is used for continuously supplying power to the IC after start-up. According to the GaN integrated chip and the GaN integrated device, the structures of a startup circuit and a power supply circuit after startup are greatly simplified, the cost is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a GaN integrated chip and a device including the GaN integrated chip. Background Art

[0002] In the prior art, the power supply of an AC / DC power control chip is often taken from an additional auxiliary winding. Due to the low efficiency of the starting circuit, after the power supply starts up, the starting circuit is often turned off, and the power is switched to the auxiliary winding of the transformer to supply the control chip. The voltage in the auxiliary winding with a fixed number of turns will change with the change of the output voltage, and an additional voltage stabilizing circuit is often required, which makes the power supply structure design complex and costly.

[0003] At the same time, cascaded GaN devices often cause overshoot of the voltage of the Si MOS lower transistor due to the capacitance matching problem during the turn-off instant, reaching or approaching avalanche, which affects the reliability of the device. Summary of the Invention

[0004] In view of this, in order to overcome the defects of the prior art, the object of the present invention is to provide a GaN integrated chip and a device, which realize the monolithic integration of a depletion-mode power switch transistor and a high-voltage starting circuit (starting circuit), replace the power supply taking method of the auxiliary winding, simplify the circuit structure, and are beneficial to reducing costs.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: A GaN integrated chip includes a depletion-mode power switch transistor and a starting circuit. The depletion-mode power switch transistor has a first source electrode, a first drain electrode, and a first gate electrode. The starting circuit at least includes a starting device, a capacitor structure, and a diode structure. The starting device has a second source electrode. One end of the first source electrode is electrically connected to the positive electrode of the diode structure. The negative electrode of the diode structure is electrically connected to one end of the second source electrode. The negative electrode of the diode structure is also electrically connected to one end of the capacitor structure. During starting, the starting device is in a conducting state. After starting, the starting device is in a turned-off state; The starting circuit is used to supply power to the IC during starting, and the first source electrode of the depletion-mode power switch transistor is used to continuously supply power to the IC after starting. Among them, the function of the diode structure is to ensure the unidirectional flow of current. When the depletion-mode power switch transistor starts to switch, the power supply path is switched to take power from one end of the first source electrode; the function of the capacitor structure is to allow a certain voltage difference to be generated on both sides thereof to turn off the starting device.

[0006] By integrating the depletion-mode power switch and the starting circuit on a single chip, after starting, it replaces the power-taking method of the auxiliary winding, takes power from one end of the first source electrode of the depletion-mode power switch with the shortest loop, and at the same time, after starting, continues to supply power to the IC (Integrated Circuit) from one end of the first source electrode of the depletion-mode power switch, greatly simplifying the structures of the starting circuit and the power supply circuit after starting, which is beneficial to cost reduction; at the same time, it avoids the voltage overshoot problem of the Si MOS lower transistor in the cascaded GaN device at the moment of turn-off.

[0007] According to some preferred implementation aspects of the present invention, the starting device further has a second drain electrode and a second gate electrode, and the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode are all used as output terminals.

[0008] According to some preferred implementation aspects of the present invention, the starting circuit includes a starting device, a capacitor structure, and a diode structure. The second gate electrode is used to connect to the control output terminal with a source control start function, and one end of the capacitor structure is used to ground. In some embodiments of the present invention, the second drain electrode is used as an output terminal to connect to a high level, the second gate electrode is used as an output terminal to connect to the control output terminal with a source control start function, the second source electrode is used as an output terminal to supply power to the IC during starting, the first drain electrode is used as an output terminal to access the main circuit of the external circuit, the first gate electrode is used as an output terminal to connect to the third source electrode of the low-voltage enhancement-mode MOS chip and then jointly used as a source extreme, and the first source electrode is used as an output terminal to connect to the third drain electrode of the low-voltage enhancement-mode MOS chip to form a cascaded device, and one end of the capacitor structure is used as an output terminal to ground.

[0009] According to some preferred implementation aspects of the present invention, the starting circuit includes a starting device, a capacitor structure, a diode structure, and a first resistor structure.

[0010] According to some preferred implementation aspects of the present invention, both ends of the first resistor structure are electrically connected to both ends of the capacitor structure, and the capacitor structure is also electrically connected to the second gate electrode.

[0011] According to some preferred implementation aspects of the present invention, the second gate electrode is used for grounding. In some embodiments of the present invention, the second drain electrode is used as an output terminal to connect to a high level, the second gate electrode is used as an output terminal for grounding, the second source electrode is used as an output terminal to supply power to the IC during startup, the first drain electrode is used as an output terminal to access the main circuit of the external circuit, the first gate electrode is used as an output terminal to be connected to the third source electrode of the low-voltage enhancement-mode MOS chip and jointly used as a source terminal, and the first source electrode is used as an output terminal to be connected to the third drain electrode of the low-voltage enhancement-mode MOS chip to form a cascaded device.

[0012] According to some preferred implementation aspects of the present invention, the startup circuit further includes a second resistor structure.

[0013] According to some preferred implementation aspects of the present invention, the first resistor structure is also electrically connected to one end of the second resistor structure, and the other end of the second resistor structure is used as an output terminal.

[0014] According to some preferred implementation aspects of the present invention, one end of the second resistor structure used as an output terminal is electrically connected to the source electrode of the cascaded low-voltage enhancement-mode MOS chip. In some embodiments of the present invention, the second drain electrode is used as an output terminal to connect to a high level, the second gate electrode is used as an output terminal for grounding (used as the ground terminal on the startup circuit side and also the ground terminal after the current detection resistor on the cascaded device side), the second source electrode is used as an output terminal to supply power to the IC during startup, the first drain electrode is used as an output terminal to access the main circuit of the external circuit, the first gate electrode is used as an output terminal to be connected to the third source electrode of the low-voltage enhancement-mode MOS chip and jointly used as a source terminal, the first source electrode is used as an output terminal to be connected to the third drain electrode of the low-voltage enhancement-mode MOS chip to form a cascaded device; one end of the second resistor structure used as an output terminal is electrically connected to the source electrode of the cascaded low-voltage enhancement-mode MOS chip.

[0015] According to some preferred implementation aspects of the present invention, the second resistor structure is used as a current detection resistor. In some embodiments of the present invention, the introduction of the current detection resistor can further simplify and reduce the peripheral circuit in the PCB board, reduce the loop parasitic parameters while reducing costs, and is beneficial to improving electromagnetic interference.

[0016] According to some preferred implementation aspects of the present invention, the startup circuit further includes a third resistor structure, and the third resistor structure is connected in series with the second drain electrode. In some embodiments of the present invention, both the first resistor structure and the third resistor structure are used for current limiting and voltage division to prevent damage to the startup device due to excessive current.

[0017] The present invention also provides a device, including a low-voltage enhancement-mode MOS chip and the GaN integrated chip as described above, and the device is formed by cascading the low-voltage enhancement-mode MOS chip and the GaN integrated chip.

[0018] According to some preferred embodiments of the present invention, including a source terminal, a drain terminal, and a gate terminal, the low-voltage enhancement-mode MOS chip has a third source electrode, a third drain electrode, and a third gate electrode. After the first gate electrode is connected to the third source electrode, they are jointly used as the source terminal, the third gate electrode is used as the gate terminal, and the first drain electrode is used as the drain terminal.

[0019] Due to the adoption of the above technical solutions, compared with the prior art, the advantages of the present invention are as follows: For a GaN integrated chip and a device of the present invention, by integrating a depletion-mode power switch and a startup circuit on a single chip, after startup, it replaces the power supply method of the auxiliary winding, takes power from one end of the first source electrode of the depletion-mode power switch with the shortest loop, and at the same time continues to supply power to the IC from one end of the first source electrode of the depletion-mode power switch after startup, greatly simplifying the structures of the startup circuit and the power supply circuit after startup, which is beneficial to cost reduction; at the same time, it avoids the voltage overshoot problem of the Si MOS lower transistor in the device formed by cascading the GaN integrated chip and the low-voltage enhancement-mode MOS chip at the moment of turn-off, which is beneficial to improving the reliability of the device. In addition, since the depletion-mode power switch generates heat, integrating the startup circuit around it is beneficial to expanding the device size, will greatly optimize the thermal resistance of the depletion-mode power switch, and thus make its performance better. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a top view structural schematic diagram of the cascaded device in Embodiment 1 of the present invention; Figure 2 It is a top view structural schematic diagram of the cascaded device in Embodiment 2 of the present invention; Figure 3 It is a top view structural schematic diagram of the cascaded device in Embodiment 3 of the present invention; Figure 4 is Figure 1 a cross-sectional schematic diagram along the direction of the dashed line A; Figure 5 is Figure 1 a cross-sectional schematic diagram along the direction of the dashed line B; Figure 6 is Figure 1 Schematic cross-sectional view along the direction of dashed line C; Figure 7 is Figure 1 Schematic cross-sectional view along the direction of dashed line D; Figure 8 is Figure 1 Schematic cross-sectional view along the direction of dashed line E; Figure 9 is Figure 2 Schematic cross-sectional view along the direction of dashed line F; Figure 10 is Figure 3 Schematic cross-sectional view along the direction of dashed line G; Figure 11 Equivalent circuit diagram of the GaN integrated chip in Embodiment 1 of the present invention; Figure 12 Equivalent circuit diagram of the GaN integrated chip in Embodiment 2 of the present invention; Figure 13 Equivalent circuit diagram of the GaN integrated chip in Embodiment 3 of the present invention; Among them, the reference numerals are: GaN integrated chip - 100, low-voltage enhancement MOS chip - 200, depletion-type power switch - 101, starting device - 102, capacitor structure - 103, diode structure - 104, first resistor structure - 105, second resistor structure - 106, third resistor structure - 107, substrate - 108, nucleation layer - 1091, buffer layer - 1092, channel layer - 1093, barrier layer - 1094, capping layer - 1095, first dielectric layer - 110, second dielectric layer - 111, third dielectric layer - 112; The first source electrode - 1, the first drain electrode - 2, the first gate electrode - 3, the second source electrode - 4, the second drain electrode - 5, the second gate electrode - 6, the third source electrode - 7, the third drain electrode - 8, the third gate electrode - 9, the first source electrode ohmic metal - 10, the first drain electrode ohmic metal - 11, the first gate electrode metal - 12, the second source electrode ohmic metal - 13, the second drain electrode ohmic metal - 14, the second gate electrode metal - 15, the first ohmic metal - 16, the second ohmic metal - 17, the third ohmic metal - 18, the Schottky metal - 19, the first field plate - 20, the second field plate - 21, the third field plate - 22, the fourth field plate - 23, the first metal connection bar - 24, the second metal connection bar - 25, the third metal connection bar - 26, the fourth metal connection bar - 27, the fifth metal connection bar - 28, the sixth metal connection bar - 29, the seventh metal connection bar - 30, the eighth metal connection bar - 31, the ninth metal connection bar - 32, the first connection segment - 33, the second connection segment - 34, the third connection segment - 35, the lower electrode - 36, the upper electrode - 37, the capacitive electrode - 38, the diode electrode - 39, the first resistor - 40, the second resistor - 41, the third resistor - 42, the first resistor electrode - 43, the second resistor electrode - 44, the third resistor electrode - 45, the bonding wire - 46, the pin - 47. Detailed implementation mode

[0022] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0023] A cascaded device of the present invention includes a low-voltage enhancement MOS chip 200 and a GaN integrated chip 100, and the cascaded device is formed by cascading the low-voltage enhancement MOS chip 200 and the GaN integrated chip 100. The GaN integrated chip 100 includes a depletion-mode power switch 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The startup circuit at least includes a startup device 102, a capacitor structure 103, and a diode structure 104. The depletion-mode power switch 101 has a first source electrode 1, a first drain electrode 2, and a first gate electrode 3. The startup device 102 has a second source electrode 4, a second drain electrode 5, and a second gate electrode 6. The low-voltage enhancement MOS chip 200 has a third source electrode 7, a third drain electrode 8, and a third gate electrode 9. The cascaded device has a source terminal, a drain terminal, and a gate terminal. In actual packaging, the first source electrode 1 is connected to the third drain electrode 8 by wire bonding 46. The first gate electrode 3 and the third source electrode 7 are connected together and used as the source terminal. The third gate electrode 9 is used as the gate terminal. The first drain electrode 2 is used as the drain terminal.

[0024] In the cascaded device of the present invention, during startup, the startup device 102 is in the on state. After startup, the startup device 102 is in the off state. The startup circuit is used to supply power to the IC during startup, and the first source electrode 1 of the depletion-mode power switch 101 is used to continuously supply power to the IC after startup.

[0025] Further, in some embodiments of the present invention, the startup circuit only includes the startup device 102, the capacitor structure 103, and the diode structure 104. Among them, one end of the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104. The negative electrode of the diode structure 104 is electrically connected to one end of the second source electrode 4. The negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103. The second drain electrode 5 is used as an output terminal to connect to a high level. The second gate electrode 6 is used as an output terminal to connect to a control output terminal with a source control startup function. The second source electrode 4 is used as an output terminal to supply power to the IC during startup. The first drain electrode 2 is used as an output terminal to access the main circuit of the external circuit. The first gate electrode 3 is used as an output terminal to be connected to the third source electrode 7 and together they are used as the source terminal. The first source electrode 1 is used as an output terminal to be connected to the third drain electrode 8. The other end of the capacitor structure 103 is used as an output terminal to be grounded.

[0026] In some other embodiments of the present invention, the startup circuit includes a startup device 102, a capacitor structure 103, a diode structure 104, and a first resistor structure 105. One end of the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, the negative electrode of the diode structure 104 is electrically connected to one end of the second source electrode 4, the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, both ends of the first resistor structure 105 are respectively electrically connected to both ends of the capacitor structure 103, and the capacitor structure 103 is also electrically connected to the second gate electrode 6. The second drain electrode 5 is used as an output terminal to connect to a high level, the second gate electrode 6 is used as an output terminal to be grounded, the second source electrode 4 is used as an output terminal to supply power to the IC during startup, the first drain electrode 2 is used as an output terminal to be connected to the main circuit of the external circuit, the first gate electrode 3 is used as an output terminal to be connected to the third source electrode 7 and then jointly used as a source terminal, and the first source electrode 1 is used as an output terminal to be connected to the third drain electrode 8.

[0027] In some other embodiments of the present invention, the startup circuit includes a startup device 102, a capacitor structure 103, a diode structure 104, a first resistor structure 105, and a second resistor structure 106. The second resistor structure 106 is used as a current detection resistor; one end of the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, the negative electrode of the diode structure 104 is electrically connected to one end of the second source electrode 4, the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, both ends of the first resistor structure 105 are respectively electrically connected to both ends of the capacitor structure 103, the capacitor structure 103 is also electrically connected to the second gate electrode 6, the first resistor structure 105 is also electrically connected to one end of the second resistor structure 106, and the other end of the second resistor structure 106 is used as an output terminal to be electrically connected to the third source electrode 7; the second drain electrode 5 is used as an output terminal to connect to a high level, the second gate electrode 6 is used as an output terminal to be grounded, the second source electrode 4 is used as an output terminal to supply power to the IC during startup, the first drain electrode 2 is used as an output terminal to be connected to the main circuit of the external circuit, the first gate electrode 3 is used as an output terminal to be connected to the third source electrode 7 and then jointly used as a source terminal, and the first source electrode 1 is used as an output terminal to be connected to the third drain electrode 8.

[0028] Further, a third resistor structure 107 may be included in the startup circuit of the present invention, and the third resistor structure 107 is connected in series with the second drain electrode 5 to play a role in current limiting and voltage division.

[0029] The structure of the cascaded device of the present invention will be introduced in detail below. Embodiment 1

[0030] As Figure 1As shown, the cascaded device in this embodiment is formed by cascading a low-voltage enhancement-type MOS chip 200 and a GaN integrated chip 100. The GaN integrated chip 100 includes a depletion-type power switch 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The stacked structure includes a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095 arranged in sequence from bottom to top. The cascaded device has a source terminal, a drain terminal, and a gate terminal.

[0031] As Figure 1 and Figure 4 shown, the depletion-type power switch 101 includes a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a first gate electrode metal 12, a first field plate 20, a second field plate 21, a first metal connection bar 24, a second metal connection bar 25, and a third metal connection bar 26. The first source electrode ohmic metal 10 and the first drain electrode ohmic metal 11 are both located in the barrier layer 1094 and the cap layer 1095; the first gate electrode metal 12 is located in the first dielectric layer 110, the first field plate 20 is located in the second dielectric layer 111, and the second field plate 21 is located in the third dielectric layer 112; the first source electrode 1, the first drain electrode 2, and the first gate electrode 3 are all located above the third dielectric layer 112; the first metal connection bar 24, the second metal connection bar 25, and the third metal connection bar 26 all penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of the first metal connection bar 24 are respectively connected to the first source electrode ohmic metal 10 and the first source electrode 1, the two ends of the second metal connection bar 25 are respectively connected to the first drain electrode ohmic metal 11 and the first drain electrode 2, and the two ends of the third metal connection bar 26 are respectively connected to the first gate electrode metal 12 and the first gate electrode 3. In this embodiment, the depletion-type power switch 101 is provided with a plurality of first source electrode ohmic metals 10 and corresponding first metal connection bars 24, a plurality of first drain electrode ohmic metals 11 and corresponding second metal connection bars 25. The plurality of first source electrode ohmic metals 10 are simultaneously electrically connected to the first source electrode 1 through the plurality of first metal connection bars 24, and the plurality of first drain electrode ohmic metals 11 are simultaneously electrically connected to the first drain electrode 2 through the plurality of second metal connection bars 25.

[0032] Further, as Figure 1 and Figure 5As shown in the figure, the startup circuit of this embodiment includes a startup device 102, a capacitor structure 103, a diode structure 104, and a third resistor structure 107. The startup device 102 includes a second source electrode 4, a second drain electrode 5, a second gate electrode 6, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a second gate electrode metal 15, a third field plate 22, a fourth field plate 23, a fourth metal connection bar 27, a fifth metal connection bar 28, and a sixth metal connection bar 29. The second source electrode ohmic metal 13 and the second drain electrode ohmic metal 14 are both located in the barrier layer 1094 and the capping layer 1095; the second gate electrode metal 15 is located in the first dielectric layer 110, the third field plate 22 is located in the second dielectric layer 111, and the fourth field plate 23 is located in the third dielectric layer 112; the second source electrode 4, the second drain electrode 5, and the second gate electrode 6 are all located above the third dielectric layer 112; the fourth metal connection bar 27, the fifth metal connection bar 28, and the sixth metal connection bar 29 all penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of the fourth metal connection bar 27 are respectively connected to the second source electrode ohmic metal 13 and the second source electrode 4, the two ends of the fifth metal connection bar 28 are respectively connected to the second drain electrode ohmic metal 14 and the second drain electrode 5, and the two ends of the sixth metal connection bar 29 are respectively connected to the second gate electrode metal 15 and the second gate electrode 6. In this embodiment, one second source electrode ohmic metal 13 of the startup device 102 and the corresponding fourth metal connection bar 27 are each provided, and one second drain electrode ohmic metal 14 and the corresponding fifth metal connection bar 28 are also each provided.

[0033] As Figure 1 and Figure 6 shown in the figure, the capacitor structure 103 of this embodiment includes a lower electrode 36, an upper electrode 37, two capacitor electrodes 38, a seventh metal connection bar 30 located on one side of the lower electrode 36, and an eighth metal connection bar 31 located on one side of the upper electrode 37. Among them, the lower electrode 36 is located in the second dielectric layer 111, the upper electrode 37 is located in the third dielectric layer 112, the two capacitor electrodes 38 are both located above the third dielectric layer 112, the seventh metal connection bar 30 penetrates through the second dielectric layer 111 and the third dielectric layer 112 and its two ends are respectively connected to the lower electrode 36 and one capacitor electrode 38, and the eighth metal connection bar 31 penetrates through the third dielectric layer 112 and its two ends are respectively connected to the upper electrode 37 and the other capacitor electrode 38.

[0034] As Figure 1 and Figure 7As shown, the diode structure 104 includes a first ohmic metal 16, a Schottky metal 19, two diode electrodes 39, and two ninth metal connection bars 32. Among them, both the first ohmic metal 16 and the Schottky metal 19 are located in the barrier layer 1094 and the capping layer 1095. Both of the two diode electrodes 39 are located above the third dielectric layer 112. Both of the two ninth metal connection bars 32 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of one ninth metal connection bar 32 are respectively connected to the first ohmic metal 16 and one diode electrode 39 to form the negative electrode of the diode structure 104, and the two ends of the other ninth metal connection bar 32 are respectively connected to the Schottky metal 19 and the other diode electrode 39 to form the positive electrode of the diode structure 104.

[0035] As Figure 1 and Figure 8 shown, the third resistor structure 107 is disposed on one side of the second drain electrode 5 of the starting device 102. The third resistor structure 107 includes a third resistor 42, second ohmic metals 17 located on both sides of the third resistor 42, two third resistor electrodes 45, and two first connection segments 33. The third resistor structure 107 is connected in series with the second drain electrode 5. Among them, the third resistor 42 is located in the channel layer 1093. Both of the two second ohmic metals 17 are located in the barrier layer 1094 and the capping layer 1095. Both of the two third resistor electrodes 45 are located above the third dielectric layer 112. Both of the two first connection segments 33 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each first connection segment 33 are respectively connected to a corresponding second ohmic metal 17 and a third resistor electrode 45. In this embodiment, the resistance value of the third resistor 42 is 1×10 3 ~5×10 7 Ω.

[0036] Furthermore, as Figure 1 and Figure 12 shown, in the GaN integrated chip 100 of this embodiment, one end of the first source electrode 1 is connected to one diode electrode 39 of the positive electrode of the corresponding diode structure 104 so that the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104. One end of the second source electrode 4 is connected to one diode electrode 39 of the negative electrode of the corresponding diode structure 104 so that the second source electrode 4 is electrically connected to the negative electrode of the diode structure 104. One capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to one diode electrode 39 of the negative electrode of the corresponding diode structure 104 so that the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103. One of the third resistor electrodes 45 is connected to the second drain electrode 5 so that the third resistor structure 107 is connected in series with the second drain electrode 5.

[0037] Furthermore, the low-voltage enhancement-mode MOS chip 200 has a third source electrode 7, a third drain electrode 8, and a third gate electrode 9. In this embodiment, the starting network formed is applicable to some active-control starting circuits, such as the IW1699 main control IC, whose ASU (Active Start-Up) pin can control the turn-off of the starting device 102. When actually packaging the GaN integrated chip 100 of this embodiment with the low-voltage enhancement-mode MOS chip 200, the first source electrode 1 is connected to the third drain electrode 8 through a wire bonding 46; the first gate electrode 3 is connected to the third source electrode 7 through a wire bonding 46, such that one end of the first gate electrode 3 is used as an output terminal and is commonly used as a source terminal after being connected to the third source electrode 7; meanwhile, the third source electrode 7 is connected to a corresponding pin 47 through a wire bonding 46; one end of the third gate electrode 9 is connected to a corresponding pin 47 through a wire bonding 46, such that the third gate electrode 9 is used as a gate terminal; one end of the first drain electrode 2 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of the first drain electrode 2 is used as an output terminal to be connected to the main circuit of an external circuit (the first drain electrode 2 is used as a drain terminal); one end of a third resistance electrode 45 away from the second drain electrode 5 is connected to a corresponding pin 47 through a wire bonding 46. Since the second drain electrode 5 in this embodiment is connected in series with a third resistance structure 107, one end of the other third resistance electrode 45 in the third resistance structure 107 that is not connected to the second drain electrode 5 is used as an output terminal to connect to a high level; one end of the second gate electrode 6 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of the second gate electrode 6 is used as an output terminal to be connected to the control output terminal ASU with an active-control starting function; one end of the second source electrode 4 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of the second source electrode 4 is used as an output terminal to supply power to the IC during start-up; one end of the capacitor electrode 38 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of a capacitor electrode 38 corresponding to the lower electrode 36 in the capacitor structure 103 is used as an output terminal to be grounded.

[0038] When starting up, the starting device 102 is in a conducting state, and the current flows through the starting device 102 to charge the capacitor structure 103. The capacitor voltage continuously rises, that is, the potential at one end of the second source electrode 4 rises until the IC starts to work. At this time, the current flows from the third resistor structure 107 through the channel of the starting device 102 to the second source electrode 4. When the startup process ends, the driving chip starts to work normally. At this time, the depletion-mode power switch 101 starts to switch. Due to the instant when the switch is turned off during the switching operation, the instant potential of the first source electrode 1 will be higher than the potential of the second source electrode 4 of the starting device 102. At this time, the current changes to flow from the first drain electrode 2 of the depletion-mode power switch 101, through its channel, then from its first source electrode 1, through the diode structure 104, and finally to the second source electrode 4 to supply power to the control chip. When the IC is normally powered, the ASU pin at this time will output a low level to pull down the gate potential of the starting device 102, thereby realizing the turn-off of the starting device 102. After that, the startup circuit has almost no power loss.

[0039] The above circuit is also applicable to an IC without an ASU pin, and only a gate pull-down loop needs to be built externally.

[0040] This embodiment also provides a preparation method of the GaN integrated chip 100, which specifically includes the following steps: Step 1: Perform nitride epitaxial growth on the substrate 108 to sequentially form a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a capping layer 1095. The materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 1091, the buffer layer 1092, the channel layer 1093, the barrier layer 1094, and the capping layer 1095 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure and being able to form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 1093 and the barrier layer 1094 to generate a conductive channel. The substrate 108 is one or a combination of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing group III nitride materials.

[0041] Step 2: Through photoresist protection, perform patterning and ion material injection above the capping layer 1095 to destroy the two-dimensional electron gas to form an isolation region. Protect the non-injected regions as the continuous region chip active regions with the first source electrode 1, the first drain electrode 2, and the first gate electrode 3, the continuous region chip active regions with the second source electrode 4, the second drain electrode 5, and the second gate electrode 6, and the regions where the capacitor structure 103, the diode structure 104, and the third resistor structure 107 are formed, and form the third resistor 42.

[0042] Step 3: Perform patterned etching above the capping layer 1095 to form a first source electrode ohmic hole, a first drain electrode ohmic hole, simultaneously etch to form a second source electrode ohmic hole, a second drain electrode ohmic hole, simultaneously etch to form a first positive electrode hole and a negative electrode hole, and simultaneously perform patterned etching on both sides of the third resistor 42 to form two first ohmic contact holes.

[0043] Step 4: Fill the first source electrode ohmic hole, the first drain electrode ohmic hole, the second source electrode ohmic hole, the second drain electrode ohmic hole, the negative electrode hole, and the two first ohmic contact holes with metal to form a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a first ohmic metal 16, and second ohmic metals 17 on both sides of the third resistor 42, and perform annealing treatment. At this time, the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, and the two second ohmic metals 17 respectively form ohmic contacts with the epitaxial material below. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0044] Step 6: Deposit a combination of one or more of SiN, SiO2, SiON, and Al2O3 above the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, and the second ohmic metal 17 to form a first dielectric layer 110, and respectively etch out a first gate trench and a second gate trench. At the same time, etch out a second positive electrode hole at the position of the first positive electrode hole covered by the first dielectric layer 110.

[0045] Step 7: Fill the metal above the first dielectric layer 110 to completely cover the first gate trench, the second gate trench, and the second positive electrode hole, and etch to form a first gate electrode metal 12 (the part located in the first gate trench) and a first field plate 20. At the same time, etch to form a second gate electrode metal 15 (the part located in the second gate trench) and a third field plate 22. At the same time, etch to form a Schottky metal 19. At the same time, etch to form a lower electrode 36.

[0046] Step 8: Deposit a combination of one or more of SiN, SiO2, SiON, and Al2O3 above the first gate electrode metal 12, the second gate electrode metal 15, and the lower electrode 36 to form a second dielectric layer 111.

[0047] Step 8: Fill with metal above the second dielectric layer 111 and etch to form a second field plate 21, a fourth field plate 23, and an upper electrode 37. Then deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 above the second field plate 21, the fourth field plate 23, and the upper electrode 37 to form a third dielectric layer 112.

[0048] Step 9: Etch downward from the third dielectric layer 112 to form a first source electrode via hole, a first drain electrode via hole, a first gate electrode via hole, a second source electrode via hole, a second drain electrode via hole, a second gate electrode via hole, two first via holes, two second via holes, and two third via holes. Among them, the first source electrode via hole, the first drain electrode via hole, the first gate electrode via hole, the second source electrode via hole, the second drain electrode via hole, the second gate electrode via hole, two second via holes, and two third via holes all penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. One first via hole penetrates through the third dielectric layer 112 and the second dielectric layer 111, and the other first via hole penetrates through the third dielectric layer 112.

[0049] Step 10: Fill the first source electrode via hole, the first drain electrode via hole, the first gate electrode via hole, the second source electrode via hole, the second drain electrode via hole, the second gate electrode via hole, two first via holes, two second via holes, and two third via holes with metal to respectively form a first metal connection strip 24, a second metal connection strip 25, a third metal connection strip 26, a fourth metal connection strip 27, a fifth metal connection strip 28, a sixth metal connection strip 29, a seventh metal connection strip 30, an eighth metal connection strip 31, two ninth metal connection strips 32, and two first connection segments 33.

[0050] Step 11: Fill the metal above the third dielectric layer 112 and etch to form the first source electrode 1, the first drain electrode 2, the first gate electrode 3, the second source electrode 4, the second drain electrode 5, the second gate electrode 6, two capacitor electrodes 38, two diode electrodes 39 and two third resistor electrodes 45. Among them, the two ends of the first metal connection strip 24 are electrically connected to the first source electrode 1 and the first source electrode ohmic metal 10 respectively, the two ends of the second metal connection strip 25 are electrically connected to the first drain electrode 2 and the first drain electrode ohmic metal 11 respectively, and the two ends of the third metal connection strip 26 are electrically connected to the first gate electrode 3 and the first gate electrode metal 12 respectively, forming a depletion-mode power switch 101; the two ends of the fourth metal connection strip 27 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13 respectively, the two ends of the fifth metal connection strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14 respectively, and the two ends of the sixth metal connection strip 29 are electrically connected to the second gate electrode 6 and the second gate electrode metal 15 respectively, forming an enabling device 102; the two ends of the seventh metal connection strip 30 are electrically connected to a capacitor electrode 38 and the lower electrode 36 respectively, the two ends of the eighth metal connection strip 31 are electrically connected to the other capacitor electrode 38 and the upper electrode 37 respectively, forming a capacitor structure 103; the two ends of a ninth metal connection strip 32 are electrically connected to a diode electrode 39 and the first ohmic metal 16 respectively, and the two ends of the other ninth metal connection strip 32 are electrically connected to a diode electrode 39 and the Schottky metal 19 respectively, forming a diode structure 104; the two ends of each first connection segment 33 are connected to the corresponding third resistor electrode 45 and the second ohmic metal 17 respectively, forming a third resistor structure 107.

[0051] Step 12: Connect one end of the first source electrode 1 to a diode electrode 39 at the positive pole of the corresponding diode structure 104, connect one end of the second source electrode 4 to a diode electrode 39 at the negative pole of the corresponding diode structure 104, connect a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 to a diode electrode 39 at the negative pole of the corresponding diode structure 104, and connect one of the third resistor electrodes 45 to the second drain electrode 5, obtaining the GaN integrated chip 100 of this embodiment. Embodiment 2

[0052] As Figure 2As shown in the figure, the cascaded device in this embodiment is formed by cascading a low-voltage enhancement-type MOS chip 200 and a GaN integrated chip 100. The GaN integrated chip 100 includes a depletion-type power switch 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The stacked structure includes a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095 arranged in sequence from bottom to top. The cascaded device has a source terminal, a drain terminal, and a gate terminal.

[0053] Further, the structure of the depletion-type power switch 101 in this embodiment is the same as that in Embodiment 1, and includes a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a first gate electrode metal 12, a first field plate 20, a second field plate 21, a first metal connection bar 24, a second metal connection bar 25, and a third metal connection bar 26. The first source electrode ohmic metal 10 and the first drain electrode ohmic metal 11 are both located in the barrier layer 1094 and the cap layer 1095; the first gate electrode metal 12 is located in the first dielectric layer 110, the first field plate 20 is located in the second dielectric layer 111, and the second field plate 21 is located in the third dielectric layer 112; the first source electrode 1, the first drain electrode 2, and the first gate electrode 3 are all located above the third dielectric layer 112; the first metal connection bar 24, the second metal connection bar 25, and the third metal connection bar 26 all penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of the first metal connection bar 24 are respectively connected to the first source electrode ohmic metal 10 and the first source electrode 1, the two ends of the second metal connection bar 25 are respectively connected to the first drain electrode ohmic metal 11 and the first drain electrode 2, and the two ends of the third metal connection bar 26 are respectively connected to the first gate electrode metal 12 and the first gate electrode 3. In this embodiment, the depletion-type power switch 101 is provided with a plurality of first source electrode ohmic metals 10 and corresponding first metal connection bars 24, a plurality of first drain electrode ohmic metals 11 and corresponding second metal connection bars 25. The plurality of first source electrode ohmic metals 10 are simultaneously electrically connected to the first source electrode 1 through the plurality of first metal connection bars 24, and the plurality of first drain electrode ohmic metals 11 are simultaneously electrically connected to the first drain electrode 2 through the plurality of second metal connection bars 25.

[0054] Further, as Figure 2As shown in the figure, the startup circuit of this embodiment includes a startup device 102, a capacitor structure 103, a diode structure 104, a third resistor structure 107, and a first resistor structure 105. Among them, the startup device 102 includes a second source electrode 4, a second drain electrode 5, a second gate electrode 6, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a second gate electrode metal 15, a third field plate 22, a fourth field plate 23, a fourth metal connection bar 27, a fifth metal connection bar 28, and a sixth metal connection bar 29. Among them, the second source electrode ohmic metal 13 and the second drain electrode ohmic metal 14 are both located in the barrier layer 1094 and the capping layer 1095; the second gate electrode metal 15 is located in the first dielectric layer 110, the third field plate 22 is located in the second dielectric layer 111, and the fourth field plate 23 is located in the third dielectric layer 112; the second source electrode 4, the second drain electrode 5, and the second gate electrode 6 are all located above the third dielectric layer 112; the fourth metal connection bar 27, the fifth metal connection bar 28, and the sixth metal connection bar 29 all penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of the fourth metal connection bar 27 are respectively connected to the second source electrode ohmic metal 13 and the second source electrode 4, the two ends of the fifth metal connection bar 28 are respectively connected to the second drain electrode ohmic metal 14 and the second drain electrode 5, and the two ends of the sixth metal connection bar 29 are respectively connected to the second gate electrode metal 15 and the second gate electrode 6. In this embodiment, one second source electrode ohmic metal 13 and the corresponding fourth metal connection bar 27 are each provided, and one second drain electrode ohmic metal 14 and the corresponding fifth metal connection bar 28 are also each provided.

[0055] The capacitor structure 103 of this embodiment includes a lower electrode 36, an upper electrode 37, two capacitor electrodes 38, a seventh metal connection bar 30 located on one side of the lower electrode 36, and an eighth metal connection bar 31 located on one side of the upper electrode 37. Among them, the lower electrode 36 is located in the second dielectric layer 111, the upper electrode 37 is located in the third dielectric layer 112, the two capacitor electrodes 38 are both located above the third dielectric layer 112, the seventh metal connection bar 30 penetrates the second dielectric layer 111 and the third dielectric layer 112, and its two ends are respectively connected to the lower electrode 36 and one capacitor electrode 38, and the eighth metal connection bar 31 penetrates the third dielectric layer 112, and its two ends are respectively connected to the upper electrode 37 and the other capacitor electrode 38.

[0056] The diode structure 104 includes a first ohmic metal 16, a Schottky metal 19, two diode electrodes 39, and two ninth metal connection bars 32. Among them, both the first ohmic metal 16 and the Schottky metal 19 are located in the barrier layer 1094 and the capping layer 1095. Both of the two diode electrodes 39 are located above the third dielectric layer 112. Both of the two ninth metal connection bars 32 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of one ninth metal connection bar 32 are respectively connected to the first ohmic metal 16 and one diode electrode 39 to form the negative electrode of the diode structure 104, and the two ends of the other ninth metal connection bar 32 are respectively connected to the Schottky metal 19 and the other diode electrode 39 to form the positive electrode of the diode structure 104.

[0057] The third resistor structure 107 is disposed on one side of the second drain electrode 5 of the enabling device 102. The third resistor structure 107 includes a third resistor 42, second ohmic metals 17 located on both sides of the third resistor 42, two third resistor electrodes 45, and two first connection segments 33. The third resistor structure 107 is connected in series with the second drain electrode 5. Among them, the third resistor 42 is located in the channel layer 1093. Both of the two second ohmic metals 17 are located in the barrier layer 1094 and the capping layer 1095. Both of the two third resistor electrodes 45 are located above the third dielectric layer 112. Both of the two first connection segments 33 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each first connection segment 33 are respectively connected to a corresponding second ohmic metal 17 and a third resistor electrode 45. In this embodiment, the resistance value of the third resistor 42 is 1×10 3 ~5×10 7 Ω.

[0058] As Figure 2 and Figure 9 shown, the first resistor structure 105 of this embodiment is disposed on one side of the capacitor structure 103 and has the same structure as the third resistor structure 107. Specifically, the first resistor structure 105 includes a first resistor 40, third ohmic metals 18 located on both sides of the first resistor 40, two first resistor electrodes 43, and two second connection segments 34. Among them, the first resistor 40 is located in the channel layer 1093. Both of the two third ohmic metals 18 are located in the barrier layer 1094 and the capping layer 1095. Both of the two first resistor electrodes 43 are located above the third dielectric layer 112. Both of the two second connection segments 34 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each second connection segment 34 are respectively connected to a corresponding third ohmic metal 18 and a first resistor electrode 43. In this embodiment, the resistance value of the first resistor 40 is 1×10 3 ~5×10 7 Ω.

[0059] Further, as Figure 2 and Figure 12 shown, in the GaN integrated chip 100 of this embodiment, one end of the first source electrode 1 is connected to a diode electrode 39 of the positive electrode of the corresponding diode structure 104 so that the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, one end of the second source electrode 4 is connected to a diode electrode 39 of the negative electrode of the corresponding diode structure 104 so that the second source electrode 4 is electrically connected to the negative electrode of the diode structure 104, a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to a diode electrode 39 of the negative electrode of the corresponding diode structure 104 so that the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, one of the third resistor electrodes 45 is connected to the second drain electrode 5 so that the third resistor structure 107 is in series with the second drain electrode 5, both ends of a capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 are respectively connected to the second gate electrode 6 and a first resistor electrode 43 close to it, and another first resistor electrode 43 is connected to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, so that the capacitor structure 103 is also electrically connected to the second gate electrode 6 and the capacitor structure 103 is electrically connected to the first resistor structure 105.

[0060] Furthermore, the low-voltage enhancement-mode MOS chip 200 has a third source electrode 7, a third drain electrode 8, and a third gate electrode 9. In this embodiment, the startup network formed is applicable to a general startup circuit. When actually packaging the GaN integrated chip 100 and the low-voltage enhancement-mode MOS chip 200 of this embodiment, the first source electrode 1 is connected to the third drain electrode 8 through a wire bonding 46; the first gate electrode 3 is connected to the third source electrode 7 through a wire bonding 46, such that one end of the first gate electrode 3 is used as an output end and is commonly used as a source end after being connected to the third source electrode 7; at the same time, the third source electrode 7 is connected to a corresponding pin 47 through a wire bonding 46; one end of the first drain electrode 2 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of the first drain electrode 2 is used as an output end to be connected to the main circuit of an external circuit (the first drain electrode 2 is used as a drain end); one end of the third gate electrode 9 is connected to a corresponding pin 47 through a wire bonding 46, such that the third gate electrode 9 is used as a gate end; one end of a third resistance electrode 45 away from the second drain electrode 5 is connected to a corresponding pin 47 through a wire bonding 46. Since the second drain electrode 5 in this embodiment is connected in series with a third resistance structure 107, the other end of the third resistance electrode 45 that is not connected to the second drain electrode 5 in the third resistance structure 107 is used as an output end to connect to a high level; one end of the second gate electrode 6 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of the second gate electrode 6 is grounded; one end of the second source electrode 4 is connected to a corresponding pin 47 through a wire bonding 46, such that one end of the second source electrode 4 is used as an output end to supply power to the IC during startup.

[0061] During startup, the startup device 102 is in a conducting state, and current flows through the device to charge the capacitor structure 103, and the capacitor voltage continuously increases, that is, the potential of one end of the second source electrode 4 increases until the IC starts to work. At this time, the current flows from the third resistance structure 107 through the channel of the startup device 102 to the second source electrode 4. After the startup process ends, the driving chip starts to work normally. At this time, the depletion-mode power switch 101 starts to switch. Since the potential of the first source electrode 1 is instantaneously higher than the potential of the second source electrode 4 of the startup device 102 at the instant of turning off during its switching operation, at this time, the current changes to flow from the first drain electrode 2 of the depletion-mode power switch 101, through its channel, then from its first source electrode 1, through the diode structure 104, and finally to the second source electrode 4 to supply power to the control chip. At the same time, the negative potential of the diode structure 104 also raises the potential of the second source electrode 4 of the startup device 102, such that the voltage between the second gate electrode 6 and the second source electrode 4 of the startup device 102 is greater than its turn-off voltage, thereby making the startup device 102 in a turn-off state, and almost no power loss occurs in its circuit.

[0062] This embodiment also provides a method for manufacturing the above-mentioned GaN integrated chip 100, which specifically includes the following steps: Step 1: Perform nitride epitaxial growth on the substrate 108 to successively form a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095. The materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 1091, the buffer layer 1092, the channel layer 1093, the barrier layer 1094, and the cap layer 1095 form a stacked structure, thereby constituting a complete semiconductor epitaxial layer structure, and capable of forming a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 1093 and the barrier layer 1094 to generate a conductive channel. The substrate 108 is one or a combination of materials such as silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing group III nitride materials.

[0063] Step 2: Through photoresist protection, perform patterning and ion material implantation above the cap layer 1095 to destroy the two-dimensional electron gas to form an isolation region. Protect the unimplanted regions as the continuous region chip active area with the first source electrode 1, the first drain electrode 2, and the first gate electrode 3, the continuous region chip active area with the second source electrode 4, the second drain electrode 5, and the second gate electrode 6, and the regions for forming the capacitor structure 103, the diode structure 104, the third resistor structure 107, and the first resistor structure 105, and form the third resistor 42 and the first resistor 40.

[0064] Step 3: Perform patterned etching above the cap layer 1095 to form the first source electrode ohmic hole, the first drain electrode ohmic hole, simultaneously etch to form the second source electrode ohmic hole and the second drain electrode ohmic hole, simultaneously etch to form the first positive electrode hole and the negative electrode hole, and simultaneously perform patterned etching on both sides of the third resistor 42 to form two first ohmic contact holes, and simultaneously perform patterned etching on both sides of the first resistor 40 to form two second ohmic contact holes.

[0065] Step 4: Fill metals in the first source electrode ohmic hole, the first drain electrode ohmic hole, the second source electrode ohmic hole, the second drain electrode ohmic hole, the negative electrode hole, the two first ohmic contact holes and the two second ohmic contact holes to respectively form the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metals 17 on both sides of the third resistor 42 and the third ohmic metals 18 on both sides of the first resistor 40, and perform annealing treatment so that the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the two second ohmic metals 17 and the two third ohmic metals 18 respectively form ohmic contacts with the epitaxial materials below them. The metal includes one or a combination of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0066] Step 5: Deposit a combination including one or more of SiN, SiO2, SiON, and Al2O3 above the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metal 17, and the third ohmic metal 18 to form the first dielectric layer 110, and respectively etch out the first gate trench and the second gate trench. At the same time, etch out the second positive electrode hole at the position of the first positive electrode hole covered by the first dielectric layer 110.

[0067] Step 6: Fill metal above the first dielectric layer 110 to completely cover the first gate trench, the second gate trench, and the second positive electrode hole, and etch to form the first gate electrode metal 12 (the part located in the first gate trench) and the first field plate 20. At the same time, etch to form the second gate electrode metal 15 (the part located in the second gate trench) and the third field plate 22. At the same time, etch to form the Schottky metal 19. At the same time, etch to form the lower electrode 36.

[0068] Step 7: Deposit a combination including one or more of SiN, SiO2, SiON, and Al2O3 above the first gate electrode metal 12, the second gate electrode metal 15, and the lower electrode 36 to form the second dielectric layer 111.

[0069] Step 8: Fill metal above the second dielectric layer 111 and etch to form the second field plate 21, the fourth field plate 23, and the upper electrode 37. Then deposit a combination including one or more of SiN, SiO2, SiON, and Al2O3 above the second field plate 21, the fourth field plate 23, and the upper electrode 37 to form the third dielectric layer 112.

[0070] Step 9: Etch downward from the third dielectric layer 112 to form a first source electrode via, a first drain electrode via, a first gate electrode via, a second source electrode via, a second drain electrode via, a second gate electrode via, two first vias, two second vias, two third vias, and two fourth vias. Among them, the first source electrode via, the first drain electrode via, the first gate electrode via, the second source electrode via, the second drain electrode via, the second gate electrode via, two second vias, two third vias, and two fourth vias all penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. One first via penetrates the third dielectric layer 112 and the second dielectric layer 111, and the other first via penetrates the third dielectric layer 112.

[0071] Step 10: Fill the first source electrode via, the first drain electrode via, the first gate electrode via, the second source electrode via, the second drain electrode via, the second gate electrode via, two first vias, two second vias, two third vias, and two fourth vias with metal to form a first metal connection bar 24, a second metal connection bar 25, a third metal connection bar 26, a fourth metal connection bar 27, a fifth metal connection bar 28, a sixth metal connection bar 29, a seventh metal connection bar 30, an eighth metal connection bar 31, two ninth metal connection bars 32, two first connection segments 33, and two second connection segments 34, respectively.

[0072] Step 11: Metal is filled above the third dielectric layer 112 and etched to form a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a second source electrode 4, a second drain electrode 5, a second gate electrode 6, two capacitor electrodes 38, two diode electrodes 39, two third resistor electrodes 45, and two first resistor electrodes 43. Among them, the two ends of the first metal connection strip 24 are electrically connected to the first source electrode 1 and the first source electrode ohmic metal 10 respectively, the two ends of the second metal connection strip 25 are electrically connected to the first drain electrode 2 and the first drain electrode ohmic metal 11 respectively, and the two ends of the third metal connection strip 26 are electrically connected to the first gate electrode 3 and the first gate electrode metal 12 respectively, forming a depletion-mode power switch 101; the two ends of the fourth metal connection strip 27 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13 respectively, the two ends of the fifth metal connection strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14 respectively, and the two ends of the sixth metal connection strip 29 are electrically connected to the second gate electrode 6 and the second gate electrode metal 15 respectively, forming an enabling device 102; the two ends of the seventh metal connection strip 30 are electrically connected to one capacitor electrode 38 and the lower electrode 36 respectively, the two ends of the eighth metal connection strip 31 are electrically connected to the other capacitor electrode 38 and the upper electrode 37 respectively, forming a capacitor structure 103; the two ends of one ninth metal connection strip 32 are electrically connected to one diode electrode 39 and the first ohmic metal 16 respectively, and the two ends of the other ninth metal connection strip 32 are electrically connected to one diode electrode 39 and the Schottky metal 19 respectively, forming a diode structure 104; the two ends of each first connection segment 33 are connected to the corresponding third resistor electrode 45 and the second ohmic metal 17 respectively, forming a third resistor structure 107; the two ends of each second connection segment 34 are connected to the corresponding first resistor electrode 43 and the third ohmic metal 18 respectively, forming a first resistor structure 105.

[0073] Step 12: One end of the first source electrode 1 is connected to one diode electrode 39 at the positive pole of the corresponding diode structure 104, one end of the second source electrode 4 is connected to one diode electrode 39 at the negative pole of the corresponding diode structure 104, one capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to one diode electrode 39 at the negative pole of the corresponding diode structure 104, one of the third resistor electrodes 45 is connected to the second drain electrode 5, the two ends of one capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 are respectively connected to the second gate electrode 6 and a first resistor electrode 43 close to it, and the other first resistor electrode 43 is connected to one capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, obtaining the GaN integrated chip 100 of this embodiment. Embodiment 3

[0074] As Figure 3As shown, the cascaded device in this embodiment is formed by cascading a low-voltage enhancement-type MOS chip 200 and a GaN integrated chip 100. The GaN integrated chip 100 includes a depletion-type power switch 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The stacked structure includes a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095 arranged in sequence from bottom to top. The cascaded device has a source terminal, a drain terminal, and a gate terminal.

[0075] Further, the structure of the depletion-type power switch 101 in this embodiment is the same as that in Embodiment 1, including a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a first gate electrode metal 12, a first field plate 20, a second field plate 21, a first metal connection bar 24, a second metal connection bar 25, and a third metal connection bar 26. Among them, the first source electrode ohmic metal 10 and the first drain electrode ohmic metal 11 are both located in the barrier layer 1094 and the cap layer 1095; the first gate electrode metal 12 is located in the first dielectric layer 110, the first field plate 20 is located in the second dielectric layer 111, and the second field plate 21 is located in the third dielectric layer 112; the first source electrode 1, the first drain electrode 2, and the first gate electrode 3 are all located above the third dielectric layer 112; the first metal connection bar 24, the second metal connection bar 25, and the third metal connection bar 26 all penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of the first metal connection bar 24 are respectively connected to the first source electrode ohmic metal 10 and the first source electrode 1, the two ends of the second metal connection bar 25 are respectively connected to the first drain electrode ohmic metal 11 and the first drain electrode 2, and the two ends of the third metal connection bar 26 are respectively connected to the first gate electrode metal 12 and the first gate electrode 3. In this embodiment, the depletion-type power switch 101 is provided with a plurality of first source electrode ohmic metals 10 and corresponding first metal connection bars 24, a plurality of first drain electrode ohmic metals 11 and corresponding second metal connection bars 25. The plurality of first source electrode ohmic metals 10 are electrically connected to the first source electrode 1 simultaneously through the plurality of first metal connection bars 24, and the plurality of first drain electrode ohmic metals 11 are electrically connected to the first drain electrode 2 simultaneously through the plurality of second metal connection bars 25.

[0076] Further, as Figure 3As shown in the figure, the starting circuit of this embodiment includes a starting device 102, a capacitor structure 103, a diode structure 104, a third resistor structure 107, a first resistor structure 105, and a second resistor structure 106. Among them, the starting device 102 includes a second source electrode 4, a second drain electrode 5, a second gate electrode 6, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a second gate electrode metal 15, a third field plate 22, a fourth field plate 23, a fourth metal connection bar 27, a fifth metal connection bar 28, and a sixth metal connection bar 29. Among them, the second source electrode ohmic metal 13 and the second drain electrode ohmic metal 14 are both located in the barrier layer 1094 and the capping layer 1095; the second gate electrode metal 15 is located in the first dielectric layer 110, the third field plate 22 is located in the second dielectric layer 111, and the fourth field plate 23 is located in the third dielectric layer 112; the second source electrode 4, the second drain electrode 5, and the second gate electrode 6 are all located above the third dielectric layer 112; the fourth metal connection bar 27, the fifth metal connection bar 28, and the sixth metal connection bar 29 all penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of the fourth metal connection bar 27 are respectively connected to the second source electrode ohmic metal 13 and the second source electrode 4, the two ends of the fifth metal connection bar 28 are respectively connected to the second drain electrode ohmic metal 14 and the second drain electrode 5, and the two ends of the sixth metal connection bar 29 are respectively connected to the second gate electrode metal 15 and the second gate electrode 6. In this embodiment, one second source electrode ohmic metal 13 and the corresponding fourth metal connection bar 27 are each provided, and one second drain electrode ohmic metal 14 and the corresponding fifth metal connection bar 28 are also each provided.

[0077] The capacitor structure 103 of this embodiment includes a lower electrode 36, an upper electrode 37, two capacitor electrodes 38, a seventh metal connection bar 30 located on one side of the lower electrode 36, and an eighth metal connection bar 31 located on one side of the upper electrode 37. Among them, the lower electrode 36 is located in the second dielectric layer 111, the upper electrode 37 is located in the third dielectric layer 112, the two capacitor electrodes 38 are both located above the third dielectric layer 112, the seventh metal connection bar 30 penetrates through the second dielectric layer 111 and the third dielectric layer 112, and its two ends are respectively connected to the lower electrode 36 and one capacitor electrode 38, and the eighth metal connection bar 31 penetrates through the third dielectric layer 112, and its two ends are respectively connected to the upper electrode 37 and the other capacitor electrode 38.

[0078] The diode structure 104 includes a first ohmic metal 16, a Schottky metal 19, two diode electrodes 39, and two ninth metal connection bars 32. Among them, both the first ohmic metal 16 and the Schottky metal 19 are located in the barrier layer 1094 and the capping layer 1095. Both of the two diode electrodes 39 are located above the third dielectric layer 112. Both of the two ninth metal connection bars 32 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of one ninth metal connection bar 32 are respectively connected to the first ohmic metal 16 and one diode electrode 39 to form the negative electrode of the diode structure 104, and the two ends of the other ninth metal connection bar 32 are respectively connected to the Schottky metal 19 and the other diode electrode 39 to form the positive electrode of the diode structure 104.

[0079] The third resistor structure 107 is disposed on one side of the second drain electrode 5 of the enabling device 102. The third resistor structure 107 includes a third resistor 42, second ohmic metals 17 located on both sides of the third resistor 42, two third resistor electrodes 45, and two first connection segments 33. The third resistor structure 107 is connected in series with the second drain electrode 5. Among them, the third resistor 42 is located in the channel layer 1093. Both of the two second ohmic metals 17 are located in the barrier layer 1094 and the capping layer 1095. Both of the two third resistor electrodes 45 are located above the third dielectric layer 112. Both of the two first connection segments 33 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each first connection segment 33 are respectively connected to a corresponding second ohmic metal 17 and one third resistor electrode 45. In this embodiment, the resistance value of the third resistor 42 is 1×10 3 ~5×10 7 Ω.

[0080] The first resistor structure 105 of this embodiment is disposed on one side of the capacitor structure 103 and has the same structure as the third resistor structure 107. Specifically, the first resistor structure 105 includes a first resistor 40, third ohmic metals 18 located on both sides of the first resistor 40, two first resistor electrodes 43, and two second connection segments 34. Among them, the first resistor 40 is located in the channel layer 1093. Both of the two third ohmic metals 18 are located in the barrier layer 1094 and the capping layer 1095. Both of the two first resistor electrodes 43 are located above the third dielectric layer 112. Both of the two second connection segments 34 penetrate through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each second connection segment 34 are respectively connected to a corresponding third ohmic metal 18 and one first resistor electrode 43. In this embodiment, the resistance value of the first resistor 40 is 1×10 3 ~5×10 7 Ω.

[0081] As Figure 3 and Figure 10As shown, the second resistor structure 106 of this embodiment is disposed on the side of the first resistor structure 105 away from the capacitor structure 103. Specifically, the second resistor structure 106 includes a second resistor 41, third connection segments 35 located on both sides of the second resistor 41, and two second resistor electrodes 44. Among them, the second resistor 41 is located in the third dielectric layer 112, both of the two second resistor electrodes 44 are located above the third dielectric layer 112, both of the two third connection segments 35 penetrate through the third dielectric layer 112, and two ends of each third connection segment 35 are respectively connected to a corresponding second resistor 41 and a second resistor electrode 44. In this embodiment, the second resistor 41 is a current detection resistor, and the current detection resistor can further simplify and reduce the peripheral circuit in the PCB board, reduce the loop parasitic parameters while reducing the cost, and is beneficial to improving electromagnetic interference.

[0082] Further, as Figure 3 and Figure 13 shown, in the GaN integrated chip 100 of this embodiment, one end of the first source electrode 1 is connected to a diode electrode 39 of the positive electrode of the corresponding diode structure 104 so that the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, one end of the second source electrode 4 is connected to a diode electrode 39 of the negative electrode of the corresponding diode structure 104 so that the second source electrode 4 is electrically connected to the negative electrode of the diode structure 104, a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to a diode electrode 39 of the negative electrode of the corresponding diode structure 104 so that the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, one of the third resistor electrodes 45 is connected to the second drain electrode 5 so that the third resistor structure 107 is in series with the second drain electrode 5, two ends of a capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 are respectively connected to the second gate electrode 6 and a first resistor electrode 43 close to it, and the other first resistor electrode 43 is connected to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, so that the capacitor structure 103 is also electrically connected to the second gate electrode 6 and the capacitor structure 103 is electrically connected to the first resistor structure 105. Then, a second resistor electrode 44 of the second resistor structure 106 away from the depletion-mode power switch 101 is connected to a first resistor electrode 43 close to it (the first resistor electrode 43 connected to the capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103), so that one end of the second resistor structure 106 is electrically connected to one end of the first resistor structure 105, and the other second resistor electrode 44 of the second resistor structure 106 serves as an output terminal.

[0083] Furthermore, the low-voltage enhancement-mode MOS chip 200 has a third source electrode 7, a third drain electrode 8, and a third gate electrode 9. When actually packaging the GaN integrated chip 100 of this embodiment with the low-voltage enhancement-mode MOS chip 200, the first source electrode 1 is connected to the third drain electrode 8 through a wire bonding 46; the first gate electrode 3 is connected to the third source electrode 7 through a wire bonding 46, so that after the first gate electrode 3 is connected to the third source electrode 7, they are jointly used as the source terminal; one end of the first drain electrode 2 is connected to a corresponding pin 47 through a wire bonding 46, so that one end of the first drain electrode 2 is used as the output terminal to access the main circuit of the external circuit (the first drain electrode 2 is used as the drain terminal); at the same time, the third source electrode 7 is connected to a second resistor electrode 44 of the second resistor structure 106 near the depletion-mode power switch 101 through a wire bonding 46, so that one end of the second resistor structure 106 is used as the output terminal to be connected to the third source electrode 7. In addition, the end where the other second resistor electrode 44 of the second resistor structure 106 of this embodiment is located is used as the ground terminal on the start-up circuit side, and is also the ground terminal after passing through the second resistor structure 106 on the depletion-mode power switch 101 side. One end of the third gate electrode 9 is connected to a corresponding pin 47 through a wire bonding 46, so that the third gate electrode 9 is used as the gate terminal; one end of a third resistor electrode 45 far from the second drain electrode 5 is connected to a corresponding pin 47 through a wire bonding 46. Since the second drain electrode 5 in this embodiment is connected in series with the third resistor structure 107, one end of the other third resistor electrode 45 in the third resistor structure 107 that is not connected to the second drain electrode 5 is used as the output terminal to connect to the high level; one end of the second gate electrode 6 is connected to a corresponding pin 47 through a wire bonding 46, so that one end of the second gate electrode 6 is grounded; one end of the second source electrode 4 is connected to a corresponding pin 47 through a wire bonding 46, so that one end of the second source electrode 4 is used as the output terminal to supply power to the IC during start-up.

[0084] The working principle of the GaN integrated chip 100 in this embodiment during start-up and after start-up is the same as that in Embodiment 2. Compared with Embodiment 2, the second resistor structure 106 (current detection resistor) is introduced in this embodiment, which is beneficial to further simplify and reduce the peripheral circuit in the PCB. While reducing costs, it can reduce loop parasitic parameters and is beneficial to improving electromagnetic interference.

[0085] This embodiment provides a preparation method for the above-mentioned GaN integrated chip 100, which specifically includes the following steps: Step 1: Perform nitride epitaxial growth on the substrate 108 to successively form a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095. The materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 1091, the buffer layer 1092, the channel layer 1093, the barrier layer 1094, and the cap layer 1095 form a stacked structure, thereby constituting a complete semiconductor epitaxial layer structure and capable of forming a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 1093 and the barrier layer 1094 to generate a conductive channel. The substrate 108 is one or a combination of materials such as silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing group III nitride materials.

[0086] Step 2: Through photoresist protection, perform patterning and ion material implantation above the cap layer 1095 to destroy the two-dimensional electron gas to form isolation regions, and protect the unimplanted regions as the continuous region chip active area with the first source electrode 1, the first drain electrode 2, and the first gate electrode 3, the continuous region chip active area with the second source electrode 4, the second drain electrode 5, and the second gate electrode 6, and the regions where the capacitor structure 103, the diode structure 104, the third resistor structure 107, the first resistor structure 105, and the second resistor structure 106 are formed, and form the third resistor 42 and the first resistor 40.

[0087] Step 3: Perform patterned etching above the cap layer 1095 to form the first source electrode ohmic hole and the first drain electrode ohmic hole, and at the same time etch to form the second source electrode ohmic hole and the second drain electrode ohmic hole, and at the same time etch to form the first positive electrode hole and the negative electrode hole. At the same time, perform patterned etching on both sides of the third resistor 42 to form two first ohmic contact holes, and perform patterned etching on both sides of the first resistor 40 to form two second ohmic contact holes.

[0088] Step 4: Fill metals into the first source electrode ohmic hole, the first drain electrode ohmic hole, the second source electrode ohmic hole, the second drain electrode ohmic hole, the negative electrode hole, the two first ohmic contact holes and the two second ohmic contact holes to respectively form the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metals 17 on both sides of the third resistor 42 and the third ohmic metals 18 on both sides of the first resistor 40, and perform annealing treatment so that the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the two second ohmic metals 17 and the two third ohmic metals 18 respectively form ohmic contacts with the epitaxial materials below them. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0089] Step 5: Deposit one or more combinations including SiN, SiO2, SiON, and Al2O3 above the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metal 17, and the third ohmic metal 18 to form the first dielectric layer 110, and respectively etch out the first gate trench and the second gate trench. At the same time, etch out the second positive electrode hole at the position of the first positive electrode hole covered by the first dielectric layer 110.

[0090] Step 6: Fill metal above the first dielectric layer 110 to completely cover the first gate trench, the second gate trench, and the second positive electrode hole, and etch to form the first gate electrode metal 12 (the part located in the first gate trench) and the first field plate 20. At the same time, etch to form the second gate electrode metal 15 (the part located in the second gate trench) and the third field plate 22. At the same time, etch to form the Schottky metal 19. At the same time, etch to form the lower electrode 36.

[0091] Step 7: Deposit one or more combinations including SiN, SiO2, SiON, and Al2O3 above the first gate electrode metal 12, the second gate electrode metal 15, and the lower electrode 36 to form the second dielectric layer 111.

[0092] Step 8: Fill the space above the second dielectric layer 111 with metal and etch to form the second field plate 21, the fourth field plate 23, the upper electrode 37, and the second resistor 41. Then, deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 above the second field plate 21, the fourth field plate 23, the upper electrode 37, and the second resistor 41 to form the third dielectric layer 112. The second resistor 41 generally uses an alloy or a single-layer metal with a low temperature coefficient, high stability, and low resistivity, including one or more combinations of Cu-Mn-Ni, Cu-Ni, Ni-Cr, Ni-Cr-Al-Cu, Cu, and Al.

[0093] Step 9: Etch downward from the third dielectric layer 112 to form a first source electrode via, a first drain electrode via, a first gate electrode via, a second source electrode via, a second drain electrode via, a second gate electrode via, two first vias, two second vias, two third vias, two fourth vias, and two fifth vias. Among them, the first source electrode via, the first drain electrode via, the first gate electrode via, the second source electrode via, the second drain electrode via, the second gate electrode via, two second vias, two third vias, and two fourth vias all penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. One first via penetrates the third dielectric layer 112 and the second dielectric layer 111, and the other first via penetrates the third dielectric layer 112. The two fifth vias both penetrate the third dielectric layer 112.

[0094] Step 10: Fill the first source electrode via, the first drain electrode via, the first gate electrode via, the second source electrode via, the second drain electrode via, the second gate electrode via, two first vias, two second vias, two third vias, two fourth vias, and two fifth vias with metal to form a first metal connection bar 24, a second metal connection bar 25, a third metal connection bar 26, a fourth metal connection bar 27, a fifth metal connection bar 28, a sixth metal connection bar 29, a seventh metal connection bar 30, an eighth metal connection bar 31, two ninth metal connection bars 32, two first connection segments 33, two second connection segments 34, and two third connection segments 35, respectively.

[0095] Step 11: Metal is filled above the third dielectric layer 112 and etched to form a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a second source electrode 4, a second drain electrode 5, a second gate electrode 6, two capacitor electrodes 38, two diode electrodes 39, two third resistor electrodes 45, two first resistor electrodes 43 and two second resistor electrodes 44. Among them, two ends of the first metal connection strip 24 are electrically connected to the first source electrode 1 and the first source electrode ohmic metal 10 respectively, two ends of the second metal connection strip 25 are electrically connected to the first drain electrode 2 and the first drain electrode ohmic metal 11 respectively, two ends of the third metal connection strip 26 are electrically connected to the first gate electrode 3 and the first gate electrode metal 12 respectively, forming a depletion-mode power switch 101; two ends of the fourth metal connection strip 27 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13 respectively, two ends of the fifth metal connection strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14 respectively, two ends of the sixth metal connection strip 29 are electrically connected to the second gate electrode 6 and the second gate electrode metal 15 respectively, forming an enabling device 102; two ends of the seventh metal connection strip 30 are electrically connected to one capacitor electrode 38 and the lower electrode 36 respectively, two ends of the eighth metal connection strip 31 are electrically connected to the other capacitor electrode 38 and the upper electrode 37 respectively, forming a capacitor structure 103; two ends of a ninth metal connection strip 32 are electrically connected to one diode electrode 39 and the first ohmic metal 16 respectively, two ends of the other ninth metal connection strip 32 are electrically connected to one diode electrode 39 and the Schottky metal 19 respectively, forming a diode structure 104; two ends of each first connection segment 33 are connected to the corresponding third resistor electrode 45 and the second ohmic metal 17 respectively, forming a third resistor structure 107; two ends of each second connection segment 34 are connected to the corresponding first resistor electrode 43 and the third ohmic metal 18 respectively, forming a first resistor structure 105; two ends of each third connection segment 35 are connected to the corresponding second resistor electrode 44 and one end of the second resistor 41 respectively, forming a second resistor structure 106.

[0096] Step 12: Connect one end of the first source electrode 1 to a diode electrode 39 corresponding to the positive electrode of the corresponding diode structure 104, connect one end of the second source electrode 4 to a diode electrode 39 corresponding to the negative electrode of the corresponding diode structure 104, connect a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 to a diode electrode 39 corresponding to the negative electrode of the corresponding diode structure 104, connect one of the third resistor electrodes 45 to the second drain electrode 5, connect both ends of a capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 to the second gate electrode 6 and a first resistor electrode 43 adjacent thereto respectively, connect another first resistor electrode 43 to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, connect a second resistor electrode 44 of the second resistor structure 106 far from the depletion-mode power switch 101 to a first resistor electrode 43 adjacent thereto, and use another second resistor electrode 44 of the second resistor structure 106 as the output terminal to obtain the GaN integrated chip 100 of this embodiment.

[0097] The above embodiments of the present invention are only used to illustrate the technical concept and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A GaN integrated chip, characterized in that, It includes a depletion-mode power switch and a starting circuit. The depletion-mode power switch has a first source electrode, a first drain electrode, and a first gate electrode. The starting circuit at least includes a starting device, a capacitive structure, and a diode structure. The starting device has a second source electrode. One end of the first source electrode is electrically connected to the positive electrode of the diode structure. The negative electrode of the diode structure is electrically connected to one end of the second source electrode. The negative electrode of the diode structure is also electrically connected to one end of the capacitive structure. During starting, the starting device is in a conducting state. After starting, the starting device is in a non-conducting state; The starting circuit is used to supply power to the IC during starting. The first source electrode of the depletion-mode power switch is used to continuously supply power to the IC after starting.

2. The GaN integrated chip according to claim 1, characterized in that, The starting device also has a second drain electrode and a second gate electrode. The first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode are all used as output terminals.

3. The GaN integrated chip according to claim 2, characterized in that, The starting circuit includes a starting device, a capacitive structure, and a diode structure. The second gate electrode is used to connect to a control output terminal with a source control start function. One end of the capacitive structure is used to ground.

4. The GaN integrated chip according to claim 2, characterized in that, The starting circuit includes a starting device, a capacitive structure, a diode structure, and a first resistor structure.

5. The GaN integrated chip according to claim 4, characterized in that, Both ends of the first resistor structure are respectively electrically connected to both ends of the capacitive structure. The capacitive structure is also electrically connected to the second gate electrode.

6. The GaN integrated chip according to claim 5, characterized in that, The second gate electrode is used to ground.

7. The GaN integrated chip according to claim 6, characterized in that, The starting circuit also includes a second resistor structure.

8. The GaN integrated chip according to claim 7, characterized in that, The first resistor structure is also electrically connected to one end of the second resistor structure. The other end of the second resistor structure is used as an output terminal.

9. The GaN integrated chip according to claim 8, characterized in that, One end of the second resistor structure used as an output terminal is electrically connected to the source electrode of a cascaded low-voltage enhancement-mode MOS chip.

10. The GaN integrated chip according to claim 9, characterized in that, The second resistor structure is used as a current sensing resistor.

11. The GaN integrated chip according to claim 2, characterized in that, The starting circuit also includes a third resistor structure. The third resistor structure is connected in series with the second drain electrode.

12. A device, characterized in that, It includes a low-voltage enhancement-mode MOS chip and a GaN integrated chip as described in any one of claims 1-11. The device is formed by cascading the low-voltage enhancement-mode MOS chip and the GaN integrated chip.

13. The device according to claim 12, characterized in that, It includes a source end, a drain end, and a gate end. The low-voltage enhancement-mode MOS chip has a third source electrode, a third drain electrode, and a third gate electrode. After the first gate electrode is connected to the third source electrode, they are jointly used as the source end. The third gate electrode is used as the gate end. The first drain electrode is used as the drain end.

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