Low-noise double-loop double-sampling phase-locked loop suitable for low power supply voltage power supply

Abstract

The invention discloses a low-noise double-loop double-sampling phase-locked loop suitable for low power supply voltage power supply, and the phase-locked loop comprises a double-sampling phase discriminator which converts the phase difference between a reference clock and a feedback signal into a voltage difference, and then the voltage difference is respectively connected to charge pumps based on a floating capacitor transconductance amplifier in an integral path and a proportional path; converting the voltage difference into a current; the active low-pass filter adds the output current values of the two paths and then filters the output current values as the control voltage of the voltage-controlled oscillator, so that the output signal frequency of the voltage-controlled oscillator can be adjusted; an output signal of the voltage-controlled oscillator generates a feedback signal through the multimode frequency divider, the steps are repeated, and the frequency and the phase of the feedback signal are consistent with those of the reference clock finally; therefore, the area of the chip is reduced, and the stability of the circuit is ensured.

Description

Technical Field

[0001] The present invention relates to the field of electronic communication technologies, and particularly to a low-noise dual-loop dual-sampling phase-locked loop suitable for low supply voltage power supply. Background Art

[0002] With the development of the information age, the continuous emergence of technologies such as 5G communication technology and Internet of Things, high-data-rate communication systems have gradually become the focus of development and research. The radio frequency transceiver is a basic module in wireless communication and is an essential component in wireless communication devices such as mobile phones, satellite communications, and radars. The radio frequency transceiver system mainly includes three functional modules: a receiver, a transmitter, and a frequency synthesizer. The frequency synthesizer provides a local oscillator signal for the transceiver, and its phase noise determines the performance of the entire transceiver system. As the most widely used frequency synthesizer, the phase-locked loop is often applied to data converters, wireless communication systems, clock generators, etc.

[0003] Modern communication technologies with high data rates pose challenging requirements for phase-locked loops (PLLs) in terms of power consumption, cost, phase noise, etc. Taking a 112 Gb / s PAM4 with a 7-bit 56 GS / s sampling rate analog-to-digital converter as an example, when the clock jitter exceeds 36 fs rms, the signal-to-noise ratio at the Nyquist rate drops by 3 dB. In a radio frequency direct sampling architecture receiver, when using a 12-bit high-speed analog-to-digital converter and the sampling rate exceeds 20 GS / s, it also faces the problem of clock jitter limiting the signal-to-noise ratio. Therefore, a low-jitter phase-locked loop circuit is very crucial in modern communication systems with increasingly high data rates.

[0004] Digital calibration and equalization circuits powered by low supply voltages are often used in analog-digital mixed-signal circuits, such as SerDes transceivers and radio frequency front-end circuits, etc., which can greatly improve the energy efficiency ratio of the circuit.

[0005] The on-resistance of MOS transistors is high and the noise performance deteriorates under low supply voltages. Therefore, it faces great challenges to achieve a high-speed and low-noise phase-locked loop under low supply voltage conditions.

[0006] Dual-sampling phase-locked loops have attracted much attention due to their extremely low phase noise. In a dual-sampling phase-locked loop, a dual-sampling phase detector based on a bootstrap switch is used instead of a traditional phase detector. The gain of the dual-sampling phase detector based on a bootstrap switch depends on the slew rate of the reference clock signal, and its gain is usually greater than that of the traditional phase detector. Therefore, it can greatly suppress the noise of the phase detector and charge pump and achieve extremely small jitter. The disadvantage is that when the gain of the phase detector increases, the bandwidth of the phase-locked loop increases, which may make the loop unstable. Therefore, the gain of the phase detector in a dual-sampling phase-locked loop needs to be compromised between phase noise and loop stability.

[0007] The double-loop phase-locked loop is widely used due to the design flexibility of its loop bandwidth. The double-loop phase-locked loop consists of two paths: an integral path and a proportional path. The low-pass filter in the traditional phase-locked loop is split into two paths. The integral path consists of an integrating capacitor and a charge pump, and the proportional path consists of a resistor, a capacitor, and a charge pump. By adjusting the ratio of the charge pump currents and the capacitors in the two paths, the pole positions can be adjusted, ensuring the stability of the phase-locked loop while reducing the capacitor area, and providing more flexibility in designing the transfer function of the phase-locked loop.

[0008] The problem is that the charge pump charging and discharging current mismatches in the two paths will introduce spurs. Especially at low supply voltages, the channel length modulation effect of MOS transistors in advanced processes is more obvious. Using a cascode current mirror structure to suppress the channel length modulation effect will reduce the output swing and thus reduce the output frequency tuning range of the voltage-controlled oscillator. Summary of the Invention

[0009] The present invention provides a low-noise double-loop double-sampling phase-locked loop suitable for low supply voltage power supply, which solves the above problems in the prior art, that is, it reduces the chip area and ensures the stability of the circuit.

[0010] The present invention provides a low-noise double-loop double-sampling phase-locked loop suitable for low supply voltage power supply, including: a double-sampling phase detector based on a bootstrap switch, a proportional charge pump based on a floating capacitor transconductance amplifier, an integrating charge pump based on a floating capacitor transconductance amplifier, an active low-pass filter, a voltage-controlled oscillator, and a multi-mode frequency divider;

[0011] The double-sampling phase detector based on a bootstrap switch is used to perform two-phase non-overlapping processing on the feedback signal to obtain a first sampling clock and a second sampling clock and sample the reference clock according to the first sampling clock the second sampling clock to obtain a first sampling signal; convert the phase difference of the first sampling signal into a voltage difference, and obtain a corresponding first voltage according to the voltage difference;

[0012] The proportional charge pump based on a floating capacitor transconductance amplifier uses the proportional charge pump and a pulse signal to convert the first voltage into a first current; wherein, the pulse signal is generated according to the first sampling clock and the second sampling clock ;

[0013] The integrating charge pump based on a floating capacitor transconductance amplifier uses the integrating charge pump and the pulse signal to convert the first voltage into a second current;

[0014] The active low-pass filter is used to filter the sum of the first current and the second current to obtain a control voltage;

[0015] The voltage-controlled oscillator is used to generate an output signal according to the control voltage;

[0016] The multi-mode frequency divider is used to obtain a feedback signal according to the output signal.

[0017] In a possible implementation manner, the reference clock is sampled according to the first sampling clock the second sampling clock to obtain a first sampling signal; converting the phase difference of the first sampling signal into a voltage difference, and obtaining a corresponding first voltage according to the voltage difference, including:

[0018] When the first sampling clock is at a falling edge, the double-sampling phase detector based on a bootstrap switch samples the reference clock to obtain a first sampling voltage; and when the second sampling clock is at a high level, the double-sampling phase detector based on a bootstrap switch performs charge sharing on the first sampling voltage to obtain the positive voltage value of the first voltage;

[0019] When the first sampling clock is at a rising edge, the double-sampling phase detector based on a bootstrap switch samples the reference clock to obtain a second sampling voltage; and when the second sampling clock is at a high level, the double-sampling phase detector based on a bootstrap switch performs charge sharing on the second sampling voltage to obtain the negative voltage value of the first voltage.

[0020] In a possible implementation manner, the double-sampling phase detector based on a bootstrap switch includes: a gate voltage bootstrap switch S1, a gate voltage bootstrap switch S2, a gate voltage bootstrap switch S3, a gate voltage bootstrap switch S4, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4;

[0021] The first end of the gate voltage bootstrap switch S1 is connected to the reference clock, and the second end of the gate voltage bootstrap switch S1 is connected to the first end of the gate voltage bootstrap switch S3 and the first end of the capacitor C1;

[0022] The second end of the gate voltage bootstrap switch S3 is connected to the first end of the capacitor C3, the positive input end of the floating-capacitor transconductance amplifier integrating charge pump, and the positive input end of the floating-capacitor transconductance amplifier proportional charge pump;

[0023] The second end of the capacitor C1 is grounded;

[0024] The second terminal of the capacitor C3 is grounded;

[0025] The first terminal of the bootstrap switch S2 is connected to the reference clock, and the second terminal of the bootstrap switch S2 is connected to the first terminal of the bootstrap switch S4 and the first terminal of the capacitor C2;

[0026] The second terminal of the bootstrap switch S4 is connected to the first terminal of the capacitor C4, the negative input terminal of the floating-capacitor transconductance amplifier-based integrating charge pump, and the negative input terminal of the floating-capacitor transconductance amplifier-based proportional charge pump;

[0027] The second terminal of the capacitor C2 is grounded;

[0028] The second terminal of the capacitor C4 is grounded.

[0029] In a possible implementation manner, the control signal of the bootstrap switch S1 is the first sampling clock

[0030] The control signal of the bootstrap switch S2 is the inverse signal of the first sampling clock ;

[0031] The control signal of the bootstrap switch S3 is the second sampling clock

[0032] The control signal of the bootstrap switch S4 is the inverse signal of the second sampling clock ;

[0033] In a possible implementation manner, the bootstrap switch S1, the bootstrap switch S2, the bootstrap switch S3, and the bootstrap switch S4 all include: transistor NMOS1, transistor NMOS2, transistor NMOS3, transistor PMOS1, transistor NMOS4, capacitor C BST ., transistor PMOS2, transistor PMOS3, transistor PMOS4, and transistor NMOS11;

[0034] The drain of the transistor NMOS1 is connected to the second terminal of the capacitor C BST , the source of the transistor NMOS4, and the drain of the transistor PMOS1; the source of the transistor NMOS1 is connected to the source of the transistor NMOS2 and grounded; the gate of the transistor NMOS1 is connected to the inverse signal of the first sampling clock ;

[0035] The gate of the transistor NMOS2 is connected to the first sampling clock Reverse signal connection; the drain of the transistor NMOS2 is connected to the source of the transistor NMOS3;

[0036] The gate of the transistor NMOS3 is connected to the voltage VDD; the drain of the transistor NMOS3 is connected to the drain of the transistor PMOS2;

[0037] The source of the transistor PMOS2 is connected to the first end of the capacitor C BST and the drain of the transistor PMOS4; the gate of the transistor PMOS2 is connected to the drain of the transistor PMOS3 and the drain of the transistor NMOS4;

[0038] The source of the transistor PMOS3 is connected to the source of the transistor PMOS4 and the voltage VDD; the gate of the transistor PMOS3 is connected to the first sampling clock and the gate of the transistor NMOS4;

[0039] The gate of the transistor PMOS1 is connected to the reverse signal of the first sampling clock ; the source of the transistor PMOS1 is connected to the reference clock and the source of the transistor NMOS11;

[0040] The gate of the transistor NMOS11 is connected to the drain of the transistor PMOS2 and the gate of the transistor PMOS4; the drain of the transistor NMOS11 is the output terminal.

[0041] In a possible implementation manner, the parameters of the floating-capacitor transconductance amplifier proportional charge pump and the floating-capacitor transconductance amplifier integrating charge pump are different, and the circuit structures are the same.

[0042] In a possible implementation manner, the floating-capacitor transconductance amplifier proportional charge pump uses the charge pump based on the floating-capacitor transconductance amplifier in the integration path to convert the first voltage into a first current according to the pulse signal including:

[0043] When the pulse signal is at a high level, the floating-capacitor transconductance amplifier 1 is in a reset state, and the output current of the floating-capacitor transconductance amplifier 1 is 0;

[0044] When the pulse signal is at a low level, the floating-capacitor transconductance amplifier 1 is in a working state, and the floating-capacitor transconductance amplifier 1 converts the first voltage into a first current.

[0045] In a possible implementation manner, the floating-capacitor transconductance amplifier proportional charge pump and the floating-capacitor transconductance amplifier integrating charge pump both include: a first output branch, a second output branch, a first reset branch, a second reset branch, a floating-capacitor branch, an upper pull tail current source branch, and a lower pull tail current source branch connected in parallel.

[0046] In a possible implementation manner, the first output branch includes: transistor PMOS5 and transistor NMOS5;

[0047] The second output branch includes: transistor NMOS8 and transistor PMOS8;

[0048] The first reset branch includes: transistor PMOS6 and transistor NMOS6;

[0049] The second reset branch includes: transistor PMOS7 and transistor NMOS7;

[0050] The upper pull tail current source branch includes: transistor M IBP1 and transistor M IBP2 ;

[0051] The lower pull tail current source branch includes: transistor M IBN1 and transistor M IBN2 ;

[0052] The floating-capacitor branch includes: transistor PMOS9, transistor NMOS9, transistor PMOS10, transistor NMOS10, switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7, switch K8, capacitor C FC1 and capacitor C FC2 ;

[0053] The source of the transistor NMOS5 is connected to the source of the transistor NMOS6, the drain of the transistor M IBN1 , and the source of the transistor NMOS9; the gate of the transistor NMOS5 is connected to the reference clock; the drain of the transistor NMOS5 is connected to the drain of the transistor PMOS5;

[0054] The gate of the transistor PMOS5 is connected to the inverted signal of the reference clock; the source of the transistor PMOS5 is connected to the source of the transistor PMOS6, the drain of the transistor M IBP1 , and the source of the transistor PMOS9;

[0055] The source of the transistor M IBP1 is connected to the source of the transistor M IBP2 and the power supply voltage VDD; the transistor MIBP1 The gate of is connected to the transistor M IBP2 The gate of, and the bias voltage VIBP are connected;

[0056] The gate of the transistor PMOS6 is connected to the reference clock; the drain of the transistor PMOS6 is connected to the drain of the transistor NMOS6;

[0057] The gate of the transistor NMOS6 is connected to the inverted signal of the reference clock;

[0058] The drain of the transistor PMOS9 is connected to the first end of the switch K3; the gate of the transistor PMOS9 is connected to the positive end of the first voltage;

[0059] The second end of the switch K3 is connected to the second end of the switch K1, the second end of the switch K5, the first end of the switch K7, the first end of the capacitor C FC2 The first end of, the first end of the capacitor C FC1 The first end;

[0060] The first end of the switch K1 is grounded; the second end of the switch K7 is grounded;

[0061] The capacitor C FC1 The second end of is connected to the second end of the switch K2, the first end of the switch K4, the first end of the switch K6, the first end of the switch K8;

[0062] The first end of the switch K2 is connected to the power supply voltage VDD; the second end of the switch K8 is connected to the power supply voltage VDD;

[0063] The second end of the switch K4 is connected to the drain of the transistor NMOS9;

[0064] The gate of the transistor NMOS9 is connected to the positive end of the first voltage;

[0065] The gate of the transistor PMOS10 is connected to the negative end of the first voltage; the source of the transistor PMOS10 is connected to the drain of the transistor M IBP2 The drain of, the source of the transistor PMOS7, the source of the transistor PMOS8 are connected; the drain of the transistor PMOS10 is connected to the first end of the switch K5;

[0066] The second end of the switch K5 is connected to the first end of the capacitor C FC2 ;

[0067] The capacitor C FC2 The second end of is connected to the first end of the switch K6;

[0068] The second terminal of the switch K6 is connected to the drain of the transistor NMOS10;

[0069] The gate of the transistor NMOS10 is connected to the negative terminal of the first voltage; the source of the transistor NMOS10 is connected to the drain of the transistor M IBN2 , the source of the transistor NMOS7, and the source of the transistor NMOS8;

[0070] The gate of the transistor M IBN1 is connected to the gate of the transistor M IBN2 and the bias voltage VIBN; the source of the transistor M IBN1 is connected to the source of the transistor M IBN2 and grounded;

[0071] The gate of the transistor NMOS7 is connected to the inverted signal of the reference clock; the drain of the transistor NMOS7 is connected to the drain of the transistor PMOS7;

[0072] The gate of the transistor NMOS8 is connected to the reference clock; the drain of the transistor NMOS8 is connected to the drain of the transistor PMOS8;

[0073] The gate of the transistor PMOS7 is connected to the reference clock;

[0074] The gate of the transistor PMOS8 is connected to the inverted signal of the reference clock.

[0075] One or more technical solutions provided in the present invention have at least the following technical effects or advantages:

[0076] By adopting a low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage, the present invention introduces a dual-loop phase-locked loop structure and an active low-pass filter suitable for the dual-loop structure. By setting the current magnitude ratio of the integration path and the loop path, the loop stability can be guaranteed while reducing the chip area; effectively solving the problem that in the case of low power supply voltage, the cascode current mirror structure that suppresses the channel length modulation effect will reduce the output swing and thus reduce the output frequency adjustment range of the voltage-controlled oscillator. Furthermore, both the chip area is reduced and the circuit stability is ensured. Description of the Drawings

[0077] Figure 1 is a schematic structural diagram of a low-noise dual-loop dual-sampling phase-locked loop circuit suitable for low power supply voltage provided by an embodiment of the present invention;

[0078] Figure 2 is a circuit diagram of a dual-sampling phase detector based on a bootstrap switch provided by an embodiment of the present invention;

[0079] Figure 3 This is the circuit diagram of the gate voltage bootstrap switch in the dual-sampling phase detector based on the bootstrap switch provided by the embodiment of the present invention;

[0080] Figure 4 This is the circuit diagram of the charge pump based on the floating-capacitor transconductance amplifier provided by the embodiment of the present invention;

[0081] Figure 5 This is the working timing diagram and linearity comparison diagram of the charge pump based on the floating-capacitor transconductance amplifier provided by the embodiment of the present invention;

[0082] Figure 6 This is the circuit diagram of the active low-pass filter provided by the embodiment of the present invention;

[0083] Figure 7 This is the working timing diagram of the active low-pass filter provided by the embodiment of the present invention. Detailed implementation manners

[0084] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0085] The present invention provides a low-noise dual-loop dual-sampling phase-locked loop applicable to low power supply voltage, see Figure 1 , including: a dual-sampling phase detector based on a bootstrap switch, a proportional charge pump based on a floating-capacitor transconductance amplifier, an integrating charge pump based on a floating-capacitor transconductance amplifier, an active low-pass filter, a voltage-controlled oscillator, and a multi-mode frequency divider.

[0086] The dual-sampling phase detector based on the bootstrap switch is used to perform two-phase non-overlapping processing on the feedback signal to obtain a first sampling clock and a second sampling clock and sample the reference clock according to the first sampling clock the second sampling clock to obtain a first sampling signal; convert the phase difference of the first sampling signal into a voltage difference, and obtain a corresponding first voltage and pulse signal according to the voltage difference

[0087] Here, sampling the reference clock according to the first sampling clock the second sampling clock to obtain a first sampling signal; converting the phase difference of the first sampling signal into a voltage difference, and obtaining a corresponding first voltage includes:

[0088] When the first sampling clock is at the falling edge, the double-sampling phase detector based on the bootstrap switch samples the reference clock to obtain the first sampling voltage; and when the second sampling clock is at a high level, the double-sampling phase detector based on the bootstrap switch performs charge sharing on the first sampling voltage to obtain the positive voltage value of the first voltage;

[0089] When the first sampling clock is at the rising edge, the double-sampling phase detector based on the bootstrap switch samples the reference clock to obtain the second sampling voltage; and when the second sampling clock is at a high level, the double-sampling phase detector based on the bootstrap switch performs charge sharing on the second sampling voltage to obtain the negative voltage value of the first voltage.

[0090] Specifically, referring to Figure 2 and Figure 3 , the double-sampling phase detector based on the bootstrap switch includes: a gate voltage bootstrap switch S1, a gate voltage bootstrap switch S2, a gate voltage bootstrap switch S3, a gate voltage bootstrap switch S4, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4; wherein, Figure 2 FCOTA in

[0091] represents a floating-capacitor transconductance amplifier-based proportional charge pump and a floating-capacitor transconductance amplifier-based integrating charge pump.

[0092] The first terminal of the gate voltage bootstrap switch S1 is connected to the reference clock, and the second terminal of the gate voltage bootstrap switch S1 is connected to the first terminal of the gate voltage bootstrap switch S3 and the first terminal of the capacitor C1;

[0093] The second terminal of the gate voltage bootstrap switch S3 is connected to the first terminal of the capacitor C3, the positive input terminal of the floating-capacitor transconductance amplifier-based integrating charge pump, and the positive input terminal of the floating-capacitor transconductance amplifier-based proportional charge pump;

[0094] The second terminal of the capacitor C1 is grounded;

[0095] The first terminal of the gate voltage bootstrap switch S2 is connected to the reference clock, and the second terminal of the gate voltage bootstrap switch S2 is connected to the first terminal of the gate voltage bootstrap switch S4 and the first terminal of the capacitor C2;

[0096] The second terminal of the gate voltage bootstrap switch S4 is connected to the first terminal of the capacitor C4, the negative input terminal of the floating-capacitor transconductance amplifier-based integrating charge pump, and the negative input terminal of the floating-capacitor transconductance amplifier-based proportional charge pump;

[0097] The second terminal of the capacitor C2 is grounded;

[0098] The second terminal of the capacitor C4 is grounded.

[0099] Specifically, in a double-sampling phase detector based on a bootstrap switch, the bootstrap switches S1, S2, S3, and S4 each include: transistor NMOS1, transistor NMOS2, transistor NMOS3, transistor PMOS1, transistor NMOS4, and capacitor C BST , transistor PMOS2, transistor PMOS3, transistor PMOS4, and transistor NMOS11.

[0100] The drain of transistor NMOS1 is connected to the second end of capacitor C BST , the source of transistor NMOS4, and the drain of transistor PMOS1; the source of transistor NMOS1 is connected to the source of transistor NMOS2 and grounded; the gate of transistor NMOS1 is connected to the inverted signal of the first sampling clock .

[0101] The gate of transistor NMOS2 is connected to the inverted signal of the first sampling clock ; the drain of transistor NMOS2 is connected to the source of transistor NMOS3;

[0102] The gate of transistor NMOS3 is connected to voltage VDD; the drain of transistor NMOS3 is connected to the drain of transistor PMOS2;

[0103] The source of transistor PMOS2 is connected to the first end of capacitor C BST , the drain of transistor PMOS4; the gate of transistor PMOS2 is connected to the drain of transistor PMOS3 and the drain of transistor NMOS4;

[0104] The source of transistor PMOS3 is connected to the source of transistor PMOS4 and voltage VDD; the gate of transistor PMOS3 is connected to the gate of transistor NMOS4; The gate of transistor NMOS4;

[0105] The drain of transistor PMOS4 is connected to the first end of capacitor C BST ;

[0106] The gate of transistor PMOS1 is connected to the inverted signal of the first sampling clock ; the source of transistor PMOS1 is connected to the reference clock and the source of transistor NMOS11;

[0107] The gate of transistor NMOS11 is connected to the drain of transistor PMOS2 and the gate of transistor PMOS4; the drain of transistor NMOS11 is the output terminal.

[0108] Exemplarily, the working principle of the double-sampling phase detector based on a bootstrap switch: At the first sampling clock When it is at a high level, the gate voltage bootstrap switch S1 conducts, and the first sampling clock When it is at a low level, the gate voltage bootstrap switch S1 turns off, and samples the reference clock voltage value at the falling edge of the first sampling clock onto the capacitor C1 and holds it; when the second sampling clock is at a high level, the gate voltage bootstrap switch S3 conducts, and charge sharing occurs between the capacitor C1 and the capacitor C3. When the first sampling clock is at a low level, the gate voltage bootstrap switch S2 conducts, and the first sampling clock When it is at a high level, the gate voltage bootstrap switch S2 turns off, and samples the reference clock voltage value at the rising edge of the first sampling clock onto the capacitor C2 and holds it; when the second sampling clock signal is at a low level, the gate voltage bootstrap switch S4 conducts, and charge sharing occurs between the capacitor C2 and the capacitor C4.

[0109] Therefore, the voltage value on the capacitor C3 corresponds to the voltage value of the reference clock at the falling edge of the first sampling clock and the voltage value on the capacitor C4 corresponds to the voltage value of the reference clock at the rising edge of the first sampling clock. Theoretically, when the phase-locked loop is locked, the voltage values on the capacitor C3 and the capacitor C4 are equal. The dual-sampling phase detector based on the bootstrap switch converts the phase difference between the reference clock and the feedback signal f into a voltage difference. Fb

[0110] Under the condition of low power supply voltage, the on-resistances of the transmission gate and the transmission tube are relatively large. Therefore Figure 2 all four switches in it adopt gate voltage bootstrap switches, which can keep the gate-source voltage of the switching tube equal to the power supply voltage, reduce the on-resistance and improve the sampling accuracy. The gain of the dual-sampling phase detector based on the bootstrap switch depends on the slope of the reference clock edge. The larger the slope, the greater the phase detector gain.

[0111] Based on the floating-capacitor transconductance amplifier proportional charge pump, the first voltage is converted into a first current by using the proportional charge pump and the pulse signal ;

[0112] Here, based on the floating-capacitor transconductance amplifier proportional charge pump, the first voltage is converted into a first current by using the proportional charge pump and the pulse signal , including:

[0113] When the pulse signal is at a high level, the floating-capacitor transconductance amplifier 1 is in a reset state, and the output current of the floating-capacitor transconductance amplifier 1 is 0;

[0114] When the pulse signal ​When it is at a low level, the floating-capacitor transconductance amplifier 1 is in an operating state, and the floating-capacitor transconductance amplifier 1 converts the first voltage into a first current.

[0115] Based on the floating-capacitor transconductance amplifier integrating charge pump, using the integrating charge pump and the pulse signal convert the first voltage into a second current;

[0116] Here, based on the floating-capacitor transconductance amplifier proportional charge pump and the floating-capacitor transconductance amplifier integrating charge pump, the parameter settings are different, but the circuit structures are the same. The charge pump circuit structures in the integration path and the proportional path are the same, but the transistor sizes in the circuit are different, and the transconductance based on the floating-capacitor transconductance amplifier is also different. For the same first voltage, the magnitudes of the output currents are different.

[0117] Specifically, referring to Figure 4 , the floating-capacitor transconductance amplifier proportional charge pump and the floating-capacitor transconductance amplifier integrating charge pump both include: a first output branch, a second output branch, a first reset branch, a second reset branch, a floating-capacitor branch, an upper pull tail current source branch, and a lower pull tail current source branch.

[0118] The first output branch includes: transistor PMOS5 and transistor NMOS5;

[0119] The second output branch includes: transistor NMOS8 and transistor PMOS8;

[0120] The first reset branch includes: transistor PMOS6 and transistor NMOS6;

[0121] The second reset branch includes: transistor PMOS7 and transistor NMOS7;

[0122] The upper pull tail current source branch includes: transistor M IBP1 and transistor M IBP2 ;

[0123] The lower pull tail current source branch includes: transistor M IBN1 and transistor M IBN2 ;

[0124] The floating-capacitor branch includes: transistor PMOS9, transistor NMOS9, transistor PMOS10, transistor NMOS10, switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7, switch K8, capacitor C FC1 and capacitor C FC2 ;

[0125] The source of transistor NMOS5 is connected to the sources of transistor NMOS6 and transistor M IBN1is connected to the drain of [transistor], the source of transistor NMOS9; the gate of transistor NMOS5 is connected to the reference clock; the drain of transistor NMOS5 is connected to the drain of transistor PMOS5;

[0126] the gate of transistor PMOS5 is connected to the inverted signal of the reference clock; the source of transistor PMOS5 is connected to the source of transistor PMOS6, the drain of transistor M IBP1 is connected to the source of transistor PMOS9;

[0127] transistor M IBP1 is connected to the source of transistor M IBP2 is connected to the source of transistor M IBP1 the gate of transistor M IBP2 is connected to the gate of transistor M, the bias voltage VIBP;

[0128] the gate of transistor PMOS6 is connected to the reference clock; the drain of transistor PMOS6 is connected to the drain of transistor NMOS6;

[0129] the gate of transistor NMOS6 is connected to the inverted signal of the reference clock;

[0130] the drain of transistor PMOS9 is connected to the first terminal of switch K3; the gate of transistor PMOS9 is connected to the positive terminal of the first voltage;

[0131] the second terminal of switch K3 is connected to the second terminal of switch K1, the second terminal of switch K5, the first terminal of switch K7, the first terminal of capacitor C FC2 the first terminal of capacitor C FC1 the first terminal;

[0132] the first terminal of switch K1 is grounded; the second terminal of switch K7 is grounded;

[0133] capacitor C FC1 the second terminal is connected to the second terminal of switch K2, the first terminal of switch K4, the first terminal of switch K6, the first terminal of switch K8;

[0134] the first terminal of switch K2 is connected to the power supply voltage VDD; the second terminal of switch K8 is connected to the power supply voltage VDD;

[0135] the second terminal of switch K4 is connected to the drain of transistor NMOS9;

[0136] the gate of transistor NMOS9 is connected to the positive terminal of the first voltage;

[0137] the gate of transistor PMOS10 is connected to the negative terminal of the first voltage; the source of transistor PMOS10 is connected to transistor M IBP2is connected to the drain of, the source of transistor PMOS7, and the source of transistor PMOS8; the drain of transistor PMOS10 is connected to the first end of switch K5;

[0138] The second end of switch K5 is connected to the first end of capacitor C FC2 ;

[0139] The second end of capacitor C FC2 is connected to the first end of switch K6;

[0140] The second end of switch K6 is connected to the drain of transistor NMOS10;

[0141] The gate of transistor NMOS10 is connected to the negative terminal of the first voltage; the source of transistor NMOS10 is connected to the drain of transistor M IBN2 and the source of transistor NMOS7 and the source of transistor NMOS8;

[0142] Transistor M IBN1 has its gate connected to the gate of transistor M IBN2 and the bias voltage VIBN; the source of transistor M IBN1 is connected to the source of transistor M IBN2 and is grounded;

[0143] The gate of transistor NMOS7 is connected to the inverted signal of the reference clock, and the drain of transistor NMOS7 is connected to the drain of transistor PMOS7;

[0144] The gate of transistor NMOS8 is connected to the reference clock; the drain of transistor NMOS8 is connected to the drain of transistor PMOS8;

[0145] The gate of transistor PMOS7 is connected to the reference clock; the source of transistor PMOS7 is connected to the drain of transistor M IBP2 and the source of transistor PMOS8;

[0146] The gate of transistor PMOS8 is connected to the inverted signal of the reference clock.

[0147] Exemplarily, the working timing of the floating-capacitor transconductance amplifier-based proportional charge pump is as Figure 5 shown. The voltage output from the bootstrap-switch-based dual-sampling phase detector is converted into a current signal and fed into the subsequent active low-pass filter. The working principle is as follows:

[0148] Transistors M IBP1 , transistors M IBP2 , transistors M IBN1 , transistors M IBN2 have currents of I IBP1 , I IBP2 , I IBN1, I IBN2 。

[0149] Transistor M IBP1 , transistor M IBP2 and transistor M IBN1 , transistor M IBN2 is controlled by the bias voltage VIBP and the bias voltage V IBN to control the current magnitude.

[0150] Among them, transistor M IBP1 has the same size as transistor M IBP2 , transistor M IBN1 has the same size as transistor M IBN2 , so I IBP1 = I IBP2 , I IBN1 = I IBN2 . When the output voltage fluctuates within a certain range, there is I IBP1 = I IBP2 = I IBN1 = I IBN2 .

[0151] When the reference clock is at a low level, the current flowing through the first output branch and the second output branch is 0, and the current I IBP1 , I IBP2 , I IBN1 , I IBN2 flows through the first reset branch and the second reset branch.

[0152] When the reference clock is at a high level, the first reset branch and the second reset branch are turned off, and the current flows through the first output branch and the second output branch. The pulse signal controls the reset and turn-on of the floating capacitor amplifier.

[0153] (1) After charge sharing is completed in the bootstrap switch-based dual-sampling phase detector, a pulse signal is generated. When the pulse signal is at a low level, the upper plates of capacitor C FC1 and capacitor C FC2 are discharged to ground, the lower plates are charged to the power supply voltage, and the capacitor floating amplifier is in the reset state. At this time, the charging current of the output node I OUT+ in the first output branch is equal to the discharging current of the output node I OUT1- in the second output branch, that is, the total output current of the floating capacitor transconductance amplifier proportional charge pump and the floating capacitor transconductance amplifier integrating charge pump is 0.

[0154] (2) When the pulse signal is at a high level, capacitor C FC1and capacitor C FC2 The upper plate starts to charge and the lower plate starts to discharge, and current flows through the first output branch, the second output branch, and the floating capacitor amplifier. Current I IBP1 、I IBP2 、I IBN1 、I IBN2 remains constant in magnitude, so we have I OUT+ =(I IBP1 -I1)-(I IBN1 -I3), I OUT- =(I IBP2 -I2)-(I IBN2 -I4), and after simplification we have I OUT+ =I3-I1, I OUT -=I4-I2.

[0155] By adjusting the aspect ratios of the transistors PMOS and NMOS in the floating capacitor branch, specifically, adjusting the aspect ratios of PMOS9, NMOS9, PMOS10, and NMOS10, such that when the input of the floating transconductance amplifier V S+ =V S- =V CM =V DDL / 2, we have I1=I3 and I2=I4, and at this time the output current is 0.

[0156] When V S+ increases and V S- decreases, I1 and I4 decrease, while I2 and I3 increase, that is, I OUT+ increases and I OUT- decreases; when V S+ decreases and V S- increases, I1 and I4 increase, while I2 and I3 decrease, that is, I OUT+ decreases and I OUT- increases. At the same time, this pseudo-differential structure makes it such that when the first voltage is near the common mode of the reference clock we have I1+I2=I3+I4, that is, I1-I3=I4-I2, and thus the output current I OUT+ =-I OUT- . Based on the floating capacitor transconductance amplifier, the differential voltage V S+ -V S- obtained from the first voltage is converted into a differential output current I OUT+ -I OUT- .

[0157] The periodic reset of the floating capacitor ensures that the charge and discharge transistors can operate in the saturation region at low supply voltages, improving the matching of the charge pump charge and discharge currents. Adding the first reset branch and the second reset branch causes when the reference clock switches from a low level to a high level, the transistor MIBP1 , transistor M IBP2 , transistor M IBN1 , transistor M IBN2 , the voltage change of the drain decreases, and the current flowing through transistor M IBP1 , transistor M IBP2 , transistor M IBN1 , transistor M IBN2 will not change suddenly, improving the stability of the output current.

[0158] The active low-pass filter is used to filter the sum of the first current and the second current to obtain a control voltage;

[0159] Exemplarily, referring to Figure 6 and Figure 7 , in the active low-pass filter, is the reference clock The differential clock generated by dividing the frequency by two, can be passed through respectively with the reference clock is generated by a logic gate.

[0160] In the integration path, the current directly charges the capacitor C LPF , and the differential output voltage is:

[0161]

[0162] where s is the complex frequency of the Laplace transform, also represents the phase when the pulse signal maintains a high level. V OUTP (s), V OUTN (s) are the output voltages of the fully differential operational amplifier, and I Int+ (s), I Int- (s) are the input integration currents.

[0163] The working principle in the proportional path: Taking single-ended input as an example, the transfer function in the case of differential input can be derived according to the superposition theorem.

[0164] (1) When is at a high level, the proportional current I Prop- charges the capacitor C Prop , and the charging time is the duration of the high level of the pulse signal The voltage of the left plate of the capacitor C rises, and the voltage of the right plate is clamped by the operational amplifier and remains at V Prop , where T CM is the period of the reference clock ref , and is half of the power supply voltage;

[0165] (2) When is at a low level and is at a high level, for the capacitor C Prop the voltages of the left and right plates are both V CM , according to the principle of charge conservation, all the charges on the capacitor C Prop are transferred to the capacitor C LPF , and the voltage of the left plate of the capacitor C LPF is V CM . Therefore,

[0166] Figure 6 in the single-ended proportional path, two capacitors C Prop are alternately charged. According to the superposition principle, the relationship expression between the output voltage of the fully differential operational amplifier in Figure 6 and the input proportional current can be obtained as:

[0167]

[0168] where I Prop+ (s), I Prop- (s) are the input proportional currents. f Ref is the reference clock frequency.

[0169] According to the superposition principle, after adding the transfer functions of the proportional path and the integral path and filtering, the overall transfer function of the active low-pass filter in Figure 1 is obtained as:

[0170]

[0171] where I Int (s) = I Int+ (s) - I Int- (s), I Prop (s) = I Prop+ (s) - I Prop- (s), I Prop (s) = α·I Int (s), R Pole is the resistor in the RC low-pass filter, and C Pole is the capacitor in the RC low-pass filter. The constant α is the ratio of the output currents of the charge pumps based on the floating-capacitor transconductance amplifier in the proportional path and the integral path.

[0172] The integral path introduces a pole at the origin in the transfer function, and the proportional path introduces a zero in the transfer function. By controlling the ratio α of the output currents of the charge pumps based on the floating-capacitor amplifier in the proportional path and the integral path, the zero position can be adjusted. The output of the fully differential operational amplifier is connected to an RC low-pass filter, which introduces a non-zero pole in the transfer function, and its output voltage VTune-p / n is the control voltage of the voltage-controlled oscillator.

[0173] The voltage-controlled oscillator is used to adjust the frequency of the output signal according to the control voltage to obtain the output signal;

[0174] The multi-mode frequency divider is used to obtain a feedback signal according to the output signal.

[0175] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, reference can be made to each other. The key points of each embodiment are the differences from other embodiments. All or part of the present invention can be used in many general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multi-processor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on.

[0176] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A low noise dual loop dual sampling phase locked loop suitable for low power supply voltage, characterized in that: include: Double sampling phase detector based on bootstrap switch, proportional charge pump based on floating capacitor transconductance amplifier, integrating charge pump based on floating capacitor transconductance amplifier, active low pass filter, voltage controlled oscillator and multi-mode divider; The dual sampling phase detector based on the bootstrap switch is used to process the feedback signal in two phases without overlapping to obtain a first sampling clock and the second sampling clock And according to the first sampling clock The second sampling clock Sampling a reference clock to obtain a first sampling signal; converting a phase difference of the first sampling signal into a voltage difference, and obtaining a corresponding first voltage according to the voltage difference; The floating capacitor transconductance amplifier proportional charge pump utilizes a proportional charge pump and a pulse signal The first voltage is converted into a first current; wherein the pulse signal is based on the first sampling clock and the second sampling clock generated; The floating capacitor transconductance amplifier based integral charge pump utilizes the integral charge pump and the pulse signal converting the first voltage into a second current; The active low-pass filter is used to add the first current and the second current and then filter to obtain a control voltage; The voltage controlled oscillator is used to generate an output signal according to the control voltage; The multi-mode frequency divider is used to obtain a feedback signal according to the output signal.

2. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 1, characterized in that: The first sampling clock The second sampling clock Sampling a reference clock to obtain a first sampling signal; Converting the phase difference of the first sampling signal into a voltage difference, and obtaining a corresponding first voltage according to the voltage difference, comprises: When the first sampling clock At the falling edge, the dual sampling phase detector based on the bootstrap switch samples the reference clock to obtain a first sampling voltage; and when the second sampling clock When it is at a high level, the dual sampling phase detector based on the bootstrap switch performs charge sharing on the first sampling voltage to obtain a forward voltage value of the first voltage; When the first sampling clock is at a rising edge, the dual sampling phase detector based on the bootstrap switch samples the reference clock to obtain a second sampling voltage; and when the second sampling clock When it is at a high level, the dual sampling phase detector based on the bootstrap switch performs charge sharing on the second sampling voltage to obtain a negative voltage value of the first voltage.

3. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 1, characterized in that: The dual sampling phase detector based on the bootstrap switch comprises: a gate voltage bootstrap switch S1, a gate voltage bootstrap switch S2, a gate voltage bootstrap switch S3, a gate voltage bootstrap switch S4, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4; The first end of the gate voltage bootstrap switch S1 is connected to the reference clock, and the second end of the gate voltage bootstrap switch S1 is connected to the first end of the gate voltage bootstrap switch S3 and the first end of the capacitor C1; The second end of the gate voltage bootstrap switch S3 is connected to the first end of the capacitor C3, the positive input end of the integral charge pump based on the floating capacitor transconductance amplifier, and the positive input end of the proportional charge pump based on the floating capacitor transconductance amplifier; The second end of the capacitor C1 is grounded; The second end of the capacitor C3 is grounded; The first end of the gate voltage bootstrap switch S2 is connected to the reference clock, and the second end of the gate voltage bootstrap switch S2 is connected to the first end of the gate voltage bootstrap switch S4 and the first end of the capacitor C2; The second end of the gate voltage bootstrap switch S4 is connected to the first end of the capacitor C4, the negative input end of the integral charge pump based on the floating capacitor transconductance amplifier, and the negative input end of the proportional charge pump based on the floating capacitor transconductance amplifier; The second end of the capacitor C2 is grounded; The second terminal of the capacitor C4 is grounded.

4. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 3, characterized in that: The control signal of the gate voltage bootstrap switch S1 is the first sampling clock The control signal of the gate voltage bootstrap switch S2 is the first sampling clock The counter signal of The control signal of the gate voltage bootstrap switch S3 is the second sampling clock The control signal of the gate voltage bootstrap switch S4 is the second sampling clock The counter signal.

5. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 3, characterized in that: The gate voltage bootstrap switch S1, the gate voltage bootstrap switch S2, the gate voltage bootstrap switch S3 and the gate voltage bootstrap switch S4 all include: a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor PMOS1, a transistor NMOS4, a capacitor C BST , transistor PMOS2, transistor PMOS3, transistor PMOS4 and transistor NMOS11; The drain of the transistor NMOS1 and the capacitor C BST The second end of the transistor NMOS4 is connected to the source of the transistor NMOS4 and the drain of the transistor PMOS1; the source of the transistor NMOS1 is connected to the source of the transistor NMOS2 and is grounded; the gate of the transistor NMOS1 is connected to the first sampling clock Reverse signal connection; The gate of the transistor NMOS2 is connected to the first sampling clock The drain of the transistor NMOS2 is connected to the source of the transistor NMOS3; The gate of the transistor NMOS3 is connected to the voltage VDD; the drain of the transistor NMOS3 is connected to the drain of the transistor PMOS2; The source of the transistor PMOS2 and the capacitor C BST The first end of the transistor PMOS2 is connected to the drain of the transistor PMOS3 and the drain of the transistor NMOS4; the gate of the transistor PMOS2 is connected to the drain of the transistor PMOS3 and the drain of the transistor NMOS4; The source of the transistor PMOS3 is connected to the source of the transistor PMOS4 and the voltage VDD; the gate of the transistor PMOS3 is connected to the first sampling clock The gate of the transistor NMOS4 is connected; The gate of the transistor PMOS1 is connected to the first sampling clock The source of the transistor PMOS1 is connected to the reference clock and the source of the transistor NMOS11; The gate of the transistor NMOS11 is connected to the drain of the transistor PMOS2 and the gate of the transistor PMOS4; the drain of the transistor NMOS11 is an output terminal.

6. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 1, characterized in that: The proportional charge pump based on the floating capacitor transconductance amplifier and the integral charge pump based on the floating capacitor transconductance amplifier have different parameter settings, but the circuit structures are the same.

7. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 6, characterized in that: The floating capacitor transconductance amplifier proportional charge pump utilizes an integral path based on the floating capacitor transconductance amplifier proportional charge pump according to the pulse signal. Converting the first voltage into a first current comprises: When the pulse signal When it is at a high level, the floating capacitor transconductance amplifier 1 is in a reset state, and the output current of the floating capacitor transconductance amplifier 1 is 0; When the pulse signal When it is at a low level, the floating capacitor transconductance amplifier 1 is in a working state, and the floating capacitor transconductance amplifier 1 converts the first voltage into a first current.

8. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 1, characterized in that: The floating capacitor transconductance amplifier-based proportional charge pump and the floating capacitor transconductance amplifier-based integral charge pump both include: a first output branch, a second output branch, a first reset branch, a second reset branch and a floating capacitor branch, a pull-up tail current source branch and a pull-down tail current source branch connected in parallel.

9. The low-noise dual-loop dual-sampling phase-locked loop suitable for low power supply voltage according to claim 8, characterized in that: The first output branch includes: a transistor PMOS5 and a transistor NMOS5; The second output branch includes: a transistor NMOS8 and a transistor PMOS8; The first reset branch includes: a transistor PMOS6 and a transistor NMOS6; The second reset branch includes: a transistor PMOS7 and a transistor NMOS7; The pull-up tail current source branch includes: a transistor M IBP1 and transistor M IBP2 ; The pull-down tail current source branch includes: a transistor M IBN1 and transistor M IBN2 ; The floating capacitor branch includes: transistor PMOS9, transistor NMOS9, transistor PMOS10, transistor NMOS10, switch K1, switch K2, switch K3, switch K4, switch K5, switch K6, switch K7, switch K8, capacitor C FC1 and capacitor C FC2 ; The source of the transistor NMOS5 and the source of the transistor NMOS6, the transistor M IBN1 The drain of the transistor NMOS9 is connected to the source of the transistor NMOS9; the gate of the transistor NMOS5 is connected to the reference clock; the drain of the transistor NMOS5 is connected to the drain of the transistor PMOS5; The gate of the transistor PMOS5 is connected to the reverse signal of the reference clock; the source of the transistor PMOS5 is connected to the source of the transistor PMOS6, the source of the transistor M IBP1 The drain of the transistor PMOS9 is connected to the source of the transistor PMOS9; The transistor M IBP1 The source of the transistor M IBP2 The source of the transistor M IBP1 The gate of the transistor M IBP2 The gate and bias voltage VIBP are connected; The gate of the transistor PMOS6 is connected to the reference clock; the drain of the transistor PMOS6 is connected to the drain of the transistor NMOS6; The gate of the transistor NMOS6 is connected to the reverse signal of the reference clock; The drain of the transistor PMOS9 is connected to the first end of the switch K3; the gate of the transistor PMOS9 is connected to the positive end of the first voltage; The second end of the switch K3 is connected to the second end of the switch K1, the second end of the switch K5, the first end of the switch K7, the capacitor C FC2 The first end of the capacitor C FC1 The first end of The first end of the switch K1 is grounded; the second end of the switch K7 is grounded; The capacitor C FC1 The second end of the switch K2 is connected to the second end of the switch K4, the first end of the switch K6, and the first end of the switch K8; The first end of the switch K2 is connected to the power supply voltage VDD; the second end of the switch K8 is connected to the power supply voltage VDD; The second end of the switch K4 is connected to the drain of the transistor NMOS9; The gate of the transistor NMOS9 is connected to the positive end of the first voltage; The gate of the transistor PMOS10 is connected to the negative end of the first voltage; the source of the transistor PMOS10 is connected to the negative end of the transistor M IBP2 The drain of the transistor PMOS10 is connected to the first end of the switch K5; the source of the transistor PMOS7 and the source of the transistor PMOS8 are connected; the drain of the transistor PMOS10 is connected to the first end of the switch K5; The second end capacitor C of the switch K5 FC2 A first end is connected; The capacitor C FC2 The second end of is connected to the first end of the switch K6; The second end of the switch K6 is connected to the drain of the transistor NMOS10; The gate of the transistor NMOS10 is connected to the negative end of the first voltage; the source of the transistor NMOS10 is connected to the negative end of the transistor M IBN2 The drain of the transistor NMOS7, the source of the transistor NMOS8 are connected; The transistor M IBN1 The gate of the transistor M IBN2 The gate of the transistor M is connected to the bias voltage VIBN; IBN1 The source of the transistor M IBN2 The source of is connected and grounded; The gate of the transistor NMOS7 is connected to the inverse signal of the reference clock, and the drain of the transistor NMOS7 is connected to the drain of the transistor PMOS7; The gate of the transistor NMOS8 is connected to the reference clock; the drain of the transistor NMOS8 is connected to the drain of the transistor PMOS8; The gate of the transistor PMOS7 is connected to the reference clock; The gate of the transistor PMOS8 is connected to the inverted signal of the reference clock.

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