An LDPC encoder, transmitter and test platform based on the DVB-S2 protocol

Abstract

The present invention discloses an LDPC encoder, a transmitting end and a test platform based on the DVB-S2 protocol. The LDPC encoder includes an information bit matrix multi-port input RAM for storing input information bits; a check matrix multi-port ROM for storing the check matrix; an accumulated sum matrix RAM for storing the accumulated sum matrix generated by a accumulated sum matrix calculation module; a check bit matrix RAM for storing the check bit matrix; a check matrix calculation module for reading the check matrix from the check matrix multi-port ROM, wherein the check matrix is converted into a cyclic shift matrix after preprocessing; a accumulated sum matrix calculation module for reading the information bits from the information bit matrix multi-port input RAM, performing cyclic right shift and accumulation operations, and calculating to obtain the accumulated sum matrix; and a check bit matrix initialization module for calculating a check bit matrix initialization vector according to the calculation result of the accumulated sum matrix calculation module.

Description

Technical Field

[0001] The present disclosure belongs to the field of satellite communication technology, and in particular relates to an LDPC encoder, a transmitter, and a test platform based on the DVB-S2 protocol. Background Art

[0002] With the rise of low-orbit satellite communications technology, satellite digital video broadcasting has ushered in new application scenarios and market demands. In this context, the DVB-S2 (Digital Video Broadcasting - Satellite Second Generation) protocol, as the core of satellite broadcasting communications, plays a crucial role.

[0003] The DVB-S2 protocol, officially released by the European Telecommunications Standards Institute, aims to improve spectrum efficiency and data transmission rates in satellite communications, replacing the first-generation DVB-S standard. DVB-S2 introduces several key technologies, including LDPC (Low-Density Parity-Check) coding, Bose-Chaudhuri-Hocquenghem (BCH) coding, high-order modulation (such as 8PSK, 16APSK, and 32APSK), and adaptive coding and modulation (ACM). The application of these technologies has enabled DVB-S2 to achieve significant improvements in spectrum efficiency and system performance, particularly in high data rates and high-reliability transmission. LDPC coding, as a key technology, offers unique advantages, primarily reflected in the following three aspects:

[0004] The first point is the longer frame length. The LDPC encoding frame length in the DVB-S2 protocol can be up to 64,800 bits, while the maximum code block length of the LDPC encoding in the 5G NR protocol is typically 8,448 bits. The longer frame length improves spectrum utilization and data transmission efficiency.

[0005] The second point is the unique ACM mechanism. The DVB-S2 protocol supports adaptive coding modulation technology, which can dynamically adjust the LDPC code rate and modulation method according to channel conditions, improving system reliability and efficiency. Other protocols, such as ATSC 3.0, do not have such a flexible ACM mechanism.

[0006] The third point is the unique parity check matrix construction. The LDPC parity check matrix in the DVB-S2 protocol uses a cyclic construction, which facilitates hardware implementation, simplifies hardware circuit design, and reduces hardware complexity. In contrast, the LDPC parity check matrix in the 5G NR protocol uses a polygon-based construction, which is relatively complex to implement in hardware. These unique advantages give the DVB-S2 protocol higher performance and adaptability in satellite communications.

[0007] Given the significant advantages of field programmable gate arrays (FPGAs) in high-throughput data processing and hardware acceleration scenarios, they have become an ideal choice for implementing DVB-S2 transmitter systems. FPGAs offer the following advantages:

[0008] (1) Highly customizable: FPGAs allow designers to customize the hardware architecture according to specific application requirements, enabling targeted optimization. For example, in a DVB-S2 system, designers can flexibly adjust the hardware structure according to different coding rates and modulation methods to achieve optimal performance.

[0009] (2) Rapid prototyping: FPGAs support rapid prototyping, allowing designers to implement and test hardware designs in a short period of time, accelerating product development cycles. This is particularly important when validating new technologies and updating standards, enabling rapid response to market demands.

[0010] (3) Parallel processing capability: FPGAs inherently support large-scale parallel processing and can execute multiple tasks simultaneously. This is particularly critical for applications that require high throughput (such as LDPC encoders) and can significantly improve data processing speed.

[0011] (4) Reconfigurability: FPGA supports online reconfiguration, allowing dynamic adjustment of hardware functions while the system is running, providing flexibility and scalability for satellite communication systems, enabling them to adapt to different mission requirements and channel conditions. Summary of the Invention

[0012] This disclosure relates to a high-speed data transmission transmitter based on the DVB-S2 protocol and its FPGA implementation. This disclosure aims to improve the data transmission rate and reliability in satellite communication systems. By optimizing the parallelized LDPC encoder and DVB-S2 transmitter system, this solution addresses the high processing latency and low hardware resource utilization of traditional solutions in high-data-rate and high-capacity transmission scenarios.

[0013] The contents of this disclosure include:

[0014] An optimized parallel algorithm based on cyclic shift matrices improves encoder throughput;

[0015] Multi-port RAM storage architecture and parity address block mechanism reduce hardware resource usage;

[0016] Compatible with ATSC 3.0 and DVB-S2 check matrices, improving bit error rate performance;

[0017] Complete DVB-S2 transmitter system design, supporting multiple modulation modes and bit rate configurations;

[0018] Build an FPGA-host computer verification platform to achieve comprehensive testing of system performance.

[0019] It has been verified that the transmitter disclosed in the present invention has a throughput of up to 23.4 Gb / s at a clock frequency of 100 MHz, has low resource utilization, and has improved bit error rate performance at different bit rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0021] Figure 1 Figure 1 shows a parity check matrix of an IRA-type LDPC code according to one embodiment of the present disclosure.

[0022] Figure 2 A diagram of a parity check matrix of a MET-type LDPC code according to one embodiment of the present disclosure.

[0023] Figure 3 A schematic diagram of check matrix preprocessing according to one embodiment of the present disclosure.

[0024] Figure 4 Appendix is a schematic diagram of a 2 / 5 code rate LDPC check matrix for a DVB-S2 normal frame according to one embodiment of the present disclosure.

[0025] Figure 5 Schematic diagram of a coe file obtained after preprocessing of the ATSC3.0 normal frame 6 / 15 code rate check matrix according to one embodiment of the present disclosure.

[0026] Figure 6 Flowchart of a check matrix preprocessing algorithm according to one embodiment of the present disclosure.

[0027] Figure 7 A hardware architecture diagram of an LDPC parallel encoder according to one embodiment of the present disclosure.

[0028] Figure 8 A flowchart of a check matrix calculation module implementation according to one embodiment of the present disclosure.

[0029] Figure 9 A flowchart of an implementation of a cumulative sum matrix calculation module according to one embodiment of the present disclosure.

[0030] Figure 10 A diagram showing the overall architecture of a DVB-S2 transmitter system and interface driver according to one embodiment of the present disclosure.

[0031] Figure 11 A diagram of the DVB-S2 transmitter system architecture according to one embodiment of the present disclosure.

[0032] Figure 12 A structural diagram of a linear feedback shift register according to one embodiment of the present disclosure.

[0033] Figure 13 A structural diagram of a data buffer FIFO module according to one embodiment of the present disclosure.

[0034] Figure 14 Experimental diagram comparing FPGA output and Matlab output at different bit rates according to one embodiment of the present disclosure.

[0035] Figure 15 Comparison diagram of output data constellation and IQ data under different modulation modes and code rates according to one embodiment of the present disclosure.

[0036] Figure 16 A comparison chart of the bit error rate performance of DVB-S2 and ATSC parity check matrices at different bit rates according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] After studying existing solutions, this paper found that in practice, there are still the following challenges when implementing an FPGA transmitter based on the DVB-S2 protocol:

[0038] 1) Limitations of current encoding algorithms.

[0039] Although the DVB-S2 protocol supports a variety of code rates and modulation schemes, traditional serial coding schemes often have limitations such as high processing latency and low hardware resource utilization in high-data-rate and high-capacity transmission scenarios. For example, in low-orbit satellite communications, high-speed data transmission between satellites and ground stations places extremely high demands on the throughput and efficiency of coding algorithms, and traditional coding schemes often struggle to meet these requirements. Furthermore, existing parallelized LDPC encoder schemes still have room for improvement in terms of parallelism, throughput, and bit error rate. For example, the latest parallelization methods, such as those reported in the literature, have a maximum parallelism of only 360, and no research has been conducted on the parity check matrix to achieve lower bit error rates. Furthermore, most of these research algorithms have not been fully tested in a complete DVB-S2 transmitter system, which also limits their effectiveness in practical applications.

[0040] 2) FPGA engineering implementation challenges.

[0041] Implementing a DVB-S2 transmitter system based on FPGA, especially a high-throughput LDPC encoder, also faces some engineering challenges.

[0042] First, satellite hardware resources are limited. Hardware resources onboard satellites (such as memory cells and logic gates) are extremely limited, while high-throughput LDPC encoders typically require a large number of parallel computing units and memory resources. Optimizing encoder design within these resource-constrained conditions to achieve high performance while reducing hardware costs is a key issue. This requires clever architectural design and resource reuse techniques to maximize resource utilization. For example, some literature has achieved high throughput, but the resource utilization is too high to be easily deployed on an FPGA.

[0043] Secondly, there are the circuit design requirements for high clock frequencies. In FPGA implementations, increasing clock frequency can significantly improve data throughput, but it also places higher demands on the timing constraints of circuit design. Especially at clock frequencies above 100MHz, operations within each clock cycle must be completed in an extremely short time. This requires careful optimization of circuit paths, reducing critical path delays, and ensuring stable system operation. Furthermore, high clock frequencies can lead to increased power consumption and heat dissipation issues, further increasing design complexity.

[0044] Therefore, the purpose of this disclosure is to provide a design and FPGA implementation method for a high-speed data transmission transmitter based on the DVB-S2 protocol to solve the problems of high processing latency and low hardware resource utilization in existing solutions under high data rate and large-capacity transmission scenarios.

[0045] According to one or more embodiments, a method for designing and implementing a high-speed data transmission transmitter based on the DVB-S2 protocol using an FPGA includes the following steps:

[0046] (1) Optimized parallelization algorithm based on cyclic shift matrix to improve encoder throughput;

[0047] (2) Multi-port RAM storage architecture and parity address block mechanism to reduce hardware resource usage;

[0048] (3) Compatible with ATSC 3.0 and DVB-S2 check matrices, improving bit error rate performance;

[0049] (4) Complete DVB-S2 transmitter system design, supporting multiple modulation modes and bit rate configurations;

[0050] (5) Build an FPGA-host computer verification platform to achieve comprehensive testing of system performance.

[0051] The optimized parallel algorithm based on the cyclic shift matrix improves the throughput of the encoder by optimizing the construction of the check matrix and the encoding process. The specific steps include:

[0052] (1) Preprocess the check matrix and convert it into a cyclic shift matrix form;

[0053] (2) Utilize the properties of the cyclic shift matrix to reduce the clock cycles required for parallel coding calculations;

[0054] (3) In hardware implementation, parallel computing is supported through multi-port read-write RAM and multi-port read-ROM.

[0055] The multi-port RAM storage architecture and parity address blocking mechanism avoid redundant storage by constructing a multi-port RAM and adopting the parity address blocking mechanism to resolve parallel read and write conflicts. The specific design includes:

[0056] (1) Customize multi-port read RAM and multi-port read ROM;

[0057] (2) Use a memory cell array to enable different address lines to access corresponding data simultaneously;

[0058] (3) The cumulative sum matrix and the check bit matrix are stored in two RAMs according to the address parity.

[0059] The compatibility between ATSC 3.0 and DVB-S2 parity check matrices further optimizes the encoder's error correction capability by replacing the parity check matrices of some bit rates in the DVB-S2 protocol with the parity check matrices of the ATSC protocol. Specific implementations include:

[0060] (1) Compare the performance of LDPC coding in DVB-S2 and ATSC 3.0 protocols;

[0061] (2) Select the check matrix corresponding to the bit rate in the ATSC 3.0 protocol for replacement;

[0062] (3) In hardware implementation, adaptive check matrix data is generated through software preprocessing.

[0063] The complete DVB-S2 transmitter system design includes the BB Frame module, FEC module, bit interleaving and mapping module, and PL Frame module. It supports multiple modulation modes such as QPSK, 8PSK, 16APSK, and 32APSK, as well as flexible bit rate configuration. Specific design details include:

[0064] (1) The BB Frame module implements the encapsulation of baseband frames, including adding baseband frame headers, CRC coding, and baseband scrambling;

[0065] (2) The FEC module implements forward error correction coding, including BCH coding and LDPC coding;

[0066] (3) The bit interleaving and mapping module implements bit interleaving and constellation mapping;

[0067] (4) The PL Frame module implements the generation of physical layer frames, including adding PL frame header, PL scrambling, frame header modulation and pilot insertion.

[0068] The FPGA-host computer verification platform is built to verify the implementation and performance of the system through hardware loopback testing. The specific steps include:

[0069] (1) Implementing an interface driver module in the FPGA, responsible for transmitting the encoded data to the host computer in real time via UDP packets;

[0070] (2) Generate random information bits in the host computer and send the data to the encoder in the FPGA through the interface driver module;

[0071] (3) The encoded data is transmitted back to the host computer via UDP packets and compared with the output results of the Matlab toolkit function to verify the correctness of the system implementation;

[0072] (4) Test key indicators such as system throughput, bit error rate performance and resource utilization to evaluate system performance.

[0073] According to one or more embodiments, to address the challenges of improving parallelism and throughput, the present disclosure proposes an LDPC encoder based on the DVB-S2 protocol. This encoder uses an optimized parallelization algorithm based on a cyclic shift matrix to improve throughput. The specific method is as follows:

[0074] 1) DVB-S2 protocol LDPC coding algorithm:

[0075] LDPC codes are roughly divided into two types: IRA (Irregular Repeat Accumulate) and MET (Multi-Edge Type). Figure 1 and Figure 2 As shown. Among them, Indicates the length of information bits , , Represents check bits of different lengths, The matrix is mainly used for encoding information bits. The main function of the matrix is to match the rate. Matrix and The matrix is responsible for the association between information bits at different positions. The matrix is a zero matrix used to introduce the cyclic property, The matrix is the identity matrix. All of the above matrices are derived by expanding the protocol-specified basis matrix. IRA-type LDPC coding is primarily used in the DVB-S2 protocol. Its regular structure makes this coding method easy to implement in hardware. MET-type LDPC coding is primarily used in the 5G NR protocol. This coding method offers high flexibility and adaptability in mobile communications. The ATSC 3.0 protocol uses both LDPC coding methods: MET is primarily used for low bit rates, while IRA is used for high bit rates.

[0076] The LDPC coding in the DVB-S2 protocol adopts the IRA type, and the coded codeword is a systematic code, so the input information bit I can be set to , the encoded check bit P is , the final codeword C is:

[0077]

[0078] Where k is the length of the information bit, r is the length of the check bit, and n=k+r represents the total length of the encoded codeword. According to the encoding principle, the check bit can be calculated using formula (2):

[0079]

[0080] Where H is the dimension The check matrix is composed of two parts:

[0081]

[0082] It is constructed according to the protocol matrix, The dimension is The lower echelon matrix of , expand the two to get:

[0083]

[0084] At the same time, since x+x=0 in the Galois field GF(2), formula (4) can be changed to:

[0085]

[0086] Observe the rule in formula (5) and set the cumulative sum to be ,in :

[0087]

[0088] Therefore, formula (5) can be simplified as:

[0089]

[0090] According to formula (7), the final check digit calculation formula can be obtained by iterative calculation:

[0091]

[0092] The algorithm can be summarized as Algorithm 1:

[0093]

[0094] Therefore, the LDPC coding algorithm can be divided into two main steps: first, calculating the value of each check bit, and second, accumulating these check bits. Therefore, the DVB-S2 LDPC code is called an irregular repeat-accumulate (IRA) code. However, this simple coding method has obvious shortcomings in efficiency because it can only output one check bit at a time, which results in a slow speed. In addition, from the perspective of hardware complexity and resource utilization, this method is also not feasible because it requires storing a large number of The matrix, and the whole message k bits with the matrix It can be seen that a major flaw of this algorithm is that it does not make full use of the matrix Therefore, in order to better utilize the sparsity of the check matrix, some scholars proposed the IRA type parallelization algorithm.

[0095] 2) IRA-type parallel encoding algorithm:

[0096] a) Accumulation and matrix calculation

[0097] In the parallel implementation of coding technology, there are mainly two strategies: one is to use multiple encoders for parallelization, by configuring multiple independent encoder modules on the FPGA, so that it can process different data streams simultaneously, thereby improving the overall coding rate. The second is to achieve parallelization through formula theoretical derivation, by analyzing the mathematical model of the coding algorithm, identifying the parts that can be executed in parallel, and then building the corresponding parallel structure in the hardware. This method not only optimizes the execution efficiency of the algorithm, but also effectively reduces resource usage and is suitable for complex coding standards. Therefore, the IRA type parallel coding algorithm is mainly based on the mathematical model of the coding algorithm for parallel hardware implementation. Reading the DVB-S2 protocol, it can be seen that when constructing the check matrix of the LDPC code, it is constructed by grouping according to 360, so it is possible to consider grouping the input data accordingly:

[0098]

[0099] in, Group by information bit length, for each ( ) indicates the length is The row vector of , specifically:

[0100]

[0101] According to the LDPC coding principle, the key to coding is to solve the value of the cumulative sum s, so s can also be grouped and constructed as follows:

[0102]

[0103] Here That is, grouping is done according to the length of the check bit, and Each row vector in the matrix For example, its bit width is 360 bits, where :

[0104]

[0105] According to formula (6), is the cumulative sum of the products of the information bits and the corresponding row elements of the check matrix. Since the check matrix is a sparse matrix, a large number of cumulative sum items with a product of 0 can be ignored. Only the check matrix elements with a value of 1, that is, The corresponding information bits can be accumulated and calculated. At the same time, the appendix of the protocol specifies the LDPC check matrix information corresponding to different frame lengths and different code rates, and specifies the row index of the element with the first column value 1 in each group of the check matrix. The corresponding row index of each column can be obtained by shifting the row index of the previous column by q bits. It is exactly the sum of each item It is composed of multiple shifts of q bits, so the row vector can be constructed in the manner specified by the protocol. However, it should be noted that the first row index of each group specified in the appendix does not necessarily match the first subscript of the row vector, so it is necessary to cyclically shift the input data right to align them during calculation. Define the function Indicates that the row vector I is circularly shifted right by z bits, and set The row index set of the first column in the x-th group specified in the appendix, the above algorithm can be summarized as Algorithm 2:

[0106]

[0107] b) Check digit matrix calculation

[0108] After calculating the cumulative sum matrix, according to formula (8), the check bit can be obtained by the cumulative sum vector. Therefore, in order to match the parallelization, the check bits need to be grouped to construct the matrix :

[0109]

[0110] Each row vector can be derived by accumulating the matrix:

[0111]

[0112] Here , its first row vector needs to be calculated separately, noting that:

[0113]

[0114] Therefore, we need to solve the initialization row vector, which can be obtained by accumulating the matrix. Let the row vector T be:

[0115]

[0116] Where L is the dimension The lower triangular matrix of is as shown in formula (17), is the transpose of the cumulative sum vector of all rows of the cumulative sum matrix.

[0117]

[0118] Now let the function The row vector I is logically shifted right by z bits, then it can be observed that the row vector T is shifted right by one bit to obtain the initialization vector:

[0119]

[0120] Therefore, the calculation algorithm for the check bit matrix can be summarized as Algorithm 3:

[0121]

[0122] After the check bit matrix is calculated, all the encoded check bits can be obtained, but the above parallelization algorithm still has two shortcomings: the first is that there is room for optimization in the clock cycle consumption of the cumulative sum matrix during the encoding calculation. Since the matrix needs to be stored in RAM when calculating the cumulative sum matrix in hardware, and its row vector is calculated based on the row index value in the appendix of the DVB-S2 protocol, and the position of the index value is not necessarily arranged in sequence, the row vector stored in the same RAM address may be calculated multiple times, so two clock cycles need to be read and written in one calculation, but when calculating the check bit matrix, only the RAM storing the matrix needs to be written, so only one clock cycle is required. Assume that the number of row index values of the single bit rate in the appendix is N, so the clock cycle required to calculate the entire check bit matrix and the check bit matrix is at least Secondly, the calculated check bit matrix stores the check bits in a column-by-column order, which is not conducive to the RAM outputting the check bits in row address order. Therefore, it is necessary to reorder the results to meet the requirements of parallel output. To address this shortcoming, this disclosure proposes a cyclic shift parallel encoding algorithm.

[0123] c) Cyclic shift parallel coding algorithm

[0124] Check matrix preprocessing: According to the properties of cyclic shift, it is easy to implement in hardware. That is, when calculating the product, we only need to know the subscript of the first row of non-zero elements, and then perform the corresponding cyclic right shift on the vector. Therefore, we can consider performing corresponding processing on the LDPC check matrix and transforming it into a cyclic shift matrix to reduce the clock cycles required for parallel coding calculation. Since the LDPC check matrix in the DVB-S2 protocol is an IRA type with the characteristics of group structure, the check matrix Construct a submatrix by splicing every q rows ,in :

[0125]

[0126] At this time, the matrix is divided into t groups according to the group length 360. ,in :

[0127]

[0128] It can be seen that by constructing the above transformation, the IRA type check matrix Converted into A matrix composed of sub-matrices , where each submatrix yes -dimensional cyclic shift matrix:

[0129]

[0130] from Figure 3 It can be seen more intuitively.

[0131] In equation (9), the input information bits have been grouped, and the cumulative sum matrix is constructed by equation (11). At this time, it is noted that the first row vector in the cumulative sum matrix, the grouped information bits, and the transformed check matrix satisfy the expression:

[0132]

[0133] Therefore, it can be deduced that other row vectors in the cumulative sum matrix also satisfy the expression:

[0134]

[0135] Notice yes dimensional cyclic shift matrix, and each matrix has multiple non-zero elements in the first row. At the same time, due to the sparsity of the check matrix, the transformed matrix There will be many zero matrices. Calculating the zero matrix will still result in a zero matrix. Therefore, we need to find a matrix that is not a zero matrix. Let's calculate. Let the set Represents calculation The corresponding circulant matrix contains non-zero elements And its corresponding Group input data , then according to the properties of the cyclic shift matrix:

[0136]

[0137] From Equation (24), we can see that if the information bits and the transformed check matrix information are pre-stored, the calculation of the row vectors can be performed in parallel. And since the check bit matrix is also calculated based on the cumulative sum matrix, the check bit matrix can be calculated in parallel according to the above derivation. Assuming the parallelism parameter m = 2, the LDPC optimization coding algorithm in the DVB-S2 protocol can be summarized as Algorithm 4:

[0138]

[0139] From the process of Algorithm 4, it can be seen that the total number of clock cycles required to complete the encoding is , because when calculating the cumulative sum matrix, the set is obtained after matrix preprocessing So that each row vector can be calculated in sequence , and can be directly written into RAM after the calculation is completed, so only one write clock cycle is required. In addition, due to the sequential calculation and different row vectors and can be calculated in parallel, so the final number of clock cycles is given by Reduce to If the degree of parallelism parameter m=2, the speed of calculating the cumulative sum matrix can be increased by about four times, and the speed of calculating the check bit can be increased by about two times. However, the speed improvement of this algorithm comes at the cost of space, that is, all the information bits of the current frame need to be stored during encoding. In addition, in order to parallelize the operation, and Hardware is required to implement multi-port read and write RAM and multi-port read ROM.

[0140] Furthermore, in order to reduce the bit error rate, the embodiment of the present disclosure proposes to establish a compatibility mechanism between ATSC 3.0 and DVB-S2 parity check matrices to reduce the bit error rate. The specific method is as follows:

[0141] a) Check matrix replacement:

[0142] The implementation and application of LDPC coding vary across different communication protocols, such as the DVB-S2 protocol and the ATSC 3.0 protocol. These two protocols, targeting satellite TV and terrestrial digital television respectively, employ different LDPC coding schemes to suit their specific application scenarios and requirements. The ATSC 3.0 standard employs two different structures: the IRA structure for high bit rates and the MET structure for low bit rates, while the DVB-S2 protocol uses only one, the IRA structure. When investigating and comparing LDPC coding performance, it was found that the ATSC 3.0 protocol achieved an FER of 100%. The gap between the required SNR and the capacity limit under the AWGN channel is better than that of the DVB-S2 protocol.

[0143] Compared to the LDPC code in the DVB-S2 protocol, the ATSC 3.0 protocol's LDPC code requires a lower signal-to-noise ratio to achieve a specific bit error rate under the same conditions and is closer to the channel capacity limit. Therefore, in the DVB-S2 hardware implementation, the parity check matrix can be replaced with the ATSC 3.0 protocol's LDPC code parity check matrix, achieving more efficient signal transmission and stronger interference immunity. However, due to the differences in the LDPC codes between the two protocols, only the common parts are replaced. Note that the ATSC 3.0 protocol's bit rates of 6 / 15, 9 / 15, 10 / 15, and 12 / 15 all use an IRA structure and correspond precisely to the DVB-S2 protocol's bit rates of 2 / 5, 3 / 5, 2 / 3, and 4 / 5, respectively. Therefore, these rates are selected for replacement.

[0144] Furthermore, in order to implement the above method on an FPGA and reduce resource utilization, the present disclosure implements the parallelized LDPC algorithm proposed in Algorithm 4 on an FPGA and designs a multi-port RAM storage architecture and an even-odd address partitioning mechanism to reduce resource utilization. The specific method is as follows:

[0145] 1) Software architecture design

[0146] The software architecture mainly uses Python code to pre-process the LDPC check matrix and replace the check matrix of the corresponding bit rate with the check matrix of the ATSC 3.0 protocol. After the calculation is completed, a coe file is generated and stored in ROM. The check matrix stored in ROM can be quickly accessed during encoding, avoiding the delay caused by real-time calculation.

[0147] a) Check matrix data structure design: The appendix of the DVB-S2 protocol document specifies the structure of the LDPC coding check matrix in detail. According to different frame lengths and code rates, the appendix sets corresponding parameters to adapt to various application requirements. According to the introduction of the coding principle in the DVB-S2 protocol, the LDPC check matrix is divided into t groups with 360 columns as a group. This grouping method makes the management and processing of the check matrix more efficient. Specifically, each row of data in the appendix represents the index of the first column value of 1 in each group. These indexes not only indicate the key position of the check bit, but also provide the necessary basis for the subsequent check bit calculation. The remaining 360-1 column value 1 index is obtained by offsetting the index value of the first column, and the offset is This structured design effectively reduces the computational complexity and improves the efficiency of the encoder. Figure 4 The data example is shown.

[0148] However, this representation method will lead to an increase in the number of clock cycles consumed when parallelizing the hardware implementation. In order to optimize this problem, it is necessary to preprocess the check matrix to reduce the clock cycles required during the encoding process. Through effective preprocessing, the complexity of the hardware implementation can be significantly reduced and the overall efficiency of the system can be improved. The specific preprocessing methods are as follows: Figure 3 This figure shows how to transform the original check matrix into a structure that is more suitable for parallel computing. Ultimately, the goal of preprocessing is to construct the set , this set will be used to store the non-zero element indexes in the transformed cyclic shift matrix and the corresponding number of input information bit groups, which needs to be processed into the form of Table 3. In this way, non-zero elements can be effectively managed and accessed, thereby accelerating the subsequent calculation process.

[0149] In order to realize hardware storage, the data in the table needs to be stored in ROM, so the data must be processed, converted into hexadecimal format, and the corresponding coe file must be generated. First, The maximum value of the number of groups of input information bits will not exceed the number of groups t. It can be stored using 7-bit binary numbers. Indicates the number of cyclic right shifts required for the information bit row vector of the current group. Since the data is grouped by 360 bits, The maximum value will not exceed 360, which means It can be stored using 9-bit binary numbers. It should be noted that the tuples in each row The number of groups may be different, but the maximum number of groups does not exceed 6. Therefore, the total number of bits required to store a row of data is ( bits. For data with less than 6 groups, all 0s will be used to fill them in order to ensure that the length of each row of data is consistent. In addition, since the data in the ROM is stored in the order of row addresses, the y value does not need to consume additional storage space and can be directly represented by the row address. Finally, all the data will be converted into hexadecimal format after processing. The result of the generated coe file is as follows Figure 5 The data example is shown.

[0150] b) Implementation of the check matrix preprocessing system

[0151] The implementation of the check matrix preprocessing system mainly relies on two core functions: GetHMatrixMap and GetHMatrixMapTable. These two functions are designed to efficiently process and generate check matrix mappings for different bit rates. The GetHMatrixMap function reads the check matrix data from the specified file, constructs the corresponding file name based on the input bit rate and type (for example, ATSC or DVB-S2), and then reads the file content. The GetHMatrixMapTable function uses the GetHMatrixMap function to obtain the check matrix mapping, thereby rearranging the matrix and obtaining the valid information index to implement the check matrix preprocessing. The specific algorithm flow of the check matrix preprocessing is as follows Figure 6 shown. Figure 6The flowchart of the check matrix preprocessing algorithm is described, which explains how to generate and process the check matrix map (matrix_map) according to the input code rate (code_rate) and protocol type (type). Among them, matrix_map represents the check matrix construction information read from the protocol, n represents the total codeword length, k is the information bit length, r is the check bit length, t is the number of information bit groups, q is the number of check bit groups, matrix_group and rearranged_matrix_group represent the constructed check matrix and the rearranged check matrix respectively, group, i and idx are used to count the number of different groups respectively, and finally the matrix subscripts i and j are used to store them in matrix_map_table, which is the data set after the check matrix preprocessing. .

[0152] 2) Hardware architecture design

[0153] The overall design of the hardware architecture is as follows Figure 7 As shown, it includes an information bit matrix multi-port RAM, a check bit matrix multi-port ROM, a check matrix calculation module, an accumulated sum matrix calculation module, an accumulated sum matrix RAM, a check bit matrix initialization module, a check bit matrix calculation module, a check bit matrix RAM and a data flow control module. First, the information bit is input through data_in and stored in the multi-port read-write RAM. Then, the check bit matrix calculation module reads multiple check matrix data from the check bit matrix multi-port read ROM at the same time to parse and obtain the corresponding The value is then read from the information bit matrix RAM, and the cumulative sum matrix calculation module performs a circular right shift and accumulation operation to obtain the cumulative sum matrix, which is stored in the cumulative sum matrix RAM. At the same time, the check bit matrix initialization vector is calculated by accumulating the row vectors obtained each time. Then the check bit matrix calculation module reads the cumulative sum matrix value of the corresponding address to calculate the check bit, reorders it, and stores it in the check bit matrix RAM. Finally, the data flow control module controls the output of the information bit and check bit through the enable signal en to obtain data_out.

[0154] Figure 7 This paper describes the hardware architecture design of a low-density parity-check code (LDPC) encoder in detail. The design consists of several key modules, each of which performs a specific function to implement the LDPC encoding process. The hardware architecture includes the following modules:

[0155] (1) Input-RAM (information bit matrix multi-port RAM) - responsible for storing the input information bits (data_in), supports multi-port access, and allows multiple data to be read from RAM at the same time for parallel processing.

[0156] (2) Hmatrix-ROM (check matrix multi-port ROM) - stores the check matrix. The multi-port ROM allows reading multiple check matrix data at the same time for subsequent calculations.

[0157] (3) SMatrix Calc Core (cumulative sum matrix calculation module) - reads information bits from Input RAM, performs circular right shift and accumulation operations, and stores the calculated cumulative sum matrix in SMatrix RAM.

[0158] (4) SMatrix RAM (Sum Matrix RAM) - stores the intermediate results generated by the sum matrix calculation module.

[0159] (5) HMatrix Calc Core (check matrix calculation module) - reads the check matrix data from the HMatrix ROM, parses it to obtain the corresponding generator polynomial (ϕ) and check polynomial (ψ) values, and uses them for check matrix calculation.

[0160] (6) PMatrix Init Core (check bit matrix initialization module) - calculates the check bit matrix initialization vector based on each calculation result of the cumulative matrix calculation module.

[0161] (7) PMatrix Calc Core (check bit matrix calculation module) - reads the value in the cumulative matrix RAM, calculates the check bit, and reorders it. The calculation result is stored in the PMatrix RAM.

[0162] (8) PMatrix RAM (check bit matrix RAM) - stores the check bits generated by the check bit matrix calculation module.

[0163] (9) Encoder Control Core (data flow control module) - responsible for controlling the data flow of the entire encoder, controlling the output of information bits and check bits through the enable signal (en), and generating the final encoded output (data_out) and valid output signal (valid_out).

[0164] The workflow of these modules includes:

[0165] The input information bits are first stored in the Input-RAM; the check matrix calculation module reads the check matrix data from the HMatrix ROM and parses it; the cumulative sum matrix calculation module reads the information bits from the Input RAM, performs circular right shift and accumulation operations, and stores the results in the SMatrix RAM. Each calculation result of the cumulative sum matrix is used to calculate the check bit matrix initialization vector; the check bit matrix calculation module reads the cumulative sum matrix value in the SMatrix RAM, calculates the check bits and reorders them, and stores the results in the PMatrix RAM; finally, the data flow control module controls the output of the information bits and check bits through the control signal en to obtain the encoded data (data_out).

[0166] Furthermore, the hardware architecture utilizes a multi-port RAM / ROM architecture. While the default IP core provided by Vivado only supports dual-port RAM, the method proposed in this disclosure supports a variety of options due to the selected degree of parallelism m. For example, if data from four addresses needs to be read simultaneously, dual-port RAM cannot achieve this. Using multiple single-port RAMs to store the same data for simultaneous reading would result in multiple copies of the data, wasting storage space. Therefore, to meet the design requirements of high-performance systems, custom multi-port RAM and ROM are key to achieving efficient data processing. The design of a multi-port RAM first requires defining several key parameters, including address width (ADDR_WIDTH), data width (DATA_WIDTH), memory depth (DEPTH), and the number of read ports (NUM_READ_PORTS). During implementation, Verilog was used to construct a custom multi-port read / single-port write RAM and a multi-port read ROM. By using a memory cell array, data can be accessed simultaneously using different address lines, significantly improving data access efficiency.

[0167] Furthermore, the statement (*ram_style = "block"*) is used within the memory cell array to instruct the synthesis tool to synthesize the RAM as block RAM (BRAM) whenever possible. Because BRAM is a dedicated memory resource within the FPGA, it offers high bandwidth and low latency, making it suitable for applications requiring fast access. Compared to dynamic random access memory (DRAM), BRAM offers faster read and write speeds and lower access latency because it resides within the FPGA's logic hierarchy and can interact directly with the logic cells. DRAM is typically used for large-capacity storage, and its structure requires row and column selection during access, resulting in higher latency. While DRAM's higher storage density makes it suitable for large-scale data storage, BRAM's low latency makes it a superior choice for high-performance applications. Therefore, choosing BRAM as a multi-port RAM implementation can significantly improve data processing speed and meet the requirements of high-performance systems.

[0168] In the write operation design, a write enable signal is set to control data writing to a specified address at a specific time. However, read-write conflicts were not specifically considered in this design, as the algorithm's implementation prevents simultaneous reading and writing of the same address. However, in practical applications, additional control logic is often required to ensure data integrity and consistency. The ROM structure is similar to RAM, but because ROM is typically used to store fixed data, a coe file is used during design to define its contents. This approach ensures that the system can quickly access required data after power-up without requiring additional write operations. Furthermore, by controlling the clock signal, multiple read ports are designed, enabling the system to read data from different addresses in parallel within the same clock cycle, facilitating the simultaneous parsing of multiple preprocessed check matrix data.

[0169] The algorithm flows of other submodules such as the check bit matrix calculation module and the cumulative sum matrix calculation module are as follows: Figure 8 and Figure 9As shown. Among them, state is used to indicate different states, matrix_rd_re is read enable, matrix_rd_addr is the read address, matrix_rd_addr_mem is used to store the read data, SM_PM_DEPTH is used to indicate the depth of the RAM for storing the cumulative matrix, calc_idx is used to count the number of groups of data to be processed, m_mem_[0 / 1] and alpha_mem_[0 / 1] respectively represent the data in the set, and i is used to count the number of sets, input_ram_rd_data[0 / 1] represents the data read from the information bit matrix, shifted_data_mem[0 / 1] is used to store the data after circular right shift, and sm_ram_wr_data[0 / 1] represents the data written to the cumulative matrix.

[0170] In these processes, the use of multi-port RAM and ROM is key to achieving efficient data processing. Custom multi-port RAM and ROM enable parallel reading of data from multiple addresses within a single clock cycle, improving data access efficiency for parity check matrix calculation in the LDPC encoder. Multi-port RAM increases data read parallelism by using different address lines to access multiple data points simultaneously. Multi-port ROM is used to store fixed data, such as the parity check matrix, and enables fast data access through multiple read ports.

[0171] In order to verify the parallel LDPC encoder implemented in this paper, a test platform was built. This paper discloses a hardware test platform for the DVB-S2 transmitter system based on FPGA, and its specific design is as follows.

[0172] 1) Overall design of the test platform architecture.

[0173] The hardware implementation of the DVB-S2 transmitter system is designed and the interface driver module is built to verify the LDPC parallel encoder and DVB-S2 transmitter system designed above. The specific architecture is as follows Figure 10 The architecture includes,

[0174] (1) Host computer: This is an external computer or control device that communicates with the FPGA system. The host computer sends UDP packets to the FPGA to test and verify the functions of the LDPC encoder and DVB-S2 transmitter system.

[0175] (2) UDP Communication Interface Module - used to process UDP packets sent by the host computer. It receives data from the host computer and distributes the data to other modules through the interface within the FPGA. It is also responsible for encapsulating the processed data into UDP packets and sending them back to the host computer.

[0176] (3) DDR3 memory module - the main storage unit in the system, used for temporary storage of data and programs, and plays a role in buffering and data management when data flows through the system.

[0177] (4) DDR Input FIFO - Input First-in-First-out (FIFO) buffer, used to temporarily store data transmitted from the UDP communication interface module to alleviate the data transmission rate mismatch problem between different modules.

[0178] (5) UDP Packet FIFO - used to store complete UDP data packets.

[0179] (6) Baseband processing module DVB-S2 transmitter - This module converts data into DVB-S2 standard format and prepares data for transmission; it reads data from the DDR3 memory module, processes the data and sends it to the DVBS2 FIFO.

[0180] (7) DDR Output FIFO - The output FIFO is used to temporarily store the data processed by the baseband processing module and control the data flow to the DVB-S2 transmitter.

[0181] (8) DVBS2 FIFO - is a transmit buffer used to store data to be transmitted via a physical medium (e.g., radio frequency).

[0182] Figure 10 The architecture shown here verifies the performance and functionality of a parallelized LDPC encoder. It tests the encoder's data processing capabilities and transmitter compatibility in a real hardware environment, ensuring the encoder's proper functioning in real-world applications. This design leverages the reconfigurable nature of the FPGA to implement a flexible data processing flow, which is controlled and monitored by an external host computer.

[0183] Furthermore, the baseband processing module design, that is, the hardware implementation design of the DVB-S2 transmitter system, the overall architecture is as follows Figure 11 As shown in Figure 1, the architecture covers the baseband processing module design for digital video broadcasting signal processing. Specifically,

[0184] BB Frame module (baseband frame module), also includes,

[0185] CRC Encoder - Cyclic Redundancy Check Encoder, used to detect errors in data transmission;

[0186] BB Scrambler - Baseband scrambler, used to reduce DC components and long strings of 0s / 1s in data for easier transmission;

[0187] Baseband signaling: baseband signal processing, which conditions the signal to adapt it to baseband transmission requirements;

[0188] The FEC module (forward error correction coding module) also includes:

[0189] BCH Encoder - Block code encoder used to introduce additional redundancy into the data to facilitate error detection and correction at the receiving end;

[0190] LDPC Encoder——Low-Density Parity Check Encoder;

[0191] The bit interleaving and mapping module includes:

[0192] Bit Mapper: maps the encoded bit stream to a constellation for modulation.

[0193] Bit Interleaver: Bit interleaver is used to scatter data to combat sudden errors and enhance signal robustness.

[0194] PL Frame module (physical layer frame module), also includes,

[0195] FIR Filter - Finite Impulse Response filter, used for pulse shaping of signals and reducing inter-symbol interference (ISI);

[0196] PL Scrambler - Physical layer scrambler, which further randomizes the data and increases transmission reliability;

[0197] PL signaling & Pilot insertion——Physical layer signal processing and pilot insertion for channel estimation and synchronization.

[0198] The output IQ_out is the processed in-phase / quadrature signal.

[0199] This hardware architecture design implements a complete DVB-S2 transmitter system, encompassing error detection coding (CRC), scrambling (BB Scrambler), forward error correction coding (FEC module), pre-modulation mapping and interleaving, and physical layer signal processing (PL Frame module). Each module works collaboratively to ensure data integrity and reliability during transmission, while meeting the technical requirements of the DVB-S2 standard. This hardware implementation is suitable for digital video broadcasting scenarios requiring high reliability and high-quality transmission. The system comprises four modules: the BB (Baseband) Frame module, the FEC (Forward Error Correction) module, the bit interleaving and mapping module, and the PL (Physical Layer) Frame module. Its primary functions include adding a baseband frame header to the information bits to be transmitted, performing BCH and LDPC encoding, bit interleaving, and mapping the bits into the constellation corresponding to the selected modulation scheme to obtain IQ values. Finally, a physical layer frame header is added and the signal is filtered through a root-raised cosine filter to obtain the final IQ value for output. This value can then be converted to an analog signal via a DAC for transmission via RF. The following describes the design of each submodule:

[0200] a) The BB Frame module's main function is to encapsulate the input bitstream into baseband frames, including adding a baseband frame header and performing baseband signal processing. The baseband frame header is added to ensure correct identification and parsing of the data frame at the receiving end. Baseband signal processing includes operations such as CRC encoding and baseband scrambling. The parameter DFL represents the valid data length. This value is determined by looking up the table specified in the protocol documentation after selecting the bitrate and frame type. The parameter UPL represents the user data packet length. Here, MPEG format packets are used, so the fixed value is 1504 bits. TSorGS indicates whether transport stream or universal stream is used. Transport stream is selected, so the value is 0. SYNC represents the synchronization byte between data packets, and the fixed value is 47H. MODCOD refers to the selected modulation mode and bitrate scheme. The value range in the protocol documentation is [0, 31]. For example, a value of 6 indicates QPSK and a 2 / 3 bitrate. The specific hardware implementation of this module is as follows: data is input from pkt_bits_in, and pkt_valid_in is used to indicate whether the data is valid. After counting a data packet, CRC encoding is performed on it. The encoding is implemented using a linear feedback shift register (LFSR), and its polynomial is ( ), generate CRC check code through shift and XOR operation. The specific hardware structure is as follows Figure 12 As shown in the figure, EXOR represents exclusive OR operation, bit_in represents input information bit, and crc_out represents CRC encoded output data.

[0201] b) The main function of the FEC module is to perform forward error correction coding, including BCH coding as the inner code and LDPC coding as the outer code. BCH coding is used to detect and correct single-bit errors, while LDPC coding has stronger error correction capabilities. Its cascaded BCH coding can avoid error flattening. BCH coding can correct 8, 10, and 12-bit errors, which are calculated by multiplying the first 8, 10, or 12 of the polynomials specified in the document to obtain the generating polynomial. When this module is implemented in hardware, the BCH encoder uses a linear feedback shift register (LFSR) to shift and XOR the code to generate the check code. Specifically, it is determined according to the code rate code_rate_idx and length, and then count the input bb_frame_out data, and The BCH check bit is calculated using LFSR and the calculated generator polynomial. LDPC encoding is performed on the 1-bit data. The LDPC encoder is implemented using the parallelized LDPC encoder described in detail in Chapters 3 and 4 and will not be described here. Finally, the LDPC-encoded data is output using the fec_out interface. The fec_valid_out signal indicates that the output data is valid.

[0202] c) The main functions of the bit interleaving and mapping module are bit interleaving and bit mapping. Bit interleaving is used to shuffle the bit order to improve the signal's anti-interference capability. Bit mapping maps bits to the constellation corresponding to the modulation scheme to generate IQ values. The DVB-S2 protocol supports four modulation schemes: QPSK, 8PSK, 16APSK, and 32APSK. The IQ values obtained by bit interleaving and constellation mapping vary depending on the selected modulation scheme. Specific parameter settings are specified in the protocol documentation. In hardware implementation, the bit interleaver of this module is implemented using memory and an address generator. Specifically, the interleaving depth and interleaving pattern are determined based on the modulation index mod_idx. The input fec_out data is counted and stored, and the address generator is used to rearrange the bits to achieve bit interleaving. The bit mapper then uses a pre-stored lookup table (LUT) to perform a one-to-one mapping of the interleaved bits to the constellation to generate IQ values. The LUT stores the mapping between bits and constellation points, allowing for rapid bit mapping to the corresponding constellation points. For example, when using QPSK, two bits correspond to a set of I / Q values, while when using 16APSK, four bits correspond to a set of I / Q values. In hardware implementation, a bit width of 11 bits, including a sign bit, is used to store an I or Q value. Finally, the I and Q data are output through the i_out and q_out interfaces. The iq_valid_out signal indicates that the output data is valid.

[0203] d) The main function of the PL Frame module is to generate physical layer frames, including adding PL frame headers, performing PL scrambling, and using BPSK modulates the frame header and generates dummy frames. The addition of the PL frame header is to enable the receiver to correctly identify and parse the data frame, and the PL scrambling is to improve the anti-interference ability of data transmission. The generated dummy frame is used to fill the idle period to ensure the continuous occupation of the channel. When this module is implemented, the state machine is used to control the switching of each state. First, when the data of the previous module has not been calculated, the state will be switched to DUMMY. In this state, a fixed length of The dummy frame of the symbol length is used to fill the idle period to ensure the continuous occupation of the channel, where the I value and Q value of each symbol are When the data is ready, the state is switched to PL_FRAME_GENERATE. At this time, a 90-code-length PL header is generated for each frame. The PL header contains a 26-code-length constant sequence (18D2E82H) used to detect the start position of the frame header at the receiving end. The remaining length is encoded into 64 code elements by the circuit specified in the protocol document. Then, if the PL header is used with the sequence If BPSK modulation, the specific formula is as follows, where :

[0204]

[0205] After calculating the frame header, the state will switch to PILOT_INSERTION, in which the length of the code element in the current frame will be counted. After the code element, a fixed length of 36 and IQ values are inserted. The pilot signal is inserted to facilitate synchronization at the receiving end. After pilot insertion, the state switches to PL_SCRAMBLE, in which the entire frame sequence is scrambled at the symbol level using the circuit diagram specified in the protocol documentation. After scrambling, the PL-frame is generated. However, to transmit this frame data, it must be filtered through a root-raised cosine filter. At this point, the state also switches to FILTERING. This filter is implemented in hardware using an FIR filter. First, the filter coefficients are generated using MATLAB's fdatool based on the root-raised cosine filter roll-off factors of 0.35, 0.25, and 0.20 specified in the protocol. Registers are then used to pre-store the coefficient values. Finally, a convolution operation is performed using the designed pipeline, and the filtered results are output through the pl_frame_i_out and pl_frame_q_out interfaces. The pl_frame_valid_out signal indicates the validity of the output data.

[0206] Furthermore, the interface driver module design includes three core modules: the DDR3 memory interface module, the UDP communication interface module, and the data buffer FIFO module. The interface driver design is a key component of the FPGA implementation of the DVB-S2 encoder, responsible for high-speed data storage, transmission, and buffering. The DDR3 memory interface module provides large-capacity, high-bandwidth data storage, the UDP communication interface module enables efficient data interaction with external devices, and the data buffer FIFO module solves clock domain and rate matching issues between different modules through a multi-level caching mechanism. Through the coordinated operation of these three modules, the system can meet the strict data throughput and real-time requirements of the DVB-S2 standard.

[0207] a) The DDR3 memory interface module is responsible for high-speed data exchange between the FPGA and external DDR3 memory. The design of the DDR3 memory interface module is primarily based on the DVB-S2 encoder's requirements for high bandwidth and large storage capacity. DDR3 memory offers a theoretical bandwidth of up to 12.8 Gbps, meeting the encoder's requirements for high data rates. Furthermore, DDR3's large storage capacity (supporting 2 GB of memory) enables the system to buffer complete satellite frame data (e.g., 64,800-bit frame length), preventing data loss or overflow. Through burst transmission optimization, the DDR3 interface can continuously transmit multiple data blocks in a single operation, reducing address switching overhead and further improving access efficiency. This design not only improves system throughput but also reduces power consumption, enabling the FPGA to efficiently handle complex encoding tasks. The implementation logic of the DDR3 memory interface module primarily revolves around a state machine. This state machine triggers read and write operations by detecting FIFO thresholds (e.g., ddr_input_fifo_rd_count > FDMA_BURST_LEN). During a write operation, the module requests a write through the fdma_wreq signal. The burst length is fixed at 512 (FDMA_BURST_LEN). Data is 128-bit aligned and transferred to the DDR3 memory via fdma_wdata. The DDR3 address is specified by DDR3_0_addr. The column address strobe signal DDR3_0_cas_n and the row address strobe signal DDR3_0_ras_n are sequentially pulled low. When the write enable signal DDR3_0_we_n is asserted, data is written to the specified address via the DDR3 data bus DDR3_0_dq. After the write operation is complete, the fdma_wvalid signal is asserted to confirm that the data has been successfully written to the DDR3 memory. During a read operation, triggered by the fdma_rreq signal, the DDR3 address is specified by DDR3_0_addr. The column address and row address strobe signals are sequentially pulled low. The read data is returned to fdma_rdata via DDR3_0_dq, and the fdma_rvalid signal indicates data validity. The arbitration state (ARBIT) switches the dual buffers (MEM1 / MEM2) via the fifo_switch signal, with address offsets set to ADDR_MEM1_OFFSET (1000) and ADDR_MEM2_OFFSET (0x100000) to avoid read / write conflicts. This design ensures efficient data transmission and storage, while further improving the system's parallel processing capabilities through the dual buffering strategy.

[0208] b) The UDP communication interface module is responsible for efficient data transmission between the FPGA and external devices. The UDP communication interface module is designed to meet the real-time and high-efficiency requirements of the DVB-S2 encoder during data transmission. In a DVB-S2 encoder, data must be transmitted quickly and accurately to external devices to ensure real-time encoding and data integrity. UDP (User Datagram Protocol), as a connectionless transport layer protocol, features low latency and high throughput, making it ideal for scenarios requiring fast data transmission. Compared to TCP (Transmission Control Protocol), UDP does not require connection establishment, reducing data transmission overhead and enabling faster data transmission from sender to receiver. This makes UDP a significant advantage in real-time data transmission, particularly in systems with strict real-time requirements, such as DVB-S2 encoders. Its use can significantly improve system performance. Furthermore, the simplicity and flexibility of the UDP protocol facilitate system design and implementation, reducing system complexity and power consumption, and improving overall performance and reliability. Therefore, choosing UDP as the communication protocol in the DVB-S2 encoder better meets the system's real-time and high-efficiency requirements. In hardware implementation, the UDP communication interface module uses a state machine to control data reception and transmission. When the module detects the data input request signal (udp_data_in_req) going high, indicating data input, the module begins reading data from the udp_data_in port. The read data is temporarily stored and output to the target device through the udp_data_out port. During data output, the module uses the udp_valid_out signal to indicate the validity of the output data, ensuring that the receiving end can correctly process the data. Simultaneously, the module uses the udp_data_out_req signal to request data output, ensuring timely delivery to the target device. During data transmission, the module synchronizes operations with the system clocks (clk_15_625 and clk_200) to ensure stable and accurate data transmission. The clk_15_625 clock signal synchronizes low-speed operations, while the clk_200 clock signal synchronizes high-speed operations. This multi-clock design enables the module to flexibly adapt to different data transmission rates, improving system adaptability and reliability. The module also provides a core reset signal (core_reset) to reset the module state during system startup or when an error occurs, ensuring that the module can operate from its initial state. Through the above design, the UDP communication interface module can efficiently support the real-time data transmission requirements of the DVB-S2 encoder, ensuring that data is transmitted to the target device quickly and accurately.

[0209] c) The data buffer FIFO module is designed to meet the real-time and high-efficiency requirements of the DVB-S2 encoder during data transmission. In the DVB-S2 encoder, the data transmission rate and clock domain between different modules may be inconsistent, so FIFO is needed for buffering and synchronization. During hardware implementation, each FIFO also controls the read and write operations of the data through a state machine. The state machine dynamically controls the read and write enable signals of each FIFO based on the status of the FIFO (such as the full flag and the empty flag) and the requirements of data transmission. It also monitors the counters of each FIFO (such as wr_count and rd_count) to ensure the correctness and timeliness of data transmission. The specific structure is as follows: Figure 13 shown. Figure 13 This paper shows a data buffer FIFO (first in first out) module used in DVB-S2 encoder. Specifically,

[0210] (1) PC (Personal Computer) - Sends UDP data packets to the DVB-S2 encoder;

[0211] (2) DDR Input FIFO - used to temporarily store UDP data packets received from the PC;

[0212] (3) DDR (Double Data Rate Synchronous Dynamic Random Access Memory) - as the main data storage unit, used to transfer data between different modules, including storing data received from the DDR Input FIFO and providing it to the DDROutput FIFO;

[0213] (4) State (state machine) - controls the data reading and writing operations of the FIFO module;

[0214] (5) UDP Packet FIFO - stores complete UDP data packets;

[0215] (6) DVBS2 FIFO - buffers processed data and sends it to the DVBS2 transmitter module;

[0216] (7) DVBS2 TX (transmitter module) - transmits data via radio frequency signals.

[0217] Figure 13 The data flow path through each module is as follows: UDP data packets are received from the PC and stored in the DDR Input FIFO; data is read from the DDR Input FIFO and stored in the DDR memory; data is transferred between the DDR memory and each FIFO according to the control of the state machine; data is read from the DDR Output FIFO, passes through the DVBS2 FIFO, and is finally transferred to the DVBS2TX transmitter module for transmission.

[0218] The state machine plays a central role in this process, ensuring that data is transferred synchronously and in an orderly manner between the various FIFOs, preventing data loss or overflow. By monitoring the FIFO counters, the state machine can dynamically adjust the data flow to accommodate varying transmission rates and processing requirements, thus meeting the DVB-S2 encoder's requirements for real-time and efficient data transmission.

[0219] Furthermore, the present disclosure tests the implemented LDPC parallel encoder and DVB-S2 transmitter system. The present disclosure builds a hardware loopback test platform for implementation verification and performance testing. The details are as follows:

[0220] 1) Test platform introduction

[0221] To comprehensively evaluate the system's performance, this paper adopts a joint testing solution based on FPGA and host computer. The interface driver module designed in Chapter 4 is implemented on the FPGA side. This module is responsible for transmitting the encoded data to the host computer in real time via UDP packets. During the testing process, we focus on the following performance indicators: (1) encoder throughput, which is evaluated by counting the amount of data transmitted per unit time; (2) bit error rate (BER) performance, which is evaluated by comparing LDPC decoding using different check matrices; (3) resource utilization, which is evaluated by obtaining the resource usage of each encoder module through the FPGA development tool.

[0222] Experimental process: When designing the parallel LDPC encoder, Python code was first used to preprocess its check matrix. Then, Verilog code was written and hardware implemented in Vivado software. The bitstream file was written to the Zynq-7000 XC7Z035-2FFG900I development board. Finally, the host computer wrote Python code to send data to the FPGA using UDP packets. The FPGA then processed the data and sent it back to the host computer using UDP packets. After receiving the data, the host computer stored it in a file. Then, the Matlab toolkit functions dvbs2WaveformGenerator and ldpcEncode were used to generate DVB-S2 protocol data and LDPC-encoded data for comparison.

[0223] 2) System implementation verification, including:

[0224] a) Parallel LDPC encoder system implementation verification

[0225] When implementing the test, first use Python to generate random information bits in the host computer, then send the information bits to the LDPC encoder in the FPGA using a UDP packet through the interface driver module, then transmit the encoded data to the host computer through the UDP packet and store it in the file fpga_ldpc_data.txt, and then use the function ldpcEncoderConfig in the Matlab toolkit to configure the LDPC encoding. The main configuration is to use the same code rate and the same protocol check matrix as the LDPC encoder in the FPGA. After the configuration is completed, the same input data is encoded through the function ldpcEncode and the result is stored in matlab_ldpc_data.txt. Finally, the data in the two txt files are compared to see if the bit data in each row is the same, and 50 values of the data are randomly sampled to draw a heat map for easy observation, as shown below. Figure 14 The bit-by-bit comparison results are the same, and it can be seen from the figure that when the code rates are 2 / 5, 3 / 5, 2 / 3, and 4 / 5, the output results of the LDPC encoder implemented by FPGA are consistent with those of the Matlab toolkit function, proving that the encoder can correctly encode at low, medium, and high code rates.

[0226] b) DVB-S2 transmitter system implementation verification

[0227] This test process is essentially the same as the previous section. Python code generates random bit information, which is then sent via a UDP packet through the interface driver module. After being processed by the FPGA, the data is then transmitted back to the host computer via a UDP packet. The difference is that the data is stored in fpga_dvbs2_data.txt. Matlab's dvbs2WaveformGenerator function is then used to configure the same parameters as the transmitter system in the FPGA. This function then generates DVB-S2 signal data and stores it in the file matlab_dvbs2_data.txt. Finally, the data from the two files is compared using Relative Mean Squared Error (MSE). MSE is a commonly used metric for measuring the similarity between two signals; the smaller the value, the more similar the two signals are. In digital communication systems, MSE is often used to evaluate the error between transmitted and received signals. Its calculation formula is:

[0228]

[0229] This formula is obtained by dividing the MSE by the power of the reference signal (i.e. ), and take the logarithm to get a value in decibels (dB). The advantage of this is that the magnitude of the error can be more intuitively represented, especially when the signal power changes greatly. In addition, a constellation diagram is drawn for the FPGA output signal to facilitate the observation of the output results under various modulation modes. The specific test conditions are as follows Figure 15 As shown in the figure. Experimental comparisons of four modulation schemes and different bit rates show that the constellation diagram drawn from the output data of the transmitter system in the FPGA conforms to the current modulation scheme. Table 1 shows that the MSE of the real and imaginary parts under the four MODCODs are generally around -79dB. This data indicates that the error power is approximately times the reference signal power, meaning that the error power is very small relative to the reference signal power. Therefore, it can be concluded that the output results of the FPGA transmitter system under the four MODCODs are basically consistent with the output results of the Matlab function, indicating that the DVB-S2 transmitter system hardware implementation is correct.

[0230] Table 1 MSE results under different modulation modes and code rates

[0231]

[0232] 3) Performance testing

[0233] a) Throughput performance test

[0234] Table 2 Comparison between the latest existing research and the present invention

[0235]

[0236] Existing latest research literature: NANNIPIERI P, BARTOLACCI G, BERTOLUCCI M, et al. Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload[J]. IEEE Access, 2024, 12: 39204-39220.

[0237] The throughput performance comparison is shown in Table 2. The encoder designed by the method proposed in this paper uses Algorithm 4 for hardware experiments and sets the parallelism parameter m=2, which is 720 parallelism, twice the parallelism of the latest research. In addition, when designing the data flow control module in Chapter 3, because it outputs first, After outputting the information bits, the rearranged bit parity bit, so the total throughput It can be calculated by formula (27):

[0238]

[0239] Therefore, the method proposed in the present disclosure can achieve a throughput of 23.4 Gb / s when using a clock frequency of 100 MHz in an FPGA of model Zynq-7000 XC7Z035-2FFG900I, which is approximately twice the throughput of 12 Gb / s in the latest research.

[0240] b) Bit error rate performance test

[0241] The bit rate performance of the LDPC encoder after replacing the check matrix of the ATSC protocol was tested at bit rates of 2 / 5, 3 / 5, 2 / 3 and 4 / 5, and the results were compared with those without replacement. Figure 16 As shown in the figure, where BER stands for bit error rate and SNR stands for signal-to-noise ratio. It can be seen that when using QPSK modulation, the BER performance of the ATSC protocol parity check matrix at bit rates of 2 / 5 and 4 / 5 is 0.1dB better than that of the original DVB-S2 protocol parity check matrix. At bit rates of 3 / 5 and 2 / 3, the BER performance of the ATSC protocol parity check matrix is 0.2dB better than that of the original DVB-S2 protocol parity check matrix. Therefore, the BER performance can be improved by 0.1-0.2dB after replacing the ATSC protocol parity check matrix.

[0242] c) Resource utilization test

[0243] Table 3 Comparison of hardware resource utilization between the latest existing research and the present invention solution

[0244]

[0245] Table 3 shows a comparison of resource utilization. As can be seen, the encoder designed by our proposed method outperforms the state-of-the-art methods in both BRAM (block RAM) and LUT (look-up table) resource utilization. Specifically, the encoder designed by our proposed method uses 34 BRAM tiles, while the state-of-the-art method uses 47. Regarding LUT resources, the encoder designed by our proposed method uses 19,878 LUT tiles, while the state-of-the-art method uses 40,354 LUT tiles. This demonstrates that the encoder designed by our proposed method is more efficient in utilizing BRAM and LUT resources. However, in terms of FF (flip-flop) resource utilization, the encoder designed by our proposed method slightly outperforms the state-of-the-art method. Specifically, the encoder designed by our proposed method uses 42,185 FF tiles, while the state-of-the-art method uses 40,526 FF tiles. Despite this slight improvement in FF resource utilization, overall, the encoder designed by our proposed method and the state-of-the-art method achieve comparable FPGA resource utilization.

[0246] In summary, the technical effects achieved by the present disclosure include:

[0247] (1) We propose an optimized parallelization algorithm based on cyclic shift matrices to improve throughput. By preprocessing the check matrix and constructing a matrix-sum parallel computing architecture, we increase the encoding throughput to 23.4 Gb / s at a 100 MHz clock, which is approximately twice the speed of the latest parallelization methods at the same clock frequency. This algorithm improves the encoder processing speed while maintaining low hardware resource utilization.

[0248] (2) Designing a multi-port RAM storage architecture and an even-odd address blocking mechanism to achieve low resource utilization. By constructing a multi-port RAM to avoid redundant storage and using an even-odd address blocking mechanism to resolve parallel read and write conflicts, a compact hardware design with low resource utilization is implemented on the Xilinx Zynq-7035 development board. This design achieves efficient storage and data processing with limited hardware resources.

[0249] (3) Establishing a mechanism for compatibility between ATSC 3.0 and DVB-S2 check matrixes to improve bit error rate performance. By replacing the check matrix, the bit error rate is reduced by 0.1-0.2dB at different bit rates, which expands the protocol adaptability of the encoder and improves the bit error rate performance of the traditional DVB-S2 system without reconstructing a new check matrix.

[0250] (4) Design and implement an FPGA-based DVB-S2 transmitter system. This system implements the BB Frame module, forward error correction coding module, bit interleaving and mapping module, and PL Frame module specified in the DVB-S2 protocol. In addition, the system integrates a parallelized LDPC encoder and supports multiple modulation modes and bit rates, meeting the requirements of high data rate and large capacity transmission.

[0251] (5) Build a hardware loopback test platform for implementation verification and performance testing. Build an FPGA-host computer test platform and implement an interface driver module that can send UDP packet data to the FPGA using the host computer, and then transmit the output data generated by the FPGA back to the host computer using UDP packets to perform system implementation verification and performance testing. The test content includes key indicators such as throughput, bit error rate performance, and resource utilization, proving the correctness and reliability of the disclosed system.

[0252] It is worth noting that although the foregoing content has described the spirit and principles of the present invention with reference to several specific embodiments, it should be understood that the present invention is not limited to the specific embodiments disclosed, and the division into various aspects does not mean that the features of these aspects cannot be combined. Such division is merely for the convenience of expression. The present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An LDPC encoder based on the DVB-S2 protocol, characterized in that: The encoder includes, An information bit matrix multi-port input RAM for storing input information bits; Check bit matrix multi-port ROM, used to store the check matrix; Accumulated sum matrix RAM, storing the accumulated sum matrix generated by the accumulated sum matrix calculation module; The check bit matrix RAM is used to store the check bit matrix calculated by the check bit matrix calculation module; A check matrix calculation module reads a check matrix from a check bit matrix multi-port ROM, and converts the check matrix into a cyclic shift matrix through matrix row transformation and ATSC check matrix matrix replacement preprocessing operations; The cumulative sum matrix calculation module reads the information bit vector from the information bit matrix multi-port input RAM, and performs accumulation and circular right shift operations on the information bit vector and the row vector read from the check bit matrix ROM to obtain the cumulative sum matrix; The check bit matrix initialization module, based on the calculation results of the cumulative sum matrix calculation module, accumulates the cumulative sum matrix row by row to obtain a row vector, and then constructs a lower triangular matrix to perform multiplication operation to obtain a check bit matrix initialization vector; The check bit matrix calculation module reads the row vectors in the cumulative matrix RAM row by row, performs accumulation operation with the check bit matrix initialization vector, obtains the check bit matrix row vector, and performs iterative calculation to obtain the check bit matrix; The data flow control module is used to control the data flow of the LDPC encoder, control the output of information bits and check bits through an enable signal, and generate LDPC encoding output.

2. The encoder according to claim 1, wherein The storage unit of the information bit matrix multi-port input RAM adopts an even address blocking mechanism to store the cumulative sum matrix and the check bit matrix in the cumulative sum matrix RAM and the check bit matrix RAM respectively according to the address parity.

3. The encoder according to claim 1, wherein The check matrix is a check matrix based on the ATSC protocol.

4. The encoder according to claim 1, wherein The working process of the encoder includes: the input information bits are first stored in the information bit matrix multi-port RAM; The check matrix calculation module reads the check matrix data from the check bit matrix multi-port ROM and performs analysis; The cumulative sum matrix calculation module reads the information bits from the information bit matrix multi-port RAM, performs cyclic right shift and accumulation operations, and stores the results in the cumulative sum matrix RAM. Each calculation result of the cumulative sum matrix calculation module is used to calculate the check bit matrix initialization vector; The check bit matrix calculation module reads the cumulative sum matrix value in the cumulative sum matrix RAM, calculates the check bit and reorders it, and stores the result in the check bit matrix RAM; Finally, the data flow control module controls the output of information bits and check bits by controlling the enable signal to obtain the encoded data output.

5. A DVB-S2 transmitter, characterized in that: It includes baseband frame module, forward error correction coding module, physical layer frame module, bit interleaving and mapping module, among which, The baseband frame module includes: CRC encoder, baseband scrambler, and baseband signal processing module; The forward error correction coding module further comprises: a block code encoder and the LDPC encoder according to claim 1; The physical layer frame module includes: a finite impulse response filter, a physical layer scrambler, a physical layer signal processing and pilot insertion module; The bit interleaving and mapping module includes: a bit mapper and a bit interleaver.

6. The transmitting end according to claim 5, characterized in that: The working process of the transmitter includes: First, the baseband frame module encapsulates the baseband frame and adds a baseband frame header. Then, the forward error correction coding module performs BCH and LDPC coding. Then, the bit interleaving and mapping module performs bit interleaving and maps the bits into the constellation diagram corresponding to the selected modulation mode to obtain the IQ value. Finally, the physical layer frame module generates the physical layer frame, including adding the PL frame header, PL scrambling, frame header modulation and pilot insertion, and passes it through the root raised cosine filter to obtain the final IQ value for output.

7. The transmitting end according to claim 6, characterized in that: The obtained output bit stream is converted into an analog signal through digital-to-analog conversion and transmitted via radio frequency.

8. A DVB-S2 transmitter test platform, characterized in that: The platform comprises a UDP communication interface module, a DDR3 storage module, the DVB-S2 transmitter as claimed in claim 5, and a data buffer FIFO module.

9. The platform according to claim 8, characterized in that The data buffer FIFO module includes: DDR input FIFO, UDP packet FIFO, DDR output FIFO, DVBS2 FIFO.

10. The platform according to claim 8, characterized in that The platform also includes a state machine for controlling the data read and write operations of the data buffer FIFO module.

Images