Clock synchronization method and system for active optical network and EtherCAT network

Abstract

The invention relates to a clock synchronization method and system for an active optical network and an EtherCAT network, and the method comprises the steps: inserting an optical network card into an EtherCAT network segment, and enabling an EtherCAT master station to be connected with the optical network card through a network cable; after receiving the EtherCAT data frame, the optical network card transmits the EtherCAT data frame to a first EtherCAT slave station through another network port; when the EtherCAT data frame is looped back by the EtherCAT network segment, the EtherCAT data frame is sent to the optical network card by the first EtherCAT slave station, and the optical network card transmits the EtherCAT data frame to the EtherCAT master station; when the EtherCAT master station issues a data frame containing a synchronous PDU (Protocol Data Unit), the optical network card lays a local clock timestamp; obtaining a deviation value between a local clock of the optical network card and a reference clock of the EtherCAT network segment, namely a local clock of a first EtherCAT slave station, and compensating synchronization of the local clock of the optical network card and the reference clock; the local clock of each node in the optical network is synchronized with the reference clock. Based on a purple light FPGA chip PG2L100H and a xilinx FPGA chip XCZU7EV, an optical terminal and an optical network card are respectively designed, and the optical network card is inserted into an Ethercat network segment to realize cross-network high-precision clock synchronization.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial optical networks, and particularly to a method and system for clock synchronization between an active optical network and an EtherCAT network. Background Art

[0002] Modern industry continues to develop towards refinement, high efficiency, and intelligence, specifically manifested as an increase in the number of devices, the number of axes, and the complexity of individual devices; an improvement in motion control accuracy; the rise of digital twins and edge computing; and the widespread application of AI and large models. From the above development trends, it can be concluded that the future distributed industrial network architecture should mainly have the following characteristics:

[0003] High bandwidth and high speed: The improvement of industrial computing power enables the introduction of algorithms such as AI and machine vision into industrial control systems, which greatly increases the bandwidth requirements of the network transmission system. Some manufacturers have already used gigabit motion control cards. Currently, 1Gbps bandwidth can basically meet the needs of most industrial production, but the peak bandwidth of related services in high-end manufacturing scenarios is very high and future demands will continue to increase.

[0004] Low latency and high synchronization: In industries such as numerical control machine tools, semiconductor manufacturing, laser processing, and robotics, strict requirements are imposed on indicators such as the latency and synchronization accuracy of fieldbuses. For example, the multi-axis linkage of numerical control machine tools is affected by the bus, resulting in processing accuracy; semiconductor equipment requires nanometer-level positioning accuracy, and its components have high response and sampling frequencies; the control accuracy and efficiency of the galvanometer in laser processing depend on the bus performance; and the synchronization of robot joint axes and human-machine collaboration require a bus with high real-time performance and synchronization accuracy. Therefore, it is necessary to upgrade industrial bus technology to reduce bus latency and jitter, so as to improve control accuracy and efficiency, and further improve the product quality and output efficiency of industrial enterprises.

[0005] Long distance and strong anti-interference: Industrial field networks need to meet higher requirements such as long distance and strong anti-interference ability proposed by intelligent production. For example, it is necessary to achieve coordination between fieldbuses with a length of 2 km, have good anti-interference performance in the complex industrial field environment, and at the same time, the fieldbus even needs to support a bandwidth capacity of up to 10Gbps to adapt to the complex production scenarios after the transformation of manufacturing methods and meet the requirements of high-quality and high-reliability data transmission.

[0006] The new generation of industrial optical network technology based on all-optical interconnection has great advantages over traditional industrial communication networks in the above-mentioned requirements due to its stable physical characteristics of optical transmission and the network architecture of P2MP parallel one-hop direct access. However, in practical applications, considering the heavy-asset nature of industry, the current application of optical networks in industry is not yet widespread. Industrial optical networks need to be compatible with traditional industrial communication networks to avoid the huge costs brought by large-scale equipment replacement, and at the same time, use general-purpose hardware as much as possible when networking industrial optical networks. For cross-bus message data transmission, it can be achieved through mechanisms such as parsing and forwarding, transparent transmission, etc. The cross-network clock synchronization technology that ensures strong synchronization is not yet mature. Summary of the Invention

[0007] The purpose of the present invention is to provide a clock synchronization method and system for an active optical network and an EtherCAT network, so as to achieve high-precision cross-network clock synchronization.

[0008] To achieve the above purpose,

[0009] In the first aspect, an embodiment of the present application provides a clock synchronization method for an active optical network and an EtherCAT network, including the following specific steps:

[0010] An optical network card is inserted into the EtherCAT network segment, located between the EtherCAT master station and the first EtherCAT slave station, and the EtherCAT master station is connected to the optical network card through a network cable;

[0011] After receiving the EtherCAT data frame, the optical network card transparently transmits it to the first EtherCAT slave station through another network port;

[0012] When the EtherCAT data frame is looped back through the EtherCAT network segment and sent by the first EtherCAT slave station to the optical network card, the optical network card then transparently transmits it to the EtherCAT master station;

[0013] When the EtherCAT master station issues a data frame containing a synchronization PDU, the optical network card stamps the local clock timestamp;

[0014] After the data frame containing the synchronization PDU is looped back, the deviation value between the local clock of the optical network card and the reference clock of the EtherCAT network segment, that is, the local clock of the first EtherCAT slave station, is calculated by parsing the data in the optical network card, and the local clock of the optical network card is compensated to synchronize with the reference clock;

[0015] The local clock of the optical terminal adopts synchronous Ethernet technology and a phase discriminator phase shifter to achieve frequency synchronization and phase synchronization with the local clock of the optical network card through the PTP mechanism, and finally realizes that the local clocks of all nodes in the optical network are synchronized with the reference clock.

[0016] The data frame containing the synchronization PDU is looped back and the data is parsed in the optical network card to calculate the deviation value between the local clock of the optical network card and the reference clock of the EtherCAT network segment, that is, the local clock of the first EtherCAT slave. To compensate for the synchronization between the local clock of the optical network card and the reference clock, specifically,

[0017] The EtherCAT master station issues a special broadcast frame to trigger the DC sync0 instruction. When the optical network card detects this special broadcast frame during data parsing, record the local clock time of the preamble arriving at the optical network card as T0. According to the EtherCAT clock synchronization mechanism, when the special broadcast frame travels upstream to the optical network card, the data written by the first EtherCAT slave is obtained through parsing. Among them, the local arrival time Receive time Port0 is recorded as T1, the local arrival time Receive time Port2 is recorded as T2, and the time when the special broadcast frame arrives at the optical network card after loopback is recorded as T3. Since the network cable operates in full duplex with link symmetry, the formula

[0018]

[0019] is used to calculate T Delay That is, the accurate one-way link delay from the optical network card to the first EtherCAT slave. At this time, the local time of the optical network card is modified to T2 + T Delay + T Δ , where T Δ is the time from T3 to the completion of the calculation, measured by the local clock of the optical network card. At this time, the synchronization between the local clock of the optical network card and the reference clock is completed.

[0020] The local clock of the optical terminal adopts synchronous Ethernet technology and a phase discriminator phase shifter to achieve frequency synchronization and phase synchronization with the local clock of the optical network card through the PTP mechanism. Specifically,

[0021] The optical network card judges the link stability in the m1 state, including the stability of the receive clock and the degree of frequency synchronization and phase margin compliance between the transmit clock and the receive clock. After meeting the conditions, it jumps to the m2 state to send a physical layer message, and a specific clock synchronization identification code 0x5a5a is inserted into the message. The optical terminal makes a similar judgment in the s1 state, and also needs to consider the master clock of the slave and the phase of the transmit clock. After stabilization, it enters the s2 state to receive the message from the optical network card. After receiving the identification code, a receive clock domain pulse is generated, and the time stamp t2 of the transmit clock domain of the slave is recorded in a cross-clock domain single-bit handshake manner, and the physical layer message transmission at the t3 moment is started;

[0022] After the optical terminal transfers the pulse at time t2 to the transmit clock domain, it sends the transmit clock synchronization identification code 0x5a5a in the next cycle of frame header 0x617a and records the transmit clock domain timestamp at time t3. The logic of the optical network card receiving the optical terminal message is symmetric to that of the optical terminal receiving the optical network card message. After receiving it, the optical network card generates a t4 receive pulse in the receive clock domain, which is transferred to the transmit clock domain through cross-clock domain transfer to generate a t4 transmit clock domain pulse and timestamp. The optical network card jumps between states m3 and m4 according to the reception situation. After generating the transmit complete pulse at time t3, the optical terminal jumps from state s2 to state s3.

[0023] The optical terminal frames and sends the t2, t3 timestamps and phase error information to the optical network card. After receiving the message, the optical network card calculates the average link delay. If it meets the requirements, it calculates the timestamp and phase compensation value; otherwise, it restarts the above sending process. The optical network card calculates the delay in multiple deterministic stages, including calculating the phase timestamp error and cycle timestamp error, handling phase carry, calculating the link delay, and judging the link stability.

[0024] After the optical network card completes the link delay calculation, it frames the result into a clock synchronization message and sends it to the optical terminal. After receiving the message, the optical terminal generates a receive pulse to trigger the state machine to jump and complete three tasks: updating the cycle timestamp and phase compensation value, performing phase shift compensation on the master clock phase, and compensating the cycle timestamp according to the compensation value, and then enters the waiting stage.

[0025] The phase shift process of the optical terminal is realized through the dynamic phase shift function in the on-chip phase-locked loop PLL of the FPGA, and phase shift operations are performed according to different conditions, and finally the clock synchronization between the master clock of the optical terminal and the master clock of the optical network card and the synchronization of the timestamp of the optical network card and the timestamp of the optical terminal are completed.

[0026] The specific implementation of the phase shift process of the optical terminal through the dynamic phase shift function in the on-chip phase-locked loop PLL of the FPGA is as follows:

[0027] The transmit clock generates a sampling clock f through the on-chip phase-locked loop PLL PLL , samples the clocks after mixing the receive clock and the transmit clock respectively, adopts a delayed multi-beat strategy to avoid metastable transfer, and counts the phase delay by detecting the rising edge of the mixed clock. The phase discrimination accuracy R of the phase detector is as follows:

[0028]

[0029] Among them, the resolution is N, the transmit clock frequency is f clk_tx , and the designed frequency of the mixed sampling clock of the master station and the slave station is selected as f PLL .

[0030] Second aspect, an embodiment of the present application provides a clock synchronization system for an active optical network and an EtherCAT network, including an optical network card inserted into the EtherCAT network segment. The optical network card is between the EtherCAT master station and the first EtherCAT slave station. The EtherCAT master station is connected to the optical network card through a network cable, and the first EtherCAT slave station is connected to the second EtherCAT slave station through a network cable; the optical network card is also connected to an optical terminal through an optical fiber.

[0031] The beneficial effects of the above embodiment are as follows: It is compatible with the active optical network and the EtherCAT network. While avoiding large-scale equipment iteration in the factory, it can achieve high-precision clock synchronization across networks. At the same time, the above embodiment can be implemented using general development hardware devices, avoiding the costs brought by hardware customization. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0033] Figure 1 It is the system structure diagram of the embodiment of the present invention;

[0034] Figure 2 It is the flowchart of optical network clock synchronization in the embodiment of the present invention;

[0035] Figure 3 It is the flowchart of optical network card clock synchronization in the embodiment of the present invention;

[0036] Figure 4 It is the flowchart of optical terminal clock synchronization in the embodiment of the present invention;

[0037] Figure 5 It is the block diagram of the phase detector FPGA logic module in the embodiment of the present invention. Detailed Embodiments

[0038] In order to make the purpose, technical solutions and advantages of the present invention clearer, the following will further describe the present invention in detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0039] It should be noted that the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. Additionally, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0040] Please refer to Figures 1 - 5 , the embodiment of the present application provides a clock synchronization method for an active optical network and an EtherCAT network, including the following specific steps:

[0041] Insert the optical network card into the EtherCAT network segment, located between the EtherCAT master station and the first EtherCAT slave station, and the EtherCAT master station is connected to the optical network card through a network cable;

[0042] After receiving the EtherCAT data frame, the optical network card forwards it transparently to the first EtherCAT slave station through another network port;

[0043] When the EtherCAT data frame is looped back through the EtherCAT network segment and sent by the first EtherCAT slave station to the optical network card, the optical network card then forwards it transparently to the EtherCAT master station;

[0044] When the EtherCAT master station issues a data frame containing a synchronization PDU, the optical network card stamps the local clock timestamp;

[0045] After the data frame containing the synchronization PDU is looped back, the deviation value between the local clock of the optical network card and the reference clock of the EtherCAT network segment, that is, the local clock of the first EtherCAT slave station, is calculated by parsing the data in the optical network card, and the local clock of the optical network card is compensated to synchronize with the reference clock;

[0046] The local clock of the optical terminal adopts synchronous Ethernet technology and a phase discriminator phase shifter to achieve frequency synchronization and phase synchronization with the local clock of the optical network card through the PTP mechanism, and finally realizes the synchronization of the local clocks of all nodes in the optical network with the reference clock.

[0047] In order to solve the above technical problems, the present invention designs an optical network master station (hereinafter referred to as optical network card) based on Xilinx FPGA chip XCZU7EV, designs an optical network slave station (hereinafter referred to as optical terminal) based on Ziguang FPGA chip PG2L100H, and designs a clock synchronization mechanism between the optical network card and the optical terminal based on the IEEE-1588 standard (Precision Time Protocol, hereinafter referred to as PTP), and implements it in the above hardware devices.

[0048] The industrial optical network adopts a tree structure, in which downlink data is broadcasted by the optical network card. Each optical module interface of the optical network card is connected to an optical terminal through an optical fiber. After the optical terminal receives the data and parses it, it selectively accepts it according to the address. The uplink data is sent to the optical network card by each optical terminal, and each optical communication link is independently configured.

[0049] The optical network card is inserted into the EtherCAT network segment, located between the Etherca master station and the first EtherCAT slave station. The EtherCAT master station is connected to the optical network card through a network cable. After receiving the EtherCAT data frame, the optical network card transparently transmits it to the first EtherCAT slave station through another network port. When the EtherCAT data frame is looped back through the EtherCAT network segment, it is sent to the optical network card by the first EtherCAT slave station. The optical network card then transparently transmits it to the EtherCAT master station. When the EtherCAT master station sends data containing synchronization PDU When a frame (hereinafter referred to as a special broadcast frame) is received, the optical network card timestamps the local clock. After the special broadcast frame is looped back, the data is parsed in the optical network card to calculate the deviation between the local clock of the optical network card and the EtherCAT network segment reference clock, that is, the local clock of the first EtherCAT slave (hereinafter referred to as the reference clock). The local clock of the optical network card is synchronized with the reference clock. The local clock of the optical terminal is synchronized with the local clock of the optical network card through the synchronous Ethernet technology and the phase detector and phase shifter, and the PTP mechanism is used to achieve frequency synchronization and phase synchronization with the local clock of the optical network card. Finally, the local clock of each node in the optical network is synchronized with the reference clock.

[0050] The overall architecture of the embodiment system is as follows Figure 1As shown, it consists of an EtherCAT network segment operating in direct connection mode and an optical network with one master and two slaves. Among them, when the EtherCAT master station sends Ethernet frames or UDP data frames (collectively referred to as data frames) through the network cable, the optical network card receives the data frames through the network port, caches them and parses them in the internal logic. At the same time, the data frames are transparently transmitted to the first EtherCAT slave through another network port. The optical network card expansion board used in the embodiment has only one network port resource, and the number of network ports is expanded through the FMC expansion board. After the data frames are looped back through the EtherCAT network segment, the first EtherCAT slave sends them to the optical network card through the network cable. The optical network card caches and parses the data frames in the internal logic, and at the same time transparently transmits and sends them to the EtherCAT master station to complete one loopback. Among them, the optical network card only plays a role of transparent transmission and will not affect the normal communication of EtherCAT data frames and the EtherCAT network segment.

[0051] According to the official standard of ETG1000, when Figure 1 the two EtherCAT slaves support clock synchronization, the master station will send a special broadcast frame to trigger the DC sync0 instruction. When the optical network card detects this special broadcast frame during data parsing, it will record the local clock time when the preamble arrives at the optical network card, denoted as T0. According to the EtherCAT clock synchronization mechanism, when the special broadcast frame travels from the master station downstream, the EtherCAT slave will record the local time when the frame arrives as Receive time Port0 and write it into the special broadcast frame. When the special broadcast frame travels upstream to the master station after loopback, the EtherCAT slave will record the local time when the frame arrives as Receive time Port1 and also write it into the special broadcast frame. Using this mechanism, when the special broadcast frame travels upstream to the optical network card, the data written by the first EtherCAT slave is obtained through parsing. Among them, the written Receive timePort0 time is denoted as T1, the Receive time Port2 time is denoted as T2, and the time when the special broadcast frame arrives at the optical network card after loopback is denoted as T3. Since the full-duplex operation of the network cable has link symmetry, through the formula

[0052]

[0053] T can be calculated Delay That is, the precise one-way link delay from the optical network card to the first EtherCAT slave. At this time, the local time of the optical network card is modified to T2 + T Delay + T Δ T Δ is the time from the moment of T3 to the completion of the calculation, measured by the local clock of the optical network card. At this time, the synchronization of the local clock of the optical network card and the reference clock is completed.

[0054] To achieve clock synchronization between the optical network card and the optical terminal, a state machine is designed in the optical network card and the optical terminal as follows Figure 2 As shown, the PTP clock synchronization function of the optical network is completed by four-message interactions between the optical network card and the optical terminal, which shows a normal optical network clock synchronization process. Among them, the first and second interactions are: the optical network card and the optical terminal send physical layer messages; the third and fourth interactions are: the optical terminal and the optical network card send physical layer messages to each other. And during this interaction process, the state machines of the master station and the slave station will also change accordingly.

[0055] There are transmission and reception clock domains in the optical network card and the optical terminal. The reception clock is obtained through the CDR clock recovery technology. The reception clock frequency of the optical terminal is the same as the transmission clock frequency of the optical network card, but there is a phase deviation. The transmission clock of the optical network card is derived from the on-board crystal oscillator clock input and calls the phase-locked loop (hereinafter referred to as PLL) IP core, which is the system master clock of the optical network. The transmission clock of the optical terminal is modulated by the reception clock through the PLL. The phase difference between the transmission and reception clocks needs to be detected by a digital double mixer phase detector to avoid metastability and ensure signal handshaking across clock domains. The source of the master clock of the optical terminal is different from that of the master station and needs to be adjustable. Therefore, a PLL is separately constructed to enable the phase shifter built into the IP core to output the master clock, and finally align the master clock frequency, phase, and timestamp of the optical terminal with the system master clock and timestamp in the optical network card.

[0056] The state machine of the optical network card is designed as follows Figure 3 As shown, starting from startup, it enters the m1 idle state. At this time, it judges whether the received clock signal cdr_lock is stable and whether the received clock and the transmitted clock maintain a stable phase. If not, it stays in this state. If satisfied, it enters the m2 clock synchronization t1 transmission state, sends the t1 physical layer message. After sending, it enters the m3 clock synchronization t4 waiting stage, waits for 4096 cycles to see if it receives the slave station physical layer message. If received, it enters the m4 clock synchronization t6 waiting stage, continues to wait for 4096 cycles for the slave station link layer feedback message. After receiving, it enters the m5 clock synchronization link delay calculation stage, calculates the link delay according to the message format and judges whether the link delay calculation counts 256 times and the range difference is less than 1 μs. If not satisfied, it continues to calculate. If satisfied, it enters the m6 clock synchronization delay compensation stage, sends the t7 link layer compensation message to the slave station and confirms whether the slave station enters the servo waiting state. If it enters, it enters the servo waiting stage. If not, it returns to execute the compensation process again.

[0057] The state machine of the optical terminal is designed as follows Figure 4As shown, the state machine starts from startup and enters the s1 idle waiting state. At this time, it judges whether the recovery clock signal cdr_lock is stable and whether the phase of main_clk is consistent with that of tx_clk after phase shift. If not satisfied, it stays in this state continuously; if satisfied, it enters the s2 clock synchronization t2 physical layer transmission state. In this state, it judges whether the t2 physical layer message is received completely and whether the t3 physical layer message is sent completely. If not completed, it stays; if completed, it enters the s3 clock synchronization t5 link layer transmission stage and judges whether the t5 link layer message is sent completely. If not completed, it stays; if completed, it enters the s4 clock synchronization t8 waiting stage. First, it judges whether the t2 physical layer message is received. If not received, it further judges whether the link layer compensation message at the master station's t7 moment is received within 4096 cycles. If neither is satisfied, it returns; if satisfied, it enters the s5 clock synchronization compensation phase shift stage and judges whether to perform compensation and phase shift according to the link layer compensation message of the master station. If not completed, it returns; if completed, it enters the servo waiting stage.

[0058] The following introduces the overall synchronization process. The optical network card judges the link stability in the m1 state, including the stability of the receiving clock and the same frequency of the sending clock and the receiving clock and the compliance degree of the phase margin. After meeting the conditions, it jumps to the m2 state to send the physical layer message, and a specific clock synchronization identification code 0x5a5a is inserted into the message. The optical terminal makes a similar judgment in the s1 state and also needs to consider the phase of the slave station's master clock and the sending clock. After stabilization, it enters the s2 state to receive the optical network card message. After receiving the identification code, it generates a receiving clock domain pulse, records the slave station's sending clock domain timestamp t2 in a cross-clock domain single-bit handshake manner, and starts to send the physical layer message at the t3 moment.

[0059] After the optical terminal transfers the t2 moment pulse to the sending clock domain, it sends the clock synchronization identification code 0x5a5a in the next cycle of the frame header 0x617a and records the sending clock domain timestamp at the t3 moment. The logic of the optical network card receiving the optical terminal message is symmetric to the logic of the optical terminal receiving the optical network card message. After the optical network card receives it, it generates a t4 receiving pulse in the receiving clock domain, which is transferred to the sending clock domain through cross-clock domain to generate a t4 sending clock domain pulse and timestamp. The optical network card jumps between the m3 and m4 states according to the receiving situation. After the optical terminal generates the sending completion pulse at the t3 moment, the state machine jumps from s2 to s3.

[0060] The optical terminal frames and sends information such as the t2, t3 timestamps and phase error to the optical network card. After the optical network card receives the message, it calculates the average value of the link delay. If it meets the requirements, it calculates the timestamp and phase compensation value, otherwise it restarts the above sending process. The optical network card calculates the delay in multiple deterministic stages, including calculating the phase timestamp error and the cycle timestamp error, processing the phase carry, calculating the link delay, judging the link stability, etc.

[0061] After the optical network card completes the link delay calculation, it frames the result into a clock synchronization message and sends it to the optical terminal. After receiving the message, the optical terminal generates a receive pulse to trigger the state machine to jump and complete three tasks: update the periodic timestamp and phase compensation value, perform phase shift compensation on the main clock phase, and perform periodic timestamp compensation according to the compensation value, and then enter the waiting stage. The phase shift process of the optical terminal is realized through the dynamic phase shift function in the FPGA's built-in PLL. It is completed by multiple state machines, including idle, sampling, calculation, carry processing, comparison output and other stages. Phase shift operations are performed according to different conditions and finally complete the clock synchronization between the optical terminal master clock and the optical network card master clock, as well as the synchronization between the optical network card timestamp and the optical terminal timestamp.

[0062] The above phase detection function is completed by the digital dual-mixing phase detector implemented in FPGA. Its principle is as follows Figure 5 As shown in the figure, the dual-mixing phase detector consists of two mixers. Its working principle includes mixing two input comparison signals with the reference signal, detecting the phase difference of the mixed output, and adjusting the system operation according to the phase difference. In the FPGA implementation, the sending clock generates the sampling clock f through the PLL. PLL , the mixed clocks of the receiving clock and the transmitting clock are sampled respectively, and a delayed multi-beat strategy is adopted to avoid metastable transmission. In this embodiment, the sampling depth is 6 beats, and the phase delay is counted by detecting the rising edge of the mixing clock. The phase discrimination accuracy R of the phase detector is as follows: clk_tx For example, accept the clock

[0063]

[0064] In this embodiment, the resolution is selected as N = 10, so the transmission clock frequency can be obtained as f clk_tx =156.25MHz, the master and slave mixing sampling clock design frequency is selected as f PLL =156.0974MHz.

[0065] When the local time of the optical network card is synchronized with the EtherCAT network reference time, the above optical network clock synchronization mechanism is started to synchronize the local time of the optical terminal with the local time of the optical network card, and finally the local time of each node in the optical network is synchronized with the EtherCAT network reference clock.

[0066] This application is based on the Tsinghua Unigroup FPGA chip PG2L100H and the Xilinx FPGA chip XCZU7EV, and designs an optical terminal and an optical network card respectively. The optical network card is inserted into the Ethercat network segment to achieve high-precision clock synchronization across the network.

[0067] Those skilled in the art can implement the present invention with various variant solutions without departing from the scope and essence of the present invention. For example, the features of one embodiment can be used in another embodiment to obtain yet another embodiment. Any modification, equivalent replacement, and improvement made within the technical concept of the present invention shall fall within the scope of the rights of the present invention.

Claims

1. A clock synchronization method for an active optical network and an EtherCAT network, characterized in that: The specific steps include: The optical network card is inserted into the EtherCAT network segment, between the EtherCAT master station and the first EtherCAT slave station. The EtherCAT master station is connected to the optical network card via a network cable. After receiving the EtherCAT data frame, the optical network card transparently transmits it to the first EtherCAT slave through another network port; When the EtherCAT data frame is looped back through the EtherCAT network segment, it is sent from the first EtherCAT slave to the optical network card, which then transparently transmits it to the EtherCAT master station; When the EtherCAT master sends a data frame containing a synchronization PDU, the optical network card timestamps the local clock; The data frame containing the synchronization PDU is looped back and then parsed in the optical network card to calculate the deviation between the local clock of the optical network card and the reference clock of the EtherCAT network segment, that is, the local clock of the first EtherCAT slave, so as to compensate for the synchronization between the local clock of the optical network card and the reference clock; The local clock of the optical terminal adopts synchronous Ethernet technology and phase detector and phase shifter, and realizes frequency synchronization and phase synchronization with the local clock of the optical network card through the PTP mechanism, and finally realizes that the local clock of each node in the optical network is synchronized with the reference clock.

2. The clock synchronization method of an active optical network and an EtherCAT network according to claim 1, characterized in that: The data frame containing the synchronous PDU is looped back and then the data is parsed in the optical network card to calculate the deviation between the local clock of the optical network card and the EtherCAT network segment reference clock, i.e., the local clock of the first EtherCAT slave. The compensation for the synchronization of the local clock of the optical network card and the reference clock is specifically as follows: the EtherCAT master station sends a special broadcast frame to trigger the DC sync0 instruction. When the optical network card detects this special broadcast frame during the data parsing process, the time when the leading code arrives at the local clock of the optical network card is recorded, which is recorded as T0. According to the EtherCAT clock synchronization mechanism, when the special broadcast frame is uplinked to the optical network card, the data written by the first EtherCAT slave is obtained after parsing, wherein the written local time of arrival Receive time Port0 is recorded as T1, and the local time of arrival Receive time Port2 is recorded as T2. The time when the special broadcast frame arrives at the optical network card after looping back is recorded as T3. The full-duplex operation of the network cable has link symmetry, which is achieved through the formula Calculate T Delay That is, the precise one-way link delay from the optical network card to the first EtherCAT slave station. At this time, the local time of the optical network card is modified to T2+T Delay +T Δ , where T Δ It is the time from time T3 to the completion of the calculation, measured by the local clock of the optical network card. At this time, the synchronization between the local clock of the optical network card and the reference clock is completed.

3. The clock synchronization method of an active optical network and an EtherCAT network according to claim 1, characterized in that: The local clock of the optical terminal adopts synchronous Ethernet technology and phase detector and phase shifter, and realizes frequency synchronization and phase synchronization with the local clock of the optical network card through the PTP mechanism, specifically, The optical network card judges the link stability in the m1 state, including the receiving clock stability and the degree of compliance of the sending clock and the receiving clock with the same frequency and phase margin. If the conditions are met, it jumps to the m2 state to send the physical layer message. The specific clock synchronization identification code 0x5a5a is inserted in the message. The optical terminal makes similar judgments in the s1 state, and also needs to consider the phase of the slave station master clock and the sending clock. After stabilization, it enters the s2 state to receive the optical network card message. After receiving the identification code, it generates a receiving clock domain pulse, records the slave station sending clock domain timestamp t2 in a cross-clock domain single-bit handshake mode, and starts sending the physical layer message at time t3; After the optical terminal passes the pulse at time t2 to the sending clock domain, it sends the clock synchronization identification code 0x5a5a in the next cycle of the frame header 0x617a and records the sending clock domain timestamp at time t3; The logic of the optical network card receiving the optical terminal message is symmetrical with the logic of the optical terminal receiving the optical network card message. After receiving the message, the optical network card generates a t4 receiving pulse in the receiving clock domain, which is transmitted to the sending clock domain across the clock domain to generate a t4 sending clock domain pulse and timestamp; The optical network card jumps between the m3 and m4 states according to the receiving situation. After the optical terminal generates the completion pulse at time t3, it jumps from the s2 state to the s3 state. The optical terminal frames the t2, t3 timestamps and phase error information and sends them to the optical network card; After receiving the message, the optical network card calculates the average link delay. If it meets the requirements, it calculates the timestamp and phase compensation value. Otherwise, it restarts the above sending process. The optical network card calculates the delay in multiple deterministic stages, including calculating the phase timestamp error and the periodic timestamp error, processing the phase carry, calculating the link delay, and judging the link stability. After the optical network card completes the link delay calculation, it frames the result into a clock synchronization message and sends it to the optical terminal. After receiving the message, the optical terminal generates a receiving pulse to trigger the state machine to jump and complete three tasks: updating the cycle timestamp and phase compensation value, performing phase shift compensation on the master clock phase, and performing cycle timestamp compensation according to the compensation value, and then enters the waiting stage; The phase shifting process of the optical terminal is realized through the dynamic phase shifting function in the FPGA's built-in chip phase-locked loop PLL. The phase shifting operation is performed according to different conditions and finally completes the clock synchronization between the optical terminal master clock and the optical network card master clock, as well as the synchronization between the optical network card timestamp and the optical terminal timestamp.

4. The clock synchronization method of an active optical network and an EtherCAT network according to claim 3, characterized in that: The optical terminal phase shifting process is implemented by the dynamic phase shifting function in the FPGA chip phase-locked loop PLL as follows: The sending clock generates the sampling clock f through the chip phase-locked loop PLL PLL , the mixed clocks of the receiving clock and the transmitting clock are sampled separately, and a delayed multi-beat strategy is adopted to avoid metastable transmission. The phase delay is counted by detecting the rising edge of the mixing clock. The phase discrimination accuracy R of the phase detector is as follows: Among them, the resolution is N, and the sending clock frequency is f clk_tx , the master station and slave station mixing sampling clock design frequency selection f PLL .

5. A clock synchronization system for an active optical network and an EtherCAT network, characterized in that: It includes an optical network card, which is inserted into the EtherCAT network segment. The optical network card is between the EtherCAT master station and the first EtherCAT slave station. The EtherCAT master station is connected to the optical network card through a network cable, and the first EtherCAT slave station is connected to the second EtherCAT slave station through the network cable; the optical network card is also connected to the optical terminal through an optical fiber.

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