Pixel-level ADC image sensor structure capable of adaptively adjusting dynamic range
By introducing a dynamic range control module and a capacitor expansion module into the CTIA circuit of the CMOS image sensor, the size of the integral capacitor is adaptively adjusted, which solves the problem of insufficient dynamic range of the image sensor under strong light conditions, and realizes dynamic range adjustment and image clarity retention in different application scenarios.
Patent Information
- Application Number
- CN202510332894.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-06-20
AI Technical Summary
When existing CMOS image sensors face sudden bright light conditions, they may cause the picture to be completely white and the image to be lost, and they cannot dynamically meet the needs of the application environment.
A pixel-level ADC image sensor structure that adaptively adjusts the dynamic range is designed. By introducing a dynamic range control module and a capacitor expansion module in the CTIA circuit, the size of the integral capacitor is adjusted according to the counter output value, thereby adaptively adjusting the dynamic range.
It realizes dynamic adjustment of the dynamic range of the image sensor in different application scenarios, avoids the full white picture and image loss caused by strong light, and ensures the clarity of the image and the retention of detailed information.
Smart Images
Figure CN120186485A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of CMOS image sensors, and particularly relates to a pixel-level ADC image sensor structure for adaptively adjusting the dynamic range. Background Art
[0002] During the operation of a CMOS image sensor, some special situations may occur, such as sudden direct sunlight, sudden explosion, etc. At this time, the image sensor is likely to cause the entire picture to turn white due to the generation of strong light and lose the image. This is unacceptable during the use of the image sensor. Therefore, we need to propose a brand-new circuit structure that can change the integration capacitor in the CTIA circuit during application, adaptively change and adjust the dynamic range, and dynamically meet the requirements of the changing application environment. Summary of the Invention
[0003] Aiming at the deficiencies of the above-mentioned prior art, the technical problem to be solved by the present invention is: to provide a pixel-level ADC image sensor structure for adaptively adjusting the dynamic range.
[0004] To solve the above technical problem, the present invention provides the following technical solutions:
[0005] A pixel-level ADC image sensor structure for adaptively adjusting the dynamic range, comprising
[0006] A CTIA circuit for converting the photocurrent signal generated by the pixel into a voltage signal through an integration capacitor and outputting it as an integration level signal; and adjusting the size of the integration capacitor according to the dynamic adjustment signal fed back by the dynamic range control module, thereby changing the dynamic range;
[0007] A hysteresis comparator circuit for comparing the voltage of the integration level signal with a first voltage reference signal and outputting a count trigger pulse and a self-reset signal according to the comparison result, and the self-reset signal is used to reset the CTIA circuit;
[0008] A counter for counting the count trigger pulses; and
[0009] A dynamic range control module for generating a dynamic adjustment signal according to the counting result.
[0010] Further, when the voltage of the integration level signal reaches the voltage of the first voltage reference signal, the signal output end of the hysteresis comparator circuit sends a count trigger pulse to the counter, and at the same time, the self-reset control end of the hysteresis comparator circuit returns a self-reset signal to the CTIA circuit.
[0011] Further, the input ports of the dynamic range control module are respectively connected to the first h bits of the high-order bits of the counter output value, and are used to output corresponding dynamic adjustment signals according to the first h bits of the high-order bits of the counter output value, where m > h ≥ 1; m represents the number of bits of the counter output value.
[0012] Further, the CTIA circuit includes a basic integration capacitor, an integration comparator, a reset circuit, and a capacitor expansion module. The non-inverting input terminal of the integration comparator is connected to a second voltage reference signal, and the level value of the second voltage reference signal is less than the level value of the first voltage reference signal; the inverting input terminal of the integration comparator is electrically connected to the output terminal of the pixel, and the inverting input terminal of the integration comparator is also electrically connected to the first end of the basic integration capacitor, and the output terminal of the integration comparator is electrically connected to the second end of the basic integration capacitor; the reset circuit is used to reset the basic integration capacitor, and the capacitor expansion module is used to connect corresponding-sized expansion integration capacitors in parallel at both ends of the basic integration capacitor according to the dynamic adjustment signal.
[0013] Further, the reset circuit includes
[0014] a global reset circuit, which is used to reset the basic integration capacitor before the integration starts; and
[0015] a self-reset circuit, which is used to reset the basic integration capacitor at the same time when the hysteresis comparator circuit sends a counting trigger pulse to the counter.
[0016] Further, the global reset circuit includes a global reset switch. The first end of the global reset switch is electrically connected to the first end of the basic integration capacitor, the second end of the global reset switch is electrically connected to the second end of the basic integration capacitor, and the control end of the global reset switch is used to connect a first global reset signal.
[0017] Further, the self-reset circuit includes a first self-reset switch. The first end of the first self-reset switch is electrically connected to the first end of the basic integration capacitor, the second end of the first self-reset switch is electrically connected to the second end of the basic integration capacitor; the control end of the first self-reset switch is electrically connected to the self-reset control end of the hysteresis comparator circuit.
[0018] Further, the self-reset circuit further includes a second self-reset switch. The first end of the second self-reset switch is electrically connected to the output terminal of the integration comparator, the second end of the second self-reset switch is connected to the second voltage reference signal; the control end of the second self-reset switch is electrically connected to the self-reset control end of the hysteresis comparator circuit.
[0019] Further, the capacitance expansion module includes g capacitance expansion units, where g ≥ 1; each capacitance expansion unit is connected in parallel with the basic integration capacitor; there are g groups of dynamic adjustment signals, and each group of dynamic adjustment signals is electrically connected to a capacitance expansion unit respectively.
[0020] Further, each capacitance expansion unit respectively includes a first expansion switch, a second expansion switch, and an expansion integration capacitor. The first end of the first expansion switch is electrically connected to the first end of the basic integration capacitor, the second end of the first expansion switch is electrically connected to the first end of the expansion integration capacitor, and the second end of the expansion integration capacitor is electrically connected to the second end of the basic integration capacitor; the second expansion switch is connected in parallel with the expansion integration capacitor;
[0021] Each group of the dynamic adjustment signals includes a first dynamic adjustment signal and a second dynamic adjustment signal, and the first dynamic adjustment signal and the second dynamic adjustment signal correspond one by one and have opposite level values; the control end of the first expansion switch is connected to the first dynamic adjustment signal, and the control end of the second expansion switch is connected to the second dynamic adjustment signal.
[0022] In the present invention, a dynamic range control module is added, and a capacitance expansion module is added to the CT IA circuit. The dynamic range control module is connected to the output end of the counter and the expansion switch of the expansion capacitor in the capacitance expansion module. The dynamic range can be expanded when the output value of the counter is relatively large, and the size of the expanded dynamic range can be controlled, so as to adaptively adjust the dynamic range of the image sensor structure to meet different application scenarios. Description of the Drawings
[0023] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:
[0024] Figure 1 It is a structural block diagram of an embodiment of a pixel-level ADC image sensor structure for adaptively adjusting the dynamic range of the present invention.
[0025] Figure 2 It is a circuit diagram of the CTIA circuit.
[0026] Figure 3 It is a schematic waveform comparison diagram of the working states of this embodiment and the traditional structure.
[0027] The reference numerals in the specification drawings are as follows:
[0028] CTIA circuit - 100; capacitance expansion module - 110; capacitance expansion unit - 111; hysteresis comparator circuit - 200; counter - 300; dynamic range control module - 400; pixel - 500;
[0029] Base integration capacitor - C1; integration comparator - D1; global reset switch - K1; first self - reset switch - K2_1; second self - reset switch - K2_2; first expansion switch - K2_1_1~K2_1_g; second expansion switch - K2_2_1~K2_2_g; expansion integration capacitors C2_1~C2_g;
[0030] First voltage reference signal - Vref_cmp; second voltage reference signal - Vref_ctia; first global reset signal - Rst_global_1; second global reset signal - Rst_global_2; self - reset signal - rst_amp; first dynamic adjustment signals - Ctrl_gain_1~Ctrl_gain_g; second dynamic adjustment signals - Ctrl_gain_n_1~Ctrl_gain_n_g. Specific embodiments
[0031] The following specific examples are used to illustrate the embodiments of the present invention. The diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0032] Please refer to Figure 1 , Figure 1 , which is a structural block diagram of an embodiment of the pixel - level ADC image sensor structure for adaptively adjusting the dynamic range of the present invention. The pixel - level ADC image sensor structure for adaptively adjusting the dynamic range in this embodiment includes a CTIA circuit 100, a hysteresis comparator circuit 200, a counter 300, and a dynamic range control module 400.
[0033] The CTIA circuit 100 is used to convert the photocurrent signal generated by the pixel 500 into a voltage signal through an integration capacitor and output it as an integration level signal; and adjust the size of the integration capacitor according to the dynamic adjustment signal fed back by the dynamic range control module 400, thereby changing the dynamic range.
[0034] The hysteresis comparator circuit 200 is used to compare the voltage of the integration level signal with the first voltage reference signal Vref_cmp and output a count trigger pulse and a self - reset signal according to the comparison result. The self - reset signal is used to reset the CTIA circuit 100. In this embodiment, when the voltage of the integration level signal reaches the voltage of the first voltage reference signal Vref_cmp, the signal output terminal of the hysteresis comparator circuit 200 sends a count trigger pulse to the counter 300. At the same time, the self - reset control terminal of the hysteresis comparator circuit 200 returns a self - reset signal rst_amp to the CTIA circuit 100.
[0035] The counter 300 is used to count the counting trigger pulses. The dynamic range control module 400 is used to generate a dynamic adjustment signal according to the counting result. In this embodiment, the input ports of the dynamic range control module 400 are respectively connected to the first h bits of the high-order bits of the output value of the counter 300 (for example, it can be extracted from the register connected to the output end of the counter 300), and are used to output a corresponding dynamic adjustment signal according to the first h bits of the high-order bits of the output value of the counter 300, where m>h≥1; m represents the number of bits of the output value of the counter 300.
[0036] Please refer to Figure 2 , the CTIA circuit 100 includes a basic integration capacitor C1, an integration comparator D1, a reset circuit, and a capacitor expansion module 110. The non-inverting input terminal of the integration comparator D1 is connected to the second voltage reference signal Vref_ctia, and the level value of the second voltage reference signal Vref_ctia is less than the level value of the first voltage reference signal Vref_cmp; the inverting input terminal of the integration comparator D1 is electrically connected to the output terminal of the pixel, and the inverting input terminal of the integration comparator D1 is also electrically connected to the first end of the basic integration capacitor C1, and the output terminal of the integration comparator D1 is electrically connected to the second end of the basic integration capacitor C1; the reset circuit is used to reset the basic integration capacitor C1, and the capacitor expansion module 110 is used to connect a corresponding-sized expansion integration capacitor in parallel at both ends of the basic integration capacitor C1 according to the dynamic adjustment signal.
[0037] The reset circuit generally includes a global reset circuit and a self-reset circuit. The global reset circuit is used to respond to the first global reset signal Rst_global_1 and reset the basic integration capacitor C1 before the integration starts. Of course, before the integration starts, the counter 300 will also be synchronously reset by the second global reset signal Rst_global_2. In this embodiment, the global reset circuit includes a global reset switch K1. The first end of the global reset switch K1 is electrically connected to the first end of the basic integration capacitor C1, the second end of the global reset switch K1 is electrically connected to the second end of the basic integration capacitor C1, and the control end of the global reset switch K1 is used to connect the first global reset signal Rst_global_1.
[0038] The self-resetting circuit is used to respond to the self-resetting signal rst_amp, and reset the basic integration capacitor C1 while the hysteresis comparator circuit 200 sends a counting trigger pulse to the counter 300. In this embodiment, the self-resetting circuit includes a first self-resetting switch K2_1. The first end of the first self-resetting switch K2_1 is electrically connected to the first end of the basic integration capacitor C1, and the second end of the first self-resetting switch K2_1 is electrically connected to the second end of the basic integration capacitor C1. The control end of the first self-resetting switch K2_1 is electrically connected to the self-resetting control end of the hysteresis comparator circuit 200. Of course, in order to reset the output of the CTIA circuit 100, the self-resetting circuit may further include a second self-resetting switch K2_2. The first end of the second self-resetting switch K2_2 is electrically connected to the output end of the integration comparator D1, and the second end of the second self-resetting switch K2_2 is connected to the second voltage reference signal Vref_ctia. The control end of the second self-resetting switch K2_2 is electrically connected to the self-resetting control end of the hysteresis comparator circuit 200.
[0039] The capacitor expansion module 110 includes g capacitor expansion units 111, where g≥1. Each of the capacitor expansion units 111 is connected in parallel with the basic integration capacitor C1. Correspondingly, there are also g groups of dynamic adjustment signals output by the dynamic range control module 400, so that each group of dynamic adjustment signals is electrically connected to a capacitor expansion unit 111 respectively.
[0040] Please continue to refer to Figure 2 , each of the capacitor expansion units 111 includes a first expansion switch (K2_1_1~K2_1_g), a second expansion switch (K2_2_1~K2_2_g) and an expansion integration capacitor (C2_1~C2_g). The first end of the first expansion switch is electrically connected to the first end of the basic integration capacitor C1, the second end of the first expansion switch is electrically connected to the first end of the expansion integration capacitor, and the second end of the expansion integration capacitor is electrically connected to the second end of the basic integration capacitor C1. The second expansion switch is connected in parallel with the expansion integration capacitor.
[0041] Each group of the dynamic adjustment signals includes a first dynamic adjustment signal and a second dynamic adjustment signal. The first dynamic adjustment signal and the second dynamic adjustment signal correspond one by one and have opposite level values. The control end of the first expansion switch is connected to the first dynamic adjustment signal, and the control end of the second expansion switch is connected to the second dynamic adjustment signal.
[0042] Next, taking the output signal of the counter 300 as four bits (i.e., m = 4) as an example, the working principle of this embodiment will be described.
[0043] Please refer to Figures 1 to 2, before the integration starts, first close the global reset switch K1 through the first global reset signal Rst_global_1 to reset the basic integration capacitor C1. At the same time, reset the counter 300 through the second global reset signal Rst_global_2 to clear the output value of the counter 300.
[0044] After that, the CTIA circuit 100 uses the basic integration capacitor C1 as the integration capacitor for integration. When the output voltage of the CTIA circuit 100 reaches the voltage of the second voltage reference signal Vref_cmp, it triggers the hysteresis comparator module to generate a counting trigger pulse, causing the counter 300 to complete one count. At the same time, the self-reset control terminal of the hysteresis comparator circuit 200 also outputs a self-reset signal rst_amp, causing both the first self-reset switch K2_1 and the second self-reset switch K2_2 of the CTIA circuit 100 to close, performing a self-reset operation on the CTIA circuit 100.
[0045] When the high bit output by the counter 300 meets the set input number of bits of the dynamic range control module 400, the dynamic range control module 400 outputs a dynamic adjustment signal to enable at least one of the corresponding extended integration capacitors (C2_1~C2_g) in the capacitor expansion module 110 to be connected and connected in parallel with the basic integration capacitor C1, so that the extended integration capacitor and the basic integration capacitor C1 perform the integration process simultaneously, completing the function of adaptive dynamic range.
[0046] For example, assume that when the dynamic range control module 400 is only connected to the most significant bit of the output signal of the counter 300 (i.e., Q<3>) (i.e., h = 1), the dynamic range control module 400 only outputs a set (i.e., the first dynamic adjustment signal Ctrl_gain_1 and the second dynamic adjustment signal Ctrl_gain_n_1). The capacitance expansion module 110 only includes one capacitance expansion unit 111 (including the first expansion switch K2_1_1, the second expansion switch K2_2_1, and the expansion integration capacitor C2_1). Before the count value output by the counter 300 reaches "1000" (binary), the first dynamic adjustment signal Ctrl_gain_1 keeps the first expansion switch K2_1_1 in the open state, and the second dynamic adjustment signal Ctrl_gain_n_1 keeps the second expansion switch K2_2_1 in the closed state, and the expansion integration capacitor C2_1 is not connected to the circuit. When the count value output by the counter 300 reaches "1000" (i.e., the most significant bit reaches "1"), the first dynamic adjustment signal Ctrl_gain_1 keeps the first expansion switch K2_1_1 in the closed state, and the second dynamic adjustment signal Ctrl_gain_n_1 keeps the second expansion switch K2_2_1 in the open state, and the expansion integration capacitor C2_1 is connected in parallel with the basic integration capacitor C1, thereby expanding the integration capacitance of the CTIA circuit 100. At this time, the CTIA circuit 100 integrates with the parallel structure of the expansion integration capacitor C2_1 and the basic integration capacitor C1 as the integration capacitance, thereby slowing down the integration speed and increasing the duration required for a single count.
[0047] Of course, the dynamic range control module 400 can also be connected to the most significant bit and the second most significant bit of the output signal of the counter 300 (i.e., Q<3> and Q<2>) (i.e., h = 2). Then, when the count value output by the counter 300 reaches "1000" (i.e., the most significant bit reaches "1"), the expansion integration capacitor C2_1 in the first capacitance expansion unit 111 can be connected to the circuit and connected in parallel with the basic integration capacitor C1, so that the CTIA circuit 100 starts the first expansion of the integration capacitance. When the count value output by the counter 300 reaches "1100" (i.e., the highest two bits reach "11"), the expansion integration capacitor C2_1 is disconnected, and another expansion integration capacitor larger than the expansion integration capacitor C2_1 in the second capacitance expansion unit 111 is connected to the circuit and connected in parallel with the basic integration capacitor C1, so that the CTIA circuit 100 starts the second expansion of the integration capacitance.
[0048] If the secondary expansion still cannot meet the requirements, the number of bits connected by the dynamic range control module 400 and the number of capacitance expansion units 111 can be further increased, so as to avoid the count value of the counter 300 reaching the maximum value within the exposure time, resulting in a completely white image and loss of details.
[0049] Please refer to Figure 3, it is a waveform comparison schematic diagram of the working state of the traditional image sensor structure and the image sensor structure with a capacitance expansion unit 111 set in this embodiment and the extended integration capacitance C2_1 connected to the circuit being equal to the basic integration capacitance C1. According to the comparison, due to the influence of strong light, the "effective exposure time of the traditional structure" in the figure of the traditional image sensor structure reaches the maximum value of the counter 300 (i.e., "1111"), and the exposure time after the "effective exposure time of the traditional structure" cannot be counted. However, in the structure of this embodiment, since the capacitance is expanded when the count value output by the counter 300 reaches "1000", the integration capacitance of the CTIA circuit 100 is increased, and the dynamic range is expanded. The output at the end of the exposure time is "1110", which does not reach the maximum value of the counter 300, so that the image information can be reflected within the actual exposure time, avoiding the situation of the image being all white and losing details.
[0050] In this embodiment, different from the traditional image sensor structure without adaptive dynamic range adjustment, a pixel-level ADC image sensor structure capable of adaptive dynamic range adjustment is proposed, which can automatically expand the integration capacitance in the CTIA circuit 100 when the count value of the counter 300 is relatively large, so as to adaptively adjust the dynamic range of the image sensor structure and meet different application scenarios.
[0051] The above embodiments only represent the preferred implementation modes of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.
Claims
1. A pixel-level ADC image sensor structure with adaptive dynamic range adjustment, characterized in that: include A CTIA circuit, used for converting a photocurrent signal generated by a pixel into a voltage signal through an integration capacitor and outputting the signal as an integration level; and adjusting the size of the integration capacitor according to the dynamic adjustment signal fed back by the dynamic range control module, thereby changing the dynamic range; a hysteresis comparator circuit, used for comparing the voltage of the integration level signal with the first voltage reference signal, and outputting a count trigger pulse and a self-reset signal according to the comparison result, wherein the self-reset signal is used for resetting the CTIA circuit; A counter, used for counting the counting trigger pulses; as well as The dynamic range control module is used to generate a dynamic adjustment signal according to the counting result.
2. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to claim 1, characterized in that: When the voltage of the integrated level signal reaches the voltage of the first voltage reference signal, the signal output terminal of the hysteresis comparator circuit sends a count trigger pulse to the counter, and at the same time, the self-reset control terminal of the hysteresis comparator circuit returns a self-reset signal to the CTIA circuit.
3. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to claim 1, characterized in that: The input port of the dynamic range control module is respectively connected to the first h bits of the high-order data of the counter output value, and is used to output the corresponding dynamic adjustment signal according to the first h bits of the high-order data of the counter output value, wherein m>h≥1; m represents the number of bits of the counter output value.
4. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to any one of claims 1 to 3, characterized in that: The CTIA circuit includes a basic integrating capacitor, an integrating comparator, a reset circuit and a capacitance extension module. The in-phase input terminal of the integrating comparator is connected to a second voltage reference signal, and the level value of the second voltage reference signal is less than the level value of the first voltage reference signal; the inverting input terminal of the integrating comparator is electrically connected to the output terminal of the pixel, the inverting input terminal of the integrating comparator is also electrically connected to the first terminal of the basic integrating capacitor, and the output terminal of the integrating comparator is electrically connected to the second terminal of the basic integrating capacitor; the reset circuit is used to reset the basic integrating capacitor, and the capacitance extension module is used to connect an extended integrating capacitor of corresponding size in parallel at both ends of the basic integrating capacitor according to a dynamic adjustment signal.
5. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment as claimed in claim 4, characterized in that: The reset circuit comprises A global reset circuit, used to reset the basic integration capacitor before integration begins; as well as The self-reset circuit is used for resetting the basic integration capacitor when the hysteresis comparator circuit sends a count trigger pulse to the counter.
6. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment as claimed in claim 5, characterized in that: The global reset circuit includes a global reset switch, a first end of the global reset switch is electrically connected to a first end of a basic integral capacitor, a second end of the global reset switch is electrically connected to a second end of the basic integral capacitor, and a control end of the global reset switch is used to connect a first global reset signal.
7. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to claim 5, characterized in that: The self-reset circuit includes a first self-reset switch, a first end of the first self-reset switch is electrically connected to the first end of the basic integral capacitor, and a second end of the first self-reset switch is electrically connected to the second end of the basic integral capacitor; a control end of the first self-reset switch is electrically connected to the self-reset control end of the hysteresis comparator circuit.
8. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to claim 7, characterized in that: The self-reset circuit also includes a second self-reset switch, a first end of the second self-reset switch is electrically connected to the output end of the integrating comparator, and a second end of the second self-reset switch is connected to a second voltage reference signal; and a control end of the second self-reset switch is electrically connected to a self-reset control end of the hysteresis comparator circuit.
9. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to claim 4, characterized in that: The capacitor extension module includes g capacitor extension units, wherein g≥1; each of the capacitor extension units is connected in parallel with the basic integrating capacitor; there are g groups of dynamic adjustment signals, and each group of dynamic adjustment signals is electrically connected to a capacitor extension unit.
10. The pixel-level ADC image sensor structure with adaptive dynamic range adjustment according to claim 9, characterized in that: Each of the capacitor extension units comprises a first extension switch, a second extension switch and an extended integral capacitor, wherein a first end of the first extension switch is electrically connected to a first end of a basic integral capacitor, a second end of the first extension switch is electrically connected to a first end of the extended integral capacitor, and a second end of the extended integral capacitor is electrically connected to a second end of the basic integral capacitor; and the second extension switch is connected in parallel to the extended integral capacitor; Each group of dynamic adjustment signals includes a first dynamic adjustment signal and a second dynamic adjustment signal, the first dynamic adjustment signal and the second dynamic adjustment signal correspond to each other one by one and have opposite level values; the control end of the first expansion switch is connected to the first dynamic adjustment signal, and the control end of the second expansion switch is connected to the second dynamic adjustment signal.