Multi-layer circuit board drilling method and device based on machine vision

Abstract

The invention relates to the technical field of PCB processing, and discloses a multi-layer circuit board drilling method and device based on machine vision, and the method comprises the steps: obtaining a multi-layer circuit board image; preprocessing the multi-layer circuit board image to obtain a to-be-identified image; inputting the to-be-recognized image into a pre-trained defect detection model to obtain defect position data; carrying out point location identification and matching on the to-be-identified image to obtain an optimal hole location coordinate, and carrying out correction according to the optimal hole location coordinate to obtain hole location information data; according to the hole site information data and the defect position data, nodes are constructed respectively, distance calculation is carried out, and a hole site node graph is generated; according to the hole site node graph, performing path planning by applying an ant colony algorithm, and performing iterative search to obtain an optimal drilling path; and drilling the multilayer circuit board according to the optimal drilling path. The method has the following effect that the drilling efficiency of the multilayer circuit board can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB board processing, and particularly to a method and device for drilling multi-layer circuit boards based on machine vision. Background Art

[0002] At present, with the continuous evolution of consumer electronics, Internet of Things devices, and wearable devices towards miniaturization and lightweight, the application of multi-layer printed circuit boards (MPCBs) is gradually expanding to a wider industrial field. MPCBs form a three-dimensional structure by thermally laminating multiple single-layer circuit boards, and their interiors not only integrate vertically staggered conductive paths but also contain thousands of through-holes as bridges for interlayer electrical connections. In the manufacturing process of MPCBs, drilling, as the core process for forming through-hole structures, its processing accuracy will directly affect signal transmission integrity, component soldering quality, and the long-term reliability of products. Traditional processing methods mainly rely on mechanical positioning references combined with manual visual adjustment. This process not only has a positioning deviation of 0.05 - 0.1 mm but also is difficult to meet the requirements of micro-hole pitch below 0.15 mm in modern high-density interconnect (HDI) board designs. Especially when dealing with stacked structures of 8 layers or more, the cumulative effect of interlayer alignment deviation will significantly reduce the yield rate.

[0003] In an existing technology, first, a high-precision industrial camera equipped with a macro lens (such as a 5-megapixel CMOS sensor) is used to optically scan the PCB substrate, and a complete digital image of the surface to be processed is obtained by taking sub-region photos. The image processing process includes three key stages: in the preprocessing stage, the Gaussian filtering algorithm is used to eliminate ambient light interference and photosensitive noise, and at the same time, the histogram equalization technique is used to enhance the image contrast; in the feature recognition stage, the Canny edge detection algorithm is combined with the feature point matching technique to locate the center point of each drill hole with sub-pixel accuracy. For special-shaped blind or buried hole structures, morphological operations are also introduced for three-dimensional feature reconstruction; finally, in the coordinate mapping stage, by establishing an affine transformation matrix containing lens distortion parameters, the two-dimensional coordinate point group identified in the image coordinate system is accurately converted into the three-dimensional machining coordinates in the machine tool motion coordinate system, and an optimized G code is generated to control the movement trajectory of the drill bit.

[0004] However, the existing technical solutions still have obvious limitations in engineering practice: when the system conducts path planning, it only calculates single-layer drilling points in isolation and does not fully consider the spatial topological relationship of the multi-layer board structure. Due to different design requirements such as vertical penetration and staggered avoidance of vias in each layer, simple planar path optimization will cause a large number of ineffective idle strokes when the drill bit switches between layers. For example, when processing a 16-layer high-density board, the traditional algorithm requires the drill bit to cross multiple processing areas to reach the corresponding position on the 4th layer after completing the drilling of the 3rd layer. This discontinuous processing path reduces the effective working time of the equipment and results in low drilling efficiency of multi-layer circuit boards. Summary of the Invention

[0005] The present invention provides a method and device for drilling multi-layer circuit boards based on machine vision to achieve the goal of improving the drilling efficiency of multi-layer circuit boards.

[0006] In a first aspect, to solve the above technical problems, the present invention provides a method for drilling multi-layer circuit boards based on machine vision, including: Obtain a multi-layer circuit board image; Preprocess the multi-layer circuit board image to obtain an image to be recognized; Input the image to be recognized into a pre-trained defect detection model to obtain defect position data; Perform point position recognition and matching on the image to be recognized to obtain the optimal hole position coordinates, and correct according to the optimal hole position coordinates to obtain hole position information data; Construct nodes based on the hole position information data and the defect position data respectively and calculate distances to generate a hole position node graph; Apply the ant colony algorithm for path planning according to the hole position node graph, and iteratively search to obtain the optimal drilling path; Drill the multi-layer circuit board according to the optimal drilling path.

[0007] In an alternative embodiment, the preprocessing of the multi-layer circuit board image to obtain an image to be recognized includes: Perform gray-scale processing on the multi-layer circuit board image to obtain an original gray-scale image; Obtain a gray-scale threshold; Perform binarization processing on the original gray-scale image and the gray-scale threshold to obtain a binarized image; Perform smoothing processing on the binarized image to obtain an image to be recognized.

[0008] In an alternative embodiment, the training process of the defect detection model includes: Construct a defect detection model based on historical circuit board images and historical defect distribution data, and train the model. When the number of training times reaches the preset upper limit or it is detected that the loss function of the model meets the conditions, determine that the training is completed to obtain the trained model; Input the image to be recognized into the trained model to obtain defect position data.

[0009] In an alternative embodiment, the method for performing point position recognition and matching on the image to be recognized to obtain the optimal hole position coordinates and correcting according to the optimal hole position coordinates to obtain hole position information data includes: Input the image to be recognized into a pre-trained feature extraction model to output a circuit board feature map; Perform corner detection on the circuit board feature map to obtain a corner coordinate matrix; Perform feature descriptor matching on the corner coordinate matrix to obtain the optimal hole position coordinates; Iteratively correct the optimal hole position coordinates through the following formula to obtain hole position information data: Among them, represents the coordinate correction amount, represents the Jacobian matrix, represents the transpose of the Jacobian matrix, represents the correction error, represents a pixel represents the actual gray value, represents the gray value of the positioning point template, represents the actual gray value at the partial derivative in the axis direction, represents the partial derivative of the actual gray value in the axis direction; Among them, the training process of the feature extraction model includes: Construct a feature extraction model based on historical circuit board images and historical feature images, and train the model. When the number of training times reaches the preset upper limit or it is detected that the loss function of the model meets the conditions, determine that the training is completed to obtain the trained model;

[0010] Input the image to be recognized into the trained model to obtain a circuit board feature map. Construct nodes according to the defect position data to obtain abnormal nodes; Construct nodes according to the hole position information data to obtain hole position nodes; Calculate the node distance based on the defect position data and the hole position information data; Generate a hole position node graph according to the abnormal node, the hole position node and the node distance; Among them, the node distance is used as the weight of the edge.

[0011] In an alternative embodiment, the application of the ant colony algorithm for path planning according to the hole position node graph, and iteratively searching for the optimal drilling path includes: Initialize the number of ants, pheromone concentration, evaporation rate and number of iterations; Use the hole position node as an ant colony node to perform ant colony search on the hole position node graph; And update the pheromone concentration according to the following formula: Among them, represents the pheromone concentration from node to node at the th iteration, , represents the evaporation rate, represents the increase in pheromone in this iteration; When the number of iterations reaches the preset upper limit, disconnect the connection relationship of the edges with pheromone concentration lower than the preset pheromone threshold; Re-iterate until there is only one remaining connected path as the optimal drilling path.

[0012] In an alternative embodiment, before using the hole position node as an ant colony node to perform ant colony search on the hole position node graph, it further includes: Set the abnormal node as inaccessible; Weakly mark the hole position nodes within a preset abnormal distance around the abnormal node to obtain weakly marked hole position nodes; Reduce the probability of ants selecting the weakly marked hole position nodes according to the preset probability rule.

[0013] In a second aspect, the present invention provides a multi-layer circuit board drilling device based on machine vision, including: A data acquisition module for acquiring multi-layer circuit board images; A preprocessing module for preprocessing the multi-layer circuit board image to obtain an image to be recognized; A defect detection module for inputting the image to be recognized into a pre-trained defect detection model to obtain defect position data; A hole position recognition module, which is used to perform point position recognition and matching on the image to be recognized to obtain the optimal hole position coordinates, and correct according to the optimal hole position coordinates to obtain hole position information data; A node graph module, which is used to construct nodes respectively according to the hole position information data and the defect position data and calculate distances to generate a hole position node graph; A path planning module, which is used to apply the ant colony algorithm for path planning according to the hole position node graph, and iteratively search to obtain the optimal drilling path; A drilling implementation module, which is used to drill a multi-layer circuit board according to the optimal drilling path.

[0014] In a third aspect, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the machine vision-based multi-layer circuit board drilling method described in any one of the above.

[0015] In a fourth aspect, the present invention also provides a computer-readable storage medium, which includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute the machine vision-based multi-layer circuit board drilling method described in any one of the above.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a machine vision-based multi-layer circuit board drilling method and device. The method includes obtaining a multi-layer circuit board image; preprocessing the multi-layer circuit board image to obtain an image to be recognized; inputting the image to be recognized into a pre-trained defect detection model to obtain defect position data; performing point position recognition and matching on the image to be recognized to obtain the optimal hole position coordinates, and correcting according to the optimal hole position coordinates to obtain hole position information data; constructing nodes respectively according to the hole position information data and the defect position data and calculating distances to generate a hole position node graph; applying the ant colony algorithm for path planning according to the hole position node graph, and iteratively searching to obtain the optimal drilling path; drilling the multi-layer circuit board according to the optimal drilling path. This method has the following effects: This method can improve the drilling efficiency of multi-layer circuit boards.

[0017] Specifically, first, an image of a multi-layer circuit board is obtained and preprocessed to generate an image to be recognized. This process effectively removes noise interference and enhances the clarity of key features, laying a foundation for subsequent analysis. Next, the pre-trained defect detection model is used to analyze the image to be recognized, and the model can accurately identify the defect position data in the image. At the same time, point position recognition is performed on the image to be recognized to extract hole position information data, ensuring the accuracy of the drilling position in subsequent processes.

[0018] Based on the above two sets of data - hole position information data and defect position data, a hole position node map is generated. This step not only integrates multi-source information but also provides an intuitive reference framework for path planning. Subsequently, path planning is carried out according to the hole position node map, and the optimal drilling path is calculated. Multiple factors such as minimizing the moving distance, avoiding obstacles (such as known defect areas), and optimizing the processing sequence are taken into account during this process, thereby improving the drilling efficiency while ensuring the quality of the finished product.

[0019] Furthermore, the drilling operation is performed on the multi-layer circuit board according to the obtained optimal drilling path. The entire process realizes the highly integrated and automated control from image acquisition to final drilling through digital means, reduces the errors caused by human intervention, and reduces the processing time of the multi-layer circuit board. At the same time, the spatial relationship is considered, and the drilling efficiency of the multi-layer circuit board is improved.

[0020] Through the collaborative application of machine vision and deep learning models, this technology realizes hole position recognition with sub-pixel accuracy (error < 5μm), and the efficiency is increased by 40% compared with traditional optical positioning; the dynamic defect detection module can real-time identify circuit defects at the level of 0.1mm², avoiding the waste board rate caused by incorrect drilling (the measured value is reduced by 18%). Based on the improved path planning algorithm, the idle stroke movement of the drill bit is reduced by 52%, and with the six-axis linkage mechanism, high-speed processing of 1200 holes per minute is achieved. The actual production data shows that this method reduces the time-consuming of the multi-layer board drilling process from 45 minutes / ㎡ in the traditional process to 28 minutes / ㎡, comprehensively improves the equipment operation rate to more than 92%, and significantly improves the drilling efficiency of the multi-layer circuit board. Brief Description of the Drawings

[0021] Figure 1 is a schematic flow chart of a method for drilling multi-layer circuit boards based on machine vision provided by the first embodiment of the present invention; Figure 2 is a schematic structural diagram of a device for drilling multi-layer circuit boards based on machine vision provided by the second embodiment of the present invention. Detailed Embodiments

[0022] Hereinafter, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] Refer to Figure 1 , the first embodiment of the present invention provides a method for drilling multi-layer circuit boards based on machine vision, including the following steps: S11, obtaining an image of the multi-layer circuit board; S12. Preprocess the multi-layer circuit board image to obtain an image to be recognized; S13. Input the image to be recognized into a pre-trained defect detection model to obtain defect location data; S14. Perform point position recognition and matching on the image to be recognized to obtain the optimal hole position coordinates, and correct according to the optimal hole position coordinates to obtain hole position information data; S15. Construct nodes according to the hole position information data and the defect location data respectively and calculate the distances to generate a hole position node graph; S16. Apply the ant colony algorithm for path planning according to the hole position node graph, and iteratively search to obtain the optimal drilling path; S17. Drill the multi-layer circuit board according to the optimal drilling path.

[0024] In step S11, obtain a multi-layer circuit board image.

[0025] In one implementation, the data acquisition process is performed according to the following steps: Install a line array camera (model: Basler raL8192-24gm) equipped with a 50 million pixel CMOS sensor, set the horizontal resolution to 8μm / pixel, and the longitudinal scanning step accuracy to ±2μm; Configure an annular LED light source system, including two array modules with wavelengths of 460nm (blue light) and 630nm (red light) respectively, and control the illuminance uniformity above 95%; Keep the circuit board parallel to the imaging system through an air bearing platform, and use a laser rangefinder to monitor the flatness deviation in real time. When the Z-axis fluctuation exceeds 5μm, trigger automatic leveling; Start the segmented scanning mode, divide the processing area into a 12×12 grid, and synchronously record the encoder coordinate values when each sub-region is photographed; During the focusing process, use the contrast peak detection method to dynamically adjust the object distance at intervals of 10ms to ensure that the MTF modulation transfer function value ≥ 0.8; After each single-layer image acquisition is completed, establish an inter-layer coordinate mapping relationship by recognizing the positioning mark (cross target tolerance ±1.5μm) to form a three-dimensional point cloud data set.

[0026] It should be noted that TIFF is a flexible and adaptable file format that supports multiple color modes (such as black and white, grayscale, RGB, etc.) and can contain multiple layer information. For application scenarios with high-precision requirements, TIFF is widely used because of its lossless compression option, which can maintain the original image quality. PNG is a bitmap graphics format that supports lossless compression and is suitable for storing images with large areas of the same color, transparency, or requiring high-quality display. It does not support animation, but it is a good choice for most static images, especially when the image has clear edges. For the application scenario of multi-layer circuit board drilling, considering the accuracy of image analysis and the requirements of subsequent processing, a lossless compression format such as TIFF or PNG will be selected to ensure the complete preservation of image quality and details.

[0027] In step S12, the multi-layer circuit board image is preprocessed to obtain an image to be recognized.

[0028] In one implementation, gray-scale processing is performed on the multi-layer circuit board image to obtain an original gray-scale image; a gray-scale threshold is obtained; binaryzation processing is performed according to the original gray-scale image and the gray-scale threshold to obtain a binary image; and smoothing processing is performed according to the binary image to obtain an image to be recognized.

[0029] In one implementation, the process of preprocessing the multi-layer circuit board image to obtain an image to be recognized is as follows: First, the obtained multi-layer circuit board color image is converted into a gray-scale image, which is achieved by calculating the weighted average value of the red, green, and blue (RGB) three channels of each pixel point. The conversion formula is as follows: where respectively represent the intensity values of the pixel point in the red, green, and blue three channels, represents the converted gray-scale value. Then, a suitable gray-scale threshold is determined. This threshold is used to distinguish the foreground (such as hole positions and defects) from the background in the image. The optimal threshold can be automatically selected by the Otsu method, which aims to minimize the between-class variance to find the threshold that makes the separation between the foreground and the background most obvious. Then, the selected gray-scale threshold is used to perform binaryzation processing on the original gray-scale image, converting the image into a black and white image, where pixels above the threshold are set to white (or 1), and pixels below the threshold are set to black (or 0). Finally, in order to remove the existing noise and smooth the edges, a smoothing processing technique is adopted, such as a Gaussian filter, which reduces image noise by calculating the weighted average value of each pixel and its neighboring pixels. The weights are determined by the Gaussian function, and the standard deviation controls the smoothing degree. The larger the standard deviation, the more obvious the smoothing effect, but at the same time, it will also cause details to be lost. After the above steps, an image to be recognized suitable for subsequent analysis is finally obtained.

[0030] It should be noted that the Otsu method (also known as the between-class variance method or Otsu's Thresholding) is a technique for automatically selecting a threshold for image segmentation. The core idea of the Otsu method is to maximize the between-class variance between foreground and background pixels. Specifically, it traverses all thresholds and calculates the mean gray values of the foreground and background and the overall gray mean when a certain gray value is used as the threshold, and then calculates the between-class variance based on these values. The selected optimal threshold is the one that maximizes the between-class variance between the foreground and the background. In theory, in this case, the foreground and the background are most clearly separated.

[0031] It should be noted that the binarization method is an intelligent algorithm for automatically determining the black-and-white segmentation point of an image, just like automatically finding the best dividing line in a black-and-white photo to clearly distinguish the main body and the background in the picture. Specifically, the algorithm analyzes all gray levels in the image (256 color levels from pure black to pure white) and finds the segmentation threshold that can make the contrast between the bright area and the dark area the strongest through mathematical calculations. This method is often used in industrial inspection to quickly locate defective areas. For example, it can automatically circle the scratched or damaged positions in a circuit board image. However, when the image has uneven light or a large amount of noise, the direct use has an unsatisfactory effect, and other image processing techniques need to be combined to optimize the image quality in advance.

[0032] In step S13, the image to be recognized is input into a pre-trained defect detection model to obtain defect location data.

[0033] In one implementation, a defect detection model is constructed based on historical circuit board images and historical defect distribution data, and the model is trained. When the number of training times reaches the preset upper limit or it is detected that the loss function of the model meets the conditions, it is determined that the training is completed, and the trained model is obtained; The image to be recognized is input into the trained model to obtain defect location data.

[0034] In one implementation, the defect detection model adopts an improved U-Net architecture combined with an attention mechanism. The specific construction and training process includes the following steps: Collect 2000 groups of historical circuit board images (resolution 4096×4096), covering 8 types of defects such as copper foil scratches, resin voids, and circuit gaps; Use polygon vector annotation when annotating the defect area, and the minimum annotation unit is a 5×5 pixel area; Perform data augmentation operations on the obtained historical circuit board images. Then insert a CBAM dual attention unit at the U-Net skip connection, set the optimizer, set the initial learning rate and decay weight, and then start training. When the number of training times reaches the preset upper limit or it is detected that the loss function of the model meets the conditions, it is determined that the training is completed, and the trained model is obtained.

[0035] It is worth mentioning that the core function of this defect detection model is to accurately identify and locate manufacturing defects of multi-layer circuit boards (PCBs) through deep learning technology. Input an image to be identified with a size of 200mm×150mm, where the imaging resolution is 8μm / pixel (corresponding to an image size of 25000×18750 pixels). The detection process includes: image block processing, that is, cutting the original image into 1024×1024 slices (468 in total). Then perform model reasoning, and detect that the 5th slice (coordinate X1200-Y800 area) is abnormal. Finally, the output result locates the actual position of the defect at X9.6mm-Y6.4mm. Defect type classification can also be performed, including: type judgment as line gap (confidence 98.7%); size measurement is length 0.25mm and width 0.08mm. The cause was traced back to the concentration deviation of the etching process solution, which led to local over-corrosion.

[0036] In step S14, point recognition and matching are performed on the image to be recognized to obtain optimal hole position coordinates, and correction is performed based on the optimal hole position coordinates to obtain hole position information data.

[0037] In one implementation, the image to be identified is input into a pre-trained feature extraction model, and a circuit board feature map is output; Perform corner point detection according to the circuit board feature map to obtain a corner point coordinate matrix; Performing feature descriptor matching on the corner point coordinate matrix to obtain optimal hole position coordinates; The optimal hole position coordinates are iteratively corrected using the following formula to obtain hole position information data: in, represents the coordinate correction amount, represents the Jacobian matrix, represents the transpose of the Jacobian matrix, Indicates the correction error, Represents pixels The actual gray value, Represents the gray value of the positioning point template, Indicates the actual gray value in The partial derivatives in the axis direction, Indicates the actual gray value in Partial derivatives in the axis direction; The training process of the feature extraction model includes: Building a feature extraction model based on historical circuit board images and historical feature images, training the model, and determining that the training is completed when the number of training times reaches a preset upper limit or the loss function of the model meets the conditions, thereby obtaining a trained model; Input the image to be recognized into the trained model to obtain a circuit board feature map.

[0038] It should be noted that, first of all, the image to be recognized will be input into a pre-trained feature extraction model. The task of this model is to extract useful features from the image, such as lines, edges, or specific shapes. For multi-layer circuit boards, these features include special marks or structures around the drilling positions. In this way, a "circuit board feature map" can be refined from the original image, which highlights the key areas that help locate the hole positions.

[0039] In one implementation, the feature extraction model is based on a deep convolutional neural network architecture, and an improved UNet or ResNet-34 is used as the backbone network. In the specific implementation, the encoder part uses the pre-trained ResNet to extract multi-level features (such as shallow edge textures and deep semantic information), and the decoder gradually reconstructs the spatial details through deconvolution operations, and finally outputs a feature heat map with the same resolution as the input image. In the training stage, the Dice Loss + BCE dual loss function is used to optimize the parameters, and the Adam optimizer (initial learning rate 3e-4) is used for end-to-end training. Considering the characteristics of circuit board images, the model embeds a Coordinate Attention module at the skip connection to enhance the ability to capture geometric features such as the circular marks of the hole positions, and the generated feature map highlights the key areas through the Sigmoid activation function.

[0040] It should be noted that the next step is the corner detection step. Corners refer to the corner points or significant change points in the image. They are the most stable parts of the image and are not easily affected by light changes or slight deformations. In this process, the algorithm scans the entire circuit board feature map to find those points with high contrast changes - that is, corners. Once these points are found, their positions will be recorded to form a corner coordinate matrix. Simply put, this step is like marking each important point to obtain the positions of the candidate holes.

[0041] In one implementation, when performing corner detection, first use the Sobel operator to calculate the gradients of the circuit board feature map in the x-axis and y-axis directions, so as to obtain the edge information of each pixel point. Then, construct the structure tensor of each pixel point based on these gradient values, and calculate the response value reflecting whether this point is a corner accordingly. Subsequently, through non-maximum suppression technology, select the point with the highest response value in each local area to ensure the stability and uniqueness of the corner. Finally, apply a preset response value threshold to filter out the points with lower response values, ensuring that only the most prominent corners are recognized, and record their positions to form a corner coordinate matrix. This process effectively marks the candidate hole positions and lays the foundation for further feature descriptor matching.

[0042] It should be noted that the last step is feature descriptor matching. The goal here is to determine which corners correspond to the actual positions where drilling is required. Each corner has its unique features (such as the surrounding texture, color distribution, etc.), and these features can be represented by a set of numbers, which is the so-called feature descriptor. The algorithm will generate such descriptors for all detected corners and try to find the most matching set of points as the final hole position coordinates.

[0043] In one implementation, in this step of feature descriptor matching, the purpose is to accurately determine which corners correspond to the actual positions where drilling is required. First, for each detected corner, a unique feature descriptor is generated based on the information in its surrounding area. This descriptor is a set of numbers that can effectively represent the characteristics such as the texture and color distribution around this corner. Commonly used feature descriptor methods include SIFT (Scale-Invariant Feature Transform), SURF (Speeded-Up Robust Features), and ORB (Oriented FAST and Rotated BRIEF), etc. Next, find the best match by comparing the similarities between these descriptors. Specifically, for the descriptor of each corner, find the most similar descriptor in the entire set, that is, the descriptor with the smallest distance (here, the Euclidean distance or Hamming distance is used as the measurement standard). To improve the accuracy of the matching, a ratio test (such as the distance ratio between the nearest neighbor and the second nearest neighbor) is also used to filter out those unreliable matches. Finally, regard the coordinates of all successfully matched corners as the final hole position coordinates. This not only ensures the accuracy of the selected hole positions, but also enhances the robustness of the system to image changes (such as rotation, scaling, and illumination changes). This process is a key step in precision manufacturing, ensuring the accuracy of the circuit board drilling positions, thus guaranteeing the performance and reliability of electronic devices. After the entire process is completed, a circuit board feature map marked with the accurate drilling positions is obtained.

[0044] In one implementation, SIFT (Scale-Invariant Feature Transform) is used for descriptor matching. When implementing SIFT feature matching, first, stable feature points in the image (such as the corners or textures of circuit board solder joints) are detected through a Gaussian pyramid, and a 128-dimensional vector is generated for each key point to describe its local gradient distribution. Then, the FLANN (Fast Library for Approximate Nearest Neighbors) algorithm is used to find the matching pairs with the smallest Euclidean distance of descriptors in the feature libraries of two images. To improve the matching reliability, the ratio screening method (retaining the matches where the ratio of the distance to the first nearest neighbor to the second nearest neighbor is less than 0.7) and the RANSAC (Random Sample Consensus) algorithm are used to eliminate false matches, and finally, a pair of matching points with geometric consistency is obtained for subsequent component positioning or image alignment, such as detecting the displacement deviation of components during the assembly process.

[0045] In step S15, nodes are respectively constructed according to the hole position information data and the defect position data, and distance calculations are performed to generate a hole position node graph.

[0046] In one implementation, nodes are constructed according to the defect position data to obtain abnormal nodes; nodes are constructed according to the hole position information data to obtain hole position nodes; distance calculations are performed according to the defect position data and the hole position information data to obtain node distances; a hole position node graph is generated according to the abnormal nodes, the hole position nodes, and the node distances; wherein, the node distances are used as the weights of the edges.

[0047] In one implementation, the construction process of the hole position node graph can be implemented in four steps: First, each defect coordinate is converted into an abnormal node with a type label (such as D1[crack]), and at the same time, the drilling coordinates are converted into hole position nodes (such as P2[hole diameter 0.8mm]); then, the Euclidean distances between all abnormal nodes and hole position nodes are calculated. For example, the distance between the defect D1(15, 30) and the hole position P3(18, 28) is √[(18 - 15)²+(28 - 30)²]=3.61 units; then, this distance value is used as the weight of the connecting edge to establish the D1-P3 connection edge; finally, a topological graph containing two types of nodes and weighted edges is formed. In an actual case, when three abnormal nodes (D1 / D2 / D3) and five hole position nodes (P1 - P5) are detected, the system automatically generates 12 connection edges (each defect is connected to each hole position). Through a visualization tool, it can be observed that the defect D2 triggers a quality warning around the hole position first because its distance from P4 is only 2.1 units (the edge weight is the smallest).

[0048] In step S16, the ant colony algorithm is applied according to the hole position node graph for path planning, and the optimal drilling path is obtained through iterative search.

[0049] In one implementation, the number of ants, the pheromone concentration, the evaporation rate, and the number of iterations are initialized; Take the hole position nodes as ant colony nodes and perform ant colony search on the hole position node graph; And update the pheromone concentration according to the following formula: Wherein, represents the pheromone concentration from node to node at the th iteration, , represents the evaporation rate, represents the increment of pheromone in this iteration; When the number of iterations reaches the preset upper limit, disconnect the connection relationship of the edges with pheromone concentration lower than the preset pheromone threshold; Re - perform the iteration until there is only one remaining connected path, which is used as the optimal drilling path.

[0050] It should be noted that, in order to plan the optimal drilling path based on the hole position node graph, a path planning method based on the ant colony algorithm is adopted. First, some key parameters are initialized, including the number of ants, the initial pheromone concentration, the evaporation rate of pheromone, and the maximum number of iterations. Here, the "number of ants" refers to the number of virtual ants used in the simulation search process; the "pheromone concentration" is a method to simulate the way ants in nature mark paths by releasing pheromones and is used as an index to measure the quality of paths in the algorithm; while the "evaporation rate" simulates the phenomenon that pheromones gradually disappear over time in nature, ensuring that the algorithm will not converge prematurely to a non - optimal solution. Then, the hole position nodes are regarded as nodes in the ant colony, and these virtual ants search on the hole position node graph to find the best path. After each iteration, the pheromone concentration on each path is updated: for those paths that are selected by more ants and show better performance (such as shorter total path length), more pheromones will be added; while for those paths that are less selected or perform poorly, their attractiveness will decrease due to the natural evaporation of pheromones. When the preset maximum number of iterations is reached, if the pheromone concentration of some paths is lower than a certain threshold, these paths are considered unsuitable as part of the final path and are thus disconnected. Repeat this process until a unique path that connects all hole position nodes and has the shortest total path is found as the optimal drilling path. This method draws on the behavior pattern of ants foraging in nature, has strong robustness and global optimization ability, and is very suitable for solving complex path planning problems.

[0051] In step S17, drill the multi - layer printed circuit board according to the optimal drilling path.

[0052] In one implementation, the optimized drilling path (such as the G-code sequence generated based on the improved ant colony algorithm) is imported into the control system of a six-axis high-precision CNC drilling machine. The path data includes the set of hole position coordinates and the corresponding drill bit travel sequence index. According to the characteristics of the PCB board material (such as FR-4 glass fiber substrate), the drill bit rotation speed (typical value 180,000 rpm), feed rate (0.8 m / min), and Z-axis drilling depth (board thickness + 0.2 mm allowance) are set. The positioning accuracy is ensured to be ≤ ±15 μm through PID closed-loop control. The coordinates feedback by the grating scale are collected in real time, and the B-spline curve interpolation algorithm is used to smooth the path. When a sudden obstacle (such as residual copper chips) is detected, the D* Lite algorithm is used to dynamically replan the local path and generate an obstacle avoidance detour trajectory.

[0053] In one implementation, when performing 256 micro-hole (hole diameter 0.15 mm) processing operations on a 12-layer HDI board, the optimized path reduces the drill bit idle travel distance from the original 3.2 m to 1.7 m. The system controls the drill bit to gradually penetrate each layer with a 30° cutting angle through the spiral drilling instruction (G02 / G03) of the G-code. At the same time, the piezoelectric ceramic vibration module assists in chip removal at a frequency of 20 kHz. Finally, the single-board processing time is reduced from the original 23 minutes to 14 minutes, and the Ra value of the hole wall roughness is stabilized within 1.6 μm.

[0054] In summary, the present invention discloses a method for drilling multi-layer circuit boards based on machine vision. The method proposed by the invention first obtains the image of the multi-layer circuit board and preprocesses it to obtain the image to be recognized, including steps such as grayscale processing, binarization processing, and smoothing processing, effectively removing noise interference and enhancing the clarity of key features, laying a foundation for subsequent analysis. Then, the pre-trained defect detection model is used to analyze the image to be recognized, and the defect position data in the image is accurately identified. At the same time, the point position recognition of the image to be recognized is carried out through corner detection and feature descriptor matching technology, ensuring the accuracy of the drilling position. The hole position node map is generated based on the above two sets of data, and this process integrates multi-source information and provides an intuitive reference framework. Next, path planning is carried out according to the hole position node map, and the ant colony algorithm is used to calculate the optimal drilling path, while considering minimizing the moving distance, avoiding obstacles, and optimizing the processing sequence to ensure the finished product quality. Finally, the drilling operation is performed on the multi-layer circuit board according to the obtained optimal drilling path.

[0055] Furthermore, the defect detection model adopts an improved U-Net architecture combined with an attention mechanism to accurately identify and locate defects through learning historical circuit board images and historical defect distribution data. Hole position recognition relies on deep convolutional neural network architectures such as ResNet-34 or improved UNet. These models can extract useful features from the original image, such as lines, edges, or specific shapes, to assist in determining the drilling positions. In addition, to improve the accuracy of hole position coordinates, an iterative correction formula is applied, which precisely adjusts the hole position coordinates based on the Jacobian matrix. In terms of constructing the hole position node graph, each defect coordinate is converted into an abnormal node, the drilling coordinates are converted into hole position nodes, and the Euclidean distance between them is calculated as the weight of the edge, forming a topological graph containing two types of nodes and their associated relationships. The path planning module uses the ant colony algorithm for search, simulates the foraging behavior of ants to find the optimal path, and gradually converges to the best solution according to the pheromone concentration update strategy.

[0056] The entire process achieves highly integrated and automated control from image acquisition to final drilling, reducing errors caused by human intervention. Specifically, images are obtained through a line array camera equipped with a 50 million pixel CMOS sensor, a ring-shaped LED light source system is configured to ensure uniform illuminance, and a laser rangefinder is used to monitor the flatness deviation in real time to ensure imaging quality. Considering the characteristics of lossless compression for TIFF or PNG formats, an appropriate image saving method is selected to maintain the quality and integrity of the original image details. In addition, through the synergistic effect of machine vision and deep learning models, this method achieves hole position recognition with sub-pixel level accuracy (error < 5μm), can identify circuit defects at the level of 0.1 mm² in real time, and avoids the waste board rate caused by incorrect drilling. Based on the improved path planning algorithm, the idle stroke movement of the drill bit is reduced, and high-speed machining is achieved in cooperation with a six-axis linkage mechanism. This method is not only applicable to drilling of ordinary multi-layer circuit boards but also can handle complex spatial layouts and design requirements, with high adaptability and flexibility, improving the drilling efficiency of multi-layer circuit boards.

[0057] Refer to Figure 2 , the second embodiment of the present invention provides a multi-layer circuit board drilling device based on machine vision, including: A data acquisition module for acquiring multi-layer circuit board images; A preprocessing module for preprocessing the multi-layer circuit board image to obtain an image to be recognized; A defect detection module for inputting the image to be recognized into a pre-trained defect detection model to obtain defect position data; A hole position recognition module for performing point position recognition and matching on the image to be recognized to obtain the optimal hole position coordinates, and correcting according to the optimal hole position coordinates to obtain hole position information data; A node diagram module, configured to construct nodes according to the hole position information data and the defect position data respectively and perform distance calculation to generate a hole position node diagram; A path planning module, configured to perform path planning according to the hole position node diagram by applying an ant colony algorithm, and iteratively search to obtain an optimal drilling path; A drilling implementation module, configured to drill a multi-layer circuit board according to the optimal drilling path.

[0058] It should be noted that a multi-layer circuit board drilling device based on machine vision provided in an embodiment of the present invention is used to execute all process steps of a multi-layer circuit board drilling method based on machine vision in the above embodiment. The working principles and beneficial effects of the two correspond one by one, so they will not be elaborated here.

[0059] An embodiment of the present invention also provides an electronic device. The electronic device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a data acquisition program. When the processor executes the computer program, the steps in the above embodiments of various multi-layer circuit board drilling methods based on machine vision are implemented, such as Figure 1 step S11 shown. Alternatively, when the processor executes the computer program, the functions of each module / unit in the above device embodiments are implemented, such as the data acquisition module.

[0060] Exemplarily, the computer program can be divided into one or more modules / units. The one or more modules / units are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0061] The electronic device can be a computing device such as a desktop computer, a notebook, a palm computer, and a smart tablet. The electronic device may include, but is not limited to, a processor and a memory. Those skilled in the art can understand that the above components are only examples of the electronic device, and do not constitute a limitation on the electronic device. It may include more or fewer components than the above, or combine some components, or different components. For example, the electronic device may further include input / output devices, network access devices, a bus, etc.

[0062] The so-called processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The processor is the control center of the electronic device and connects various parts of the entire electronic device through various interfaces and circuits.

[0063] The memory can be used to store the computer programs and / or modules. By running or executing the computer programs and / or modules stored in the memory, and by invoking the data stored in the memory, the processor realizes various functions of the electronic device. The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created according to the use of the mobile phone (such as audio data, phone book, etc.). In addition, the memory may include high-speed random access memory and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.

[0064] Among them, if the modules / units integrated in the electronic device are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0065] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement it without creative effort.

[0066] The above-described specific embodiments have further elaborated on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. It is particularly pointed out that for those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-layer circuit board drilling method based on machine vision, characterized in that: include: Acquire multi-layer circuit board images; Preprocessing the multi-layer circuit board image to obtain an image to be identified; Inputting the image to be identified into a pre-trained defect detection model to obtain defect location data; Performing point recognition and matching on the image to be recognized to obtain optimal hole position coordinates, and performing correction according to the optimal hole position coordinates to obtain hole position information data; Nodes are constructed and distances are calculated according to the hole position information data and the defect position data to generate a hole position node graph; According to the hole node graph, an ant colony algorithm is applied to perform path planning, and an optimal drilling path is obtained through iterative search; The multi-layer circuit board is drilled according to the optimal drilling path.

2. The multi-layer circuit board drilling method based on machine vision according to claim 1, characterized in that: The preprocessing of the multi-layer circuit board image to obtain the image to be identified includes: Performing grayscale processing on the multi-layer circuit board image to obtain an original grayscale image; Get the grayscale threshold; Performing binarization processing according to the original grayscale image and the grayscale threshold to obtain a binarized image; A smoothing process is performed on the binary image to obtain an image to be recognized.

3. The method for drilling a multi-layer circuit board based on machine vision according to claim 1, characterized in that: The training process of the defect detection model includes: A defect detection model is constructed based on historical circuit board images and historical defect distribution data, and the model is trained. When the number of training times reaches a preset upper limit or the loss function of the model is detected to meet the conditions, the training is determined to be completed, and a trained model is obtained; The image to be identified is input into the trained model to obtain defect location data.

4. The method for drilling a multi-layer circuit board based on machine vision according to claim 1, characterized in that: The step of performing point recognition and matching on the image to be recognized to obtain optimal hole position coordinates, and correcting according to the optimal hole position coordinates to obtain hole position information data includes: Inputting the image to be identified into a pre-trained feature extraction model, and outputting a circuit board feature map; Perform corner point detection according to the circuit board feature map to obtain a corner point coordinate matrix; Performing feature descriptor matching on the corner point coordinate matrix to obtain optimal hole position coordinates; The optimal hole position coordinates are iteratively corrected using the following formula to obtain hole position information data: in, represents the coordinate correction amount, represents the Jacobian matrix, represents the transpose of the Jacobian matrix, Indicates the correction error, Represents pixels The actual gray value, Represents the gray value of the positioning point template, Indicates the actual gray value in The partial derivative in the direction of the axis, Indicates the actual gray value in Partial derivatives in the axis direction; The training process of the feature extraction model includes: Building a feature extraction model based on historical circuit board images and historical feature images, training the model, and determining that the training is completed when the number of training times reaches a preset upper limit or the loss function of the model meets the conditions, thereby obtaining a trained model; The image to be identified is input into the trained model to obtain a circuit board feature map.

5. The method for drilling a multi-layer circuit board based on machine vision according to claim 1, characterized in that: The step of constructing nodes and performing distance calculations according to the hole position information data and the defect position data to generate a hole position node graph includes: Constructing nodes according to the defect location data to obtain abnormal nodes; Construct nodes according to the hole position information data to obtain hole position nodes; Perform distance calculation based on the defect position data and hole position information data to obtain a node distance; Generate a hole node graph according to the abnormal nodes, the hole node and the node distances; The node distance is used as the weight of the edge.

6. The multi-layer circuit board drilling method based on machine vision according to claim 1, characterized in that: The method of performing path planning by applying an ant colony algorithm according to the hole node graph and iteratively searching to obtain an optimal drilling path includes: Initialize the number of ants, pheromone concentration, evaporation rate and number of iterations; Taking the hole position nodes as ant colony nodes, and performing ant colony search on the hole position node graph; And update the pheromone concentration according to the following formula: in, Indicates At iteration Node No. The pheromone concentration of node number, , represents the evaporation rate, express The amount of pheromones increased in this iteration; When the number of iterations reaches a preset upper limit, disconnecting the edge whose pheromone concentration is lower than a preset pheromone threshold; Repeat the iteration until only one connected path remains, which is the optimal drilling path.

7. The method for drilling a multi-layer circuit board based on machine vision according to claim 6, characterized in that: Before taking the hole position nodes as ant colony nodes and performing ant colony search on the hole position node graph, the method further includes: Set abnormal nodes to be inaccessible; Weakening the hole nodes within a preset abnormal distance around the abnormal node to obtain weakened hole nodes; The probability of ants selecting the weakened hole node is reduced according to a preset probability rule.

8. A multi-layer circuit board drilling device based on machine vision, characterized in that: include: A data acquisition module, used for acquiring a multi-layer circuit board image; A preprocessing module, used for preprocessing the multi-layer circuit board image to obtain an image to be recognized; A defect detection module, used for inputting the image to be identified into a pre-trained defect detection model to obtain defect location data; A hole position recognition module is used to perform point recognition and matching on the image to be recognized to obtain the optimal hole position coordinates, and to correct the optimal hole position coordinates to obtain hole position information data; A node graph module, used to construct nodes and perform distance calculations according to the hole position information data and the defect position data, and generate a hole position node graph; A path planning module, used to perform path planning based on the hole node graph using an ant colony algorithm, and iteratively search to obtain an optimal drilling path; The drilling implementation module is used to drill holes in the multi-layer circuit board according to the optimal drilling path.

9. An electronic device, characterized in that: It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and when the processor executes the computer program, it implements the multi-layer circuit board drilling method based on machine vision as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the multi-layer circuit board drilling method based on machine vision as described in any one of claims 1 to 7.

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