Memory cell for 3D NAND flash memory

Abstract

According to one aspect, there is provided a memory cell for a 3D NAND flash memory, the memory cell comprising: a gate layer; a channel layer; a memory stack disposed between the gate layer and the channel layer and including a charge trap layer facing the gate layer and a tunneling oxide layer; and an insulating piezoelectric gate layer disposed on the gate layer, wherein the piezoelectric gate layer and the memory stack are separated by an air gap. According to another aspect, a vertical memory array for a 3D NAND flash memory is provided. According to yet another aspect, a method of forming a vertical memory array for a 3D NAND flash memory is provided.

Description

Technical Field

[0001] The present invention generally relates to memory cells for 3D NAND flash memory, vertically stacked memory arrays including the memory cells, and methods of forming a memory array for 3D NAND flash memory. Background Art

[0002] NAND flash plays a key role in electronic storage, leveraging a NAND gate-based architecture to achieve non-volatile data retention. NAND technology is characterized by high-density, cost-effective data storage with fast access times. Its inherent ability to maintain data integrity during power-off makes it indispensable in various applications including USB drives, SSDs, and memory cards. Nowadays, vertically stacked NAND flash represents the dominant NAND flash technology. In such a memory, flash memory cells are vertically stacked along so-called memory strings.

[0003] NAND memory stores information in the form of charge carriers in a charge trap layer or a floating gate that is part of a flash memory cell transistor. The concentration of the stored charge carriers corresponds to the stored information bits and can be read through the resulting threshold voltage shift of the flash memory cell. Additionally, quantum tunneling is utilized to change the concentration of charge carriers in the flash memory cell for writing or erasing information. The performance of a NAND flash memory cell can be characterized by its programming start point and programming efficiency. The programming start point is related to the voltage required to provide a significant threshold voltage change in the memory cell, while the programming efficiency is related to the rate of change of the threshold voltage with increasing applied voltage. Thus, both the programming start point and programming efficiency determine the programming voltage, which is the voltage required to achieve a target threshold voltage shift corresponding to the programmed cell state. In this regard, a low programming voltage is generally desirable.

[0004] Furthermore, high programming efficiency is beneficial for the interference behavior of the memory cells as it increases the difference between the threshold voltage shifts occurring during read and program modes. It also enlarges the window between different programming levels in multi-level cell operation. However, in order to obtain an early programming start point and high programming efficiency, the blocking oxide used in the memory cells should meet conflicting requirements. First, to lower the start point, a high dielectric constant of the blocking oxide is needed as it increases the electric field across the tunneling oxide during a programming operation, thereby enhancing the injection of carriers into the charge storage layer. Second, to achieve high programming efficiency, a low dielectric constant of the blocking oxide is needed as it increases the effect of the stored charge on the cell threshold voltage during a read operation. Third, to prevent a reduction in programming efficiency due to excessive carrier flow to the gate of the memory cell, a sufficient conduction band offset is needed between the blocking oxide and the charge storage layer. Despite numerous attempts to mitigate the above conflicting requirements, there is still room for improvement in providing efficient NAND flash memory. SUMMARY OF THE INVENTION

[0005] In view of the above, an object of the present invention is to provide an improved memory cell for 3D NAND flash memory, which solves at least some of the needs for the conflict of the blocking oxide, and to provide a vertical memory array of 3D NAND flash memory including a plurality of memory cells and a method for forming the vertical memory array.

[0006] Another object is to provide a memory cell for 3D NAND flash memory having a low programming start point and high programming efficiency.

[0007] Another object is to provide a memory cell for 3D NAND flash memory having improved programming efficiency compared to existing memory cells.

[0008] To achieve the above object and at least one other object that will be apparent from the following description, there is provided a memory cell for 3D NAND flash memory having the features defined in claim 1. There is provided a vertical memory array of 3D NAND flash memory including a plurality of memory cells according to claim 5. There is provided a method for forming a vertical memory array for 3D NAND flash memory according to claim 11. Embodiments of the present invention will be apparent from the dependent claims.

[0009] Thus, according to one aspect of the present invention, there is provided a memory cell for 3D NAND flash memory, the memory cell comprising: a gate layer; a channel layer; a memory stack disposed between the gate layer and the channel layer and including a charge trap layer and a tunneling oxide layer, the charge trap layer facing the gate layer; and an insulating piezoelectric gate layer disposed on the gate layer, wherein the piezoelectric gate layer and the memory stack are spaced apart by an air gap.

[0010] Accordingly, the memory cell according to this aspect is based on the idea that the programming start point and programming efficiency can be improved by replacing the conventional blocking oxide of the memory cell for 3D NAND flash memory with an insulating piezoelectric gate layer (hereinafter abbreviated as: "piezoelectric gate layer") in combination with an air gap. By arranging the piezoelectric gate layer on the gate layer and separating the piezoelectric gate layer and the memory stack by an air gap, the thickness of the piezoelectric gate layer will increase when the piezoelectric gate layer is subjected to a voltage. As a result, the air gap will become smaller when the thickness of the piezoelectric gate layer increases and the piezoelectric gate layer expands into the air gap. This means that the thickness of the piezoelectric gate layer will increase more during the programming operation than during the read operation of the memory cell, because programming the memory cell is performed using a higher voltage compared to reading the memory cell. In fact, about 15 - 20 volts can be used during the programming operation, while about 5 - 10 volts can be used during the read operation. The above behavior of the piezoelectric gate layer and the air gap will thus result in a higher combined dielectric constant during the programming operation compared to the read operation of the memory cell.

[0011] By customizing the material and thickness of the piezoelectric gate layer, a negligible change or (substantially) no change in the thickness of the piezoelectric gate can be achieved during the read operation, while a significant increase in the thickness of the piezoelectric gate layer can be achieved during the programming operation. For this purpose, the combined dielectric constant of the piezoelectric gate layer and the air gap can be substantially unaffected during the read operation, but can increase during the programming operation at the same time. The above behavior of the piezoelectric gate layer and the air gap will thus result in a different equivalent oxide thickness (EOT) during the programming operation compared to the read operation of the memory cell. More specifically, the EOT of the piezoelectric gate layer and the air gap will decrease as the thickness of the piezoelectric gate layer increases and the piezoelectric gate layer expands into the air gap. This means that the EOT of the piezoelectric gate layer and the air gap will be lower during the programming operation compared to the read operation. Therefore, both the programming start point and programming efficiency of the memory cell can be improved. In addition, the retention characteristics of the memory cell can be improved because the presence of the air gap can reduce the loss of charge carriers entering the gate layer compared to when using a high-k blocking oxide. More specifically, the presence of the air gap (in combination with the piezoelectric gate layer) can result in a higher band offset compared to the existing high-k blocking oxide.

[0012] "The charge trap layer faces the gate layer" herein means that the charge trap layer is closer to the gate layer than the tunneling oxide layer.

[0013] "Air gap" herein refers to the space or void separating the piezoelectric gate layer and the memory stack. This space may contain air and / or other ambient gases present in the process environment in which the memory cells are fabricated. This space typically may be free of any solid material. However, this space may include traces of solid material used in forming the air gap. To this end, the traces of solid material may form a sparse porous structure or network. Such traces may have no significant effect or no effect on the expansion of the piezoelectric gate layer into the air gap.

[0014] In some embodiments, the size of the air gap may be in the range of 0.5 nm to 5 nm. Since the air gap has a size in the range of 0.5 nm to 5 nm, the air gap can be thin enough such that when a voltage is applied to the gate layer of the memory cell during a programming operation, charge carriers can tunnel from the channel layer through the tunneling oxide and into the charge trap layer. Additionally, since the air gap has a size in the range of 0.5 nm to 5 nm, the piezoelectric gate layer can expand into the air gap without contacting the memory stack (assuming a typical range of programming voltages). Thus, the piezoelectric gate layer can expand into the air gap without completely closing the air gap, which reduces the risk of static friction or adhesion between the piezoelectric gate layer and the memory stack. The air gap size herein refers to the size in the non-biased state, i.e., the size when there is no electric field on the piezoelectric gate layer.

[0015] In some embodiments, the size of the air gap may be in the range of 0.5 nm to 2 nm.

[0016] In some embodiments, the piezoelectric gate layer may have a thickness in the range of 2 nm to 10 nm and a thickness expansion rate per volt applied to the piezoelectric gate layer in the range from 0.2% to 1.2%, which is advantageous because the piezoelectric gate layer can expand during the programming operation of the memory cell such that the combined dielectric constant of the piezoelectric gate layer and the air gap is increased during the programming operation.

[0017] "Thickness expansion rate per volt applied to the piezoelectric gate layer" herein refers to the degree of increase in the thickness of the piezoelectric gate layer per volt applied across the piezoelectric gate layer (i.e., along the thickness of the piezoelectric gate layer (as looking from the gate layer towards the memory stack)).

[0018] The thickness of the piezoelectric gate layer may increase by at least 5% in response to a voltage in the range of 10 - 20 volts.

[0019] The thickness of the piezoelectric gate layer may advantageously increase by approximately 10% in response to a voltage in the range of 10 - 20 volts.

[0020] In some embodiments, the piezoelectric gate layer may include one or more of HfO2, Si-doped HfO2, ZnO, BN, BaTiO3, AlN, and GaN.

[0021] According to another aspect of the present invention, there is provided a vertical memory array for 3D NAND flash memory, including a plurality of memory cells according to the previous aspect, wherein these memory cells are stacked on top of each other in a vertical direction to form a memory cell stack. Generally speaking, the features of this aspect provide advantages similar to those discussed above with reference to the previous aspect. Therefore, in order to avoid unnecessary repetition, the said advantages will not be repeated.

[0022] In some embodiments, the air gap of each memory cell can be formed by a corresponding portion of a common air gap that extends continuously in the vertical direction through the memory cell stack. Thus, each memory cell can be located at a corresponding portion of the air gap that is common to all the memory cells of the vertical memory array.

[0023] In some embodiments, the piezoelectric gate layer of each memory cell can be a discrete (insulating) piezoelectric gate layer disposed between a corresponding pair of inter-gate spacer layers. Thus, "discrete" refers to the corresponding discrete (i.e., separate and disconnected) portions of the piezoelectric gate layer. More specifically, each memory cell can have an associated discrete piezoelectric gate layer that is separate from the corresponding discrete piezoelectric gate layers of adjacent memory cells. In this way, the voltage applied to the discrete piezoelectric gate layer of a memory cell can affect adjacent memory cells less compared to when a common piezoelectric gate layer extends through the memory cell stack in the vertical direction.

[0024] In some embodiments, the vertical memory array can include inter-gate spacer layers that are alternately arranged with the gate layers. Such inter-gate spacer layers can be formed of a dielectric material that is typically an oxide.

[0025] In some embodiments, when the piezoelectric gate layer of each memory cell is a discrete piezoelectric gate layer disposed between a corresponding pair of inter-gate spacer layers, the air gap of each memory cell can be formed by a corresponding portion of a common air gap that extends continuously in the vertical direction through the memory cell stack.

[0026] In some embodiments, the air gap of each memory cell can be a discrete air gap disposed between a corresponding pair of inter-gate spacer layers. Thus, each memory cell can have an associated discrete air gap that is separate from the corresponding discrete air gaps of adjacent memory cells.

[0027] In some embodiments, the vertical memory array can further include an insulating liner layer that extends continuously in the vertical direction through the memory cell stack at a position between the air gap of each memory cell and the charge trap layer. This insulating liner layer can assist in forming the air gap during the manufacture of the vertical memory array.

[0028] According to another aspect of the present invention, there is provided a method of forming a vertical memory array for 3D NAND flash memory, the method comprising: forming a layer stack on a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers; sequentially forming a piezoelectric gate layer, a dummy layer, and an insulating layer along sidewalls surrounding memory holes in the layer stack; performing a heat treatment process on the dummy layer, the heat treatment process being adapted to convert the dummy layer into an air gap, wherein the air gap is laterally formed between the piezoelectric gate layer and the insulating liner layer; after the heat treatment process, forming a charge trapping layer along the insulating liner layer and subsequently forming a tunneling oxide layer and a channel layer.

[0029] By this method, an improved vertical memory array for 3D NAND flash memory can be formed. Thus, by this method, a vertical memory array for 3D NAND flash memory can be formed in which an air gap is located between a piezoelectric gate layer and an insulating liner layer. This means in practice that the air gap separates the piezoelectric gate layer from the memory stack of the vertical memory array being formed.

[0030] Generally speaking, the features of this aspect provide advantages similar to those discussed above with reference to the previous aspect. Therefore, to avoid unnecessary repetition, the said advantages will not be repeated.

[0031] In some embodiments, the method may further include, before forming the piezoelectric gate layer: forming a recessed area in the sidewall of the layer stack by laterally etching the gate layer from the memory holes; wherein the piezoelectric layer is selectively formed in the recessed area such that discrete piezoelectric gate layers are formed in each recessed area.

[0032] In some embodiments, the dummy layer may be selectively formed on the discrete piezoelectric gate layers in each recessed area. By selectively forming the dummy layer on the discrete piezoelectric gate layers in each recessed area, discrete air gaps can be formed in each recessed area.

[0033] In some embodiments, the dummy layer may be formed as a continuous layer along the sidewalls of the memory holes. By forming the dummy layer as a continuous layer along the sidewalls of the memory holes, a common air gap that extends continuously in the vertical direction through the memory cell stack can be formed.

[0034] In some embodiments, the dummy layer may be formed of a polymer-containing material. There are many polymers that can be effectively and reliably removed using a heat treatment process (e.g., by evaporation), leaving substantially no organic residues in the air gap being formed (although non-polymeric traces may remain).

[0035] In some embodiments, the insulating liner layer may be deposited at a temperature lower than the temperature that causes the conversion of the dummy layer. Thus, accidental conversion of the dummy layer before the air gap is "sealed" by the liner layer can be avoided.

[0036] In some embodiments, the insulating liner layer is formed of low thermal oxide (LTO). The low thermal oxide (e.g., LTO SiO2) can be reliably deposited without triggering the conversion of the dummy layer.

[0037] In some embodiments, the thickness of the insulating liner layer is in the range of 1 - 4 nm or 1 - 2 nm. The insulating liner layer within this thickness range allows the decomposed components (e.g., gas-phase components) formed during the conversion of the dummy layer into an air gap to leave (i.e., diffuse) through the liner layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will now be described in more detail with reference to the drawings showing embodiments of the invention.

[0039] Figure 1 A memory cell according to an embodiment is schematically shown.

[0040] Figure 2a -b schematically shows a schematic cross-sectional view and a top view of a starting structure for forming a memory array according to an embodiment, respectively.

[0041] Figure 3 The structure after forming the insulating piezoelectric gate layer, the dummy layer, and the insulating liner is shown.

[0042] Figure 4 The structure after converting the dummy layer into an air gap is shown.

[0043] Figure 5 The structure after forming the charge trap layer and the tunneling oxide layer is shown.

[0044] Figure 6 The structure after forming the channel layer is shown.

[0045] Figure 7 The structure after forming the recessed region in the gate layer is shown Figure 2a is shown.

[0046] Figure 8 The structure after forming the piezoelectric gate layer and the dummy layer is shown.

[0047] Figure 9 The structure after forming the insulating liner is shown.

[0048] Figure 10 The structure after converting the dummy layer into an air gap is shown.

[0049] Figure 11 The structure after forming the charge trap layer and the tunneling oxide layer is shown.

[0050] Figure 12Shows the structure after the formation of the channel layer. Detailed Description

[0051] Embodiments of memory cells and memory arrays for 3D NAND flash memories, such as 3D gate-all-around NAND (3D GAA NAND), and methods for forming such memory arrays will now be described with reference to the accompanying drawings. The drawings are merely schematic, and the relative dimensions of certain structures and layers may be exaggerated and not drawn to scale. Instead, the dimensions may be adjusted to make the illustration clear and to assist in understanding the following description. When present in the figures, the indicated axes X, Y, and Z consistently refer to the first horizontal or lateral direction, the second horizontal or lateral direction, and the vertical direction, respectively. As used herein, the terms "horizontal" and "lateral" refer to directions parallel to the support substrate of the memory structure. The term "vertical" refers to a direction parallel to the substrate normal, i.e., transverse to the substrate.

[0052] Figure 1 A memory cell 100 for a 3D NAND flash memory according to an embodiment is schematically shown. The depicted memory cell 100 includes a gate layer 14 and a channel layer 32. A memory stack 40 is disposed between the gate layer 14 and the channel layer 32. The memory stack 40 includes a charge trap layer 27 and a tunneling oxide layer 30. The charge trap layer 27 faces the gate layer 14. That is, the charge trap layer 27 is closer to the gate layer 14 than the tunneling oxide layer 30. An insulating piezoelectric gate layer 50 is disposed on the gate layer 14. The piezoelectric gate layer 50 will hereinafter be referred to as the PZ layer 50. The PZ layer 50 and the memory stack 40 are separated by an air gap 52.

[0053] The gate layer 14 can be a nitride-containing layer, such as a SiN layer, thereby forming a sacrificial gate layer 14, which is intended to be replaced by a replacement metal gate (RMG) stack in subsequent process steps. The gate layer 14 can also be a functional gate layer, such as a metal layer or a layer containing highly doped polysilicon.

[0054] The channel layer 32 can be formed of any suitable channel material commonly used in the industry for channel layers, typically a semiconductor material, such as Si, SiGe, or Ge.

[0055] The charge trap material 27 of the memory stack 40 can include SiN (i.e., Si3N4) or some other oxide material suitable for use as a charge trap material. The charge trap layer 27 can have a thickness in the range of 4 nm to 8 nm.

[0056] The tunneling oxide layer 30 of the memory stack 40 can be formed of any material commonly used in the industry, a non-limiting example being SiON. The tunneling oxide 30 can have a thickness in the range of 3 nm to 8 nm.

[0057] The PZ layer 50 can be formed of a suitable insulating piezoelectric material, such as a piezoelectric oxide or nitride. The PZ layer 50 can have a thickness ranging from 2 nm to 10 nm. That is, the thickness as seen along the Figure 1 X-axis can be from 2 nm to 10 nm. Non-limiting examples of suitable materials for the PZ layer 50 are HfO2, Si-doped HfO2, ZnO, BN, BaTiO3, and GaN. Such suitable materials for the PZ layer 50 will expand when subjected to a voltage. That is, the thickness of the PZ layer 50 formed of the material will increase when the PZ layer 50 is subjected to a voltage. Thus, when the PZ layer 50 is subjected to a voltage, the thickness of the PZ layer 50 will increase such that the PZ layer 50 expands into the air gap 52 while the thickness of the air gap 52 decreases accordingly. By forming the PZ layer 50 of the suitable material, the PZ layer 50 can have a thickness expansion rate ranging from 0.2% to 1.2% per volt applied to the PZ layer 50.

[0058] The air gap 52 can have a size ranging from 0.5 nm to 5 nm. That is, the thickness as seen along the Figure 1 X-axis can be from 0.5 nm to 5 nm.

[0059] Hereinafter, a method for forming a vertical memory array 1 for 3D NAND flash memory including a plurality of memory cells 100 of the above type will be described with reference to FIGS. 2-6.

[0060] Figure 2a -b schematically show a cross-sectional view and a top view of the structure 1 at the initial stage of the method, respectively. The structure 1 includes a layer stack 10 representing a precursor or starting structure for the vertical memory array 1 to be formed and on which the processing steps of the method disclosed hereinafter will be performed as Figure 7 shown.

[0061] The layer stack 10 is formed on a substrate 2 and includes an alternating sequence of gate layers 14 and inter-gate spacer layers 12.

[0062] The substrate 2 can be a conventional substrate suitable for semiconductor processing and for supporting the memory structure of the 3D NAND flash memory. The substrate 2 can be, for example, a Si substrate, a Ge substrate, or a SiGe substrate. Other examples include a silicon-on-insulator (SOI) substrate, a GeOI substrate, or a SiGeOI substrate.

[0063] The gate layer 14 can be a nitride-containing layer, such as a SiN layer, thus forming a sacrificial gate layer 14, which is intended to be replaced by an RMG stack in subsequent process steps. The gate layer 14 can also be a functional gate layer, such as a layer containing highly doped polysilicon.

[0064] The inter-gate spacer layer 12 can be an oxide-containing layer, such as a SiO2 layer or another suitable interlayer dielectric (e.g., low-k). The inter-gate spacer layer 12 is arranged in the layer stack 10 to provide a vertical separation between the memory cells / word lines of the memory device to be formed.

[0065] The layer stack 10 can be formed by alternately depositing gate materials (e.g., nitrides) and inter-gate spacer materials (e.g., oxides) layers using deposition processes known in the art, such as chemical vapor deposition (CVD), physical vapor deposition, or atomic layer deposition (ALD).

[0066] The inter-gate spacer layer 12 and the gate layer 14 can be formed in large numbers according to the expected number of stacked memory cells of the memory device. It should be noted that the number of layers 12, 14 in the shown layer stack 10 is only a non-limiting example, and the methods disclosed herein are compatible with stacks of substantially any number (such as 64, 128, 256, or greater) of memory cells currently used or expected in the industry.

[0067] As an example, the inter-gate spacer layer 12 and the gate layer 14 can be formed to have corresponding layer thicknesses in the range of 5 - 25 nm. The z-spacing of the layer stack 10 (i.e., the combined thickness of one inter-gate spacer layer and one gate layer 14) can be in the range of about 45 nm to 15 nm or less.

[0068] After depositing the layers 12 and 14 in the layer stack 10, memory holes 4 can be patterned in the layer stack 14, for example, by photolithography and etching processes. While Figure 2a -b shows a portion of the layer stack 10 surrounding a single memory hole 4, it should be noted that corresponding memory holes 4 can be patterned at each location where a corresponding vertical memory cell string is needed. As shown, the memory holes 4 can be formed to extend through each of the inter-gate spacer layers 12 and the gate layers 14 in the layer stack 10. As further shown in Figure 2b a top view, the memory holes 4 can be formed to have a circular cross-sectional shape such that the memory holes 4 can be formed to have a substantially circular cylindrical shape. However, the memory holes 4 can also be formed to have other cross-sectional shapes, such as elliptical or polygonal.

[0069] Although not shown in Figure 2a it is known in the art that the layer stack 10 can further include a sub-stack of a selection layer and a source layer for respectively forming a selection plate and a source plate of the memory device below the layers 12, 14. The selection layer and the source layer can thus form the bottom sub-stack of the layer stack 10. The selection layer and the source layer can be formed of conventional techniques and materials (e.g., doped semiconductor layers (e.g., polysilicon)) and separated by an interlayer dielectric layer.

[0070] In Figure 3 , the PZ layer 50, the dummy layer 23, and the insulating liner layer 26 have been formed in sequence along the sidewalls of the memory hole 4 around the layer stack 10. The PZ layer 50 can be formed of any example of an insulating piezoelectric material referred to in Figure 1 .

[0071] The PZ layer 50 can have a thickness of 2 nm to 10 nm. That is, the thickness as seen along the Figure 1 X-axis can be 2 nm to 10 nm. Non-limiting examples of suitable materials for the PZ layer 50 are HfO2, Si-doped HfO2, ZnO, BN, BaTiO3, AlN, and GaN. The PZ layer 50 can be formed by depositing the material of the PZ layer via ALD or CVD.

[0072] The depicted dummy layer 23 is conformally deposited (e.g., using ALD) along the sidewalls of the memory hole 4 after the PZ layer 50 is formed. Thus, the dummy layer 23 is conformally deposited on the PZ layer 50, as Figure 3 shown. After deposition, the dummy layer 23 can be anisotropically etched in the top-down orientation (negative Z direction) to remove portions of the dummy layer 23 deposited on the horizontal surfaces of the structure 1 (such as the bottom of the memory hole 4 and the top surface of the layer stack 10). Conventional dry etching processes such as reactive ion etching (RIE), ion beam etching (IBE), or other plasma etching can be used. Thus, the dummy layer 23 can be formed as a continuous layer along the sidewalls of the memory hole 4. The dummy layer 23 defines a temporary placeholder for the air gap 52 to be formed later. The dummy layer 23 is formed of a dummy material selected to be convertible into the air gap 52 through a heat treatment process. Example materials for the dummy layer 23 include polymer-containing materials such as a tetracyclododecene (TD)-based sacrificial polymer, a polycycloolefin polymer (such as a polynorbornene polymer), or some other conventional thermally degradable polymer that can be deposited on the PZ layer 50.

[0073] The depicted insulating liner layer 26 is conformally deposited (e.g., using ALD) to cover the sidewalls of the memory hole 4 and thereby cover the dummy layer 23. As Figure 3 shown, the insulating liner layer 26 is also deposited to cover the topmost inter-gate spacer layer 12. That is, the insulating liner layer 26 covers the top surface of the layer stack 10 and the sidewalls of the memory hole 4. After the insulating liner layer 26 is deposited, the dummy layer 23 is thus sealed from the memory hole 4. More specifically, the dummy layer 23 is sandwiched between the insulating liner layer 26 and the PZ layer 50.

[0074] The liner layer 26 is deposited to a certain thickness to allow the decomposed components (e.g., gaseous components) of the dummy layer 23 to leave (i.e., diffuse) through the insulating liner layer 26. When the dummy layer 23 is converted into an air gap 52 during a subsequent heat treatment process, the decomposed components of the dummy layer 23 are formed. The insulating liner layer 26 can be formed to have a thickness in the range of 1 - 4 nm or 1 - 2 nm. The insulating liner layer 26 can be formed of porous SiO2. The insulating liner layer 26 can be a low thermal oxide (LTO) such as LTO SiO2. By depositing the insulating liner layer 26 with a thermal budget that has a sufficient margin at the conversion temperature of the dummy material towards the dummy layer 23, premature conversion of the dummy layer 23 can be avoided. For example, for any of the above dummy material examples, a deposition temperature of 300 °C or lower for the liner layer 26 can generally provide a sufficient margin.

[0075] Figure 4 Structure 1 after converting the dummy layer 23 into an air gap 52 is shown. Thus, the air gap 52 is laterally formed between the PZ layer 50 and the insulating liner layer 26. This conversion is achieved by performing a heat treatment process on the dummy layer 23, which is adapted to convert the dummy material (e.g., polymer) of the dummy layer 23 into an air gap 52. This treatment process can be performed by performing a thermal annealing (e.g., in a reaction chamber or furnace). As those skilled in the art will understand, the thermal energy required to achieve a sufficient conversion ratio depends on the specific dummy material of the dummy layer 23. For example, for any of the above dummy material examples, heating the environment of structure 1 or the structure to about 500 °C is generally sufficient to completely convert the dummy layer 23 without forming any significant residues in the resulting air gap 52.

[0076] It is further contemplated that the dummy material can include components or additives that are converted or retained during the heat treatment process to form a low - k sparse matrix or a porous air - gap structure 28 (organic or inorganic) that remains in the air gap 52, such as silicate compounds, such as (low - k) organosilicate (SiOC) or fluorosilicate (SiOF). Thus, the air gap 52 is not limited to a void that spans the entire volume previously occupied by the dummy material, but can also include a low - k sparse structure with pores surrounded by or containing air. However, even in the case where the sparse structure is retained, at least a majority of the volume spanned by the air gap 52 is typically filled with air.

[0077] Figure 5 Structure 1 after forming a charge - trap layer 27 along the insulating liner layer 26 and then forming a tunneling oxide layer 30 is shown. Thus, along the sidewalls of the memory hole 4, a charge - trap layer 27 is formed in the memory hole 4 and then a tunneling oxide layer 30 is formed. Thus, the charge - trap layer 27 is formed along the liner layer 26, and the tunneling oxide layer 30 is formed along the charge - trap layer 27.

[0078] The charge trap layer 27 can be conformally deposited on the insulating liner layer 26 (e.g., using ALD). The charge trap layer 27 can include any suitable charge trap material conventionally used in the industry for charge trap layer 27, and a non-limiting example is SiN. The charge trap layer 27 can be formed to have a thickness in the range of 4 - 8 nm.

[0079] The tunneling oxide layer 30 can be formed from any material conventionally used in the industry for tunneling oxide layers, and a non-limiting example is SiON.

[0080] Figure 6 Structure 1 is shown after the channel layer 32 has been formed along the sidewalls of the memory hole 4. As Figure 6 shown, the insulating liner layer 26, the charge trap layer 27, and the tunneling oxide layer 30 can be etched back above the layer stack 10 and at the bottom of the memory hole 4 before forming the channel layer 32. Thus, a top-down anisotropic etching process can be used to remove the insulating liner layer 26, the charge trap layer 27, and the tunneling oxide layer 30 from the horizontal surfaces of structure 1 (e.g., the bottom of the memory hole 4, the top surface of the layer stack 10) before forming the channel layer 32. Thus, the insulating liner layer 26, the charge trap layer 27, and the tunneling oxide layer 30 can be removed using an anisotropic etching process such as RIE, IBE, or other plasma etching. In the example shown, the etch back was performed after each of the insulating liner layer 26, the charge trap layer 27, and the tunneling oxide layer 30 was deposited. However, the etch back of the insulating liner layer 26 and the charge trap layer 27 can also be performed first, after which the tunneling oxide layer 30 is deposited and then the etch back of the tunneling oxide layer 30 is performed.

[0081] The channel layer 32 can be formed from any suitable channel material conventionally used in the industry for channel layers, typically a semiconductor material such as Si, SiGe, or Ge.

[0082] Figure 6 The depicted channel layer 32 of is a macaroni-type channel layer 32, where the channel layer 32 extends along the sidewalls of the storage hole 4. In the case of the macaroni-type channel layer 32, the remaining portion of the memory hole 4 can typically be filled with a fill oxide after the channel layer 32 is formed. Although not shown, the channel layer can be formed as a so-called full channel layer, where the channel layer fills the entire memory hole 4.

[0083] Although Figure 6 not shown in, the channel layer 32 can exhibit an extension beyond the shown portion of structure 1 to facilitate connection to peripheral semiconductor devices and circuits (such as select transistors), as is known to those skilled in the art.

[0084] Thus, in Figure 6In a 3D NAND flash memory, a vertical memory array 1 including a plurality of memory cells 100 has been formed. In the vertical memory array 1, the memory cells 100 are stacked on top of each other in a vertical direction to form a memory cell stack. As Figure 6 shown. An air gap 52 of each memory cell may be formed by a corresponding portion of a common air gap 52 that extends continuously in the vertical direction through the memory cell stack.

[0085] If the gate layer 14 is a sacrificial gate layer, the method may continue with replacing the sacrificial gate layer 14 with a replacement metal gate (RMG) stack. The sacrificial gate layer 14 may be removed by etching back the sacrificial gate layer 14 from a second hole (not shown) in the layer stack 10 (e.g., referring to the memory hole 4 as a front-side hole or opening, the second hole may be referred to as a back-side hole or opening). Subsequently, the lateral cavities thus formed at each layer of the sacrificial gate layers 14 may be filled with a replacement metal gate stack that replaces the sacrificial gate layer 14. As is known in the art, the replacement metal gate stack deposition may include depositing one or more conductive layers, such as metals, such as one or more of TiN and W. Before depositing the (respective) conductive layers, a (conformal) high-k gate dielectric may be deposited.

[0086] Hereinafter, an alternative method of forming a vertical memory array 1 for 3D NAND flash memory including a plurality of memory cells 100 will be described with reference to Figures 7 - 12 description.

[0087] Figure 7 shows the structure 1 of Figure 2a and 2b after further processing steps have been performed on the structure 1. In Figure 7 a recessed region 18 has been formed in the sidewall surrounding the memory hole 4 by etching back the gate layer 14 laterally from the memory hole 4 with respect to the inter-gate spacer layer 12.

[0088] The gate layer 14 is selectively etched laterally (along the X-axis) with respect to the inter-gate spacer layer 12 such that a recessed region 18 is formed between the inter-gate spacer layers 12. That is, each recessed region / recess in the recessed region 18 is formed between a pair of inter-gate spacer layers 12. Since the sidewall extends around the circumference of the memory hole 4, the recessed region 18 may extend circumferentially around the memory hole 4. In the example of a circular memory hole 4, the recessed region 18 may thus be annular.

[0089] The gate layer 14 can be etched back using an etching process adapted to selectively etch the gate layer 14 with respect to the inter-gate spacer layer 12. That is, the etching process can be adapted to selectively etch (i.e., remove) the material of the gate layer 14 (e.g., nitride material) with respect to the material of the inter-gate spacer layer 12 (e.g., oxide material), such that the gate layer 14 can be etched laterally back without causing any substantial etching of the inter-gate spacer layer 12. The etching process can be applied to the sidewalls of the layer stack 10 via the memory holes 4. Any suitable selective etching process (such as an isotropic etching process), whether wet or dry, that provides a sufficient lateral etching component with respect to the gate layer 14 can be used.

[0090] The recessed region 18 can be formed to have a depth (along the X-axis) that matches the expected combined lateral thickness of the PZ layer 50 and the air gap 52 to be formed. The depth of the recessed region 18 (i.e., the amount of lateral etching) can be, for example, in the range of 2.5 - 15 nm. The depth of the recessed region 18 can be controlled by timing the lateral etching.

[0091] In Figure 8 the PZ layer 50 and the dummy layer 23 have been formed in sequence around the memory holes 4 of the layer stack 10 in the recessed region 18.

[0092] The PZ layer 50 can be of the type described above in connection with Figure 1 However, as Figure 8 shown, the PZ layer can be selectively formed in the recessed region 18 such that the PZ layer 50 includes a plurality of discrete portions separated along the vertical direction of the memory holes 4.

[0093] The dummy layer 23 can be of the type described above in connection with Figure 1 As Figure 8 shown, the dummy layer 23 can be selectively formed on the PZ layer 50 in the recessed region 18 such that the dummy layer 23 includes a plurality of discrete portions separated along the vertical direction of the memory holes 4.

[0094] To this end, the PZ layer 50 can be formed using area-selective deposition techniques. That is, the PZ layer 50 can be formed in the recessed region 18 without being formed or substantially not being formed on the inter-gate spacer layer 12. The PZ layer 50 can be deposited using any deposition process (such as an ALD or CVD process) that allows for area-selective deposition of the PZ layer 50 such that the PZ layer 50 is deposited on the growth-promoting or seed crystal surface portions in the recessed region 18 but not on the growth-inhibiting regions of the inter-gate spacer layer 12. The growth-promoting surface portions can be particularly defined by the surface portions of the etched-back gate layer 14 exposed in the recessed region 18 (i.e., Figure 7 the end faces 14a shown in

[0095] The dummy layer 23 can be deposited using any deposition process (e.g., ALD or CVD process) that allows for area-selective deposition of the dummy material such that the dummy material 23 is deposited on the growth-promoting or seed crystal surface portions in the recessed regions 18, but not on the growth-inhibiting regions of the inter-gate spacer layer 12. The growth-promoting surface portions can be particularly defined by the already-deposited PZ layer 50.

[0096] To facilitate the selective deposition of the PZ layer 50, a processing step can be performed on the layer stack 10 prior to depositing the PZ layer 50, the processing step being adapted to functionalize the surface portions / end faces 14a of the etched-back gate layer 14 in the recessed regions 18 and then deposit the PZ layer 50 on the functionalized surface portions in the recessed regions 8. For example, the functionalization can include depositing a deposition-promoting layer (not shown) on the surface portions 14a of the etched-back gate layer 14 in the recessed regions 18.

[0097] Additionally or alternatively, a processing process can be performed on the layer stack 10 that is adapted to passivate the exposed surface portions of the inter-gate spacer layer 12 with respect to the selective deposition of the PZ layer 50 and the dummy layer 23. For example, as is known in the art, certain deposition processes favor deposition on hydrogen-terminated surfaces (e.g., the deposition process preferentially deposits material on hydrogen-terminated surfaces). Thus, the processing process can be adapted to increase the occurrence of hydrogen-terminated bonds on the gate layer 14 (thereby facilitating deposition thereon) and / or reduce the occurrence of hydrogen-terminated bonds on the inter-gate spacer layer 12 (thus inhibiting deposition thereon). However, this is merely a non-limiting example, and other techniques are known to those skilled in the art.

[0098] As an alternative to the area-selective deposition of the PZ layer 50, the PZ layer 50 can also be deposited conformally and then an etch-back process can be performed to remove the portions of the PZ layer 50 deposited outside the recesses 18. The etch-back can include anisotropic etching oriented in the top-down direction (negative Z-axis) such that the portions of the PZ layer 50 in the recesses 18 are shielded or masked from above and can thus be preserved. By depositing the PZ layer 50 to a thickness that fills the recesses 18 (meaning the local thickness of the PZ layer 50 in the recesses 18 is greater than outside the recesses 18), an isotropic etch-back can also be used to etch back the PZ layer 50. By stopping the etch-back when the end faces of the inter-gate spacer layer 12 are exposed, portions of the PZ layer 50 are thus retained in the recesses 18 to define the final PZ layer 50 selectively formed in the recesses 18. A similar method can be applied to selectively form the dummy layer 23 on the PZ layer 50 in the recesses 18.

[0099] In Figure 9 an insulating liner layer 26 has been formed. The insulating liner layer 26 can be of the type described above in connection with Figure 3 description.

[0100] Figure 9 The insulating liner layer 26 shown is conformally deposited (e.g., using ALD) to cover the sidewalls of the memory holes 4 and thereby cover the dummy layer 23 and the end faces of the inter-gate spacer layers 12. As Figure 9 shown, the insulating liner layer 26 is also deposited to cover the uppermost inter-gate spacer layer 12. That is, the insulating liner layer 26 covers the top surface of the layer stack 10 and the sidewalls of the memory holes 4. After the insulating liner layer 26 is deposited, each discrete portion of the dummy layer 23 is thus sealed from the memory holes 4. More specifically, each discrete portion of the dummy layer 23 is sandwiched between the insulating liner layer 26 and the PZ layer 50 while being vertically limited (i.e., along the Z-axis) by a pair of inter-gate spacer layers 12 in the memory holes 4, as Figure 9 shown. Thus, the PZ layer 50 of each memory cell is a discrete PZ layer 50 arranged between a corresponding pair of inter-gate spacer layers 12 (i.e., arranged vertically).

[0101] In Figure 10 , the dummy layer 23 has been converted into an air gap 52. Thus, Figure 10 the air gap 52 for each memory cell is a discrete air gap 52 arranged between a corresponding pair of inter-gate spacer layers 12. The dummy layer 23 can be converted into an air gap 52, as already described in connection with Figure 4 .

[0102] Figure 11 shows the structure 1 after forming the charge trap layer 27 along the insulating liner layer 26 and then forming the tunneling oxide layer 30. The charge trap layer 27 and the tunneling oxide layer 30 can be formed, as described above in connection with Figure 5 .

[0103] Figure 12 shows the structure 1 after forming the channel layer 32 along the sidewalls of the memory holes 4. As Figure 12 shown, as in Figure 6 , the insulating liner layer 26, the charge trap layer 27, and the tunneling oxide layer 30 can be etched back above the layer stack 10 and at the bottom of the memory holes 4, after which the channel layer 32 is formed. The channel layer 32 can be formed, as described above in connection with Figure 6 .

[0104] Thus, in Figure 12 , a vertical memory array 1 for 3D NAND flash including a plurality of memory cells 100 has been formed. In the vertical memory array 1, the memory cells 100 are stacked on top of each other in the vertical direction to form a memory cell stack. As Figure 12 shown, the air gap 52 of each memory cell 100 is a discrete air gap 52 arranged between a corresponding pair of inter-gate spacer layers 12.

[0105] If the gate layer 14 is a sacrificial gate layer, the method can continue to replace the sacrificial gate layer 14 with a replacement metal gate stack, as described above.

[0106] Those skilled in the art will recognize that the present invention is in no way limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims. According to one example, the PZ layer 50 of each memory cell 100 can be formed as discrete PZ layers 50 disposed between a corresponding pair of inter-gate spacer layers 12, while at the same time the air gap 52 of each memory cell 100 can be formed from corresponding portions of a common air gap 52 that extends continuously in the vertical direction through the memory cell stack.

[0107] To this end, the gate layer 14 can be etched back from the memory holes 4 to form recessed regions 18 in the sidewalls of the layer stack 10, as described above in connection with Figure 7 described. The PZ layer 5050 can then be formed to fill the recessed regions 18 such that the PZ layer 50 is formed as discrete PZ layers 50 disposed between a corresponding pair of inter-gate spacer layers 12. The recessed regions 18 can thus be formed to have a depth (along the X-axis) that matches the expected lateral thickness of the PZ layer 50 to be formed. The dummy layer 23, which will later be converted into the air gap 52, can then be formed as a continuous dummy layer 23 along the sidewalls of the memory holes 4. Thus, when the dummy layer 23 is later converted into the air gap 52, a common air gap 52 that extends continuously in the vertical direction through the memory cell stack can be formed. Thus, the air gap 52 of each memory cell 100 can be formed from the corresponding portions of the common air gap 52 in this manner.

Claims

1. A memory cell for a 3D NAND flash memory, the memory cell comprising: Gate layer; Channel layer; a memory stack, the memory stack being arranged between the gate layer and the channel layer and comprising a charge trap layer and a tunnel oxide layer, the charge trap layer facing the gate layer; as well as An insulated piezoelectric gate layer is disposed on the gate layer, wherein the piezoelectric gate layer is disposed between the gate layer and the memory stack, and the piezoelectric gate layer and the memory stack are separated by an air gap.

2. The memory cell of claim 1, wherein a size of the air gap is in the range from 0.5 nm to 5 nm.

3. The memory cell of claim 2, wherein the piezoelectric gate layer has a thickness ranging from 2 nm to 10 nm and a thickness expansion ratio ranging from 0.2% to 1.2% per volt applied to the piezoelectric gate layer.

4. The memory cell of claim 1, wherein the piezoelectric gate layer comprises one or more of HfO2, Si-doped HfO2, ZnO, BN, BaTiO3, AlN, and GaN.

5. A vertical memory array for a 3D NAND flash memory, comprising a plurality of memory cells according to any one of the preceding claims, wherein the memory cells are stacked on top of each other in a vertical direction to form a memory cell stack.

6. The vertical memory array of claim 5, wherein the air gap of each memory cell is formed by a respective portion of a common air gap extending continuously through the memory cell stack in the vertical direction.

7. The vertical memory array of claim 5, wherein the piezoelectric gate layer of each memory cell is a discrete piezoelectric gate layer disposed between a corresponding pair of inter-gate spacer layers.

8. The vertical memory array of claim 7, wherein the air gap of each memory cell is formed by a respective portion of a common air gap extending continuously through the memory cell stack in the vertical direction.

9. The vertical memory array of claim 7, wherein the air gap of each memory cell is a discrete air gap disposed between a corresponding pair of inter-gate spacer layers.

10. The vertical memory array of claim 5, further comprising an insulating liner layer extending continuously through the memory cell stack in the vertical direction at a location between the air gap and the charge trap layer of each memory cell.

11. A method of forming a vertical memory structure for a 3D NAND flash memory, the method comprising: forming a layer stack on a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers; forming a piezoelectric gate layer, a dummy layer, and an insulating liner layer in sequence along a sidewall surrounding a memory hole in the layer stack; performing a thermal treatment process on the dummy layer, the thermal treatment process being adapted to convert the dummy layer into an air gap, wherein the air gap is formed laterally between the piezoelectric gate layer and the insulating liner layer; After the heat treatment process, a charge trap layer is formed along the insulating liner layer and then a tunnel oxide layer and a channel layer are formed.

12. The method of claim 11, further comprising, before forming the piezoelectric gate layer: forming a recessed region in the sidewall of the layer stack by laterally etching back the gate layer from the memory hole; The piezoelectric layer is selectively formed in the recessed regions such that a discrete piezoelectric gate layer is formed in each recessed region. 13 . The method of claim 12 , wherein the dummy layer is selectively formed on the discrete piezoelectric gate layer in each recessed region.

14. The method of claim 12, wherein the dummy layer is formed as a continuous layer along the sidewall of the memory hole.

15. The method of claim 11, wherein the dummy layer is formed of a material including a polymer.

Images