Vertical non-volatile memory device including strings of memory cells and electronic device

Abstract

The invention relates to a vertical non-volatile memory device including a string of memory cells and an electronic apparatus. The vertical non-volatile memory device may include a plurality of memory cell strings arranged two-dimensionally. Each of the plurality of memory cell strings may include a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of spacers alternately arranged in the first direction and each extending in a second direction, a gate insulating film extending in the first direction and between the channel layer and the plurality of gate electrodes, and a resistance change layer extending in the first direction along a surface of the channel layer. The second direction may intersect the first direction. A material in the resistance change layer may be switchable between a first state having a first threshold voltage and a second state having a second threshold voltage. The second threshold voltage may be greater than the first threshold voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2023 - 0185070, filed with the Korean Intellectual Property Office on December 18, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] This disclosure relates to a vertical (perpendicular) non - volatile memory device including a string of memory cells. Background art

[0004] Non - volatile memory devices, such as semiconductor memory devices, include a plurality of memory cells that can retain information even in a power - off state and reuse the stored information when powered on. Non - volatile memory devices can be used in mobile phones, digital cameras, personal digital assistants (PDAs), portable computer devices, stationary computer devices, and other devices.

[0005] Examples of non - volatile memory devices include vertical NAND (VNAND). VNAND is a memory device with improved integration by vertically stacking a large number of memory cells. A variety of techniques have been proposed to achieve high capacity in the same area by increasing the number of VNAND stacks. For example, to implement VNAND, various techniques have been proposed, such as methods using charge trapping, methods using phase - change materials, methods using resistance - change materials, methods using ferroelectric materials, etc. In addition, various materials have been studied to improve the performance of non - volatile memory devices, such as improvement of data reliability, improvement of drive speed, reduction of power consumption, improvement of integration, etc. Summary of the invention

[0006] Provide a vertical non - volatile memory device including a string of memory cells.

[0007] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the presented embodiments.

[0008] According to one embodiment of the present disclosure, a vertical non-volatile memory device may include a plurality of memory cell strings arranged two-dimensionally. Each of the plurality of memory cell strings may include a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of spacers alternately arranged in the first direction and each extending in a second direction intersecting the first direction, a gate insulating film extending in the first direction and between the channel layer and the plurality of gate electrodes, and a resistive change layer extending in the first direction along the surface of the channel layer. The material in the resistive change layer may be capable of switching between a first state having a first threshold voltage and a second state having a second threshold voltage. The second threshold voltage may be greater than the first threshold voltage.

[0009] In some embodiments, if the resistive change layer is in the first state and a voltage less than the first threshold voltage is applied to the resistive change layer, no current flows in the resistive change layer; if the resistive change layer is in the first state and a voltage greater than or equal to the first threshold voltage is applied to the resistive change layer, current flows in the resistive change layer; if the resistive change layer is in the second state and a voltage less than the second threshold voltage is applied to the resistive change layer, no current flows in the resistive change layer; and if the resistive change layer is in the second state and a voltage greater than or equal to the second threshold voltage is applied to the resistive change layer, current flows in the resistive change layer.

[0010] In some embodiments, the resistive change layer may be configured to switch from the first state to the second state when a sufficient negative (-) bias voltage is applied to the resistive change layer in response to the resistive change layer being in the first state, and the resistive change layer may be configured to switch from the second state to the first state when a positive (+) bias voltage greater than the second threshold voltage is applied to the resistive change layer in response to the resistive change layer being in the second state.

[0011] In some embodiments, the non-volatile memory device may be configured to perform a read operation including applying a read voltage between the first threshold voltage and the second threshold voltage to the resistive change layer.

[0012] In some embodiments, the resistive change layer may have a single-layer structure including at least one amorphous (non-crystalline) multicomponent chalcogenide material among the following: GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeSbIn, GeAsSeTe, GeAsSeTeIn, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeIn, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, and GeAsTe.

[0013] In some embodiments, the ratio of germanium (Ge) in the resistive change layer may be 10 atomic % to 30 atomic %.

[0014] In some embodiments, the ratio of arsenic (As) in the resistive change layer may be 10 atomic % to 50 atomic %.

[0015] In some embodiments, the ratio of selenium (Se) in the resistive change layer may be 40 atomic % to 80 atomic %.

[0016] In some embodiments, the ratio of indium (In) in the resistive change layer may be 1 atomic % to 10 atomic %.

[0017] In some embodiments, the resistive change layer may include a plurality of driving regions and a plurality of pristine-state regions alternately arranged in the first direction.

[0018] In some embodiments, each of the plurality of driving regions may face a corresponding gate electrode of the plurality of gate electrodes in the second direction, and each of the plurality of pristine-state regions may face a corresponding insulating spacer of the plurality of insulating spacers in the second direction.

[0019] In some embodiments, in response to applying a voltage greater than or equal to the first threshold voltage to the resistive change layer, the resistance of the plurality of pristine-state regions may be greater than the resistance of the plurality of driving regions.

[0020] In some embodiments, in response to applying a voltage greater than or equal to the first threshold voltage to both the plurality of pristine-state regions and the plurality of driving regions, the resistance of the plurality of pristine-state regions may be greater than the resistance of the plurality of driving regions.

[0021] In some embodiments, each of the plurality of driving regions may include a first region and a second region having different densities of activated traps.

[0022] In some embodiments, if the resistive change layer is in the first state, the density of the activated traps in the second region may be greater than the density of the activated traps in the first region. If the resistive change layer is in the second state, the density of the activated traps in the second region may be less than the density of the activated traps in the first region.

[0023] In some embodiments, the thickness of the second region in the first direction may be less than the thickness of the first region in the first direction.

[0024] In some embodiments, the thickness of the first region in the first direction may be 2 to 10 times the thickness of the second region in the first direction.

[0025] In some embodiments, the resistive change layer may have the following property: during the switching between the first state and the second state, the elemental composition distribution in the first region and the second region may remain constant.

[0026] In some embodiments, the thickness of the resistive change layer in the second direction may be 5 nm to 100 nm.

[0027] In some embodiments, each of the plurality of memory cell strings may further include a blocking layer extending in the first direction between the channel layer and the resistive change layer. The blocking layer may include a carbon-based non-conductor or a nitrogen-based non-conductor, and the thickness of the blocking layer in the second direction may be greater than 0 nm and less than or equal to 10 nm.

[0028] According to one embodiment of the present disclosure, an electronic device may include: a processing circuitry (processing circuit); and a vertical non-volatile memory device connected to the processing circuitry, the vertical non-volatile memory device including a plurality of memory cell strings arranged two-dimensionally. Each of the plurality of memory cell strings may include: a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers alternately arranged in the first direction and each extending in a second direction, the second direction intersecting the first direction; a gate insulating film extending in the first direction between the channel layer and the plurality of gate electrodes; and a resistive change layer extending in the first direction along the surface of the channel layer. The material in the resistive change layer may be capable of switching between a first state having a first threshold voltage and a second state having a second threshold voltage. The second threshold voltage may be greater than the first threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a block diagram of a memory system according to an embodiment;

[0031] Figure 2 is a display Figure 1 block diagram of an example of a memory device;

[0032] Figure 3 is Figure 1 block diagram of a memory cell array;

[0033] Figure 4 is an equivalent circuit corresponding to a memory area (memory block) according to an embodiment;

[0034] Figure 5 is a schematic vertical cross-sectional view showing the structure of a memory cell string according to an embodiment;

[0035] Figure 6 is a schematic horizontal cross-sectional view showing the structure of a memory cell string according to an embodiment;

[0036] Figure 7 is a graph showing the voltage-current characteristics of the resistance change layer of a memory cell string according to an embodiment;

[0037] Figure 8A is a graph showing examples of biases for a "1" write operation (SET operation) and a read operation in the resistance change layer of a memory cell string according to an embodiment;

[0038] Figure 8B is a graph showing examples of biases for a "0" write operation (RESET operation) and a read operation in the resistance change layer of a memory cell string according to an embodiment;

[0039] Figure 9A is a conceptual diagram showing an example of a trap state (captured state) in a resistance change layer material when the resistance change layer material is in an original state, and Figure 9B is a schematic energy band diagram of the resistance change layer material in the original state;

[0040] Figure 10A is a conceptual diagram showing an example of a trap state in a resistance change layer material after applying a positive (+) bias for primary sintering to the resistance change layer material in the original state, Figure 10B is a schematic energy band diagram of the resistance change layer material around the first end after primary sintering, and Figure 10C is a schematic energy band diagram of the resistance change layer material around the second end after primary sintering;

[0041] Figure 11AIt is a conceptual diagram showing an example of trap states in a resistive change layer material after applying a negative (-) bias voltage to the resistive change layer material that has been initially sintered. Figure 11B It is a schematic energy band diagram of the resistive change layer material around the first end after applying a negative bias voltage, and Figure 11C It is a schematic energy band diagram of the resistive change layer material around the second end after applying a negative bias voltage;

[0042] Figure 12A It illustrates an example of the setup operation of a memory cell string according to one embodiment, and Figure 12B Schematically shows an example of the reset operation of a memory cell string according to one embodiment;

[0043] Figure 13 It illustrates an example of a region formed in the resistive change layer after the initial sintering of a memory cell string according to one embodiment;

[0044] Figure 14 It is a vertical cross-sectional view showing the structure that is fabricated to examine the actual operation of a memory cell string according to one embodiment;

[0045] Figure 15 It is a graph showing an example of the voltage-current characteristics of the Figure 14 structure in the original state, the set state, and the reset state;

[0046] Figure 16 It is a schematic vertical cross-sectional view showing the structure of a memory cell string according to another embodiment;

[0047] Figure 17 It is a schematic conceptual diagram of a device architecture of an example electronic device to which a memory device according to one embodiment can be applied; and

[0048] Figure 18 It is a schematic block diagram of a neuromorphic device including a memory device according to one embodiment. Detailed Description

[0049] Embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, where like reference numerals always denote like elements. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described only by referring to the drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The phrase "at least one (of)" when preceding or following a list of elements modifies the entire list of elements and not individual elements of the list. For example, "at least one (of) A, B, and C" and similar language (e.g., "selected from at least one (of) A, B, and C") can be interpreted to mean only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0050] When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances around the stated numerical value (e.g., ±10%). Moreover, when the terms "substantially" and "about" are used in connection with a geometric shape, it is intended that the geometric shape need not be exact, but that tolerances for the shape are within the scope of the present disclosure. Further, whether a numerical value or a shape is modified with "about" or "substantially", it will be understood that these values and shapes should be interpreted to include manufacturing or operational tolerances around the stated numerical value or shape (e.g., ±10%). When a range is stated, the range includes all values therebetween, such as increments of 0.1%.

[0051] Hereinafter, a vertical nonvolatile memory device including a memory cell string will be described in detail with reference to the accompanying drawings. In all of the figures, like reference numerals denote like elements, and for convenience of explanation and clarity, the dimensions of components in the figures may be enlarged. Further, since the embodiments described below are examples, other variations may be derived from the embodiments.

[0052] When one component is disposed "on" or "above" another component, the component may be disposed directly on the other component or above the other component in a non-contact manner. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. Further, it will be further understood that the terms "comprises" and / or "comprising" when used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0053] In the context of describing the present disclosure, the use of the terms "a", "an", "the", and similar reference terms will be construed to cover both the singular and the plural. Moreover, the operations of all methods described herein may be performed in any suitable order, unless otherwise stated herein or clearly contradicted by the context. The present disclosure is not limited to the order of the steps described.

[0054] In addition, terms such as “… part”, “… unit”, “… module”, and “… block” stated in the specification may represent a unit for processing at least one function or operation, and the unit may be implemented by hardware, software, or a combination of hardware and software.

[0055] In addition, the connection lines or connectors shown in the various figures presented are intended to represent the functional relationships and / or physical or logical couplings between the various elements. It should be noted that there may be many alternative or additional functional relationships, physical connections, or logical connections in an actual device.

[0056] The use of any and all examples or language (e.g., "such as") provided herein is only intended to better illustrate the present disclosure and does not constitute a limitation on the scope of the present disclosure, unless otherwise required.

[0057] Figure 1 is a block diagram of a memory system 10 according to an embodiment. Referring to Figure 1 , a memory system 10 according to an embodiment may include a memory controller 100 and a memory device 200. The memory controller 100 may perform control operations on the memory device 200. In an example, the memory controller 100 may program (or write), read, or erase the memory device 200 by providing an address ADD and a command CMD to the memory device 200. In addition, data for programming operations and read data may be transmitted and received between the memory controller 100 and the memory device 200. The memory device 200 may provide a pass / fail P / F signal to the memory controller 100 according to the read result of the read data, and the memory controller 100 may control the write / read operations of the memory cell array 210 in response to the pass / fail signal.

[0058] The memory device 200 may include a memory cell array 210 and a voltage generator 220. The memory cell array 210 may include a plurality of memory cells disposed in a region where a plurality of word lines and a plurality of bit lines cross each other. The memory cell array 210 may include non-volatile memory cells that store data non-volatilely, and as non-volatile memory cells, the memory cell array 210 may include flash memory cells, such as a NAND flash memory cell array, a NOR flash memory cell array, etc. In the following description, it is assumed that the embodiments of the present disclosure are described as follows: the memory cell array 210 includes a flash memory cell array, and thus, the memory device 200 is a non-volatile memory device.

[0059] The memory controller 100 may include a write / read controller 110, a voltage controller 120, and a data determination unit 130.

[0060] The write / read controller 110 may generate an address ADD and a command CMD to perform programming / read and erase operations on the memory cell array 210. In addition, the voltage controller 120 may generate a voltage control signal to control at least one voltage level (voltage grade) used in the non-volatile memory device 200. For example, the voltage controller 120 may generate a voltage control signal to control the voltage level of the word line, so as to read data from the memory cell array 210 or program data into the memory cell array 210.

[0061] The data determination unit 130 may perform a determination operation on the data read from the memory device 200. For example, by determining the data read from the memory cell, the data determination unit 130 may determine the number of on-cells and / or off-cells in the memory cell. As an example operation, when programming a plurality of memory cells, by using a certain read voltage to determine the data state of the memory cell, it can be determined whether the programming is normally completed for all cells.

[0062] As described above, the memory cell array 210 may include non-volatile memory cells, such as flash memory cells. In addition, the flash memory cells may be implemented in various forms. For example, the memory cell array 210 may include three-dimensional (or vertical) NAND (VNAND) memory cells.

[0063] Figure 2 is a block diagram of an example of the memory device 200 that displays Figure 1 Referring to Figure 2 , the memory device 200 may include a row decoder 230, an input / output I / O circuit 240, and a control logic 250.

[0064] The memory cell array 210 can be connected to one or more string select lines SSLs, multiple word lines WL1 to WLm, and one or more common source lines CSLs, and can also be connected to multiple bit lines BL1 to BLn. The voltage generator 220 can generate one or more word line voltages V1 to Vi, and the word line voltages V1 to Vi can be provided to the row decoder 230. Signals for programming / reading / erasing operations can be applied to the memory cell array 210 through the bit lines BL1 to BLn.

[0065] In addition, data to be programmed can be provided to the memory cell array 210 through the I / O circuit 240, and the read data can be provided to the outside (e.g., the memory controller 100) through the I / O circuit 240. The control logic 250 can provide a plurality of control signals related to the memory operation to the row decoder 230 and the voltage generator 220.

[0066] The word line voltages V1 to Vi can be provided through multiple lines (SSLs, WL1 to WLm, CSLs) according to the decoding operation of the row decoder 230. For example, the word line voltages V1 to Vi can include a string select voltage, a word line voltage, and a ground select voltage, and the string select voltage can be provided to the string select lines SSLs, the word line voltage can be provided to the word lines WL1 to WLm, and the ground select voltage can be provided to the common source lines CSLs.

[0067] Figure 3 is Figure 1 a block diagram of the memory cell array 210. Referring to Figure 3 , the memory cell array 210 can include a plurality of memory blocks BLK1 to BLKz. Each memory block BLK can have a three-dimensional structure (or a vertical structure). For example, each memory block BLK can include a structure extending in the first to third directions. For example, each memory block BLK can include a plurality of memory cell strings extending in the first direction (Z direction). In addition, the plurality of memory cell strings can be two-dimensionally arranged in the second and third directions (X and Y directions). Each memory cell string is connected to a bit line BL, a string select line SSL, a word line WL, and a common source line CSL. Therefore, the memory blocks BLK1 to BLKz can be respectively connected to the bit lines BLs, the string select lines SSLs, the word lines WLs, and the common source lines CSLs. Referring to Figure 4 The memory blocks BLK1 to BLKz configured as described above are described in detail.

[0068] Figure 4 is an equivalent circuit corresponding to a memory block according to an embodiment. For example, Figure 4 illustrates Figure 3 one of the memory blocks BLK1 to BLKz of the memory cell array 210. Referring to Figure 3 and 4, the memory banks BLK1 to BLKz may each include a plurality of memory cell strings CS11 to CSkn. The memory cell strings CS11 to CSkn may be two-dimensionally arranged in a row direction and a column direction to thereby form rows and columns. Each of the memory cell strings CS11 to CSkn may include a plurality of memory cells MC and a plurality of string selection transistors SST. The memory cells MC and the string selection transistors SST of each of the memory cell strings CS11 to CSkn may be stacked in a height direction.

[0069] The rows of the memory cell strings CS11 to CSkn are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST of the memory cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SST of the memory cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

[0070] In addition, the columns of the memory cell strings CS11 to CSkn are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and the string selection transistors SST of the memory cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and the string selection transistors SST of the memory cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

[0071] In addition, the rows of the memory cell strings CS11 to CSkn may be respectively connected to different common source lines CSL1 to CSLk. For example, the string selection transistors SST of the memory cell strings CS11 to CS1n may be commonly connected to the common source line CSL1, and the string selection transistors SST of the memory cell strings CSk1 to CSkn may be commonly connected to the common source line CSLk.

[0072] The memory cells MC located at the same height from the substrate (or the string selection transistors SST) may be commonly connected to one word line WL, and the memory cells MC located at different heights may be respectively connected to different word lines WL1 to WLm.

[0073] Figure 4 The memory bank shown in is an example. The technical concept of the present disclosure is not limited to Figure 4The memory regions shown in, for example, the number of rows of the memory cell strings CS11 to CSkn can be increased or decreased. When the number of rows of the memory cell strings CS11 to CSkn changes, the number of string selection lines SSL1 to SSLk connected to the rows of the memory cell strings CS11 to CSkn, and the number of memory cell strings CS11 to CSkn connected to one bit line can also change. When the number of rows of the memory cell strings CS11 to CSkn changes, the number of common source lines CSL1 to CSLk connected to the rows of the memory cell strings CS11 to CSkn can also change. In addition, the number of columns of the memory cell strings CS11 to CSkn can be increased or decreased. When the number of columns of the memory cell strings CS11 to CSkn changes, the number of bit lines BL connected to the columns of the memory cell strings CS11 to CSkn, and the number of memory cell strings CS11 to CSkn connected to one string selection line SSL can also change.

[0074] The height of each of the memory cell strings CS11 to CSkn can be increased or decreased. For example, the number of memory cells MC stacked on each of the memory cell strings CS11 to CSkn can be increased or decreased. When the number of memory cells MC stacked on each of the memory cell strings CS11 to CSkn changes, the number of word lines WL can also change. For example, the number of string selection transistors SST provided to each of the memory cell strings CS11 to CSkn can be increased. When the number of string selection transistors SST provided to each of the memory cell strings CS11 to CSkn changes, the number of string selection lines SSL or common source lines CSL can also change. When the number of string selection transistors SST increases, the string selection transistors SST can be stacked in the same form as the memory cells MC.

[0075] For example, write and read operations can be performed on each row of the memory cell strings CS11 to CSkn. Each row of the memory cell strings CS11 to CSkn can be selected through the common source lines CSLs, and each row of the memory cell strings CS11 to CSkn can be selected through the string selection lines SSLs. In the selected rows of the memory cell strings CS11 to CSkn, write and read operations can be performed on each page. For example, one page can be a row of memory cells MC connected to one word line WL. The memory cells MC can be selected for each page through the word lines WL in the selected rows of the memory cell strings CS11 to CSkn.

[0076] The memory cells MC in each of the memory cell strings CS11 to CSkn can correspond to a circuit in which a transistor and a resistor are connected in parallel. For example, Figure 5 is a schematic vertical cross-sectional view showing the structure of each memory cell string CS according to an embodiment. Refer to Figure 5, the memory cell string CS may include a plurality of insulating spacers 311 and a plurality of gate electrodes 312 alternately stacked in a vertical direction (i.e., in a first direction (Z direction)) perpendicular to a second direction (X direction). The insulating spacers 311 and the gate electrodes 312 may extend in a horizontal direction (i.e., the second direction). Each gate electrode 312 may be connected to a word line WL, or each gate electrode 312 may be a word line WL as it is.

[0077] The insulating spacer 311 may include one of the following: various insulating dielectric materials such as silicon oxide, aluminum oxide, silicon nitride, etc., but the present disclosure is not limited thereto. The gate electrode 312 may include at least one of the following: a conductive material such as tungsten (W), molybdenum (Mo), ruthenium (Ru), polysilicon, TiN, a two-dimensional metallic (metal) material, or a combination thereof. The two-dimensional metallic material may include, for example, at least one of the following materials: graphene, TaS2, TaSe2, NbS2, NbSe2, PdTe2, PtTe2, NbTe2, TiSe2, VSe2, AuSe, and MoTe2. In some embodiments, although not shown, the gate electrode 312 may include a gate layer (e.g., W, Mo, Ru, polysilicon) surrounded by a gate blocking layer (e.g., TiN, a two-dimensional material such as graphene, but not limited thereto), and the gate blocking layer covers at least one of the side surface, the lower surface, and the upper surface of the gate layer.

[0078] In addition, the memory cell string CS may include a channel hole penetrating the insulating spacer 311 and the gate electrode 312 in the first direction. A plurality of layers for forming a resistance and a channel may be disposed in the channel hole. For example, the memory cell string CS may include an insulating support 324 disposed at the center of the channel hole and extending in the first direction, a resistance change layer 323 disposed to surround the insulating support 324 and extending in the first direction, a channel layer 322 disposed to surround the resistance change layer 323 and extending in the first direction, and a gate insulating film 321 disposed to surround the channel layer 322 and extending in the first direction. The gate insulating film 321 may be disposed between the channel layer 322 and the gate electrode 312 and between the channel layer 322 and the insulating spacer 311.

[0079] Figure 6 is a schematic horizontal cross-sectional view showing the structure of a memory cell string CS according to an embodiment. Referring to Figure 6 , the insulating support 324, the resistance change layer 323, the channel layer 322, and the gate insulating film 321 may be concentrically arranged in sequence from the center. The gate insulating film 321 may have a cylindrical shape surrounding the channel layer 322, the channel layer 322 may have a cylindrical shape surrounding the resistance change layer 323, and the resistance change layer 323 may have a cylindrical shape surrounding the insulating support 324. Although in Figure 6Not shown in the figure, but the insulating spacers 311 and the gate electrodes 312 may be alternately stacked in the first direction while surrounding the gate insulating film 321. Although in Figure 6 not shown in the figure, a blocking layer may be concentrically disposed between the resistive change layer 323 and the channel layer 322 (see Figure 16 the blocking layer 325 in

[0080] For this purpose, the gate insulating film 321 may be conformally deposited on the insulating spacers 311 and the gate electrodes 312 to extend in the first direction. The channel layer 322 may be conformally deposited along the surface of the gate insulating film 321 to extend in the vertical direction (i.e., in the first direction). The resistive change layer 323 may be conformally deposited along the surface of the channel layer 322 to extend in the first direction. The insulating support 324 may be arranged to fill the remaining space in the center of the channel hole to extend in the first direction.

[0081] As a result, the resistive change layer 323 has a shape extending in the first direction facing the insulating spacers 311 and the gate electrodes 312, the channel layer 322 has a shape extending in the first direction between the resistive change layer 323 and the gate electrodes 312, and the gate insulating film 321 has a shape extending in the first direction between the channel layer 322 and the gate electrodes 312.

[0082] Although not shown, a drain (Drain) may be disposed on the uppermost surface of the memory cell string CS to cover at least the channel layer 322. The drain may include a doped silicon material. The bit line BL may be connected to the drain.

[0083] The channel layer 322 may include, for example, polysilicon (polycrystalline Si), but the present disclosure is not limited thereto, and the channel layer 322 may include a variety of other conductive semiconductor materials. For example, the channel layer 322 may include a two-dimensional semiconductor material having p-type electrical characteristics. The channel layer 322 may include, for example, at least one of the following two-dimensional semiconductor materials: tellurene, black phosphorus, and WSe2. In addition, the gate insulating film 321 and the insulating support 324 may include, for example, at least one of the following materials: silicon oxide (SiO), aluminum oxide (AlO), magnesium oxide (MgO), aluminum nitride (AlN), hafnium oxide (HfO), and gallium nitride (GaN), but the present disclosure is not limited thereto.

[0084] Returning to Figure 5, as shown by the dashed box, any one of the gate electrodes 312, and a part of the gate insulating film 321, a part of the channel layer 322, and a part of the resistive change layer 323 that are adjacent to each other in the horizontal direction (i.e., the second direction) with respect to one gate electrode 312 are components of a memory cell MC. In particular, one gate electrode 312, and the part of the gate insulating film 321 and the part of the channel layer 322 that are adjacent to one gate electrode 312 in the horizontal direction can form a transistor, and the part of the resistive change layer 323 can form a resistor. Therefore, each of the memory cells MC can correspond to a circuit in which the transistor and the resistor are connected in parallel with each other. Since the memory cells MC are arranged in a vertical stacked structure, a corresponding memory cell string CS can be formed. The thickness of one of the memory cells MC can be determined based on the height t1 of one gate electrode 312 in the first direction, and the interval between two memory cells MC that are adjacent to each other in the first direction can be determined by the height t2 of one of the insulating spacers 311 in the first direction. The integration degree of the memory cells MC can be improved by reducing the height t1 of one gate electrode 312 in the first direction and the height t2 of one insulating spacer 311 in the first direction. For example, the height t1 of one gate electrode 312 in the first direction can be about 20 nm or less, and the height t2 of one insulating spacer 311 in the first direction can be about 20 nm or less.

[0085] The thickness d1 of the gate insulating film 321 in the second direction can be, for example, about 5 nm to about 50 nm. The thickness d2 of the channel layer 322 in the second direction can be, for example, about 2.5 nm to about 20 nm. In addition, the thickness d3 of the resistive change layer 323 in the second direction can be, for example, about 5 nm to about 100 nm, or about 5 nm to about 40 nm.

[0086] According to one embodiment, the resistance change layer 323 may include a material having a bi-directional threshold switching (OTS) characteristic, through which, when a voltage less than the threshold voltage is applied, the resistance change layer 323 turns into a high-resistance state, and when a voltage greater than the threshold voltage is applied, the resistance change layer 323 turns into a low-resistance state. In addition, the resistance change layer 323 may have the following characteristic: through this characteristic, the threshold voltage moves (shifts) according to the polarity and intensity of the applied bias voltage. For example, the resistance change layer 323 may switch between a first state having a relatively low first threshold voltage and a second state having a second threshold voltage greater than the first threshold voltage. To this end, the resistance change layer 323 may include an amorphous multi-component chalcogenide material. The resistance change layer 323 may have a single-layer structure including at least one of the following materials: for example, GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeSbIn, GeAsSeTe, GeAsSeTeIn, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeIn, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, and GeAsTe.

[0087] When the resistance change layer 323 includes germanium (Ge), the ratio of Ge in the resistance change layer 323 may be about 10 atomic % to about 30 atomic %. When the resistance change layer 323 includes arsenic (As), the ratio of As in the resistance change layer 323 may be about 10 atomic % to about 50 atomic %, and when the resistance change layer 323 includes selenium (Se), the ratio of Se in the resistance change layer 323 may be about 40 atomic % to about 80 atomic %. In addition, when the resistance change layer 323 includes indium (In), the ratio of In in the resistance change layer 323 may be about 1 atomic % to about 10 atomic %, about 1 atomic % to about 8 atomic %, or about 3 atomic % to about 5 atomic %. The ratio of a specific element (e.g., Ge, As, Se) in the resistance change layer 323 may refer to the ratio of the specific element in the resistance change layer 323 to all elements. In other words, for GeAsSe, the ratio of Ge may refer to the amount of Ge compared to the total amount of combined Ge, As, and Se.

[0088] Figure 7 is a diagram showing an example of the voltage-current characteristics of the resistance change layer 323 of the memory cell string CS according to one embodiment. Refer to Figure 7, the resistance change layer 323 can have either a first state (low Vth state; LVS) in which the threshold voltage is relatively low or a second state (high Vth state; HVS) in which the threshold voltage is relatively high. For example, in the first state, the first threshold voltage of the resistance change layer 323 can be a first voltage V1, and in the second state, the second threshold voltage of the resistance change layer 323 can be a second voltage V2 greater than the first voltage V1. When the resistance change layer 323 is in the first state and a voltage less than the first voltage V1 is applied to the resistance change layer 323, almost no current flows through the resistance change layer 323, and when a voltage greater than or equal to the first voltage V1 is applied to the resistance change layer 323, the resistance change layer 323 turns on (conducts), allowing current to flow through the resistance change layer 323. In addition, when the resistance change layer 323 is in the second state and a voltage less than the second voltage V2, which is the second threshold voltage, is applied to the resistance change layer 323, almost no current flows through the resistance change layer 323, and when a voltage greater than or equal to the second voltage V2 is applied to the resistance change layer 323, the resistance change layer 323 turns on, allowing current to flow through the resistance change layer 323.

[0089] Therefore, a voltage within the range between the first voltage V1 and the second voltage V2 can be selected as the read voltage VR. When the resistance change layer 323 is in the first state and the read voltage VR is applied to the resistance change layer 323, current can flow through the resistance change layer 323, and in this state, the data value stored in the resistance change layer 323 can be defined as "1". When the resistance change layer 323 is in the second state and the read voltage VR is applied to the resistance change layer 323, almost no current flows through the resistance change layer 323, and in this state, the data value stored in the resistance change layer 323 can be defined as "0". In other words, when the read voltage VR is applied to the resistance change layer 323, the data value stored in the resistance change layer 323 can be read by measuring the current flowing through the resistance change layer 323.

[0090] Meanwhile, when the resistance change layer 323 is in the first state and a negative (-) bias voltage is applied to the resistance change layer 323, the threshold voltage of the resistance change layer 323 increases, enabling the resistance change layer 323 to switch to the second state. For example, when a negative third voltage V3 is applied to the resistance change layer 323, the resistance change layer 323 can switch to the second state. Such an operation can be referred to as a "reset" operation. In addition, when the resistance change layer 323 is in the second state and a positive (+) bias voltage greater than the second voltage V2 is applied to the resistance change layer 323, the threshold voltage of the resistance change layer 323 decreases, enabling the resistance change layer 323 to switch to the first state. Such an operation can be referred to as a "set" operation.

[0091] Figure 8AFIG. is an example showing the biases for a “1” write operation (set operation) and a read operation in the resistance change layer 323 of a memory cell string CS according to an embodiment. Refer to Figure 8A , in the set operation, a positive bias (positive pulse) greater than or equal to the second voltage V2 may be applied to the resistance change layer 323. Then, the threshold voltage of the resistance change layer 323 may be shifted to the first voltage V1. Then, in the read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the resistance change layer 323. When the read voltage VR is applied, the resistance change layer 323 may be turned on.

[0092] Figure 8B FIG. is an example showing the biases for a “0” write operation (reset operation) and a read operation in the resistance change layer 323 of a memory cell string CS according to an embodiment. Refer to Figure 8B , in the reset operation, a negative bias (negative pulse) (i.e., the third voltage V3) may be applied to the resistance change layer 323. The absolute value of the third voltage V3 may be substantially equal to, slightly greater than, or slightly less than the second voltage V2. For example, the absolute value of the third voltage V3 may be about 0.8 to about 1.2 times the second voltage V2. Then, the threshold voltage of the resistance change layer 323 may be shifted to the second voltage V2 greater than the first voltage V1. Then, in the read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the resistance change layer 323. When the read voltage VR is applied, the resistance change layer 323 may be turned off.

[0093] Thus, the resistance change layer 323 including the amorphous multicomponent chalcogenide material having the above composition may have a bi-directional threshold switching characteristic and at the same time have a storage characteristic in which the threshold voltage changes, as shown in Figure 7 , 8A and 8B. In particular, the threshold voltage of the resistance change layer 323 may be shifted according to the polarity of the bias applied to the resistance change layer 323. In this regard, it can be seen that the resistance change layer 323 according to an embodiment may have a polarity-dependent threshold voltage shift characteristic.

[0094] The polarity-dependent threshold voltage shift behavior may be described by a change in the trap state in the material of the resistance change layer 323. Figures 9A to 11C FIG. is a diagram for the concept for describing the change in the trap state in the material of the resistance change layer 323. In particular, Figure 9A is a conceptual diagram showing an example of the trap state in the resistance change layer material 23 when the resistance change layer material 23 is in an original state, and Figure 9B is a schematic energy band diagram of the resistance change layer material 23 in the original state. Figure 10Ais a conceptual diagram showing an example of trap states in the resistive change layer material 23 after applying a positive (+) bias for primary sintering to the resistive change layer material 23 in its original state, Figure 10B is a schematic energy band diagram of the resistive change layer material 23 around the first end after primary sintering, and Figure 10C is a schematic energy band diagram of the resistive change layer material 23 around the second end after primary sintering. Figure 11A is a conceptual diagram showing an example of trap states in the resistive change layer material 23 after applying a negative (-) bias to the resistive change layer material 23 that has been primarily sintered, Figure 11B is a schematic energy band diagram of the resistive change layer material 23 around the first end after applying the negative bias, and Figure 11C is a schematic energy band diagram of the resistive change layer material 23 around the second end after applying the negative bias.

[0095] Refer to Figure 9A , deactivated traps (inactivated traps) mainly exist in the resistive change layer material 23 in its original state just after manufacturing. For the sake of explanation, in Figure 9A , deactivated traps are represented by dashed circles. For example, deactivated traps can be mainly formed by covalent bonds (Se-Se) between adjacent Se atoms in the resistive change layer material 23.

[0096] In addition, in the figure of Figure 9B , "CB" represents the conduction band, "VB" represents the valence band, and the horizontal axis direction represents the density of states. Refer to Figure 9B , the energy band formed by deactivated traps is represented by a thin dashed line. In Figure 9B , the energy band represented by a solid line is formed by materials other than Se in the resistive change layer material 23. The energy band formed by deactivated traps can be distributed near the Fermi level Ef.

[0097] To primarily sinter the resistive change layer material 23 in its original state, a positive (+) bias can be applied to the resistive change layer material 23. For example, a bias can be applied to the resistive change layer material 23 such that current flows from the first end E1 to the second end E2 of the resistive change layer material 23. Refer to Figure 10A , since some of the deactivated traps are activated by primary sintering, activated traps can be formed. Activated traps can be mainly formed by selenium ions Se 2- formed as the covalent bonds between Se atoms are broken. These activated traps can form a percolation path in the resistive change layer material 23, and as the percolation path is formed, the threshold voltage of the resistive change layer material 23 can be reduced.

[0098] In Figure 10AIn [the figure], the activation traps are represented by hatched pattern circles and reticulated pattern circles. As Figure 10A shown in [the figure], from the second end portion E2 to the first end portion E1, the amount of activation traps in the resistive change layer material 23 may increase. In particular, a large amount of activation traps may be produced in the region of the resistive change layer material 23 near the first end portion E1. Thus, after the first sintering, the resistive change layer material 23 may include a first region 23a in which the density of activation traps is relatively low and a second region 23b in which the density of activation traps is relatively high. The length of the second region 23b may be less than the length of the first region 23a. For example, the length of the first region 23a may be 2 to 10 times the length of the second region 23b.

[0099] The first region 23a is a region adjacent to the second end portion E2 to which a negative (-) voltage is applied during the first sintering. The activation traps in the first region 23a are represented by hatched pattern circles. In the first region 23a, the density of activation traps may slightly increase toward the boundary with the second region 23b, but the amount of increase may be relatively small. The second region 23b is a region adjacent to the first end portion E1 to which a positive (+) voltage is applied during the first sintering. In addition, the second region 23b may be in direct contact with the first region 23a and disposed between the first region 23a and the first end portion E1. The activation traps in the second region 23b may be represented by reticulated pattern circles. In the second region 23b, near the first end portion E1, the density of activation traps may increase relatively significantly. Thus, the density of activation traps in the second region 23b may be greater than the density of activation traps in the first region 23a. In this case, the resistive change layer material 23 may be in a first state in which the threshold voltage is relatively low. In other words, when the resistive change layer material 23 is in the first state, the density of activation traps in the second region 23b is greater than the density of activation traps in the first region 23a.

[0100] Referring to Figure 10B , in the first region 23a, the energy band formed by the activation traps is represented by a dotted line. The energy band formed by the activation traps may be at an energy level slightly lower than the Fermi level Ef. In addition, referring to Figure 10C , in the second region 23b, the energy band formed by the activation traps is represented by a thick dotted line. Comparing Figure 10B with Figure 10C , it can be seen that the energy distribution of the energy band formed by the activation traps in the second region 23b is slightly greater than that of the energy band formed by the activation traps in the first region 23a. In addition, it can be seen that the density of states of the activation traps in the second region 23b is greater than the density of states of the activation traps in the first region 23a. Thus, it can be seen that the amount of activation traps in the second region 23b is greater than the amount of activation traps in the first region 23a.

[0101] A high activation trap density around the first end portion E1 after the first sintering can have a great influence on the threshold voltage shift behavior of the resistive change layer material 23. For example, the activation trap density in the second region 23b can be relatively easily changed according to the polarity of the bias voltage, and thus, the threshold voltage of the resistive change layer material 23 can be relatively easily shifted.

[0102] When a negative (-) bias voltage is applied to the resistive change layer material 23 that has been first sintered (i.e., a bias voltage is applied to the resistive change layer material 23 in the reverse direction such that current flows from the second end portion E2 to the first end portion E1), some of the activation traps in the second region 23b near the first end portion E1 are annihilated and become deactivated traps. This can be described as selenium ions Se 2- recombining with each other to thereby form a covalent bond (Se-Se). As a result, the density of the activation traps in the resistive change layer material 23 decreases.

[0103] Comparison Figure 10A With Figure 11A After applying a negative bias voltage to the resistive change layer material 23, the density of the activation traps can decrease in both the first region 23a and the second region 23b. In particular, the density of the activation traps in the second region 23b can even further decrease. In contrast, the amount of change in the density of the activation traps in the first region 23a can be smaller than the amount of change in the density of the activation traps in the second region 23b. Therefore, after applying a negative bias voltage to the resistive change layer material 23, the density of the activation traps in the second region 23b can be smaller than the density of the activation traps in the first region 23a. Therefore, an interface tunneling barrier (ITB) can be formed at the boundary between the first region 23a and the second region 23b.

[0104] In addition, comparison Figure 10B With Figure 11B After applying a negative bias voltage to the resistive change layer material 23, the density of states of the activation traps in the first region 23a can slightly decrease. In contrast, comparison Figure 10C With Figure 11C After applying a negative bias voltage to the resistive change layer material 23, the density of states of the activation traps in the second region 23b can decrease relatively significantly. In addition, comparison Figure 11B With Figure 11C After applying a negative bias voltage to the resistive change layer material 23, it can be seen that the density of states of the activation traps in the second region 23b is smaller than the density of states of the activation traps in the first region 23a.

[0105] When the amount of activated traps in the resistive change layer material 23, particularly in the second region 23b near the first end E1, decreases, a relatively large bias voltage is required to form a conductive path, and thus, the threshold voltage of the resistive change layer material 23 can increase. In this state, the resistive change layer material 23 can be in a second state in which the threshold voltage is relatively high. In other words, when the resistive change layer material 23 is in the second state, the density of activated traps in the second region 23b can be smaller than the density of activated traps in the first region 23a. Further, the density of activated traps in the first region 23a and the density of activated traps in the second region 23b when the resistive change layer material 23 is in the second state can be respectively smaller than the density of activated traps in the first region 23a and the density of activated traps in the second region 23b when the resistive change layer material 23 is in the first state.

[0106] Then, when a positive bias voltage greater than or equal to the threshold voltage is applied to the resistive change layer material 23, the amount of activated traps in the resistive change layer material 23, particularly in the second region 23b, increases, and thus, the threshold voltage of the resistive change layer material 23 can decrease again. Then, the resistive change layer material 23 can change back to the first state. In this way, by the change in the state of the activated traps in the resistive change layer material 23, particularly the significant change in the state of the activated traps in the second region 23b near the first end E1, the threshold voltage shift behavior can be implemented. Since the density of the activated traps in the original state is smaller than the density of the activated traps in the state where a negative bias voltage is applied after the initial sintering, the positive bias voltage required for the initial sintering can be greater than the positive bias voltage used to decrease the threshold voltage of the resistive change layer material 23 after the negative bias voltage is applied.

[0107] As described above, the threshold voltage shift in the resistive change layer material 23 does not occur by the ion migration phenomenon, but occurs by the change in the state of the activated traps or the change in the density of the activated traps. Therefore, in the state before the initial sintering, in the state after the initial sintering, and in the state where a negative bias voltage is applied after the initial sintering, almost no change in the composition of the resistive change layer material 23 occurs, and thus, the elemental composition distribution in the resistive change layer material 23 can remain substantially constant. The expression "remain constant" for the elemental composition distribution can mean that there is no significant change in terms of the concentration of each element included in the resistive change layer material 23, for example, in the first region 23a and the second region 23b of the resistive change layer material 23. In particular, the expression "remain constant" for the elemental composition distribution can include the case where the difference in the concentration of the corresponding elements included in the first region 23a and the second region 23b of the resistive change layer material 23 when the resistive change layer material 23 is in the first state and the second state is within 10%.

[0108] In other words, when the resistive change layer material 23 changes from the first state to the second state or from the second state to the first state, the ratios of elements such as Ge, As, Se, etc. in the first region 23a and the second region 23b of the resistive change layer material 23 can remain constant. For example, when the resistive change layer material 23 includes Se, there is little difference between the selenium concentration in the first region 23a when the resistive change layer material 23 is in the first state and the selenium concentration in the first region 23a when the resistive change layer material 23 is in the second state.

[0109] When the resistive change layer material 23 including the amorphous multicomponent chalcogenide material having the above composition is used as the resistive change layer 323 of the memory cell string CS, the memory device 200 can have a relatively fast driving speed. For example, even when a voltage having a pulse width of about 1 nanosecond or less is applied thereto, the resistive change layer 323 including the amorphous multicomponent chalcogenide material having the above composition can perform threshold voltage switching. Therefore, the memory device 200 can have a relatively fast driving speed of, for example, about 1 nanosecond or less.

[0110] In the memory cell string CS including the resistive change layer 323 having the above characteristics, the set operation and the reset operation can be independently performed for each memory cell MC of the memory cell string CS. Figure 12A An example of the set operation of the memory cell string CS according to one embodiment will be described, and Figure 12B An example of the reset operation of the memory cell string CS according to one embodiment is schematically shown.

[0111] Referring to Figure 12A , a gate voltage less than the threshold voltage can be applied to the gate electrode 312 of the selected memory cell sMC to which the set operation is to be performed through the word line WL. Alternatively, no gate voltage may be applied thereto. Here, the threshold voltage refers to the threshold voltage of a transistor formed by a gate electrode 312, a part of the gate insulating film 321 adjacent to the gate electrode 312 in the horizontal direction (e.g., the second direction or the third direction), and a part of the channel layer 322. A gate voltage greater than or equal to the threshold voltage can be applied to the gate electrodes 312 of all other non-selected memory cells nMC to which the set operation is not performed through the word line WL. Therefore, all the transistors of the non-selected memory cells nMC are turned on, so that current can flow through the channel layer 322 of the non-selected memory cells nMC, and the transistor of the selected memory cell sMC is turned off, so that no current flows through the channel layer 322 of the selected memory cell sMC.

[0112] A voltage greater than Figure 7 and 8AThe positive (+) bias of the second voltage V2 described in

[0113] Referring to Figure 12B , while a gate voltage less than the threshold voltage can be applied to the gate electrode 312 of the selected memory cell sMC to which a reset operation is to be performed, a gate voltage greater than or equal to the threshold voltage can be applied to the gate electrodes 312 of all other non-selected memory cells nMC. A third voltage V3 or a negative (-) bias less than the third voltage V3 can be applied to the channel layer 322 through the bit line BL. Then, a partial region of the resistive change layer 323 in the selected memory cell sMC can be switched to the second state.

[0114] When only a gate voltage less than the threshold voltage is applied to the gate electrode 312 of the selected memory cell sMC and a gate voltage greater than or equal to the threshold voltage is applied to the gate electrodes 312 of all non-selected memory cells nMC, a read operation can be performed by applying a positive read voltage VR between a first voltage V1 as the first threshold voltage and a second voltage V2 as the second threshold voltage to the channel layer 322.

[0115] Such a setting operation, reset operation, and read operation can be performed after the resistive change layer 323 is initially sintered. The initial sintering can also be performed independently for each memory cell MC. In other words, after the memory cell string CS is manufactured, the initial sintering can be sequentially performed for each memory cell MC in the memory cell string CS one by one. For example, when only a gate voltage less than the threshold voltage is applied to the gate electrode 312 of the selected memory cell sMC and a gate voltage greater than or equal to the threshold voltage is applied to the gate electrodes 312 of all non-selected memory cells nMC, an initial sintering voltage greater than the positive bias for the setting operation can be applied to the channel layer 322. The initial sintering can be performed as follows: The selected memory cell sMC is sequentially changed until the regions of the resistive change layer 323 corresponding to all the memory cells MC in the memory cell string CS are initially sintered.

[0116] After the initial sintering of all memory cells MC in a memory cell string CS is completed, the regions of the resistive change layer 323 between two memory cells MC adjacent to each other in the vertical direction (e.g., the first direction) can remain in the original state. In other words, when only partial regions of the resistive change layer 323 adjacent to the gate electrode 312 in the second direction or the third direction are in the state of being initially sintered, the partial regions of the resistive change layer 323 adjacent to the insulating spacer 311 in the second direction or the third direction can remain in the original state. Therefore, in one memory cell string CS, the resistive change layer 323 can have a plurality of driving regions and a plurality of original state regions in the vertical direction (e.g., the first direction).

[0117] Figure 13 An example of the regions formed in the resistive change layer 323 after the initial sintering of a memory cell string according to an embodiment is described. Refer to Figure 13 , in the resistive change layer 323 in one memory cell string CS, a plurality of driving regions 323F and a plurality of original state regions 323P alternately arranged in the first direction can be included. Each of the driving regions 323F can be arranged to face any corresponding one of the gate electrodes 312 in the second direction, and each of the original state regions 323P can be arranged to face any corresponding one of the insulating spacers 311 in the second direction. The concentration of the activated traps in the original state regions 323P can be less than the concentration of the activated traps in the driving regions 323F. In addition, when a voltage greater than or equal to the first threshold voltage is applied to the resistive change layer 323, the resistance of each of the original state regions 323P can be greater than the resistance of each of the driving regions 323F.

[0118] As Figure 13As described above, each of the driving regions 323F may include a first region 323a and a second region 323b, which have different densities of activated traps. The length or thickness of the second region 323b in the first direction may be smaller than the length or thickness of the first region 323a in the first direction. For example, the length or thickness of the first region 323a in the first direction may be 2 to 10 times the length or thickness of the second region 323b in the first direction. When the driving region 323F of the resistance change layer 323 is in the first state, the density of the activated traps in the second region 323b is greater than the density of the activated traps in the first region 323a. On the contrary, when the driving region 323F of the resistance change layer 323 is in the second state, the density of the activated traps in the second region 323b may be smaller than the density of the activated traps in the first region 323a. In addition, the density of the activated traps in the first region 323a and the density of the activated traps in the second region 323b when the driving region 323F of the resistance change layer 323 is in the second state may be respectively smaller than the density of the activated traps in the first region 323a and the density of the activated traps in the second region 323b when the driving region 323F of the resistance change layer 323 is in the first state.

[0119] In addition, as described above, in the original state region 323P, the first region 323a of the driving region 323F, and the second region 323b of the driving region 323F, almost no change in the elemental composition in the resistance change layer 323 may occur. Therefore, the elemental composition distributions in the original state region 323P, the first region 323a, and the second region 323b may be substantially the same.

[0120] Figure 14 is a vertical cross-sectional view showing the following structure: It is fabricated to examine the actual operation of a memory cell string CS according to an embodiment. Referring to Figure 14 , layers of polysilicon, silicon oxide, and polysilicon are sequentially stacked in the first direction, and a threshold switching memory material (TSM) is formed along the sidewalls of the stacked polysilicon, silicon oxide, and polysilicon. The two polysilicons may correspond to the channels of the non-selected memory cells nMC, and the silicon oxide may correspond to the channel of the selected memory cell sMC. The threshold switch memory material TSM may correspond to the resistance change layer 323 and may include the material of the resistance change layer 323 described above. In Figure 14 's structure, a primary sintering voltage, a reset voltage, and a set voltage are sequentially applied to the polysilicon.

[0121] Figure 15 is a graph showing an example of the voltage-current characteristics of the Figure 14 's structure in the original state, set state, and reset state. In Figure 15In [description], graph (a) shows the voltage-current characteristics in the original state, graph (b) shows the voltage-current characteristics in the set state, and graph (c) shows the voltage-current characteristics in the reset state. GeAsSeIn is used as the threshold switch memory material TSM. Refer to Figure 15 , in the original state, the resistance of the threshold switch memory material TSM is the highest and no threshold voltage is observed. After the first sintering, the resistance of the threshold switch memory material TSM decreases. In the set state, a threshold voltage at which the current suddenly increases is observed at about 6.9 V. In the reset state, a threshold voltage at which the current suddenly increases is observed at about 8 V. At the applied voltage between about 6.9 V and about 8 V, the resistance of the threshold switch memory material TSM in the set state is less than the resistance of the threshold switch memory material TSM in the reset state. Therefore, in Figure 15 the example shown in [description], it can be seen that the first voltage V1 as the first threshold voltage is about 6.9 V, and the second voltage V2 as the second threshold voltage is about 8 V.

[0122] Figure 16 is a schematic vertical cross-sectional view showing the structure of a memory cell string CS' according to another embodiment. Refer to Figure 16 , the memory cell string CS' according to another embodiment may further include a blocking layer 325 disposed between the channel layer 322 and the resistive change layer 323. The blocking layer 325 may be conformally deposited along the surface of the channel layer 322 to extend in a first direction, and the resistive change layer 323 may be conformally deposited along the surface of the blocking layer 325 to extend in a vertical direction. The blocking layer 325 may limit and / or prevent the diffusion of materials between the channel layer 322 and the resistive change layer 323. The blocking layer 325 may include a carbon- or nitrogen-based insulator. For example, the blocking layer 325 may include at least one of CN and SiN. However, in a case where the material of the resistive change layer 323 is less likely to be oxidized when the resistive change layer 323 is formed along the surface of the blocking layer 325, the blocking layer 325 may include an oxide such as Al2O3. In order to limit and / or minimize the power loss caused by the blocking layer 325, the blocking layer 325 may be formed as thin as possible. For example, the thickness d4 of the blocking layer 325 in the second direction may be greater than 0 nm and about 10 nm or less.

[0123] As described above, a memory device 200 according to one embodiment having the characteristics of a voltage-driven device may operate similarly to a charge-trapping flash (CTF)-VNAND. In addition, the memory device 200 according to one embodiment may have a relatively fast driving speed. In particular, since there is almost no interference between memory cells MC adjacent to each other in the memory cell string CS, the memory device 200 according to one embodiment may have high reliability. For example, since the resistance change layer 323 includes a pristine state region 323P having the lowest concentration of activation traps between memory cells MC adjacent to each other, almost no interference may occur between two driving regions 323F adjacent to each other in the first direction. Therefore, since the interval between adjacent memory cells MC, that is, the thickness (or height in the first direction) of the insulating spacer 311, may be reduced, the memory device 200 may be manufactured with a high degree of integration, and thus the capacity of the memory device 200 may be improved.

[0124] The above-described memory device 200 may be used to store data in various electronic devices. Figure 17 is a schematic conceptual diagram of a device architecture of an electronic device 400 to which a memory device according to an embodiment may be applied. Referring to Figure 17 , the electronic device 400 may include a main memory 410, an auxiliary memory 420, a central processing unit (CPU) 430, and an input / output device 440. The CPU 430 may include a cache (high-speed buffer) memory 431, an arithmetic logic unit (ALU) 432, and a control unit 433. The cache memory 431 may include a static random access memory (SRAM). The main memory 410 may include DRAM devices, and the auxiliary memory 420 may include a memory device 200 according to one embodiment. Alternatively, the cache memory 431, the main memory 410, and the auxiliary memory 420 may all include a memory device 200 according to one embodiment. In some cases, the electronic device 400 may be implemented in such a form that a computing unit device and a storage unit device are adjacent to each other in one chip without distinguishing the above-described sub-units.

[0125] In addition, the memory device 200 may be used as a neuromorphic computing platform. For example, Figure 18 is a schematic block diagram of a neuromorphic device 1000 including a memory device 200 according to one embodiment. Referring to Figure 18 , the neuromorphic device 1000 may include a processing circuitry 1010 and / or an on-chip memory 1020. The on-chip memory 1020 of the neuromorphic device 1000 may include a memory device 200 according to one embodiment.

[0126] The processing circuitry 1010 can be configured to control the functions of the neuromorphic device 1000. For example, the processing circuitry 1010 can be configured to control the neuromorphic device 1000 by executing a program stored in the on-chip memory 1020 of the neuromorphic device 1000. The processing circuitry 1010 can include hardware such as logic circuits, combinations of hardware such as logic circuits; hardware / software combinations such as a processor that executes software; or combinations thereof. For example, the processor can include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1000, an arithmetic logic unit (ALU), a digital processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In addition, the processing circuitry 1010 can be configured to read and write multiple data from / to an external device 1030 and execute the neuromorphic device 1000 by using the data. The external device 1030 can include a sensor array, which includes an external memory and / or an image sensor (e.g., a CMOS image sensor circuit).

[0127] Figure 18 The neuromorphic device 1000 can be applied to a machine learning system. Such a machine learning system can utilize various artificial neural network architectures and processing models, such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent (recursive) neural networks (RNNs) optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0128] Such a machine learning system can include other forms of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models can be used to provide various services, such as image classification services, user authentication services based on biometric or biometric data, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., and can be installed and executed by other electronic devices.

[0129] One or more of the elements disclosed above may include or be implemented as follows: processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0130] It should be understood that the vertical non-volatile memory devices including strings of memory cells described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of a feature or aspect within an embodiment should typically be considered as applicable to other similar features or aspects in other embodiments.

[0131] Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A vertical non-volatile memory device comprising: A plurality of memory cell strings are arranged in two dimensions, wherein Each of the plurality of storage cell strings comprises: a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of spacers alternately arranged in the first direction and each extending in a second direction intersecting the first direction, a gate insulating film extending in the first direction and between the channel layer and the plurality of gate electrodes, and a resistance change layer extending in the first direction along a surface of the channel layer, The material in the resistance change layer is switchable between a first state having a first threshold voltage and a second state having a second threshold voltage, and The second threshold voltage is greater than the first threshold voltage.

2. The vertical non-volatile memory device of claim 1, wherein If the resistance change layer is in the first state and a voltage less than the first threshold voltage is applied to the resistance change layer, no current flows in the resistance change layer, If the resistance change layer is in the first state and a voltage greater than or equal to the first threshold voltage is applied to the resistance change layer, current flows in the resistance change layer, If the resistance change layer is in the second state and a voltage less than the second threshold voltage is applied to the resistance change layer, no current flows in the resistance change layer, and If the resistance change layer is in the second state and a voltage greater than or equal to the second threshold voltage is applied to the resistance change layer, current flows in the resistance change layer.

3. The vertical non-volatile memory device of claim 2, wherein The resistance change layer is configured to switch from the first state to the second state when a negative (-) bias voltage is applied to the resistance change layer in response to the resistance change layer being in the first state, and The resistance change layer is configured to switch from the second state to the first state when a positive (+) bias voltage greater than the second threshold voltage is applied to the resistance change layer in response to the resistance change layer being in the second state.

4. The vertical non-volatile memory device of claim 1, wherein The nonvolatile memory device is configured to perform a read operation including applying a read voltage between the first threshold voltage and the second threshold voltage to the resistance change layer.

5. A vertical non-volatile memory device as described in claim 1, wherein the resistance change layer has a single-layer structure including at least one amorphous multi-component chalcogenide material of the following: GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeSbIn, GeAsSeTe, GeAsSeTeIn, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeIn, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, and GeAsTe. 6 . The vertical nonvolatile memory device of claim 5 , wherein when the resistance change layer includes germanium (Ge), a ratio of germanium (Ge) in the resistance change layer is 10 atomic % to 30 atomic %. 7 . The vertical nonvolatile memory device of claim 5 , wherein when the resistance change layer includes arsenic (As), a ratio of arsenic (As) in the resistance change layer is 10 atomic % to 50 atomic %. 8 . The vertical nonvolatile memory device of claim 5 , wherein when the resistance change layer includes selenium (Se), a ratio of selenium (Se) in the resistance change layer is 40 atomic % to 80 atomic %. 9 . The vertical nonvolatile memory device of claim 5 , wherein when the resistance change layer includes indium (In), a ratio of indium (In) in the resistance change layer is 1 atomic % to 10 atomic %.

10. The vertical non-volatile memory device of claim 1, wherein The resistance change layer includes a plurality of driving regions and a plurality of original state regions alternately arranged in the first direction.

11. The vertical non-volatile memory device of claim 10, wherein The plurality of driving regions each face a corresponding gate electrode of the plurality of gate electrodes in the second direction, and Each of the plurality of original-state regions faces a corresponding spacer of the plurality of spacers in the second direction.

12. The vertical non-volatile memory device of claim 10, wherein In response to application of a voltage greater than or equal to the first threshold voltage to the resistance change layer, resistances of the plurality of original-state regions are greater than resistances of the plurality of driving regions.

13. The vertical non-volatile memory device of claim 10, wherein Each of the plurality of driving regions includes a first region and a second region having different densities of activation wells.

14. The vertical non-volatile memory device of claim 13, wherein If the resistance change layer is in the first state, the density of activation wells in the second region is greater than the density of activation wells in the first region, and If the resistance change layer is in the second state, a density of activation wells in the second region is smaller than a density of activation wells in the first region. 15 . The vertical nonvolatile memory device of claim 13 , wherein a thickness of the second region in the first direction is smaller than a thickness of the first region in the first direction. 16 . The vertical nonvolatile memory device of claim 13 , wherein a thickness of the first region in the first direction is 2 to 10 times a thickness of the second region in the first direction.

17. The vertical non-volatile memory device of claim 1, wherein The resistance change layer has a property in which element composition distributions in the first region and the second region remain constant during switching between the first state and the second state. 18 . The vertical nonvolatile memory device of claim 1 , wherein a thickness of the resistance change layer in the second direction is 5 nm to 100 nm.

19. The vertical non-volatile memory device of claim 1, wherein Each of the plurality of memory cell strings further includes a barrier layer extending in the first direction between the channel layer and the resistance change layer, The barrier layer comprises a carbon-based nonconductor or a nitrogen-based nonconductor, and The thickness of the barrier layer in the second direction is greater than 0 nm and less than or equal to 10 nm.

20. Electronic equipment, including: Processing circuit system; and A vertical non-volatile memory device as claimed in any one of claims 1 to 19 connected to the processing circuitry.

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