Memory cell preparation method for improving interface characteristics of memory cell electrode of memory

Abstract

The invention discloses a memory cell preparation method for improving the interface characteristic of a memory cell electrode of a memory, and the memory cell sequentially comprises a lower electrode, an intermediate dielectric layer, an upper electrode material thin layer, and an upper electrode from bottom to top. The method sequentially comprises the following steps of: a, sequentially and respectively depositing to form a lower electrode and an intermediate dielectric layer of the storage unit; b, an upper electrode material thin layer is formed on the middle dielectric layer in a deposition mode, and the thickness of the thin layer is smaller than that of a subsequently-formed upper electrode; then, introducing a treatment gas selected from the group consisting of oxygen-containing gas, nitrogen-containing gas and / or halogen-containing gas, and carrying out surface treatment on the upper electrode material thin layer; and c, depositing on the upper electrode material thin layer to form an upper electrode. According to the method, the defects that the asymmetry of voltage and current in the operation process of the storage unit is increased and marks are easy to form due to the asymmetry of the storage unit structure can be eliminated.

Description

Technical Field

[0001] This application relates to the field of semiconductor memories, specifically to novel non-volatile memories, and particularly to a method for fabricating a memory cell that improves the electrode interface characteristics of the memory cells of novel non-volatile memories. Background Art

[0002] In recent years, in the semiconductor memory industry, novel memories such as ferroelectric memories (FRAM), resistive random access memories (RRAM), phase change memories (PCRAM), and magnetic random access memories (MRAM) have both the functions of random access memories and are non-volatile memories, and at the same time have the potential for further miniaturization of the manufacturing process, attracting much attention in the industry. These novel non-volatile memories have higher storage efficiency, lower cost, and can be miniaturized in the manufacturing process, and are developing very fast.

[0003] The memory cells of the FRAM, RRAM, PCRAM, and MRAM memories all include upper and lower electrodes and an intermediate dielectric layer between the two electrodes, only the materials of the intermediate dielectric layer are different. The intermediate dielectric layer of the memory cell of FRAM is a ferroelectric material layer, that of RRAM is a resistive change material layer, that of PCRAM is a phase change material layer, and that of MRAM is a ferromagnetic material layer. The functions of these memory cells in each memory are similar, and all use the electromagnetic property changes of the dielectric layer material to store information. For example, when the direction of the applied electric field changes in a ferroelectric material, the polarization of the ferroelectric domains in the dielectric layer material will reverse, and the polarization state will change. The high and low polarization states before and after the electric field reversal are used to store information. The resistive change material stores information by forming and breaking filaments (i.e., conductive paths) in the material to form high and low resistance states. The phase change material can change between crystallization (low resistance state) and amorphous (high resistance state), and the difference in resistance before and after the phase change is used to store information. When the magnetization orientation of the ferromagnetic layer material changes, the resistance of the magnetic tunnel junction can change between a low resistance state and a high resistance state, and the high and low resistance states are used to store information.

[0004] The preparation method of the storage unit of the above-mentioned memory is usually as follows: first, a lower electrode is deposited and formed, then an intermediate dielectric layer is deposited and formed, and finally an upper electrode is deposited and formed. During the deposition process of forming the intermediate dielectric layer, according to the type of material of the dielectric layer to be formed, an oxygen-containing gas or a halogen-containing gas is usually introduced, and sometimes a nitrogen-containing gas is also introduced, and the deposition process has a high temperature above 200 °C. In addition, after the upper electrode deposition is completed, there is a subsequent high-temperature treatment at 200 - 420 °C. In this way, the material on the upper surface of the lower electrode will combine with the introduced oxygen or halogen-containing gas to form an oxide or a halogen-containing substance. Taking the electrode made of TiN as an example, TiN will combine with the introduced oxygen and become TiON or even TiO. In this way, the upper surface of the lower electrode becomes a special interface layer, with a structure and composition different from that of the lower electrode, located between the dielectric layer and the lower electrode. However, during the deposition process of forming the upper electrode, a similar situation will not occur on the lower surface of the upper electrode in contact with the intermediate dielectric layer. This results in the interface between the upper electrode and the intermediate dielectric layer being different from that of the lower electrode, making the structure of the storage unit asymmetric, increasing the asymmetry of the voltage and current during the operation of the storage unit, and also prone to forming imprints. As the number of erasing and writing operations of the memory increases, the imprint effect will further deteriorate, leading to the failure of the memory. Summary of the Invention

[0005] The object of the present application is to provide a preparation method for the storage unit of a new type of memory, which can improve the electrode interface characteristics of the storage unit and eliminate the above-mentioned defects caused by the structural asymmetry of the storage unit.

[0006] The present invention provides a method for preparing a storage unit for improving the electrode interface characteristics of a storage unit of a memory. The storage unit sequentially includes from bottom to top: a lower electrode, an intermediate dielectric layer, a thin layer of upper electrode material, and an upper electrode. The method sequentially includes the following steps: a. Depositing and forming the lower electrode and the intermediate dielectric layer of the storage unit respectively; b. Depositing and forming a thin layer of upper electrode material on the intermediate dielectric layer, and the thickness of the thin layer is less than the thickness of the subsequent formed upper electrode; then, introducing a processing gas selected from the following: an oxygen-containing gas, a nitrogen-containing gas, and / or a halogen-containing gas to perform surface treatment on the thin layer; c. Depositing and forming an upper electrode on the thin layer of upper electrode material.

[0007] In a preferred embodiment, the processing gas is oxygen, ozone, nitrogen, ammonia, and / or sulfur sublimation gas.

[0008] In another preferred embodiment, the thin layer of upper electrode material is formed by atomic layer deposition. The thickness of the thin layer is preferably 1 - 40 angstroms.

[0009] In still another preferred embodiment, the time of the surface treatment is at least 5 seconds, more preferably 5 - 300 seconds.

[0010] In yet another preferred embodiment, the surface treatment is carried out in the temperature range from room temperature to 400°C.

[0011] In yet another preferred embodiment, the lower electrode, the intermediate dielectric layer, and the upper electrode are formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or metal-organic chemical vapor deposition. More preferably, they are all formed by atomic layer deposition.

[0012] In yet another preferred embodiment, the memory of the present invention is a novel non-volatile memory, preferably a ferroelectric memory, a resistive random access memory, a phase change memory, or a magnetic random access memory.

[0013] By forming a thin layer of upper electrode material between the intermediate dielectric layer and the upper electrode, the present invention can eliminate the above-mentioned defects caused by the asymmetry of the memory cell structure. After the surface treatment, the thin layer of upper electrode material has a structure similar to and / or the same function as the interface layer on the upper surface of the lower electrode, and can eliminate the defects of the memory cell such as the increase in the asymmetry of voltage and current during operation and the easy formation of imprinting. Description of the Drawings

[0014] Figure 1 Shows the steps of depositing to form the lower electrode of a memory cell of the present invention.

[0015] Figure 2 Shows the steps of depositing to form the intermediate dielectric layer of a memory cell of the present invention, and at the same time forming an interface layer on the upper surface of the lower electrode.

[0016] Figure 3 Shows the steps of depositing to form a thin layer of upper electrode material of a memory cell of the present invention.

[0017] Figure 4 Shows the steps of surface-treating the thin layer of upper electrode material of a memory cell of the present invention.

[0018] Figure 5 Shows the steps of depositing to form the upper electrode of a memory cell of the present invention. Detailed Description of the Invention

[0019] The present invention will be described in detail below. All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

[0020] In general, terms can be understood according to their meaning in the context. "One or more", at least in part depending on the context, can be understood to describe any feature, structure, or property in the singular form, or a combination of features, structures, or properties in the plural form. Similarly, terms such as "a", "an", or "the" can be understood to express the singular or the plural at least in part according to the context. Unless otherwise defined, the singular forms of "a" and "the" include explicit support for plural objects. For example, "the layer" can include a plurality of such layers.

[0021] It is readily understood that the meanings of "on", "above", and "over" in the present invention should be interpreted in the broadest manner, such that "on" not only refers to directly on something, but also can include being on something in the case where there are intermediate features or intermediate layers between the two, and "above" or "over" not only refers to being above or over something, but also can include being above or over something in the case where there are no intermediate features or intermediate layers between the two (i.e., directly on something). Similarly, "under", "below", or "beneath or below" have similar meanings.

[0022] In addition, spatially related terms such as "below", "beneath", "lower", "above", "upper", etc. can be used herein to describe the spatial relationship of one element or feature with respect to another element or feature shown in the drawings. The spatially related terms are intended to cover not only the spatial position and orientation of the device described in the drawings, but also other orientations of the device during use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially related descriptions used herein can correspondingly apply as well.

[0023] The term "layer" as used herein refers to a portion of a material that includes a region having a certain thickness. The layer can extend over all or part of the region of the underlying / overlying structure. In addition, the layer can be a region in a homogeneous or heterogeneous continuous structure, and the thickness of this region is less than the thickness of the continuous structure. For example, the layer can be located between any pair of horizontal planes, or at the top or bottom surface of a continuous structure. The layer can extend horizontally, vertically, and / or along a conical surface. The substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, and / or one or more layers thereunder. The meaning of a layer can include multiple layers therein. For example, an interconnect layer can include one or more conductor and contact layers (where contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0024] Next, a more detailed description will be given of the method for manufacturing the non-volatile memory cell of the present invention.

[0025] The non-volatile memory according to the present invention includes a ferroelectric memory, a resistive random access memory, a phase change memory, or a magnetic random access memory. The storage cells of these memories all include upper and lower electrodes and a dielectric layer therebetween for storing information. The process of forming the storage cell is as follows: from bottom to top, the lower electrode, the intermediate dielectric layer, and the upper electrode are sequentially deposited in turn.

[0026] For ferroelectric memories, most resistive random access memories, and magnetic random access memories, the intermediate dielectric layer is usually a metal oxide. When depositing the intermediate dielectric layer, an oxygen-containing gas (and sometimes a nitrogen-containing gas) is introduced. For phase change memories and a few resistive random access memories, the intermediate dielectric layer is usually a halogen metal alloy, such as a chalcogen metal alloy. When depositing the intermediate dielectric layer, a halogen-containing gas is introduced.

[0027] The inventors of the present invention have found that: when depositing the intermediate dielectric layer, the introduced oxygen-containing gas, nitrogen-containing gas, or halogen-containing gas will combine with the metal ions on the surface material of the lower electrode at the deposition high temperature, making the upper surface of the lower electrode become an interfacial layer rich in oxygen, nitrogen, or halogen atoms. The thickness is very thin, about less than 10 angstroms. This interfacial layer will prevent the oxygen atoms or halogen atoms in the metal oxide or halogen metal alloy of the intermediate dielectric layer from migrating downward to the lower electrode, avoiding the formation of oxygen vacancies or halogen vacancies in the intermediate dielectric layer, which is beneficial to improving the stability and reliability of the device. However, there is no such interfacial layer and its effect on the lower surface of the upper electrode, which makes the upper and lower electrode structures of the storage cell asymmetric, increases the asymmetry of voltage and current during the operation of the storage cell, and is also prone to form imprinting.

[0028] Therefore, the inventors of the present invention form a thin layer of upper electrode material between the intermediate dielectric layer and the upper electrode, and perform surface treatment with an oxygen-containing gas, a nitrogen-containing gas, and / or a halogen-containing gas, and then form the upper electrode. Preferably, the surface treatment gas is the same as the gas introduced when depositing the intermediate dielectric layer, so that the structure and composition of the thin layer of upper electrode material are the same as or close to those of the interfacial layer on the upper surface of the lower electrode, thereby improving the interfacial characteristics of the lower surface of the upper electrode and eliminating the asymmetry of the storage cell structure and the defects caused thereby. In addition, the surface treatment gas can also be different from the gas introduced when depositing the intermediate dielectric layer. In this case, the thin layer of upper electrode material also has the same function as the interfacial layer on the upper surface of the lower electrode, that is, preventing the oxygen atoms or halogen atoms in the intermediate dielectric layer from migrating outwards. This is because during the surface treatment process of the thin layer, the atoms of the treatment gas can be adsorbed or complexed by the metal ions in the thin layer, saturating the coordination of the metal ions and no longer being able to combine with the oxygen atoms or halogen atoms migrating out from the intermediate dielectric layer. Thus, the defects of increased asymmetry of voltage and current during the operation of the storage cell and easy formation of imprinting caused by the asymmetry of the storage cell structure can also be eliminated.

[0029] The materials of the upper and lower electrodes of the non-volatile memory cell of the present invention are preferably the same. Preferably, they are metals or metal nitrides. Including but not limited to: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiNx), titanium aluminum nitride (TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), tungsten carbonitride (WCNx), ruthenium (Ru), iridium (Ir), or composites of these materials.

[0030] For ferroelectric memories, most resistive random access memories, and magnetic random access memories, the intermediate dielectric layer of their memory cells is preferably a metal oxide. Including but not limited to oxides of the following metals: zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), nickel (Ni), and / or iron (Fe). It can also be doped with Group II elements calcium (Ca), strontium (Sr), or barium (Ba), or doped with Group III elements scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga), and indium (In)), or doped with lanthanide elements lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu).

[0031] For phase change memories and a few resistive random access memories, the intermediate dielectric layer of their memory cells is preferably a chalcogenide metal alloy. Including but not limited to chalcogenide alloys of the following metals: antimony, bismuth, gallium, indium, cobalt, and / or palladium.

[0032] The surface treatment gas of the thin layer of the upper electrode material of the present invention is preferably oxygen, ozone, nitrogen, ammonia, and / or sublimed sulfur gas. More preferably, it is oxygen, a mixed gas of oxygen and nitrogen, or sublimed sulfur gas. When using a mixed gas, the ratio or content between various gases is not particularly limited. In the mixed gas containing oxygen, the content of oxygen is preferably greater than 50% by volume.

[0033] The thicknesses of the upper and lower electrodes and the intermediate dielectric layer of the memory cell of the present invention are not particularly limited and are conventional selections in this industry. The thickness of the electrode can be about 10 nm - 200 nm, and preferably the thicknesses of the upper and lower electrodes are the same; the thickness of the intermediate dielectric layer can be about 3 nm - 20 nm.

[0034] The thin layer of the upper electrode material of the present invention is thinner than the upper electrode. The thickness of the thin layer is preferably 1 - 40 angstroms, more preferably 3 - 20 angstroms, and still more preferably 5 - 15 angstroms. Most preferably, it is close to the thickness of the interface layer on the upper surface of the lower electrode, which is about 5 - 10 angstroms.

[0035] The lower electrode, intermediate dielectric layer, thin upper electrode material layer, and upper electrode of the present invention can be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or metal-organic chemical vapor deposition.

[0036] Since the thickness of the thin upper electrode material layer is very thin, it is preferably formed by atomic layer deposition, which makes it easier to control the very thin thickness required to be formed. More preferably, the lower electrode, intermediate dielectric layer, and upper electrode are also formed by atomic layer deposition.

[0037] The surface treatment of the thin upper electrode material layer can be carried out in the chamber where the layer is deposited, or the layer can be removed from the deposition chamber and then surface-treated. Preferably, it is carried out in-situ in the deposition chamber.

[0038] There is no particular limitation on the temperature for carrying out the surface treatment. It is preferably in the range of room temperature to 400 °C, more preferably 50 °C - 380 °C, still more preferably 150 - 350 °C, still more preferably 200 - 330 °C, and most preferably close to the temperature for forming the interfacial layer on the upper surface of the lower electrode when depositing the intermediate dielectric layer, which is 250 - 300 °C.

[0039] There is also no particular limitation on the surface treatment time. It is preferably at least 5 seconds, more preferably 5 - 300 seconds, still more preferably 10 - 180 seconds. The higher the temperature, the shorter the time can be. When treating at room temperature, it can be treated for 150 - 300 seconds. When treating at a temperature of 250 - 300 °C, it can be treated for 10 - 60 seconds.

[0040] The technical solutions of the present application will be clearly and completely described below in conjunction with the accompanying drawings and the embodiments of the present application.

[0041] It should be understood that the specific embodiments shown in the drawings are illustrative, and the terms used in the description are only for the purpose of describing specific embodiments and are not intended to be limiting; moreover, the drawings are not necessarily drawn to scale. Although the description of the specific embodiments and their preparation contains many details for illustrative purposes, those of ordinary skill in the art will understand that many changes and substitutions can be made to these details, and these changes and substitutions are considered to be included within the scope of the present invention. Additionally, those skilled in the art will recognize that the embodiments of the present invention can be implemented without one or more of the following specific details. And in some cases, some well-known structures, materials, or operations are not shown or described in detail to avoid making the embodiments of the present invention overly cumbersome.

[0042] Example 1

[0043] According to the following method, a storage cell of a ferroelectric memory is prepared, and this storage cell has improved electrode interface characteristics. The materials of the upper and lower electrodes of this storage cell are TiN, and the middle dielectric layer is a hybrid structure formed by alternately depositing zirconium oxide atomic layers and hafnium oxide atomic layers in a cycle. The thickness of the upper and lower electrodes is about 100 nm, and the thickness of the middle dielectric layer is about 10 nm. The thickness of the thin layer of the upper electrode material is about 10 angstroms.

[0044] The lower electrode, the middle dielectric layer, the thin layer of the upper electrode material, and the upper electrode are all formed by atomic layer deposition. The whole process is as follows in sequence Figures 1-5 shown.

[0045] As Figure 1 shown, first deposit and form the lower electrode 1. Then, as Figure 2 shown, introduce oxygen, and deposit and form the middle dielectric layer 3 at a temperature of about 280 °C. At the same time, a oxygen-rich interface layer 2 with a thickness of about 10 angstroms is formed on the upper surface of the lower electrode. Next, as Figure 3 shown, deposit and form the thin layer 4 of the upper electrode material on the middle dielectric layer 3, and control the thickness of this thin layer to be about 10 angstroms. Subsequently, as Figure 4 shown, right in the chamber where this thin layer 4 is deposited and formed, introduce oxygen at a temperature of about 280 °C, and perform surface treatment on this thin layer 4 for 50 seconds. Finally, as Figure 5 shown, deposit and form the upper electrode 5 on this thin layer 4.

[0046] This storage cell eliminates the defect of structural asymmetry between the upper and lower electrodes, and also eliminates the defects of increased asymmetry of voltage and current during the operation of the storage cell and easy formation of imprinting.

[0047] The above description of the embodiments is for the convenience of those of ordinary skill in the art to understand and apply this application. Those who are familiar with the technology in this field can obviously make various modifications to these embodiments easily, and apply the general principles described here to other embodiments without having to pay creative labor. Therefore, this application is not limited to the embodiments here. Improvements and modifications made by those skilled in the art according to the content disclosed in this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. A method for fabricating a memory cell that improves the interface characteristics of the electrodes of the memory cell. The memory cell sequentially includes, from bottom to top: a lower electrode, an intermediate dielectric layer, a thin layer of upper electrode material, and an upper electrode. The method sequentially includes the following steps: a. Depositing and forming the lower electrode and the intermediate dielectric layer of the memory cell respectively one after another; b. Depositing and forming a thin layer of upper electrode material on the intermediate dielectric layer, the thickness of this thin layer being less than the thickness of the upper electrode formed subsequently; then, introducing a processing gas selected from the following: an oxygen-containing gas, a nitrogen-containing gas, and / or a halogen-containing gas, and performing surface treatment on the thin layer of upper electrode material; c. Depositing and forming the upper electrode on the thin layer of upper electrode material.

2. The method according to claim 1, wherein the processing gas is oxygen, ozone, nitrogen, ammonia, and / or sublimed sulfur gas.

3. The method according to claim 1, wherein the thin layer of upper electrode material in step (b) is formed by atomic layer deposition.

4. The method according to any one of claims 1-3, wherein the time of the surface treatment is at least 5 seconds.

5. The method according to any one of claims 1-3, wherein the surface treatment is carried out in a temperature range from room temperature to 400°.

6. The method according to any one of claims 1-3, wherein the thickness of the thin layer of upper electrode material is 1-40 angstroms.

7. The method according to any one of claims 1-3, wherein the lower electrode, the intermediate dielectric layer, and the upper electrode are formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, or metal-organic chemical vapor deposition.

8. The method according to claim 7, wherein the lower electrode, the intermediate dielectric layer, and the upper electrode are all formed by atomic layer deposition.

9. The method according to claim 4, wherein the time of the surface treatment is 5-300 seconds.

10. The method according to any one of claims 1-3, wherein the memory is a non-volatile memory selected from: ferroelectric memory, resistive random access memory, phase change memory, or magnetic random access memory.

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