Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a substrate which comprises a substrate and an insulating structure located in the substrate; the plurality of groove structures are separately arranged in the substrate; wherein the insulating structure comprises at least one first sub-part, the first sub-part is located between two adjacent groove structures, and in the arrangement direction of the two adjacent groove structures, the extension length of the first sub-part is equal to the distance between the two adjacent groove structures; the capacitor structure comprises a plurality of stacked electrode layers and first dielectric layers at least located between every two adjacent electrode layers, and the capacitor structure at least covers the inner walls of the groove structures.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous growth of the market demand for high-performance, miniaturized, and low-power chips, the application prospect of high-density silicon capacitors in advanced packaging is broad, especially in the fields of high-performance computing, 5G communication, Internet of Things (IoT), artificial intelligence (AI), and automotive electronics. The mainstream technology of existing high-density silicon capacitors is the deep trench capacitor (DTC) technology proposed by TSMC. In packaging, the silicon capacitor can be placed in the middle of the packaging substrate or under the chip. Such a position selection helps to achieve lower equivalent series inductance (ESL) characteristics, thereby improving the filtering performance.

[0003] However, the current deep trench capacitors have the problem of high losses in high-frequency applications. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate including a substrate and an insulating structure located in the substrate; a plurality of trench structures, separately disposed in the substrate; wherein, the insulating structure includes at least one first sub-part, the first sub-part is located between two adjacent trench structures, and in the arrangement direction of two adjacent trench structures, the extension length of the first sub-part is equal to the distance between two adjacent trench structures; a capacitor structure, including a plurality of electrode layers stacked and at least a first dielectric layer located between two adjacent electrode layers, the capacitor structure at least covering the inner walls of a plurality of trench structures.

[0005] In some embodiments, a plurality of trench structures and the first sub-part located between two adjacent trench structures are defined as a target structure; the insulating structure further includes a second sub-part connected to the first sub-part, the second sub-part surrounding the side wall of the target structure and partially located below the target structure, and a plurality of trench structures are located in the space defined by the insulating structure.

[0006] In some embodiments, the material of the insulating structure is silicon oxide.

[0007] In some embodiments, the capacitor structure further covers a part of the upper surface of the substrate, and the edge of the part of the capacitor structure covering the upper surface of the substrate includes a step structure; The semiconductor structure further includes: a second dielectric layer covering at least the step structure; and a plurality of contact plugs respectively extending from the top surface of the second dielectric layer to the surfaces of the plurality of electrode layers of the step structure and electrically connected to the plurality of electrode layers in one-to-one correspondence.

[0008] An embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: Providing a substrate, and forming a plurality of discrete trench structures and an insulating structure in the substrate, the insulating structure including at least one first sub-part located between two adjacent trench structures, and in the arrangement direction of two adjacent trench structures, the extension length of the first sub-part being equal to the distance between two adjacent trench structures; Forming a capacitive structure covering at least the inner walls of the plurality of trench structures, the capacitive structure including a plurality of electrode layers arranged in layers and at least a first dielectric layer located between two adjacent electrode layers.

[0009] In some embodiments, forming a plurality of discrete trench structures and an insulating structure in the substrate includes: Etching the substrate to form a plurality of discrete trench structures in the substrate and a spacer structure located between two adjacent trench structures; Performing an oxidation process on part of the substrate from the sidewalls and bottoms of the plurality of trench structures to completely oxidize the spacer structure located between two adjacent trench structures to form the first sub-part.

[0010] In some embodiments, defining the plurality of trench structures and the spacer structure located between two adjacent trench structures as an initial target structure; performing an oxidation process on part of the substrate from the sidewalls and bottoms of the plurality of trench structures further includes: Oxidizing part of the substrate surrounding the sidewalls of the initial target structure and part of the substrate located below the target structure to form a second sub-part, the first sub-part and the second sub-part being connected to each other to form the insulating structure, and the plurality of trench structures being located within the space defined by the insulating structure.

[0011] In some embodiments, the oxidation process includes a dry oxidation process and / or a wet oxidation process.

[0012] In some embodiments, the reaction temperature range of the oxidation process is between 550°C and 1300°C.

[0013] In some embodiments, the capacitive structure further covers the upper surfaces of the substrate and the insulating structure; the method further includes: Etch a part of the capacitor structure located on the substrate and the insulating structure to form a stepped structure at the edge of the capacitor structure; Form a second dielectric layer that at least covers the stepped structure; Etch the second dielectric layer to form a plurality of contact holes, and the plurality of contact holes respectively expose a plurality of electrode layers of the stepped structure; Form contact plugs in the contact holes, and the contact plugs are electrically connected to the electrode layers.

[0014] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a substrate and an insulating structure located in the substrate; a plurality of trench structures separately disposed in the substrate; wherein the insulating structure includes at least one first sub - part located between two adjacent trench structures, and in the arrangement direction of two adjacent trench structures, the extension length of the first sub - part is equal to the distance between two adjacent trench structures; a capacitor structure including a plurality of electrode layers stacked and at least a first dielectric layer located between two adjacent electrode layers, and the capacitor structure at least covers the inner walls of a plurality of trench structures. The insulating structure provided by the embodiments of the present disclosure at least includes a first sub - part disposed between two adjacent trench structures. The material of the insulating structure has a relatively high resistivity. When the capacitor structure conducts signal transmission, especially high - frequency signal transmission, in the substrate, the presence of the first sub - part with a relatively high resistivity reduces the energy loss caused by electron movement between capacitor structures, thereby reducing the delay and attenuation of signals in the substrate.

[0015] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the specification and drawings. Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 Schematic diagram of the semiconductor structure provided by the embodiments of the present disclosure; Figure 2 For Figure 1 Top - view schematic diagram of the substrate and the insulating structure in Figure 3 Flow block diagram of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure; Figure 4The process flow of the semiconductor structure provided by the embodiments of the present disclosure during manufacturing Figure 1 ; Figure 5 The process flow of the semiconductor structure provided by the embodiments of the present disclosure during manufacturing Figure 2 ; Figure 6 The process flow of the semiconductor structure provided by the embodiments of the present disclosure during manufacturing Figure 3 ; Figure 7 The process flow of the semiconductor structure provided by the embodiments of the present disclosure during manufacturing Figure 4 ; Figure 8 The process flow of the semiconductor structure provided by the embodiments of the present disclosure during manufacturing Figure 5 . Detailed implementation manners

[0018] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0019] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0020] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not imply that a first element, component, region, layer or part necessarily exists in the present disclosure.

[0022] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0024] With the growing market demand for high-performance, miniaturized, and low-power chips, the application prospect of high-density silicon capacitors in advanced packaging is broad, especially in the fields of high-performance computing, 5G communication, Internet of Things (IoT), artificial intelligence (AI), and automotive electronics. The mainstream technology for existing high-density silicon capacitors is the Deep Trench Capacitor (DTC) technology proposed by TSMC. In packaging, the silicon capacitor can be placed in the middle of the packaging substrate or under the chip, and such a position selection helps to achieve lower Equivalent Series Inductance (ESL) characteristics, thereby improving the filtering performance.

[0025] In the related art, high-resistivity silicon can be used as the material of the substrate. The deep trench capacitor is usually formed in the high-resistivity silicon substrate. Compared with the ordinary silicon substrate, the high-resistivity silicon has a lower carrier concentration and a higher resistivity. Usually, its resistivity is above 1000 Ω·cm, and it has good insulation performance and chemical stability. Therefore, it can reduce the parasitic capacitance and signal loss of the silicon capacitor. However, since silicon is a semiconductor material, in high-frequency applications, the deep trench capacitor formed in the high-resistivity silicon substrate has the problem of high loss.

[0026] Based on this, the technical solutions of the embodiments of the present disclosure are proposed.

[0027] In the embodiments of the present disclosure, an insulating structure is provided in the substrate, and the insulating structure at least includes a first sub-part disposed between two adjacent trench structures. The material of the insulating structure has a high resistivity. When the capacitive structure transmits signals in the substrate, especially high-frequency signals, the presence of the first sub-part with a high resistivity reduces the energy loss caused by electron movement between the capacitive structures, thereby reducing the delay and attenuation of the signals in the substrate.

[0028] The following will describe in detail the specific embodiments of the present disclosure with reference to the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of description, the schematic diagrams will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present disclosure herein.

[0029] As Figure 1 and Figure 2As shown, the present disclosure provides a semiconductor structure, including: a substrate 10, including 11 and an insulating structure 13; a plurality of trench structures 12, separately disposed in the substrate 10; wherein, the insulating structure 13 includes at least one first sub - part 131, the first sub - part 131 is located between two adjacent trench structures 12, and in the arrangement direction of the two adjacent trench structures 12, the extension length of the first sub - part 131 is equal to the distance between the two adjacent trench structures 12; a capacitor structure 14, including a plurality of electrode layers 141 stacked and at least a first dielectric layer 142 located between at least two adjacent electrode layers 141, and the capacitor structure 14 at least covers the inner walls of the plurality of trench structures 12.

[0030] In some embodiments, the substrate 11 may be a semiconductor substrate and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III - V compound semiconductor material, at least one II - VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate 11 may be a high - resistivity silicon substrate.

[0031] In some embodiments, the trench structure 12 may be a trench with a high aspect ratio. As Figure 2 shown, in some embodiments, the plurality of trench structures 12 may be arranged along a first direction parallel to the plane of the substrate 10 and extend along a second direction parallel to the plane of the substrate 10, the first direction and the second direction intersect, and the trench structure 12 and the first sub - part 131 of the insulating structure 13 are alternately arranged along the first direction. However, it is not limited thereto, and the plurality of trench structures 12 may also have other arrangement manners, such as being arranged in an array, and the first sub - part 131 is located between two adjacent trench structures 12 in any direction.

[0032] In the embodiments of the present disclosure, the capacitor structures 14 formed in two adjacent trench structures 12 are separated by the first sub - part 131. In the embodiments of the present disclosure, by providing the first sub - part 131 between two adjacent trench structures 12, and the material of the insulating structure 13 is an insulating material, compared with high - resistivity silicon, the insulating material has a higher resistivity (for example, between 10 8 Ω•m and 10 22 Ω•m), a lower dielectric constant (for example, between 3.9 and 4.1), and a lower dielectric loss (for example, less than 10 -3), with almost no free carriers inside. When the capacitive structure 14 transmits signals, especially high-frequency signals, within the substrate 10, the insulating structure 13 can reduce the energy loss and parasitic capacitance caused by electron movement between the capacitive structures 14. In this way, the electric field can more easily penetrate the insulating structure 13, thereby reducing the energy loss during signal propagation and further reducing the delay and attenuation of signals in the substrate 10. Here, the dielectric loss, also known as the loss tangent angle, is an indicator for measuring the energy dissipation ability of materials in an alternating current field.

[0033] In this application, in the arrangement direction of two adjacent trench structures 12, the extension length of the first sub-part 131 located between the two adjacent trench structures 12 is equal to the distance between the two adjacent trench structures 12. That is to say, there is no conductor or semiconductor capable of carrier transmission between the two adjacent trench structures 12. In this way, insertion loss between two adjacent capacitive structures 14 is avoided.

[0034] As Figure 1 and Figure 2 shown, in some embodiments, a plurality of trench structures 12 and the first sub-part 131 located between two adjacent trench structures 12 are defined as the target structure 20; the insulating structure 13 further includes a second sub-part 132 connected to the first sub-part 131. The second sub-part 132 surrounds the side wall of the target structure 20 and is partially located below the target structure 20. A plurality of trench structures 12 are located within the space surrounded by the insulating structure 13. The second sub-part 132 separates the plurality of trench structures 12 from the substrate 11. The material of the second sub-part 132 is an insulating material. In this way, the existence of the second sub-part 132 further reduces the signal delay and attenuation during signal transmission.

[0035] In some embodiments, the material of the insulating structure 13 includes silicon oxide, which has a high resistivity, a low dielectric constant, and a dielectric loss. In this way, the above effects can be achieved.

[0036] In actual operation, the etching process can be first performed on the substrate 11 to form a plurality of trench structures 12 and the spacer structures located between two adjacent trench structures 12 within the substrate 11. Then, a dry oxidation process and / or a wet oxidation process are performed on the side walls and the bottom of the plurality of trench structures 12 to completely oxidize the spacer structures between two adjacent trench structures 12 to form the first sub-part 131, and to oxidize the part of the substrate 11 located below and on the peripheral side walls of the trench structures 12 and the spacer structures to form the second sub-part 132. In the embodiments of the present disclosure, the insulating structure 13 is formed by performing an oxidation process on a part of the substrate 11. In this way, the insulating structure 13 is relatively tightly combined with the substrate 11 and has high mechanical stability, thereby improving the mechanical stability of the capacitive structure 14.

[0037] AsFigure 1 As shown, in some embodiments, the capacitive structure 14 also covers the upper surface of a part of the substrate 10. Specifically, the capacitive structure 14 at least covers the upper surface of the first sub - part 131, and the capacitive structures 14 located in the plurality of trench structures 12 are sequentially connected through the capacitive structures 14 located on the first sub - part 131. The capacitive structure 14 may also cover the upper surface of the second sub - part 132 and the upper surface of a part of the substrate 11.

[0038] As Figure 1 shown, the electrode layer 141 and the first dielectric layer 142 of the capacitive structure 14 are alternately stacked and conformally cover the inner wall of the trench structure 12 and the upper surface of a part of the substrate 10. The materials of the electrode layer 141 and the first dielectric layer 142 may be materials with good step coverage.

[0039] In some embodiments, the materials of any two of the plurality of electrode layers 141 may be the same or different. The material of each electrode layer 141 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, etc. For example, the electrode layer 141 may be a titanium nitride thin film formed by an atomic layer deposition (ALD) process.

[0040] In some embodiments, the first dielectric layer 142 may also cover the uppermost electrode layer 141 among the plurality of electrode layers 141 stacked. For example, when the number of electrode layers 141 is two, the number of the first dielectric layers 142 may also be 2. One layer is located between the adjacent two electrode layers 141, and the other layer covers the uppermost electrode layer 141.

[0041] In actual operation, the material of the first dielectric layer 142 may be one or more of silicon nitride, zirconium oxide, aluminum oxide, hafnium oxide, etc. formed by an atomic layer deposition process or a furnace tube method. And when the material of the first dielectric layer 142 is multiple layers, the materials of any two of the plurality of first dielectric layers 142 may be the same or different.

[0042] As Figure 1As shown, in some embodiments, the semiconductor structure further includes a third dielectric layer 15 that at least covers the upper surface of the substrate 11, and a part of the third dielectric layer 15 is located between the substrate 11 and the capacitor structure 14, for protecting the substrate 11 and electrically isolating the substrate 11 and the capacitor structure 14. In some embodiments, the third dielectric layer 15 may also cover the upper surface of the insulating structure 13. The third dielectric layer 15 may be formed by a thin film deposition process or by performing an oxidation process on the surface of the substrate 11. The material of the third dielectric layer 15 includes, but is not limited to, one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), and oxynitrides (such as silicon oxynitride).

[0043] As Figure 1 shown, in some embodiments, the edge of a part of the capacitor structure 14 located on the upper surface of the substrate 10 includes a stepped structure 16. The semiconductor structure further includes: a second dielectric layer 17 that at least covers the stepped structure 16; and a plurality of contact plugs 19 that respectively extend from the upper surface of the second dielectric layer 17 to the surfaces of a plurality of electrode layers 141 of the stepped structure 16 and are electrically connected to the plurality of electrode layers 141 in one-to-one correspondence.

[0044] In some embodiments, the second dielectric layer 17 also fills the remaining space of the trench structure 12 and covers the entire capacitor structure 14. As Figure 1 shown, in some embodiments, the second dielectric layer 17 includes a first sub-layer 171 and a second sub-layer 172. The first sub-layer 171 fills the remaining space of the trench structure 12 and covers the electrode layer 141 located in the topmost layer; the second sub-layer 172 covers the first sub-layer 171 and the stepped structure 16.

[0045] In actual operation, the first sub-layer 171 and the second sub-layer 172 may be formed in different process steps, and the materials of the first sub-layer 171 and the second sub-layer 172 may be the same or different. For example, the materials of the first sub-layer 171 and the second sub-layer 172 include, but are not limited to, one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), and oxynitrides (such as silicon oxynitride).

[0046] As Figure 1 shown, the stepped structure 16 includes a plurality of upward stepped surfaces 161. The stepped surfaces 161 may be electrode layers 141 or the first dielectric layer 142. In the case where the stepped surface 161 is an electrode layer 141, the contact plug 19 penetrates through the second dielectric layer 17 to reach the surface of the electrode layer 141 and is electrically connected thereto; in the case where the stepped surface 161 is the first dielectric layer 142, the contact plug 19 penetrates through the second dielectric layer 17 and the first dielectric layer 142 serving as the stepped surface 161 to reach the electrode layer 141 located below the first dielectric layer 142 and is electrically connected thereto.

[0047] In some embodiments, the number of electrode layers 141 is n, where n is a positive integer greater than or equal to 2. The n electrode layers 141 can be sequentially denoted as the first layer, the second layer, …, the nth layer from bottom to top. In some embodiments, the plurality of contact plugs 19 include one or more first contact plugs 191 and one or more second contact plugs 192. The one or more first contact plugs 191 are respectively and electrically connected to one or more odd-layer electrode layers 141 in a one-to-one correspondence, and the one or more second contact plugs 192 are respectively and electrically connected to one or more even-layer electrode layers 141 in a one-to-one correspondence.

[0048] In some embodiments, the semiconductor structure further includes a first interconnect layer 211 and a second interconnect layer 212 located on the second dielectric layer 17. The first interconnect layer 211 is electrically connected to the first contact plug 191, and the odd-layer electrode layers 141 are electrically connected to each other through the first interconnect layer 211 and the first contact plug 191 to serve as one electrode of the capacitor structure 14; the second interconnect layer 212 is electrically connected to the second contact plug 192, and the even-layer electrode layers 141 are electrically connected to each other through the second interconnect layer 212 and the second contact plug 192 to serve as the other electrode of the capacitor structure 14.

[0049] In actual operation, the materials of the contact plug 19, the first interconnect layer 211, and the second interconnect layer 212 can be copper, aluminum, or other metal materials with better high-temperature stability (such as tungsten) or metal compound materials (such as titanium nitride), etc.

[0050] It should be noted that Figure 1 the number of electrode layers 141 shown in is 3 layers, and the number of the first dielectric layers 142 is 2 layers. However, this is not limited thereto, and the number of electrode layers 141 can be more or less, such as 2 layers, 5 layers, 7 layers, 10 layers, etc.

[0051] The embodiments of the present disclosure further provide a manufacturing method of a semiconductor structure, as Figure 3 shown, the method includes the following steps: Step S101: Provide a substrate, and form a plurality of discretely arranged trench structures and an insulating structure in the substrate. The insulating structure includes at least one first sub-part. The first sub-part is located between two adjacent trench structures, and in the arrangement direction of the two adjacent trench structures, the extension length of the first sub-part is equal to the distance between the two adjacent trench structures; Step S102: Form a capacitor structure covering at least the inner walls of the plurality of trench structures. The capacitor structure includes a plurality of electrode layers arranged in a stacked manner and at least a first dielectric layer located between two adjacent electrode layers.

[0052] The following further describes in detail the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure with reference to the accompanying drawings.

[0053] First, perform step S101, as Figures 4 to 6 shown, provide a substrate 11, and form a plurality of discretely arranged trench structures 12 and an insulating structure 13 in the substrate 11. The insulating structure 13 includes at least one first sub - part 131. The first sub - part 131 is located between two adjacent trench structures 12, and in the arrangement direction of the two adjacent trench structures 12, the extension length of the first sub - part 131 is equal to the distance between the two adjacent trench structures 12.

[0054] In some embodiments, the substrate 11 may be a semiconductor substrate, and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate), at least one III - V compound semiconductor material, at least one II - VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a specific embodiment, the substrate 11 may be a high - resistivity silicon substrate.

[0055] Specifically, forming a plurality of discretely arranged trench structures 12 and an insulating structure 13 in the substrate 11 includes: Etch the substrate 11 to form a plurality of discretely arranged trench structures 12 and a spacer structure 111 located between two adjacent trench structures 12 (as Figures 4 to 5 ); Perform an oxidation process on a part of the substrate 11 from the sidewalls and bottom of the plurality of trench structures 12, so that the spacer structure 111 located between two adjacent trench structures 12 is completely oxidized to form the first sub - part 131 (as Figure 6 ).

[0056] Refer again to Figure 4 , in some embodiments, before forming the trench structure 12 in the substrate 11, a third dielectric layer 15 may also be formed on the surface of the substrate 11. The third dielectric layer 15 is used to protect the substrate 11 when forming the trench structure 12 subsequently. The third dielectric layer 15 may be formed by one or more thin - film deposition processes or by performing an oxidation process on the surface of the substrate 11. The material of the third dielectric layer 15 includes, but is not limited to, one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), and oxynitrides (such as silicon oxynitride).

[0057] Refer again to Figure 4 and Figure 5 , in actual operation, the trench structure 12 can be formed in the substrate 11 by the following method: First, form a mask pattern M on the third dielectric layer 15, then etch the third dielectric layer 15 using the mask pattern M as a mask to form an opening (not labeled) exposing the substrate 11, and then etch the substrate 11 exposed by the opening to form a plurality of trench structures 12.

[0058] In some embodiments, the trench structure 12 may be a trench with a high aspect ratio. As Figure 2 shown, in some embodiments, a plurality of trench structures 12 may be arranged in a first direction parallel to the plane of the substrate 10 and extend in a second direction parallel to the plane of the substrate 10. The spacer structure 111 located between two adjacent trench structures 12 may be a wall-like structure, and the first direction and the second direction intersect. However, this is not limited thereto. The plurality of trench structures 12 may also have other arrangements, such as an array arrangement, and the first sub-part 131 is located between two adjacent trench structures 12 in any direction.

[0059] As Figure 6 shown, before performing the oxidation process on the substrate 11, the third dielectric layer 15 on the surface of the substrate 11 may not be removed; however, this is not limited thereto, and the third dielectric layer 15 may also be removed. When the oxidation process is subsequently performed, an oxide layer may be re-formed on the upper surface of the substrate 11.

[0060] As Figure 6 shown, in actual operation, when performing the oxidation process on the substrate 11 from the sidewalls of the plurality of trench structures 12, the width of the part of the substrate 11 oxidized in the oxidation process may be greater than or equal to half of the extension length of the spacer structure 111 in the arrangement direction of two adjacent trench structures 12. Thus, after performing the oxidation process on part of the substrate 11, the spacer structure 111 can be completely oxidized, and in the arrangement direction of two adjacent trench structures 12, the extension length of the formed first sub-part 131 is equal to the distance between two adjacent trench structures 12. Here, the width of the part of the substrate 11 oxidized refers to the dimension in which the part of the substrate 11 oxidized extends from the sidewall of the trench structure 12 into the substrate 11 in a direction parallel to the substrate 11.

[0061] Referring again to Figure 6 , in some embodiments, the plurality of trench structures 12 and the isolation structure 111 are defined as the initial target structure 20'; performing the oxidation process on part of the substrate 11 from the sidewalls and the bottom of the plurality of trench structures 12 further includes: oxidizing the part of the substrate 11 surrounding the sidewall of the initial target structure 20' and the part of the substrate 11 located below the initial target structure 20' to form a second sub-part 132. The first sub-part 131 and the second sub-part 132 are connected to each other to form an insulating structure 13, and the plurality of trench structures 12 are located in the space defined by the insulating structure 13. In some embodiments, the plurality of trench structures 12 and the first sub-part 131 formed after oxidation are defined as the target structure 20, and the second sub-part 132 surrounds the sidewall of the target structure 20 and is partially located below the target structure 20.

[0062] In actual operation, the first sub - portion 131 and the second sub - portion 132 can be formed simultaneously in one oxidation process. In some examples, an oxidation process can be performed on a partial substrate 11 through a wet oxidation process, a dry oxidation process, or a combination of a wet oxidation process and a dry oxidation process to form the insulating structure 13. In the embodiments of the present disclosure, the insulating structure 13 is formed by performing an oxidation process on the partial substrate 11. Thus, the insulating structure 13 is tightly combined with the substrate 11 and has high mechanical stability, thereby improving the mechanical stability of the capacitive structure 14.

[0063] In some embodiments, the material of the substrate 11 is silicon, and the insulating structure 13 with the material of silicon dioxide is formed by performing an oxidation process on the partial substrate 11. Among them, the chemical reaction formula of the wet oxidation process is: Si (solid) + H2O (gas) → SiO2 (solid) + 2H2 (gas); the chemical reaction formula of the dry oxidation process is: Si (solid) + O2 (gas) → SiO2 (solid).

[0064] In some embodiments, the reaction temperature range of the oxidation process is between 550 °C and 1300 °C (including the end - point values), such as 550 °C, 850 °C, 1000 °C, 1100 °C, 1250 °C, etc. By controlling the reaction temperature within the above range, the spacer structure 111 can be fully oxidized, so that the spacer structure 111 is completely oxidized.

[0065] Next, step S102 is executed, as Figure 7 shown, a capacitive structure 14 is formed that at least covers the inner walls of a plurality of trench structures 12. The capacitive structure 14 includes a plurality of electrode layers 141 stacked and at least a first dielectric layer 142 located between adjacent two electrode layers 141.

[0066] In the embodiments of the present disclosure, a first sub - portion 131 is provided between two adjacent trench structures 12, that is, the capacitive structures 14 located in adjacent trench structures 12 are separated by the first sub - portion 131, and the material of the insulating structure 13 is an insulating material. Compared with high - resistivity silicon, the insulating material has a higher resistivity (for example, between 108 Ω•m and 1022 Ω•m), a lower dielectric constant (for example, between 3.9 and 4.1), and a lower dielectric loss (for example, less than 10 -3 ) and almost no free carriers inside. When the capacitive structure 14 transmits signals, especially high - frequency signals, in the substrate 10, the insulating structure 13 can reduce the energy loss and parasitic capacitance caused by electron movement between the capacitive structures 14. Thus, the electric field can more easily penetrate the insulating structure 13, thereby reducing the energy loss during signal propagation and further reducing the delay and attenuation of signals in the substrate 10. Here, the dielectric loss is also called the loss tangent angle, which is an index to measure the energy dissipation ability of materials in an alternating current field.

[0067] In this application, the extension length of the first sub - part 131 is equal to the distance between two adjacent trench structures 12. That is to say, the part of the substrate 11 located between two adjacent trench structures 12 is completely oxidized, and there is no conductor or semiconductor capable of carrier transmission between two adjacent trench structures 12, thus avoiding insertion loss between two adjacent capacitor structures 14.

[0068] In some embodiments, the insulating structure 13 further includes a second sub - part 132 connected to the first sub - part 131. The second sub - part 132 surrounds the sidewall of the target structure 20 and is partially located below the target structure 20. A plurality of trench structures 12 are located within the space surrounded by the insulating structure 13. The second sub - part 132 spaces the plurality of trench structures 12 apart from the substrate 11. The material of the second sub - part 132 is an insulating material. Thus, the presence of the second sub - part 132 further reduces signal delay and attenuation during signal transmission.

[0069] In some embodiments, the material of the insulating structure 13 includes silicon oxide, which has a high resistivity, a low dielectric constant, and low dielectric loss. Thus, the above - mentioned effects can be achieved.

[0070] As Figure 7 shown, in some embodiments, the capacitor structure 14 also covers the upper surfaces of the substrate 11 and the insulating structure 13. In actual operation, the electrode layer 141 and the first dielectric layer 142 can be alternately deposited on the inner walls of the trench structures 12, as well as on the substrate 11 and the insulating structure 13, through one or more thin - film deposition processes. In some embodiments, the capacitor structure 14 also covers the third dielectric layer 15, and the third dielectric layer 15 is located between the upper surfaces of the substrate 11 and the insulating structure 13 and the capacitor structure 14.

[0071] Here, the thin - film deposition processes include chemical vapor deposition (CVD), plasma - enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, etc.

[0072] In some embodiments, the materials of the electrode layer 141 and the first dielectric layer 142 can be materials with good step coverage.

[0073] In some embodiments, the materials of any two electrode layers 141 among the plurality of electrode layers 141 can be the same or different. The material of each electrode layer 141 can include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, etc. For example, the electrode layer 141 can be a titanium nitride thin film formed by the atomic layer deposition (ALD) process.

[0074] In some embodiments, the first dielectric layer 142 may also cover the topmost electrode layer 141 among the multiple electrode layers 141 stacked; for example, when the number of electrode layers 141 is two, the number of the first dielectric layers 142 may also be 2 layers, one layer is located between the adjacent two electrode layers 141, and the other layer covers the topmost electrode layer 141.

[0075] In actual operation, the material of the first dielectric layer 142 may be one or more of silicon nitride, zirconium oxide, aluminum oxide, hafnium oxide, etc. formed by atomic layer deposition process or furnace tube method, and when the material of the first dielectric layer 142 is multiple layers, the materials of any two of the multiple first dielectric layers 142 may be the same or different.

[0076] As Figure 8 shown, in some embodiments, the method further includes: etching a part of the capacitor structure 14 located on the substrate 11 and the insulating structure 13 to form a step structure 16 at the edge of the capacitor structure 14; the step structure 16 includes multiple upward step surfaces 161, and the step surface 161 may be the electrode layer 141 or the first dielectric layer 142. In actual operation, the step structure 16 can be formed by multiple photolithography and etching processes.

[0077] In some embodiments, the method further includes: forming a second dielectric layer 17, and the second dielectric layer 17 covers at least the step structure 16. Specifically, forming the second dielectric layer 17 includes: First, as Figure 7 shown, after forming the capacitor structure 14, forming a first sub-layer 171, and the first sub-layer 171 fills the remaining space of the trench structure 12 and covers the capacitor structure 14; then, as Figure 8 shown, during the process of forming the step structure 16, removing a part of the first sub-layer 171, and the remaining first sub-layer 171 fills the remaining space of the trench structure 12 and covers the topmost electrode layer 141; then, as Figure 1 shown, forming a second sub-layer 172, and the second sub-layer 172 covers the first sub-layer 171 and the step structure 16.

[0078] The materials of the first sub-layer 171 and the second sub-layer 172 may be the same or different. For example, the materials of the first sub-layer 171 and the second sub-layer 172 include but are not limited to one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), and oxynitrides (such as silicon oxynitride).

[0079] Continue to refer to Figure 1, in some embodiments, after forming the second dielectric layer 17, the method further includes: etching the second dielectric layer 17 to form a plurality of contact holes V, and the plurality of contact holes V respectively expose a plurality of electrode layers 141 of the step structure 16; forming contact plugs 19 in the contact holes V, and the contact plugs 19 are electrically connected to the electrode layers 141.

[0080] Specifically, when the step surface 161 of the step structure 16 is the electrode layer 141, the contact plug 19 penetrates through the second dielectric layer 17 to reach the surface of the electrode layer 141 and is electrically connected thereto; when the step surface 161 is the first dielectric layer 142, the contact plug 19 penetrates through the second dielectric layer 17 and the first dielectric layer 142 serving as the step surface 161 to reach the electrode layer 141 located below the first dielectric layer 142 and is electrically connected thereto.

[0081] In some embodiments, the number of the electrode layers 141 is n, where n is a positive integer greater than or equal to 2, and the n electrode layers 141 can be sequentially denoted as the first layer, the second layer... the nth layer from bottom to top. In some embodiments, the plurality of contact plugs 19 include one or more first contact plugs 191 and one or more second contact plugs 192, and the one or more first contact plugs 191 are respectively electrically connected to the one or more odd-layer electrode layers 141 in a one-to-one correspondence, and the one or more second contact plugs 192 are respectively electrically connected to the one or more even-layer electrode layers 141 in a one-to-one correspondence.

[0082] As Figure 1 shown, in some embodiments, the method further includes: forming a first interconnect layer 211 and a second interconnect layer 212 on the second dielectric layer 17, the first interconnect layer 211 is electrically connected to the first contact plug 191, and the odd-layer electrode layers 141 are electrically connected to each other through the first interconnect layer 211 and the first contact plug 191 to serve as one electrode of the capacitor structure 14, the second interconnect layer 212 is electrically connected to the second contact plug 192, and the even-layer electrode layers 141 are electrically connected to each other through the second interconnect layer 212 and the second contact plug 192 to serve as the other electrode of the capacitor structure 14.

[0083] In actual operation, the materials of the contact plugs 19, the first interconnect layer 211, and the second interconnect layer 212 can be copper, aluminum, or other metal materials with better high-temperature stability (such as tungsten) or metal compound materials (such as titanium nitride), etc.

[0084] It should be noted that Figures 7 to 8 and Figure 1 the number of layers of the electrode layer 141 shown in

[0085] It should be noted that the above are only the preferred embodiments of the present disclosure, and are not used to limit the protection scope of the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate comprising a substrate body and an insulating structure located within the substrate body; A plurality of trench structures, separately disposed within the substrate; wherein, the insulating structure includes at least one first sub - portion, the first sub - portion is located between two adjacent ones of the trench structures, and in the arrangement direction of two adjacent ones of the trench structures, the extension length of the first sub - portion is equal to the distance between two adjacent ones of the trench structures; A capacitor structure, comprising a plurality of electrode layers stacked and at least a first dielectric layer located between two adjacent ones of the electrode layers, the capacitor structure at least covering the inner walls of a plurality of the trench structures.

2. The semiconductor structure according to claim 1, characterized in that, Define a plurality of the trench structures and the first sub - portion located between two adjacent ones of the trench structures as a target structure; the insulating structure further includes a second sub - portion connected to the first sub - portion, the second sub - portion surrounds the side wall of the target structure and is partially located below the target structure, and a plurality of the trench structures are located within the space defined by the insulating structure.

3. The semiconductor structure according to claim 1, characterized in that, The material of the insulating structure is silicon oxide.

4. The semiconductor structure according to claim 1, characterized in that, The capacitor structure further covers a part of the upper surface of the substrate, and the edge of the part of the capacitor structure covering the upper surface of the substrate includes a step structure; The semiconductor structure further includes: a second dielectric layer, at least covering the step structure; a plurality of contact plugs, respectively extending from the top surface of the second dielectric layer to the surfaces of a plurality of electrode layers of the step structure and being electrically connected to the plurality of electrode layers in one - to - one correspondence.

5. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Provide a substrate body, and form a plurality of separately disposed trench structures and an insulating structure within the substrate body, the insulating structure includes at least one first sub - portion, the first sub - portion is located between two adjacent ones of the trench structures, and in the arrangement direction of two adjacent ones of the trench structures, the extension length of the first sub - portion is equal to the distance between two adjacent ones of the trench structures; Form a capacitor structure at least covering the inner walls of a plurality of the trench structures, the capacitor structure comprising a plurality of electrode layers stacked and at least a first dielectric layer located between two adjacent ones of the electrode layers.

6. The manufacturing method according to claim 5, characterized in that, Forming a plurality of separately disposed trench structures and an insulating structure within the substrate body, including: Etch the substrate body to form a plurality of separately disposed trench structures within the substrate body and a spacer structure located between two adjacent ones of the trench structures; Perform an oxidation process on part of the substrate body from the side walls and the bottom of a plurality of the trench structures, so that the spacer structure located between two adjacent ones of the trench structures is completely oxidized to form the first sub - portion.

7. The manufacturing method according to claim 6, characterized in that, Define a plurality of the trench structures and the spacer structure located between two adjacent ones of the trench structures as an initial target structure; Performing an oxidation process on part of the substrate body from the side walls and the bottom of a plurality of the trench structures further includes: Oxidize the part of the substrate body surrounding the side wall of the initial target structure and the part of the substrate body located below the target structure to form a second sub - portion, the first sub - portion and the second sub - portion are connected to each other to form the insulating structure, and a plurality of the trench structures are located within the space defined by the insulating structure.

8. The manufacturing method according to claim 6 or 7, characterized in that, The oxidation process includes using a dry oxidation process and / or a wet oxidation process.

9. The manufacturing method according to claim 6 or 7, characterized in that, The reaction temperature range of the oxidation process is between 550°C and 1300°C.

10. The manufacturing method according to claim 5, characterized in that, The capacitor structure also covers the upper surfaces of the substrate and the insulating structure; the method further includes: Etching a part of the capacitor structure located on the substrate and the insulating structure to form a step structure at the edge of the capacitor structure; Forming a second dielectric layer that covers at least the step structure; Etching the second dielectric layer to form a plurality of contact holes, and the plurality of contact holes respectively expose a plurality of electrode layers of the step structure; Forming contact plugs in the contact holes, and the contact plugs are electrically connected to the electrode layers.

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