Semiconductor epitaxial structure and semiconductor epitaxial growth method

Abstract

The embodiment of the invention provides a semiconductor epitaxial structure and a semiconductor epitaxial growth method, and relates to the technical field of semiconductor epitaxial growth, the semiconductor epitaxial structure comprises a substrate, a nucleation layer, a stress regulation and control layer, a superlattice layer, a channel layer, a barrier layer and a cap layer, the nucleation layer is arranged on the substrate; the stress regulation and control layer is arranged on the nucleation layer; the superlattice layers are sequentially stacked on the stress regulation and control layers; the channel layer is arranged on the superlattice layer; the barrier layer is arranged on the channel layer; the cap layer is arranged on the barrier layer; wherein the thermal expansion coefficient of the channel layer is smaller than that of the substrate, the lattice constant of the stress regulation and control layer is larger than that of the channel layer, and the stress regulation and control layer is configured to provide tensile stress. Compared with the prior art, the semiconductor epitaxial structure provided by the embodiment of the invention can provide an effective stress regulation and control mechanism for large-size epitaxial growth, effectively regulate and control the bow value, and alleviate the problem of bow value deviation.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor epitaxial growth, and in particular, to a semiconductor epitaxial structure and a semiconductor epitaxial growth method. Background Art

[0002] In the prior art, on a sapphire substrate, a common buffer layer material is composed of one of AlN, GaN, and AlGaN materials, and GaN material is grown thereon subsequently.

[0003] Since the thermal expansion coefficient of GaN is 5.59E-6K -1 lower than that of sapphire, which is 7.3E-6K -1 When the temperature drops, the shrinkage of the sapphire material will be faster than that of the GaN material. Therefore, when the epitaxial layer grows and then cools down to room temperature, the bow value of the epitaxial wafer is positively biased, and the overall shape is convex (bow > 0). The larger the substrate diameter size and the thicker the epitaxial layer, the more positive the bow value (> 50μm), which will affect the chip and the subsequent packaging process.

[0004] In addition, when using traditional buffer layer materials to fabricate small-size sapphire-based GaN HEMT devices (diameter < 6 inches), the problem of positive bow value is not prominent. When switching to the growth of large-size sapphire-based GaN materials, the bow value will increase exponentially, so the problem of positive bow value has to be considered. Summary of the Invention

[0005] The purpose of the present invention is to provide a semiconductor epitaxial structure and a semiconductor epitaxial growth method, which can provide an effective stress regulation mechanism for large-size epitaxial growth, effectively regulate the bow value, and mitigate the problem of positive bow value.

[0006] In a first aspect, the present invention provides a semiconductor epitaxial structure, including:

[0007] A substrate;

[0008] A nucleation layer disposed on the substrate;

[0009] A stress regulation layer disposed on the nucleation layer;

[0010] A superlattice layer sequentially stacked on the stress regulation layer;

[0011] A channel layer disposed on the superlattice layer;

[0012] A barrier layer disposed on the channel layer;

[0013] A cap layer disposed on the barrier layer;

[0014] Among them, the thermal expansion coefficient of the channel layer is less than that of the substrate, the lattice constant of the stress regulation layer is greater than that of the channel layer, and the stress regulation layer is configured to provide tensile stress.

[0015] In an alternative embodiment, the stress regulation layer includes In y Ga 1-y N (0 < y < 1); the channel layer includes GaN.

[0016] In an alternative embodiment, the superlattice layer includes multiple growth cycle layers, and each growth cycle layer includes a first semiconductor layer and a second semiconductor layer grown in sequence. The first semiconductor layer includes GaN, and the second semiconductor layer includes In z Ga 1-z N (0 < z < y).

[0017] In an alternative embodiment, the number of layers of the growth cycle layer is greater than or equal to 3.

[0018] In an alternative embodiment, the superlattice layer includes In t Ga 1-t N (y ≥ t ≥ 0), where the In content t in the superlattice layer gradually decreases from y to 0 along the growth direction.

[0019] In an alternative embodiment, the superlattice layer includes multiple growth cycle layers, and each growth cycle layer includes a first semiconductor layer and a second semiconductor layer grown in sequence. The first semiconductor layer includes In z Ga 1-z N (0 < z < 1), and the second semiconductor layer includes GaN.

[0020] In an alternative embodiment, the substrate includes a sapphire substrate, and the nucleation layer includes In x Ga 1-x N (0 < x < 1).

[0021] In an alternative embodiment, the semiconductor epitaxial structure further includes a breakdown voltage layer, and the breakdown voltage layer is disposed between the superlattice layer and the channel layer.

[0022] In an alternative embodiment, the breakdown voltage layer includes GaN doped with C.

[0023] In a second aspect, the present invention provides a semiconductor epitaxial growth method for preparing the semiconductor epitaxial structure according to any one of the foregoing embodiments. The growth method includes:

[0024] Growing a nucleation layer on a substrate;

[0025] Growing a stress regulation layer on the nucleation layer;

[0026] Grow a superlattice layer on the stress regulation layer;

[0027] Grow a channel layer on the superlattice layer;

[0028] Grow a barrier layer on the channel layer;

[0029] Grow a capping layer on the barrier layer;

[0030] Wherein, the thermal expansion coefficient of the channel layer is smaller than that of the substrate, and the lattice constant of the stress regulation layer is larger than that of the channel layer.

[0031] The beneficial effects of the embodiments of the present invention include:

[0032] The semiconductor epitaxial structure and the semiconductor epitaxial growth method provided by the embodiments of the present invention form a nucleation layer, a stress regulation layer, a superlattice layer, a channel layer, a barrier layer and a capping layer on a substrate in sequence. Among them, the setting of the superlattice layer can improve the subsequent crystal quality. Moreover, the thermal expansion coefficient of the channel layer is smaller than that of the substrate, and the lattice constant of the stress regulation layer is larger than that of the channel layer, and the stress regulation layer can provide tensile stress. Since the thermal expansion coefficient of the substrate is relatively large, when the temperature drops during epitaxial growth, the shrinkage of the substrate will be faster than that of the channel layer, resulting in a positive bow value of the epitaxial wafer, and the overall state is convex, especially this phenomenon is particularly prominent in large-size epitaxial growth. And the lattice constant of the stress regulation layer is larger than that of the channel layer, which can provide tensile stress for channel growth, so that the bow value turns towards the negative direction. Compared with the prior art, the semiconductor epitaxial structure provided by the embodiments of the present invention can provide an effective stress regulation mechanism for large-size epitaxial growth, effectively regulate the bow value, and slow down the problem of positive bow value deviation. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0034] Figure 1 Schematic diagram of the first semiconductor epitaxial structure provided by the embodiments of the present invention;

[0035] Figure 2 Schematic diagram of the second semiconductor epitaxial structure provided by the embodiments of the present invention;

[0036] Figure 3Schematic diagram of the third semiconductor epitaxial structure provided by the embodiments of the present invention;

[0037] Figures 4 to 9 Process flow chart of the semiconductor epitaxial growth method provided by the embodiments of the present invention.

[0038] Icon: 100 - semiconductor epitaxial structure; 110 - substrate; 120 - nucleation layer; 130 - stress regulation layer; 140 - superlattice layer; 141 - growth cycle layer; 142 - first semiconductor layer; 143 - second semiconductor layer; 150 - channel layer; 160 - barrier layer; 170 - capping layer; 180 - breakdown voltage layer. Detailed implementation manners

[0039] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. Components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0041] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0042] In the description of the present invention, it should be noted that if terms such as "upper", "lower", "inner", "outer", etc. are used to indicate the orientation or positional relationship, it is based on the orientation or positional relationship shown in the accompanying drawings or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention.

[0043] In addition, if terms such as "first", "second", etc. are used only for distinguishing descriptions, they cannot be understood as indicating or implying relative importance.

[0044] As disclosed in the background art, existing epitaxial growth structures generally have the following several configurations: 1. A GaN HEMT device epitaxial structure, on which a GaN buffer layer is sequentially grown on a sapphire substrate, and then a GaN channel layer and an AlGaN electron blocking layer are grown (CN220652021U); 2. A GaN HEMT device epitaxial structure, on which an AlN buffer layer is sequentially grown on a sapphire substrate, and then a GaN channel layer, an AlGaN electron blocking layer, and a Cap capping layer are grown (CN220208973U); 3. A light-emitting diode epitaxial structure, on which an AlGaN buffer layer, unintentionally doped GaN, N-type doped GaN, low-temperature PGaN, MQW quantum well, P-type doped AlGaN, and P-type doped GaN are sequentially grown on a sapphire substrate (CN105679892A).

[0045] When using traditional buffer layer materials for small-sized sapphire-based GaN HEMT devices (diameter < 6 inches), the problem of bow value deviation is not prominent. However, when switching to the growth of large-sized sapphire-based GaN materials, the bow value will increase exponentially. Therefore, the problem of bow value deviation has to be considered. Traditional sapphire-based buffer layer materials lack effective stress regulation and cannot adjust the bow in the negative direction. The main reason is that the lattice constant of the buffer layer material is not greater than that of GaN, resulting in compressive stress on the subsequent GaN growth by the buffer layer, and the bow of the epitaxial layer further turns in the positive direction. This leads to the situation that when the bow < 50 μm, the epitaxial layer cannot be grown too thick (thickness > 3.5 μm), or when the thickness of the epitaxial layer is greater than 3.5 μm, the bow cannot be controlled to be < 50 μm.

[0046] To solve the above problems, embodiments of the present invention provide a novel semiconductor epitaxial structure and a semiconductor epitaxial growth method. It should be noted that, without conflict, the features in the embodiments of the present invention can be combined with each other.

[0047] See Figure 1 , embodiments of the present invention provide a semiconductor epitaxial structure, which can provide an effective stress regulation mechanism for large-sized epitaxial growth, effectively regulate the bow value, slow down the problem of bow value deviation, and enable the bow to be still controlled within the range of 0 - 50 μm when the growth thickness of the epitaxial layer is greater than 3.5 μm. At the same time, the growth quality is good and the breakdown voltage performance is better.

[0048] The semiconductor epitaxial structure 100 provided by the embodiment of the present invention includes a substrate 110, a nucleation layer 120, a stress regulation layer 130, a superlattice layer 140, a channel layer 150, a barrier layer 160, and a cap layer 170. The nucleation layer 120 is disposed on the substrate 110; the stress regulation layer 130 is disposed on the nucleation layer 120; the superlattice layer 140 is sequentially stacked on the stress regulation layer 130; the channel layer 150 is disposed on the superlattice layer 140; the barrier layer 160 is disposed on the channel layer 150; the cap layer 170 is disposed on the barrier layer 160. Wherein, the thermal expansion coefficient of the channel layer 150 is less than that of the substrate 110, and the lattice constant of the stress regulation layer 130 is greater than that of the channel layer 150. The stress regulation layer 130 is configured to provide tensile stress.

[0049] It should be noted that in this embodiment, the substrate 110 is a large-size substrate 110 (diameter≥6inch). Due to the relatively large thermal expansion coefficient of the substrate 110, the shrinkage of the substrate 110 is faster than that of the channel layer 150 during the cooling of epitaxial growth, resulting in a positive bow value of the epitaxial wafer and presenting a convex state as a whole. This phenomenon is particularly prominent in large-size epitaxial growth. The lattice constant of the stress regulation layer 130 is greater than that of the channel layer 150, which can provide tensile stress for channel growth, making the bow value turn towards the negative direction. Therefore, the bow value of the overall epitaxial structure can be reduced, providing an effective stress regulation mechanism for the epitaxial growth of large-size GaN HEMT, so that when the growth thickness of the epitaxial layer is greater than 3.5μm, the bow can still be controlled within the range of 0-50μm.

[0050] In some embodiments, the stress regulation layer 130 includes In y Ga 1-y N (0<y<1); the channel layer 150 includes GaN. In y Ga 1-y N grows on the nucleation layer 120, and its lattice constant is greater than that of GaN, which can provide tensile stress for the subsequent growth of GaN, making the bow value turn towards the negative direction. Moreover, the stress regulation layer 130 can reduce the stress caused by the lattice mismatch between the InGaN material and the substrate 110, which is beneficial to the subsequent growth of GaN.

[0051] In some embodiments, the superlattice layer 140 includes multiple growth period layers 141. Each growth period layer 141 includes a first semiconductor layer 142 and a second semiconductor layer 143 grown in sequence. The first semiconductor layer 142 is GaN, and the second semiconductor layer 143 is In z Ga 1-z N (0<z<y). Specifically, GaN and In z Ga 1-zThe superlattice layer 140 is composed of alternating growth of N(0 < z < y), where GaN and In z Ga 1-z N is a growth cycle layer 141. Among them, the number of layers M of the growth cycle layer 141 is greater than or equal to 3. Preferably, the number of layers M of the growth cycle layer 141 is between 10 and 40. The superlattice GaN and In z Ga 1-z N grow alternately for M cycles. The periodically grown material can filter the threading dislocations in the underlying layer and improve the crystal quality of the subsequent GaN. At the same time, the introduction of In z Ga 1-z N material further introduces tensile stress for the subsequent GaN growth, making the bow value further shift in the negative direction.

[0052] See Figure 2 , in other preferred embodiments of the present invention, the superlattice layer 140 includes multiple growth cycle layers 141. Each growth cycle layer 141 includes a first semiconductor layer 142 and a second semiconductor layer 143 that grow in sequence. The first semiconductor layer 142 is In z Ga 1-z N(0 < z < 1), and the second semiconductor layer 143 is GaN. Specifically, In z Ga 1-z N and GaN can exchange their growth positions, which can also filter the threading dislocations in the underlying layer and improve the crystal quality of the subsequent GaN. At the same time, the introduction of In z Ga 1-z N material further introduces tensile stress for the subsequent GaN growth, making the bow value further shift in the negative direction.

[0053] See Figure 3 , in other preferred embodiments of the present invention, the superlattice layer 140 includes In t Ga 1-t N(y ≥ t ≥ 0), where the In content t in the superlattice layer 140 gradually decreases from y to 0 along the growth direction. Specifically, the superlattice layer 140 can be an In t Ga 1-t N layer, and t gradually changes from y to 0, that is, the superlattice layer 140 closer to the substrate 110 is In y Ga 1-y N, and the superlattice layer 140 closer to the channel layer 150 is GaN. With this structure, it can also filter the threading dislocations in the underlying layer and improve the crystal quality of the subsequent GaN. At the same time, the introduction of In y Ga 1-y N material further introduces tensile stress for the subsequent GaN growth, making the bow value further shift in the negative direction.

[0054] Please refer toFigures 1 to 3 , in some embodiments, the substrate 110 includes a sapphire substrate 110, and the nucleation layer 120 includes In x Ga 1-x N (0 < x < 1). Specifically, the material of the nucleation layer 120 is In x Ga 1-x N, which can nucleate at low temperature and the nucleation is polycrystalline, greatly reducing the stress caused by the lattice mismatch with the sapphire substrate 110 and facilitating the growth of the stress control layer 130.

[0055] In some embodiments, the semiconductor epitaxial structure 100 further includes a breakdown voltage layer 180, and the breakdown voltage layer 180 is disposed between the superlattice layer 140 and the channel layer 150. Specifically, the breakdown voltage layer 180 can provide higher breakdown voltage, thereby improving the device breakdown voltage and device performance.

[0056] Furthermore, the breakdown voltage layer 180 includes GaN doped with C. Specifically, C can be actively doped during growth to further improve the breakdown voltage of the device.

[0057] The embodiment of the present invention also provides a semiconductor epitaxial growth method for preparing the aforementioned semiconductor epitaxial structure 100, and the growth method includes the following steps:

[0058] S1: Grow the nucleation layer 120 on the substrate 110.

[0059] See Figure 4 , specifically, first, a 6-inch or 8-inch sapphire substrate 110 can be taken, and the sapphire substrate 110 is heated to 1000 °C - 1100 °C in a hydrogen atmosphere, the pressure is controlled at 50 mbar - 100 mbar, and maintained for 5 - 10 min. Then it is cooled to 500 °C - 660 °C, the atmosphere is switched to nitrogen, the pressure is controlled at 100 mbar - 200 mbar, trimethylindium (TMIn), trimethylgallium (TMGa) and ammonia (NH3) are introduced, and In x Ga 1-x N nucleation layer 120 is grown, and the growth thickness is 5 nm - 30 nm. The component ratio of In x Ga 1-x N can be controlled by controlling the flow rate of process gases.

[0060] S2: Grow the stress control layer 130 on the nucleation layer 120.

[0061] See Figure 5 , specifically, the temperature can be raised to 700 °C - 850 °C, the pressure is controlled at 150 mbar - 200 mbar, and In y Ga 1-yN stress control layer 130, where y = 0.3 and the growth thickness is 50 nm - 150 nm.

[0062] S3: Grow the superlattice layer 140 on the stress control layer 130.

[0063] See Figure 6 , specifically, heat up to 800 °C - 950 °C, control the pressure at 100 mbar - 400 mbar, replace TMGa with triethylgallium (TEGa), and grow In z Ga 1-z N with z = 0.1 and a growth thickness of 3 nm - 5 nm. Then turn off TMIn and switch the atmosphere to hydrogen, and grow GaN of the superlattice layer 140 with a growth thickness of 10 nm - 30 nm. The superlattice layer 140 can be continuously grown for 10 - 40 growth cycle layers 141, and each growth cycle layer 141 is composed of In z Ga 1-z N and GaN.

[0064] S4: Grow the pressure-resistant layer 180 on the superlattice layer 140.

[0065] See Figure 7 , specifically, after the growth of GaN in the last cycle of the superlattice is completed, the hydrogen atmosphere remains unchanged, the chamber pressure is reduced to 50 mbar - 100 mbar, the temperature is raised to 950 °C - 1030 °C, replace TEGa with TMGa, and grow GaN doped with carbon actively with a growth thickness of 1000 nm - 2000 nm to further improve the voltage resistance of the device.

[0066] S5: Grow the channel layer 150 on the superlattice layer 140.

[0067] See Figure 8 , specifically, raise the temperature to 1000 °C - 1050 °C, increase the chamber pressure to 200 mbar - 300 mbar, and grow the GaN channel layer 150 with a growth thickness of 200 nm - 400 nm.

[0068] S6: Grow the barrier layer 160 on the channel layer 150.

[0069] See Figure 9 , specifically, raise the temperature to 1010 °C - 1060 °C, reduce the chamber pressure to 50 mbar - 100 mbar, introduce trimethylaluminum (TMAl), and grow the barrier layer 160 with a growth thickness of 15 nm - 30 nm.

[0070] S7: Grow the capping layer 170 on the barrier layer 160;

[0071] Please continue to see Figure 1, specifically, with the temperature and pressure remaining unchanged, the supply of TMAl is stopped, and the capping layer 170 is grown with a growth thickness of 2 nm - 5 nm.

[0072] Among them, the thermal expansion coefficient of the channel layer 150 is smaller than that of the substrate 110, and the lattice constant of the stress regulation layer 130 is larger than that of the channel layer 150.

[0073] The semiconductor epitaxial structure 100 and the semiconductor epitaxial growth method provided by the embodiments of the present invention sequentially form a nucleation layer 120, a stress regulation layer 130, a superlattice layer 140, a channel layer 150, a barrier layer 160, and a capping layer 170 on the substrate 110. Among them, the setting of the superlattice layer 140 can improve the subsequent crystal quality. And, the thermal expansion coefficient of the channel layer 150 is smaller than that of the substrate 110, and the lattice constant of the stress regulation layer 130 is larger than that of the channel layer 150. The stress regulation layer 130 can provide tensile stress. Since the thermal expansion coefficient of the substrate 110 is relatively large, when the temperature drops during epitaxial growth, the shrinkage of the substrate 110 will be faster than that of the channel layer 150, resulting in a positive bow value of the epitaxial wafer and presenting a convex state as a whole. This phenomenon is particularly prominent in large-size epitaxial growth. And the lattice constant of the stress regulation layer 130 is larger than that of the channel layer 150, which can provide tensile stress for channel growth and make the bow value turn towards the negative direction. Among them, In x Ga 1-x The N nucleation layer 120 can nucleate at a low temperature, reduce the stress with the sapphire substrate 110, and facilitate the growth of In y Ga 1-y N; In y Ga 1-y The N stress regulation layer 130 can reduce the stress caused by the lattice mismatch with the substrate 110, and at the same time provide tensile stress for GaN growth, making the bow value turn towards the negative direction. The superlattice layer 140 can not only filter out the dislocations in the bottom layer and improve the subsequent GaN crystal quality, but also provide tensile stress for GaN, making the bow value further turn towards the negative direction. Therefore, the semiconductor epitaxial structure 100 provided by the embodiments of the present invention can provide an effective stress regulation mechanism for large-size epitaxial growth, effectively regulate the bow value, slow down the problem of positive bow value, and can achieve the growth of the HEMT epitaxial layer on the large-size sapphire substrate 110 with a thickness of more than 3.5 μm. At the same time, the bow of the epitaxial wafer can be controlled below 50 μm.

[0074] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claimed rights.

Claims

1. A semiconductor epitaxial structure, characterized in that: include: A substrate (110); A nucleation layer (120) disposed on the substrate (110); A stress regulating layer (130) disposed on the nucleation layer (120); A superlattice layer (140) is sequentially stacked on the stress regulating layer (130); A channel layer (150) disposed on the superlattice layer (140); A barrier layer (160) disposed on the channel layer (150); A cap layer (170) disposed on the barrier layer (160); The thermal expansion coefficient of the channel layer (150) is smaller than the thermal expansion coefficient of the substrate (110), the lattice constant of the stress regulation layer (130) is larger than the lattice constant of the channel layer (150), and the stress regulation layer (130) is configured to provide tensile stress.

2. The semiconductor epitaxial structure according to claim 1, characterized in that: The stress regulation layer (130) includes In y Ga 1-y N (0 < y < 1); the channel layer (150) includes GaN.

3. The semiconductor epitaxial structure according to claim 2, characterized in that: The superlattice layer (140) comprises a plurality of growth period layers (141), each of the growth period layers (141) comprising a first semiconductor layer (142) and a second semiconductor layer (143) grown in sequence, the first semiconductor layer (142) comprising GaN, and the second semiconductor layer (143) comprising In z Ga 1-z N(0 <z<y)。 4. The semiconductor epitaxial structure according to claim 3, characterized in that: The number of layers of the superlattice layer (140) is greater than or equal to 3.

5. The semiconductor epitaxial structure according to claim 2, characterized in that: The superlattice layer (140) includes In t Ga 1-t N(y≥t≥0), wherein the In content t in the superlattice layer (140) gradually decreases from y to 0 along the growth direction.

6. The semiconductor epitaxial structure according to claim 2, characterized in that: The superlattice layer (140) includes multiple growth cycle layers (141), and each growth cycle layer (141) includes a first semiconductor layer (142) and a second semiconductor layer (143) grown in sequence. The first semiconductor layer (142) includes In z Ga 1-z N (0 < z < 1), and the second semiconductor layer (143) includes GaN.

7. The semiconductor epitaxial structure according to claim 2, characterized in that: The substrate (110) includes a sapphire substrate (110), and the nucleation layer (120) includes In x Ga 1-x N(0 <x<1)。 8. The semiconductor epitaxial structure according to claim 1, characterized in that: The semiconductor epitaxial structure further comprises a voltage-resistant layer (180), wherein the voltage-resistant layer (180) is arranged between the superlattice layer (140) and the channel layer (150).

9. The semiconductor epitaxial structure according to claim 8, characterized in that: The voltage-resistant layer (180) includes C-doped GaN.

10. A semiconductor epitaxial growth method for preparing a semiconductor epitaxial structure according to any one of claims 1 to 9, characterized in that: The growing method comprises: Growing a nucleation layer (120) on a substrate (110); Growing a stress regulating layer (130) on the nucleation layer (120); Growing a superlattice layer (140) on the stress regulating layer (130); Growing a channel layer (150) on the superlattice layer (140); Growing a barrier layer (160) on the channel layer (150); Growing a cap layer (170) on the barrier layer (160); The thermal expansion coefficient of the channel layer (150) is smaller than the thermal expansion coefficient of the substrate (110), and the lattice constant of the stress regulation layer (130) is larger than the lattice constant of the channel layer (150).

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