Image sensing device

Abstract

An image sensing device includes: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in the first direction, each of the plurality of second conductive lines being disposed adjacent to each of the first conductive lines; a top test pad circuit including a first top test pad and a second top test pad; a bottom test pad circuit including a first bottom test pad and a second bottom test pad; a top switching circuit configured to connect a first terminal of each of the plurality of first conductive lines to the first top test pad and a first terminal of each of the plurality of second conductive lines to the second top test pad based on a first switching signal; and a bottom switching circuit configured to connect a second terminal of each of the plurality of first conductive lines to the first bottom test pad and a second terminal of each of the plurality of second conductive lines to the second bottom test pad based on a second switching signal.

Description

Technical Field

[0001] The technology and implementation method disclosed in this patent document generally relate to an image sensing device. Background Art

[0002] An image sensing device is a device that converts an optical image into an electrical signal. With the development of the automotive, medical, computer, and communication industries, the demand for highly integrated and higher-performance image sensing devices in various electronic devices such as digital cameras, video cameras, personal communication systems (PCS), video game consoles, surveillance cameras, medical micro-cameras, and robots has increased rapidly. Summary of the Invention

[0003] Various embodiments of the disclosed technology relate to an image sensing device that allows the location of a signal transmission line where column fixed pattern noise (CFPN) occurs and the location where the signal transmission line is short-circuited.

[0004] In an embodiment of the disclosed technology, an image sensing device may include: a plurality of first wires extending in a first direction; a plurality of second wires extending in the first direction, each of the plurality of second wires being disposed adjacent to each of the first wires; a top test pad circuit including a first top test pad and a second top test pad; a bottom test pad circuit including a first bottom test pad and a second bottom test pad; a top switch circuit configured to connect a first terminal of each of the plurality of first wires to the first top test pad and a first terminal of each of the plurality of second wires to the second top test pad based on a first switch signal; and a bottom switch circuit configured to connect a second terminal of each of the plurality of first wires to the first bottom test pad and a second terminal of each of the second wires to the second bottom test pad based on a second switch signal.

[0005] In another embodiment of the disclosed technology, an image sensing device may include: a plurality of first conductive lines configured to extend parallel to each other in a first direction; a plurality of second conductive lines positioned adjacent to the first conductive lines and configured to extend parallel to each other in the first direction; a top test pad circuit configured to include a first top test pad and a second top test pad; a bottom test pad circuit configured to include a first bottom test pad and a second bottom test pad; a plurality of first top switching elements, wherein first source terminals or first drain terminals of the plurality of first top switching elements are connected to first terminals of the first conductive lines in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of first top switching elements are commonly connected to the first top test pad; a plurality of second top switching elements, wherein first source terminals or first drain terminals of the plurality of second top switching elements are connected to first terminals of the second conductive lines in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of second top switching elements are commonly connected to the second top test pad; a plurality of first bottom switching elements, wherein first source terminals or first drain terminals of the plurality of first bottom switching elements are connected to second terminals of the first conductive lines in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of first bottom switching elements are commonly connected to the first bottom test pad; and a plurality of second bottom switching elements, wherein first source terminals or first drain terminals of the plurality of second bottom switching elements are connected to second terminals of the second conductive lines in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of second bottom switching elements are commonly connected to the second bottom test pad.

[0006] It will be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features and advantageous aspects of the disclosed technology will become readily apparent when considered in conjunction with the following detailed description with reference to the accompanying drawings.

[0008] Figure 1 is a plan view showing the structure of a pixel array in an image sensing device based on some implementations of the disclosed technology.

[0009] Figure 2 is a cross-sectional view showing an exemplary structure of a pixel array along the line X-X' shown in Figure 1 based on some implementations of the disclosed technology.

[0010] Figure 3 is a circuit diagram showing an exemplary structure of a unit pixel (PX) formed in the pixel array shown in Figure 1 based on some implementations of the disclosed technology.

[0011] Figure 4It is a schematic diagram showing an example structure of an image sensing device based on an embodiment of the disclosed technology.

[0012] Figure 5 It shows some implementations based on the disclosed technology Figure 4 A schematic diagram showing an example structure of a part of the top switch circuit shown.

[0013] Figure 6 It shows some implementations based on the disclosed technology Figure 4 A schematic diagram showing an example of a part of the bottom switch circuit shown.

[0014] Figure 7 It is a diagram showing how to locate a short - circuited wire among all wires and the position where the short - circuit occurs in the short - circuited wire when column fixed pattern noise (CFPN) occurs due to a short - circuit between a first wire and a second wire adjacent to each other.

[0015] Figure 8 It is a schematic diagram showing an example structure of an image sensing device based on another embodiment of the disclosed technology. Detailed implementation

[0016] This patent document provides implementations and examples of an image sensing device, which can be used to substantially solve one or more technical or engineering problems and alleviate limitations or drawbacks encountered in some other image sensing devices. The disclosed technology can be implemented in some embodiments to easily locate the "noisy" signal transmission lines where column fixed pattern noise (CFPN) occurs in an image sensing device and the position where the short - circuit occurs in the noisy signal transmission lines.

[0017] Now, specific embodiments will be referred to in detail, and examples thereof are shown in the drawings. As long as possible, the same reference numerals will be used throughout the drawings to represent the same or similar parts. In the following description, detailed descriptions of related known configurations or functions included herein will be omitted to avoid obscuring the subject matter.

[0018] Hereinafter, various embodiments will be described with reference to the drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0019] Figure 1 It is a plan view showing the structure of a pixel array in an image sensing device based on some implementations of the disclosed technology. Figure 2 It shows some implementations based on the disclosed technology along Figure 1 A cross - sectional view showing an example structure of the pixel array along the line X - X' shown.

[0020] Reference Figure 1 and Figure 2 ,the image sensing device may include a substrate layer 110 and an interconnect layer 120.

[0021] The substrate layer 110 may include a pixel array 10. The pixel array 10 may include a plurality of unit pixels (or image sensing pixels) (PX) arranged in rows and columns. Each unit pixel (PX) may include a photoelectric conversion element PD, a color filter CF, a microlens ML, and a pixel transistor PXT.

[0022] The photoelectric conversion element PD may be formed in the substrate SS and may generate and accumulate photo charges corresponding to incident light. For example, the photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof, but is not limited thereto.

[0023] The color filter CF and the microlens ML may be formed above the rear surface of the substrate SS. The pixel transistor PXT may be formed on the front surface opposite to the rear surface of the substrate SS. A grid structure GRD may be formed between the color filters CF and may prevent crosstalk between adjacent color filters.

[0024] The interconnect layer 120 may be formed below the front surface of the substrate SS. The interconnect layer 120 may include an interlayer insulating layer IL and a wire CL formed in the interlayer insulating layer IL. The wire CL may be electrically connected to the pixel transistor PXT.

[0025] Figure 3 is a circuit diagram showing an example structure of a unit pixel (PX) formed in the pixel array based on some implementations of the disclosed technology. Figure 1

[0026] Reference Figure 3 ,each unit pixel (PX) may include a photoelectric conversion element PD, a floating diffusion node FD, a transfer transistor T1, a reset transistor T2, a source follower transistor T3, and a selection transistor T4.

[0027] The transfer transistor T1 may transfer the photo charges accumulated in the photoelectric conversion element PD to the floating diffusion node FD based on a transfer signal TX. For example, the transfer transistor T1 may include an NMOS transistor that is connected to the floating diffusion node FD and the photoelectric conversion element PD and receives the transfer signal TX through its gate terminal.

[0028] The floating diffusion node FD may receive and accumulate the photo charges generated by the photoelectric conversion element PD. The source follower transistor T3 may be controlled based on the amount of photo charges accumulated in the floating diffusion node FD.

[0029] The reset transistor T2 can periodically reset the floating diffusion node FD. When the reset signal RX is enabled and the reset transistor T2 is turned on, the first pixel supply voltage (VDDPX) is transferred to the floating diffusion node FD. Thus, the optical charges accumulated in the floating diffusion node FD can be discharged, enabling the floating diffusion node FD to be reset. For example, the reset transistor T2 can include an NMOS transistor that is connected to the floating diffusion node FD and the pixel supply voltage (VDDPX) node and receives the reset signal RX through its gate terminal.

[0030] The source follower transistor T3 can be a source follower buffer amplifier or include a source follower buffer amplifier that generates a source-drain current proportional to the charge amount of the floating diffusion node FD. The source follower transistor T3 can amplify the potential change at the floating diffusion node FD, and the amplified signal can be output as a pixel signal (Vout) to the selection transistor T4. For example, the source follower transistor T3 can include an NMOS transistor that is connected to the floating diffusion node (FD) through its gate terminal and is connected to the pixel supply voltage (VDDPX) node and the selection transistor T4.

[0031] The selection transistor T4 can receive the pixel signal (Vout) from the source follower transistor T3 and output the pixel signal (Vout) to the output line (or column line) 12 based on the row selection signal SX. For example, the selection transistor T4 can include an NMOS transistor that is connected to the source follower transistor T3 and the output line 12 and receives the row selection signal SX through its gate terminal.

[0032] Figure 4 is a schematic diagram showing an example structure of an image sensing device based on an embodiment of the disclosed technology.

[0033] Referring to Figure 4 , the image sensing device can include a plurality of first wires 12, a plurality of second wires 14, a top switch circuit 20a, a bottom switch circuit 20b, a top test pad circuit 30a, and a bottom test pad circuit 30b.

[0034] The first wires 12 can be arranged to vertically overlap with the pixel array 10 including a plurality of unit pixels (PX) arranged in the pixel array 10, and can include a plurality of wires arranged in a first direction (e.g., column direction). For example, in Figure 2In the case of the backside illumination (BSI) type image sensing device shown, the first wire 12 may include metal wires that extend parallel to each other in the column direction of the pixel array 10 within an interconnection layer 120 provided below the front surface of a substrate layer 110 on which the pixel array 10 is formed. The pixel array 10 includes an array of image sensing pixels arranged in rows and columns, and each image sensing pixel includes an optical detector that converts light into a pixel signal, such that the pixel array 10 can capture image information carried by incident light received and detected by the image sensing pixels.

[0035] The first wire 12 may include, as Figure 3 shown, pixel signal output lines that transmit pixel signals (Vout) generated through the photoelectric conversion of incident light in unit pixels. For example, the first wire 12 may include wires that are commonly connected to selection transistors T4 of unit pixels (PX) located at the same column line within the pixel array 10 to transmit the pixel signals (Vout) generated by the unit pixels (PX) of the corresponding column line. In an embodiment of the disclosed technology, the case where the first wire 12 is a pixel signal output line will be described exemplarily.

[0036] The second wire 14 may be arranged to overlap the pixel array 10 in the vertical direction and may include multiple wires arranged adjacent to the first wire 12 in a first direction. For example, the second wire 14 may be respectively positioned adjacent to the first wire 12 in the same layer or at the same height as the first wire 12. The second wire 14 may include metal wires (power transmission lines) that supply a ground voltage (Vss).

[0037] Referring to Figure 4 , in an image sensing device based on an embodiment, two first wires 12 and three second wires 14 may be alternately arranged to form a wire group, and a wire for transmitting a power supply voltage (VDD) may be arranged between corresponding wire groups, but the disclosed technology is not limited thereto.

[0038] The top switch circuit 20a may selectively connect the first wire 12 and the second wire 14 to the top test pad circuit 30a according to a switch signal. For example, upon receiving the switch signal, the top switch circuit 20a may selectively connect one of the first wires 12 to the first top test pad 32a and may selectively connect one of the second wires 14 to the second top test pad 34a. In some implementations, the first wire connected to the first top test pad 32a and the second wire connected to the second top test pad 34a may be wires positioned adjacent to each other.

[0039] The top switch circuit 20a may include top switch elements (e.g., transistors) disposed between the top test pad circuit 30a and one end of the corresponding wire such that the top switch elements may be arranged in one-to-one correspondence with the first wire 12 and the second wire 14. Each top switch element may be electrically connected to one end of the corresponding wire. Additionally, each top switch element may be electrically connected to the first top test pad 32a or the second top test pad 34a. For example, all the top switch elements connected to the first wire 12 may be connected to the first top test pad 32a, and all the top switch elements connected to the second wire 14 may be connected to the second top test pad 34a.

[0040] The bottom switch circuit 20b may selectively connect the first wire 12 and the second wire 14 to the bottom test pad circuit 30b according to a switch signal. For example, upon receiving the switch signal, the bottom switch circuit 20b may selectively connect one of the first wires 12 to the first bottom test pad 32b and may selectively connect one of the second wires 14 to the second wire 14. In this case, the first wire connected to the first bottom test pad 32b and the second wire connected to the second bottom test pad 34b may refer to wires positioned adjacent to each other.

[0041] The first wire and the second wire connected to the bottom test pad circuit 30b through the bottom switch circuit 20b may be the same wires as the first wire and the second wire connected to the top test pad circuit 30a through the top switch circuit 20a. For example, one of the first wires 12 may be electrically connected to the first top test pad 32a through the top switch circuit 20a and may also be electrically connected to the first bottom test pad 32b through the bottom switch circuit 20b. Similarly, one of the second wires 14 may be electrically connected to the second top test pad 34a through the top switch circuit 20a and may be electrically connected to the second bottom test pad 34b through the bottom switch circuit 20b.

[0042] The bottom switch circuit 20b may include bottom switch elements (e.g., transistors) disposed between the bottom test pad circuit 30b and the other end of the corresponding wire such that the bottom switch elements are arranged in one-to-one correspondence with the first wire 12 and the second wire 14. Each bottom switch element may be electrically connected to the other end of the corresponding wire. Additionally, each bottom switch element may be electrically connected to the first bottom test pad 32b or the second bottom test pad 34b. For example, all the bottom switch elements connected to the first wire 12 may be connected to the first bottom test pad 32b, and all the bottom switch elements connected to the second wire 14 may be connected to the second bottom test pad 34b.

[0043] The top test pad circuit 30a may include a first top test pad 32a connected to the first wire 12 through the top switch circuit 20a and a second top test pad 34a connected to the second wire through the top switch circuit 20a. In the test mode, a high-level voltage may be applied to the first top test pad 32a, and a low-level voltage may be applied to the second top test pad 34a.

[0044] The bottom test pad circuit 30b may include a first bottom test pad 32b connected to the first wire 12 through the bottom switch circuit 20b and a second bottom test pad 34b connected to the second wire through the bottom switch circuit 20b. In the test mode, a high-level voltage may be applied to the first bottom test pad 32b, and a low-level voltage may be applied to the second bottom test pad 34b. In some implementations, the same voltage may be applied to the first top test pad 32a and the first bottom test pad 32b, and the same voltage may be applied to the second top test pad 34a and the second bottom test pad 34b.

[0045] Figure 5 is a schematic diagram showing an example of the detailed structure of a part of the top switch circuit based on some implementations of the disclosed technology Figure 4 shown. Figure 6 is a schematic diagram showing an example of a part of the bottom switch circuit based on some implementations of the disclosed technology Figure 4 shown.

[0046] Referring to Figure 5 , the top switch circuit 20a may include a first top switch circuit 22a and a second top switch circuit 24a.

[0047] The first top switch circuit 22a may include a plurality of first top switch elements (T11a, T12a), one terminal of which (e.g., "the first source extreme or the first drain extreme") is connected to the first top test pad 32a, and the other terminal (e.g., "the second source extreme or the second drain extreme") is connected to the corresponding first wire (12_1, 12_2). The first top switch elements (T11a, T12a) may receive output line switch signals (OLS1a, OLS2a) through their gate terminals respectively, and may be turned on or off based on the output line switch signals (OLS1a, OLS2a) respectively. For example, one of the first top switch elements (T11a, T12a) may be selectively turned on through the output line switch signals (GLS1a, GLS2a), and the other first top switch elements except the turned-on one may be turned off. The first top switch elements (T11a, T12a) may be turned on one by one in sequence. The first top switch elements (T11a, T12a) may include MOS transistors.

[0048] The second top switch circuit 24a may include a plurality of second top switch elements (T21a, T22a, T23a). In one example, one terminal of each of the plurality of second top switch elements (T21a, T22a, T23a) is connected to the second top test pad 34a, and the other terminal of each of the plurality of second top switch elements (T21a, T22a, T23a) is respectively connected to a corresponding second wire (14_1, 14_2, 14_3). The second top switch elements (T21a, T22a, T23a) may receive ground wire switch signals (GLS1a, GLS2a, GLS3a) respectively through their gate terminals, and may be turned on or off respectively based on the ground wire switch signals (GLS1a, GLS2a, GLS3a). For example, one of the second top switch elements (T21a, T22a, T23a) may be selectively turned on through the ground wire switch signals (GLS1a, GLS2a, GLS3a), and the other second top switch elements except the turned-on second top switch element may be turned off. The second top switch elements (T21a, T22a, T23a) may be turned on one by one in sequence. The second top switch elements (T21a, T22a, T23a) may include MOS transistors.

[0049] Referring to Figure 6 , the bottom switch circuit 20b may include a first bottom switch circuit 22b and a second bottom switch circuit 24b.

[0050] The first bottom switch circuit 22b may include a plurality of first bottom switch elements (T11b, T12b). In one example, one terminal of each of the plurality of first bottom switch elements (T11b, T12b) is connected to the first bottom test pad 32b, and the other terminal of each of the plurality of first bottom switch elements (T11b, T12b) is connected to its corresponding first wire (12_1 or 12_2). The first bottom switch elements (T11b, T12b) may receive output line switch signals (OLS1b, OLS2b) respectively through their gate terminals, and may be turned on or off respectively based on the output line switch signals (OLS1b, OLS2b). For example, one of the first bottom switch elements (T11b, T12b) may be selectively turned on through the output line switch signals (GLS1b, GLS2b), and the other first bottom switch elements except the turned-on first bottom switch element may be turned off. The first bottom switch elements (T11b, T12b) may be turned on one by one in the same order as the first top switch elements (T11a, T12a). The first bottom switch elements (T11b, T12b) may include MOS transistors.

[0051] The second bottom switch circuit 24b may include a plurality of second bottom switch elements (T21b, T22b, T23b). In one example, one terminal of each of the plurality of second bottom switch elements (T21b, T22b, T23b) is connected to the second bottom test pad 34b, and the other terminal of each of the plurality of second bottom switch elements (T21b, T22b, T23b) is connected to its corresponding second wire (14_1, 14_2, or 14_3). The second bottom switch elements (T21b, T22b, T23b) may receive ground wire switch signals (GLS1b, GLS2b, GLS3b) respectively through their gate terminals, and may be turned on or off respectively based on the ground wire switch signals (GLS1b, GLS2b, GLS3b). For example, one of the second bottom switch elements (T21b, T22b, T23b) may be selectively turned on through the ground wire switch signals (GLS1b, GLS2b, GLS3b), and the other second bottom switch elements except the turned-on second bottom switch element may be turned off. The second bottom switch elements (T21b, T22b, T23b) may be turned on one by one in the same order as the second top switch elements (T21a, T22a, T23a). The second bottom switch elements (T21b, T22b, T23b) may include MOS transistors.

[0052] The first top switch circuit 22a and the first bottom switch circuit 22b may connect one of the first wires (12_1, 12_2) to the first top test pad 32a and the first bottom test pad 32b based on the output line switch signals (OLS1a, OLS2a, OLS1b, OLS2b). For example, the output line switch signals (OLS1a, OLS1b) may be enabled simultaneously, and the first top switch element T11a and the first bottom switch element T11b may be turned on simultaneously, so that the first wire 12_1 may be connected to the first top test pad 32a and the first bottom test pad 32b.

[0053] In addition, the second top switch circuit 24a and the second bottom switch circuit 24b may connect one of the second wires (14_1, 14_2, 14_3) to both the second top test pad 34a and the second bottom test pad 34b based on the ground wire switch signals (GLS1a, GLS2a, GLS3a, GLS1b, GLS2b, GLS3b). For example, the ground wire switch signals (GLS1a, GLS1b) may be enabled simultaneously, and the second top switch element T21a and the second bottom switch element T21b may be turned on simultaneously, so that the second wire 14_1 adjacent to the first wire 12_1 may be connected to the second top test pad 34a and the second bottom test pad 34b.

[0054] The switching elements (T11a, T12a, T11b, T12b, T21a, T22a, T23a, T21b, T22b, T23b) of the top switching circuit 20a and the bottom switching circuit 20b are all formed to have the same size (e.g., the same channel resistance).

[0055] Figure 7 FIG. is a diagram showing the principle of finding a shorted wire among all wires and the position where a short occurs in the shorted wire when CFPN (column fixed pattern noise) occurs due to a short circuit between a first wire and a second wire adjacent to each other.

[0056] Refer to Figures 3 to 6 , during the test mode, a test device (not shown) can apply a preset high-level voltage to the first top test pad 32a and the first bottom test pad 32b, and can apply a preset low-level voltage to the second top test pad 34a and the second bottom test pad 34b.

[0057] When a voltage is applied to the test pads (32a, 32b, 34a, 34b), the test device can sequentially connect the first wire 12 to the first top test pad 32a and the first bottom test pad 32b, and sequentially connect the second wire 14 to the second top test pad 34a and the second bottom test pad 34b. In some implementations, the first wire connected to the first top test pad 32a and the first bottom test pad 32b and the second wire connected to the second top test pad 34a and the second bottom test pad 34b can be adjacent to each other.

[0058] For example, the test device can connect only the second wire 14_1 and the first wire 12_1 to the corresponding top test pad and the corresponding bottom test pad by using output line switch signals (OLS1a, OLS2a, OLS1b, OLS2b) and ground line switch signals (GLS1a, GLS2a, GLS3a, GLS1b, GLS2b, GLS3b). Subsequently, the test device can connect only the first wire 12_1 and the second wire 14_2 to the corresponding top test pad and the corresponding bottom test pad. In some implementations, since the second wires (14_1, 14_2) are positioned adjacent to both sides of the first wire 12_1, when the connection of the second wires (14_1, 14_2) is replaced, the test device can enable the first wire 12_1 to remain connected to the top test pad 32a and the bottom test pad 32b.

[0059] Subsequently, the test device can connect only the second wire 14_2 and the first wire 12_2 to the corresponding top test pad and the corresponding bottom test pad. Similarly, since the first wires (12_1, 12_2) are positioned adjacent to both sides of the second wire 14_2, when the connection of the first wires (12_1, 12_2) is replaced, the test device can enable the second wire 14_2 to remain connected to the top test pad 34a and the bottom test pad 34b.

[0060] The test device can connect both the first wire 12 and the second wire 14 to the corresponding top test pad and bottom test pad in the same manner as described above in sequence.

[0061] In the above process, as Figure 7 shown, if a short circuit occurs between the adjacent first wire 12_1 and the second wire 14_1, a current path through the corresponding short circuit path can be formed between each of the first top test pad 32a and the first bottom test pad 32b that receive a high-level voltage and each of the second top test pad 34a and the second bottom test pad 34b that receive a low-level voltage. For example, as Figure 7 shown, a current path (path1) can be formed between the first top test pad 32a and the second top test pad 34a through the short circuit path, and a current path (path2) can be formed between the first bottom test pad 32b and the second bottom test pad 34b.

[0062] The test device can determine whether a current path (path1) is formed between the top test pads 32a and 34a and whether a current path (path2) is formed between the bottom test pads 32b and 34b, and can determine whether a short circuit occurs between the wires while determining which wires are short-circuited. For example, when the current paths (path1, path2) are formed, the test device can determine that a short circuit has occurred between the first wire and the second wire connected to the test pads (32a, 34a, 32b, 34b).

[0063] In addition, the test device can determine the resistance value R1 of the current path (path1) by using the voltage difference between the first top test pad 32a and the second top test pad 34a and the current value flowing through the current path (path1), and can determine the resistance value R2 of the current path (path2) by using the voltage difference between the first bottom test pad 32b and the second bottom test pad 34b and the current value flowing through the current path (path2).

[0064] The test device can estimate the area where a short circuit has occurred in the corresponding wire based on the ratio of these resistance values (R1, R2) {R1 / (R1+R2), R2 / (R1+R2)}. For example, when the first wire 12 and the second wire 14 have the same material and the same line width (e.g., critical dimension CD), the resistance values (R1, R2) can be proportional to the distances of the corresponding current paths (path1, path2). As a result, the test device can use the ratio of the resistance values (R1, R2) {R1 / (R1+R2), R2 / (R1+R2)} to estimate which area is short-circuited.

[0065] In some implementations, the output lines of the image sensing device can be positioned adjacent to the ground lines. As Figure 7 shown, when a short circuit occurs between the output line and the ground line, CFPN (column fixed pattern noise) may occur. The position of the output line where CFPN occurs can also be confirmed through the light-emitting image obtained by the light-emitting test. However, since CFPN appears throughout the corresponding output line, it is difficult to locate the area where the short circuit occurs in the output line. However, in an embodiment, the position of the output line where CFPN occurs and the position where the short circuit occurs in the corresponding output line can be easily located.

[0066] Figure 8 is a schematic diagram showing an example structure of an image sensing device according to another embodiment based on the disclosed technology.

[0067] In Figure 8 the embodiment of, the same reference numerals are used for components that are the same as those of Figure 4 the components, so redundant descriptions thereof will be omitted herein. Hereinafter, the following embodiment of Figure 4 will be described focusing on the differences from the embodiment of Figure 7 to avoid redundant descriptions.

[0068] Referring to Figure 8 , the image sensing device can include a plurality of first wires 12, a plurality of second wires 14, a top switch circuit 20c, a bottom switch circuit 20d, a top test pad circuit 30a, and a bottom test pad circuit 30b.

[0069] In Figure 8 , one end of each first wire 12 can be commonly connected through a first top common line 42a, and the other end of each first wire 12 can be commonly connected through a first bottom common line 42b. Additionally, one end of each second wire 14 can be commonly connected through a second top common line 44a, and the other end of each second wire 14 can be commonly connected through a second bottom common line 44b.

[0070] The top switch circuit 20c can selectively connect the first top common line 42a and the second top common line 44a to the top test pad circuit 30a according to a switch signal. The top switch circuit 20c can include top switch elements (T31a, T32a).

[0071] The top switch element T31a can connect the first top common line 42a to the first top test pad 32a of the top test pad circuit 30a according to an output line switch signal (OLS1c). The top switch element T32a can connect the second top common line 44a to the second top test pad 34a of the top test pad circuit 30a according to a ground line switch signal (GLS1c). The switch signals (OLS1c, GLS1c) can be enabled only in the test mode.

[0072] The bottom switch circuit 20d can selectively connect the first bottom common line 42b and the second bottom common line 44b to the bottom test pad circuit 30b according to a switch signal. The bottom switch circuit 20d can include bottom switch elements (T31b, T32b).

[0073] The bottom switch element T31b can connect the first bottom common line 42b to the first bottom test pad 32b of the bottom test pad circuit 30b according to an output line switch signal (OLS1d). The bottom switch element T32b can connect the second bottom common line 44b to the second bottom test pad 34b of the bottom test pad circuit 30b according to a ground line switch signal (GLS1d). The switch signals (OLS1d, GLS1d) can be enabled only in the test mode. The switch signals (OLS1c, GLS1c, OLS1d, GLS1d) can be enabled simultaneously in the test mode.

[0074] In an embodiment, when a short-circuited wire between the wires 12 and 14 is confirmed through a separate test process, the image sensing device can be used to check where the short circuit occurs in the corresponding wire. For example, the short-circuited wire can be confirmed through a light-emitting image.

[0075] A test device (not shown) can apply a preset high-level voltage to the first top test pad 32a and the first bottom test pad 32b, and can apply a preset low-level voltage to the second top test pad 34a and the second bottom test pad 34b. Additionally, the test device (not shown) can enable all the switch signals (OLS1c, GLS1c, OLS1d, GLS1d) so that the common lines (42a, 42b, 44a, 44b) can be connected to the corresponding test pads (32a, 32b, 34a, 34b).

[0076] In some implementations, when a short circuit occurs between a first wire and a second wire adjacent to each other, a current path can be formed between the top test pads (32a, 34a) through the corresponding short circuit path, and a current path can be formed between the bottom test pads (32b, 34b) through the corresponding short circuit path.

[0077] The test device can use both the voltage difference between the first top test pad 32a and the second top test pad 34a and the current value of the corresponding current path to determine the resistance value R1, and can use both the voltage difference between the first bottom test pad 32b and the second bottom test pad 34b and the current value of the corresponding current path to determine the resistance value R2.

[0078] The test device can estimate the point where a short circuit occurs in the previously identified wire based on the ratio of these resistance values (R1, R2) {R1 / (R1 + R2), R2 / (R1 + R2)}.

[0079] It is obvious from the above description that an image sensing device based on some implementations of the disclosed technology can easily locate the transmission line where column fixed pattern noise (CFPN) occurs and the location where a short circuit occurs in the transmission line.

[0080] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly identified through the above patent documents.

[0081] Although multiple exemplary embodiments have been described, it should be understood that various modifications or enhancements of the disclosed embodiments and other embodiments can be conceived based on what is described and / or illustrated in this patent document.

[0082] Cross - reference to related applications

[0083] This patent document claims the priority and benefits of Korean Patent Application No. 10 - 2023 - 0184458, filed on December 18, 2023, the entire disclosure of which is incorporated herein by reference as part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines, the plurality of second conductive lines extending in the first direction, each of the plurality of second conductive lines being disposed adjacent to each of the first conductive lines; a top test pad circuit, the top test pad circuit comprising a first top test pad and a second top test pad; a bottom test pad circuit, the bottom test pad circuit comprising a first bottom test pad and a second bottom test pad; a top switch circuit that connects a first terminal of each of the plurality of first conductive lines to the first top test pad and connects a first terminal of each of the plurality of second conductive lines to the second top test pad based on a first switch signal; as well as A bottom switch circuit connects a second terminal of each of the plurality of first conductive lines to the first bottom test pad and connects a second terminal of each of the plurality of second conductive lines to the second bottom test pad based on a second switch signal.

2. The image sensing device according to claim 1, wherein: The top switch circuit: Based on the first switch signal, one of the plurality of first conductive lines is connected to the first top test pad and one of the plurality of second conductive lines is connected to the second top test pad.

3. The image sensing device according to claim 2, wherein: The top switch circuit comprises: a plurality of first top switch elements, wherein first terminals of the plurality of first top switch elements are connected to the plurality of first conductive lines in a one-to-one correspondence, and second terminals of the plurality of first top switch elements are commonly connected to the first top test pad; and A plurality of second top switch elements, wherein first terminals of the plurality of second top switch elements are connected to the plurality of second conductive lines in a one-to-one correspondence, and second terminals of the plurality of second top switch elements are commonly connected to the second top test pad.

4. The image sensing device according to claim 2, wherein: The bottom switch circuit: Based on the second switch signal, one of the plurality of first conductive lines is connected to the first bottom test pad and one of the plurality of second conductive lines is connected to the second bottom test pad.

5. The image sensing device according to claim 4, wherein: The bottom switch circuit: Based on the second switch signal, a first wire connected to the first top test pad among the plurality of first wires is connected to the first bottom test pad, and a second wire connected to the second top test pad among the plurality of second wires is connected to the second bottom test pad.

6. The image sensing device according to claim 4, wherein: The bottom switch circuit comprises: a plurality of first bottom switch elements, wherein first terminals of the plurality of first bottom switch elements are connected to the plurality of first conductive lines in a one-to-one correspondence, and second terminals of the plurality of first bottom switch elements are commonly connected to the first bottom test pad; and A plurality of second bottom switch elements, first terminals of the plurality of second bottom switch elements are connected to the plurality of second conductive lines in a one-to-one correspondence, and second terminals of the plurality of second bottom switch elements are commonly connected to the second bottom test pad.

7. The image sensing device according to claim 1, wherein: The top switch circuit: Based on the first switch signal, all of the plurality of first conductive lines are connected to the first top test pad, and all of the plurality of second conductive lines are connected to the second top test pad.

8. The image sensing device according to claim 7, further comprising: a first top common line commonly connected to the first terminals of all the plurality of first conductive lines; as well as A second top common line is commonly connected to the first terminals of all the second conductive lines.

9. The image sensing device according to claim 8, wherein: The top switch circuit comprises: a first top switching element, a first terminal of the first top switching element being connected to the first top common line, and a second terminal of the first top switching element being connected to the first top test pad; and A second top switching element, a first terminal of the second top switching element is connected to the second top common line, and a second terminal of the second top switching element is connected to the second top test pad.

10. The image sensing device according to claim 7, wherein: The bottom switch circuit: Based on the second switch signal, all of the plurality of second conductive lines are connected to the first bottom test pad, and all of the plurality of second conductive lines are connected to the second bottom test pad.

11. The image sensing device according to claim 10, further comprising: a first bottom common line commonly connected to the second terminals of all the plurality of first conductive lines; as well as A second bottom common line is commonly connected to the second terminals of all the second conductive lines.

12. The image sensing device according to claim 11, wherein: The bottom switch circuit comprises: a first bottom switching element, a first terminal of the first bottom switching element being connected to the first bottom common line, and a second terminal of the first bottom switching element being connected to the first bottom test pad; and A second bottom switching element, a first terminal of the second bottom switching element is connected to the second bottom common line, and a second terminal of the second bottom switching element is connected to the second bottom test pad.

13. The image sensing device according to claim 1, wherein: The plurality of first conductive lines and the plurality of second conductive lines include conductive lines disposed to vertically overlap the pixel array including unit pixels arranged in the pixel array.

14. The image sensing device according to claim 13, wherein: The plurality of first conductive lines and the plurality of second conductive lines extend parallel to each other in the first direction within the same metal layer.

15. The image sensing device according to claim 1, wherein: The plurality of first conductive lines include: A signal output line is formed to transmit a pixel signal generated by a unit pixel through photoelectric conversion of incident light.

16. The image sensing device according to claim 1, wherein: The plurality of second conductive lines include: A power transmission line is formed to supply a power supply voltage.

17. An image sensing device, comprising: a plurality of first conductive lines extending parallel to each other in a first direction; a plurality of second conductive lines, the plurality of second conductive lines being positioned adjacent to the first conductive line and extending parallel to each other in the first direction; a top test pad circuit, the top test pad circuit comprising a first top test pad and a second top test pad; a bottom test pad circuit, the bottom test pad circuit comprising a first bottom test pad and a second bottom test pad; a plurality of first top switch elements, wherein first source terminals or first drain terminals of the plurality of first top switch elements are connected to the first terminal of the first wire in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of first top switch elements are commonly connected to the first top test pad; a plurality of second top switch elements, wherein first source terminals or first drain terminals of the plurality of second top switch elements are connected to the first terminal of the second wire in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of second top switch elements are commonly connected to the second top test pad; a plurality of first bottom switch elements, wherein first source terminals or first drain terminals of the plurality of first bottom switch elements are connected to the second terminal of the first wire in a one-to-one correspondence, and second source terminals or second drain terminals of the plurality of first bottom switch elements are commonly connected to the first bottom test pad; as well as A plurality of second bottom switch elements, wherein the first source terminals or the first drain terminals of the plurality of second bottom switch elements are connected one-to-one with the second terminal of the second wire, and the second source terminals or the second drain terminals of the plurality of second bottom switch elements are commonly connected to the second bottom test pad.

18. The image sensing device according to claim 17, wherein: The plurality of first conductive lines include: A signal output line is formed to transmit a pixel signal generated by a unit pixel through photoelectric conversion of incident light.

19. The image sensing device according to claim 17, wherein: The plurality of second conductive lines include: A power transmission line is formed to supply a power supply voltage.

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