Regional selective deposition preparation method of lead sulfide infrared focal plane detector

Abstract

The invention discloses a lead sulfide infrared focal plane detector regioselective deposition preparation method. The method comprises the following steps: S1, depositing a modification layer on a substrate; s2, preparing a lead sulfide film on the modification layer; s3, preparing a cadmium selenide thin film on the lead sulfide thin film; s4, preparing an electron transport layer on the cadmium selenide thin film; s5, filling the modification layer with an insulating substance layer; and S6, preparing a top electrode layer on the electron transport layer. According to the embodiment of the invention, the modification layer is deposited on the substrate, so that the lead sulfide film can obtain a patterned structure without an etching process, the integration process is simplified, the pattern resolution and edge alignment are improved, and the damage of the etching process to the performance of the device is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor optoelectronic devices, and particularly relates to a method for preparing a lead sulfide infrared focal plane detector by region-selective deposition. Background Art

[0002] One of the key steps in the preparation of infrared focal plane detectors is the patterning of infrared-sensitive materials. There are many patterning techniques, including ultraviolet lithography, anisotropic etching, laser direct writing, electron beam lithography, nanoimprinting, inkjet printing, screen printing, and so on. These techniques have their own advantages and disadvantages in terms of accuracy, speed, yield, compatibility, reliability, flexibility, etc. Correspondingly, according to their characteristics, these techniques are applied to different scenarios in industrial production.

[0003] In the field of microelectronics technology, the current mainstream patterning process is as follows: First, metal, semiconductor thin films, and dielectric materials are uniformly deposited on the substrate surface by physical vapor deposition; then, the transfer of the pattern is achieved through a photolithography exposure process; finally, the regions that do not require the target material are removed by etching. However, with the continuous reduction of the critical dimensions of chips and the diversification of chip functions, the disadvantages of the multiple etching process have gradually emerged. For example, as the number of 3D NAND stacking layers increases to 512 layers, the etching process has become one of the most difficult processes. In addition, the etching process will also cause damage to the material, and further treatment is required for repair. Compared with physical vapor deposition, the preparation of semiconductor thin films by liquid-phase chemical deposition is a balanced steady-state growth process, and the process of thin film deposition has a certain selectivity for the substrate. When preparing a lead sulfide detector, by modifying the substrate, the deposition of the lead sulfide thin film can be made selective. Finally, while preparing the lead sulfide infrared focal plane, its patterning is achieved, that is to say, the patterning is determined by the substrate. This solution does not require an active layer etching process, simplifying the difficulty of the integration process. Summary of the Invention

[0004] The technical problem to be solved by the present invention is that, in order to solve various deficiencies existing in the preparation of existing infrared focal plane detectors, the present invention provides a method for preparing a lead sulfide infrared focal plane detector by region-selective deposition.

[0005] In order to solve the above technical problem, an embodiment of the present invention provides a method for preparing a lead sulfide infrared focal plane detector by region-selective deposition, including the following steps:

[0006] S1: Deposit a modification layer on the substrate;

[0007] S2: Prepare a lead sulfide thin film on the modification layer;

[0008] S3: Prepare a cadmium selenide thin film on the lead sulfide thin film;

[0009] S4: Prepare an electron transport layer on the cadmium selenide thin film;

[0010] S5: Fill an insulating material layer on the modification layer;

[0011] S6: Prepare a top electrode layer on the electron transport layer;

[0012] Among them, the step S1 is specifically: By thermal evaporation, deposit a first modification material identical to the pattern of the first mask on the substrate; then deposit a second modification material identical to the pattern of the second mask by magnetron sputtering or spin coating; the pattern of the first mask is complementary to the pattern of the second mask, so that the first modification material and the second modification material are staggered and distributed on the substrate; the lead sulfide thin film is formed on the first modification material; the surface tension of the second modification material is less than 49 dyn·cm -1 .

[0013] Preferably, the first modification material includes one or more combinations of Al, Ag, and Au; the second modification material includes one or more combinations of nickel oxide, 2-(9H-carbazol-9-yl)ethylphosphonic acid (SAM), polymethyl methacrylate, and polydimethylsilane.

[0014] Preferably, the step S2 is specifically: Mix sodium hydroxide solution and lead nitrate solution in equal proportions to obtain a precursor solution, and then mix it with thiourea solution to form a mixed solution; place the hole transport layer in step S2 in the mixed solution, and keep it in an incubator at 20°C to 30°C for 2 h to 4 h to obtain a lead sulfide thin film.

[0015] Preferably, the concentration of the sodium hydroxide solution is 0.01 g / mL to 0.02 g / mL; the concentration of the lead nitrate solution is 0.02 g / mL to 0.03 g / mL; the concentration of the thiourea solution is 0.01 g / mL to 0.02 g / mL; the content ratio of the precursor solution to the thiourea solution is 150:1 to 300:1.

[0016] Preferably, the step S3 is specifically: Mix a 2 mg / mL cadmium chloride solution and a 1 mg / mL selenourea solution in equal proportions to obtain a second mixed solution; adjust the pH of the second mixed solution to 7 - 8 with dilute nitric acid and ammonia water, place the lead sulfide thin film in an incubator at 20°C to 30°C, and take it out after 0.5 h to 2 h to obtain a cadmium selenide thin film.

[0017] Preferably, the step S3 is specifically: Use the pattern of the first mask to spin-coat a cadmium selenide quantum dot solution on the lead sulfide thin film to form a cadmium selenide thin film.

[0018] Preferably, step S5 is specifically as follows: Using a second mask pattern, deposit an insulating material on the second modifying material to form an insulating material layer; wherein, the insulating material layer is flush with the electron transport layer.

[0019] Preferably, step S4 is specifically as follows: Deposit an electron transport layer on the cadmium selenide thin film by magnetron sputtering or solution spin coating;

[0020] The electron transport layer includes: one or more combinations of SnO2, TiO2, ZnO, PC 61 BM.

[0021] Preferably, step S6 is specifically as follows: Using a first mask pattern, prepare an ITO top electrode by magnetron sputtering or a metal top electrode by thermal evaporation; the metal top electrode includes one or more of Al, Ag, and Au.

[0022] The present invention also provides a lead sulfide infrared focal plane detector, and the lead sulfide infrared focal plane detector is prepared by the above-mentioned lead sulfide infrared focal plane detector area-selective deposition preparation method.

[0023] Implementing the embodiments of the present invention has the following beneficial effects:

[0024] (1) In the embodiments of the present invention, a first mask pattern and a second mask pattern are used to deposit a first modifying material and a second modifying material, so that the substrate is divided by the first modifying material and the second modifying material. Then, by using a material with a surface tension less than 49 dyn·cm -1 as the second modifying material, lead sulfide is only generated on the first modifying material, so that a patterned lead sulfide thin film can be prepared without an etching process. Finally, the integration process is simplified, the pattern resolution and edge alignment are increased, the damage to the device performance caused by the etching process is avoided, and a more efficient production of lead sulfide infrared focal plane detectors is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 It is a flowchart of a method for preparing a lead sulfide infrared focal plane detector by area-selective deposition according to an embodiment of the present invention;

[0027] Figure 2Process flow chart of step S1 of a method for preparing a lead sulfide infrared focal plane detector by area-selective deposition provided by an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of the pattern structure of the first mask provided by an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the pattern structure of the second mask provided by an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the pattern structure of the third mask provided by an embodiment of the present invention;

[0031] Figure 6 Process flow chart of a method for preparing a lead sulfide infrared focal plane detector by area-selective deposition provided by an embodiment of the present invention. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0033] See Figure 1 , an embodiment of the present invention also provides a method for preparing a lead sulfide infrared focal plane detector by area-selective deposition. The method for preparing a lead sulfide infrared focal plane detector by area-selective deposition includes the following steps:

[0034] S1: Deposit a modification layer on a substrate;

[0035] S2: Prepare a lead sulfide thin film on the modification layer;

[0036] S3: Prepare a cadmium selenide thin film on the lead sulfide thin film;

[0037] S4: Prepare an electron transport layer on the cadmium selenide thin film;

[0038] S5: Fill an insulating material layer on the modification layer;

[0039] S6: Prepare a top electrode layer on the electron transport layer;

[0040] The step S1 is specifically as follows: depositing a first modifying material having the same pattern as the first mask on the substrate by thermal evaporation. Then depositing a second modifying material having the same pattern as the second mask on the substrate by magnetron sputtering or spin coating. The first mask pattern is complementary to the second mask pattern, so that the first modifying material and the second modifying material are alternately distributed on the substrate. The lead sulfide film is formed on the first modifying material. The surface tension of the second modifying material is less than 49 dyn·cm -1 , so that lead sulfide cannot nucleate and grow on its surface. Wherein, the first modifying material includes one or more combinations of Al, Ag, and Au. The second modifying material includes one or more combinations of nickel oxide, 2-(9H-carbazole-9-yl)ethylphosphonic acid, polymethyl methacrylate, and polydimethylsilane. The thickness of the second modifying material is arbitrary.

[0041] Before performing step S1, the substrate needs to be cleaned. The cleaning is specifically: using deionized water, ethanol, and isopropanol solvents to clean the substrate in sequence. The substrate includes but is not limited to rigid and flexible substrates such as silicon / quartz / glass / sapphire / calcium fluoride / PEI / PEN / PI / PC and readout circuit substrates.

[0042] The step S2 specifically comprises: mixing sodium hydroxide solution and lead nitrate solution in equal proportions to obtain a precursor solution, and then mixing with thiourea solution to form a mixed solution; placing the hole transport layer in the step S2 in the mixed solution, and keeping it in a constant temperature box at 20°C to 30°C for 2h to 4h to obtain a lead sulfide film. The concentration of the sodium hydroxide solution is 0.01g / mL to 0.02g / mL; the concentration of the lead nitrate solution is 0.02g / mL to 0.03g / mL; the concentration of the thiourea solution is 0.01g / mL to 0.02g / mL; and the content ratio of the precursor solution to the thiourea solution is 150:1 to 300:1.

[0043] The step S2 uses a liquid phase chemical deposition method to prepare a lead sulfide thin film, and the lead sulfide thin film can be selectively grown on different substrates or substrate modification materials. The device structures used include lead sulfide homogeneous pn junctions, PbS / CdSe, PbS / CdS and other heterogeneous pn junctions.

[0044] The step S3 is specifically as follows: 2 mg / mL cadmium chloride solution and 1 mg / mL selenourea solution are mixed in equal proportions to obtain a second mixed solution. The pH of the second mixed solution is adjusted to 7-8 using dilute nitric acid and ammonia water, and the lead sulfide film is placed in a constant temperature box at 20° C. to 30° C. and taken out after 0.5 h to 2 h to obtain a cadmium selenide film.

[0045] The step S3 may also be: using a first mask pattern, spin-coating a cadmium selenide quantum dot solution on the lead sulfide thin film to form a cadmium selenide thin film.

[0046] The cadmium selenide thin film can also be prepared by methods such as electrochemistry, thermal evaporation, molecular beam epitaxy, chemical vapor deposition, etc., and the thickness can be arbitrary.

[0047] The step S4 is specifically: depositing an electron transport layer on the cadmium selenide thin film by magnetron sputtering or solution spin-coating. Among them, the electron transport layer includes: one or more combinations of SnO2, TiO2, ZnO, PC 61 BM.

[0048] The step S5 is specifically: using a second mask pattern, depositing an insulating substance on the second modification material to form an insulating substance layer. Among them, the insulating substance layer is flush with the electron transport layer. The insulating substance is an insulating material such as SiNx.

[0049] The step S6 is specifically: using a first mask pattern, preparing an ITO top electrode by magnetron sputtering or preparing a metal top electrode by thermal evaporation. The metal top electrode includes one or more of Al, Ag, and Au.

[0050] The first mask pattern and the second mask pattern can be selected according to the actual situation. When the substrate is a common substrate such as a rigid and flexible substrate like silicon / quartz / glass / sapphire / calcium fluoride / PEI / PEN / PI / PC, the first mask pattern does not include the common electrode pin area, and only the pixel area and the blocking area exist. The pixel area is a hollow area for placing the first modification material, etc. The second mask pattern is complementary to the first mask pattern, and the hollow part is complementary to the hollow area of the first mask pattern. When the substrate is a readout circuit substrate, the first mask pattern in steps S1 - S5 is the same as that of the common substrate. The first mask pattern of step S6 includes a pixel area, a blocking area, and a common electrode pin area. The common electrode pin area is also a hollow area. Thus, materials such as lead sulfide in steps S2 - S5 are prevented from contaminating the common electrode pins. The common electrode pin area is used as the common electrode pin of the lead sulfide infrared focal plane detector formed by the readout circuit substrate, and finally a patterned lead sulfide detector focal plane array is obtained.

[0051] See Figure 2 and the specific process flow of step S1 is:

[0052] (1) Clean the substrate successively with deionized water, ethanol, and isopropanol solvents.

[0053] (2) Deposit a layer of the first modification material on the clean substrate;

[0054] (3) Spin-coat a layer of photoresist on the first modification material;

[0055] (4) Use the first mask pattern for exposure, development, and etching to finally obtain the first modification material identical to the first mask pattern. The first modification material is preferably an Au electrode array.

[0056] (5) Use the second mask pattern complementary to the first mask pattern to prepare a patterned layer of the second modification material with any thickness by magnetron sputtering or spin-coating. The preparation process is the same as that of the first modification material, just replace the first mask pattern with the second mask pattern. The second modification material is preferably NiO, and lead sulfide cannot nucleate and grow on its surface.

[0057] In step S1, the first modification material and the second modification material are deposited by using the first mask pattern and the second mask pattern, so that the substrate is covered with the first modification material and the second modification material. Since the lead sulfide thin film cannot grow on the NiO layer, the lead sulfide only grows and forms on the Au electrode array. For the lead sulfide detector focal plane array to be used, the lead sulfide must be patterned. Directly etching the lead sulfide thin film not only has a complex process, but also has low pattern resolution and edge alignment. Therefore, by using step S1 to generate the lead sulfide infrared focal plane detector, not only can a patterned lead sulfide thin film be prepared without etching the lead sulfide thin film, but also the integration process is simplified, the pattern resolution and edge alignment are increased, and the damage to the device performance caused by the etching process is avoided. More efficient production of the lead sulfide infrared focal plane detector is achieved.

[0058] See Figures 3-6 , the specific process flow of the method for region-selective deposition preparation of the lead sulfide infrared focal plane detector is as follows:

[0059] Step 1: Clean the substrate successively with deionized water, ethanol, and isopropyl alcohol solvents. First, use the first mask pattern and deposit an Au electrode array identical to the first mask pattern on the clean substrate by electron beam thermal evaporation. Secondly, use the second mask pattern complementary to the first mask pattern to prepare a patterned NiO layer with any thickness by magnetron sputtering or spin-coating. The NiO layer is the substrate modification material, and lead sulfide cannot nucleate and grow on its surface.

[0060] Step 2: Prepare a sodium hydroxide solution with a concentration of 0.012 g / mL and a lead nitrate solution with a concentration of 0.025 g / mL using deionized water, mix the two in equal proportions, and take 20 mL. Prepare a thiourea solution with a concentration of 0.114 g / mL using deionized water and take 0.1 mL. Mix the above two solutions and place the patterned substrate obtained in step 1. Place it in a constant temperature oven at 25 °C, take it out after 3 h, and obtain a lead sulfide thin film.

[0061] Step 3: Prepare a cadmium chloride solution with a concentration of 2 mg / mL and a selenourea solution with a concentration of 1 mg / mL using deionized water. Mix the two in equal proportions and take 10 mL. Adjust the pH to 7.8 using dilute nitric acid and ammonia, and place the lead sulfide thin film obtained in Step 2. Place it in a constant temperature oven at 25 °C, take it out after 1 h to obtain a cadmium selenide thin film. Among them, the cadmium selenide thin film is also prepared by a liquid-phase chemical deposition method, and the cadmium selenide thin film cannot grow on the NiO layer either. Therefore, the formation of the cadmium selenide thin film also has the characteristics of area-selective deposition. Therefore, there is no need to use a mask pattern.

[0062] Step 4: Use the first mask pattern to deposit an electron transport layer material such as SnO2, TiO2, ZnO, or PC61BM on the thin film obtained in Step 4 by magnetron sputtering or solution spin coating.

[0063] Step 5: If the thickness of the NiO deposited in Step 1 is different from the device thickness, the thickness needs to be filled. At this time, a second mask pattern is required to fill the insulating material such as SiNx on the original NiO.

[0064] Step 6: Use the first mask pattern to prepare an ITO top electrode by magnetron sputtering or an Al, Ag, Au top electrode by thermal evaporation. Among them, when the substrate used is a readout circuit substrate, a third mask pattern is used. The third mask pattern has a pixel area and a common electrode pin area; the pixel area and the common electrode pin area are hollow areas.

[0065] The present invention also provides a lead sulfide infrared focal plane detector, which is prepared by the above-mentioned area-selective deposition preparation method of the lead sulfide infrared focal plane detector. The lead sulfide infrared focal plane detector uses the N-type layer of cadmium selenide and the P-type layer of PbS to construct a heterojunction p-n junction, enabling the monolithic integrated lead sulfide detector to significantly reduce the dark current of the device body, improve the signal-to-noise ratio, and have a time constant of less than 1 microsecond, allowing high frame rate operation and realizing the tracking of rapid changes of objects.

[0066] The above-disclosed is only a preferred embodiment of the present invention. Of course, it cannot be used to limit the scope of the rights of the present invention. Those of ordinary skill in the art can understand the entire or part of the processes of the above embodiments, and the equivalent changes made according to the claims of the present invention still fall within the scope covered by the invention.

Claims

1. A method for preparing a lead sulfide infrared focal plane detector by regional selective deposition, characterized in that: The following steps are involved: S1: depositing a modification layer on a substrate; S2: preparing a lead sulfide film on the modified layer; S3: Preparation of cadmium selenide film on lead sulfide film; S4: preparing an electron transport layer on the cadmium selenide film; S5: filling an insulating material layer on the modified layer; S6: preparing a top electrode layer on the electron transport layer; The step S1 specifically comprises: depositing a first modifying material having the same pattern as the first mask on the substrate by thermal evaporation; depositing a second modifying material having the same pattern as the second mask by magnetron sputtering or spin coating; the first mask pattern and the second mask pattern are complementary, so that the first modifying material and the second modifying material are alternately distributed on the substrate; the lead sulfide film is formed on the first modifying material; the surface tension of the second modifying material is less than 49 dyn·cm -1 .

2. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The first modifying material includes one or more combinations of Al, Ag, and Au; the second modifying material includes one or more combinations of nickel oxide, 2-(9H-carbazole-9-yl)ethylphosphonic acid, polymethyl methacrylate, and polydimethylsilane.

3. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The step S2 specifically comprises: mixing sodium hydroxide solution and lead nitrate solution in equal proportions to obtain a precursor solution, and then mixing it with thiourea solution to form a mixed solution; placing the hole transport layer in the step S2 in the mixed solution, and keeping it warm in a constant temperature box at 20° C. to 30° C. for 2 h to 4 h to obtain a lead sulfide film.

4. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 3, characterized in that: The concentration of the sodium hydroxide solution is 0.01 g / mL to 0.02 g / mL; the concentration of the lead nitrate solution is 0.02 g / mL to 0.03 g / mL; the concentration of the thiourea solution is 0.01 g / mL to 0.02 g / mL; and the content ratio of the precursor solution to the thiourea solution is 150:1 to 300:

1.

5. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The step S3 is specifically as follows: 2 mg / mL cadmium chloride solution and 1 mg / mL selenourea solution are mixed in equal proportions to obtain a second mixed solution; the pH value of the second mixed solution is adjusted to 7-8 using dilute nitric acid and ammonia water, and the lead sulfide film is placed in a constant temperature box at 20° C. to 30° C., and taken out after 0.5 h to 2 h to obtain a cadmium selenide film.

6. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The step S3 specifically comprises: using a first mask pattern to spin-coat a cadmium selenide quantum dot solution on the lead sulfide film to form a cadmium selenide film.

7. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The step S5 specifically includes: using a second mask pattern to deposit an insulating material on the second modifying material to form an insulating material layer; wherein the insulating material layer is flush with the electron transport layer.

8. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The step S4 specifically comprises: depositing an electron transport layer on the cadmium selenide film by magnetron sputtering or solution spin coating; The electron transport layer includes: SnO2, TiO2, ZnO, PC 61 One or more combinations of BM.

9. The method for preparing the lead sulfide infrared focal plane detector by regional selective deposition according to claim 1, characterized in that: The step S6 specifically includes: using the first mask pattern to prepare an ITO top electrode by magnetron sputtering or a metal top electrode by thermal evaporation; the metal top electrode includes one or more of Al, Ag, and Au.

10. A lead sulfide infrared focal plane detector, characterized in that: The lead sulfide infrared focal plane detector is prepared by using any one of the lead sulfide infrared focal plane detector regional selective deposition preparation methods described in claims 1-9.

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