Preparation method of TBC battery and TBC battery

Abstract

The embodiment of the invention discloses a preparation method of a TBC battery and the TBC battery. The preparation method comprises the following steps: firstly, providing a TBC battery process sheet; wherein the TBC battery process piece comprises an N-type silicon substrate, a first area and a second area, the first area and the second area are alternately arranged in an interdigital mode, then first metal slurry is adopted, a first main grid line is formed in the first area, a second main grid line is formed in the second area, and finally second metal slurry is adopted, and carrying out silk-screen printing and sintering treatment in the preset fine grid line preparation sub-region corresponding to the first region by adopting a first metal paste to form a first fine grid line, and carrying out silk-screen printing and sintering treatment in the preset fine grid line preparation sub-region corresponding to the second region by adopting a third metal paste to form a second fine grid line to prepare the TBC battery, wherein the silver content in the third metal paste is smaller than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is smaller than the silver content in the first metal paste.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of solar cells, and in particular, to a preparation method of a TBC cell and a TBC cell. Background Art

[0002] A TBC cell is a tunnel oxide passivated contact back contact structure crystalline silicon solar cell, which is a structure of TOPCon (Tunnel Oxide Passivated Contact) superimposed with BC (Back Contact) technology. A P region and an N region with good quality and arranged in a finger-like and spaced manner are formed on the back of the cell. The characteristics of the TBC cell are that both the PN junction and the metal contact are on the back of the cell, and there is no influence of any metal grid line occlusion on the front surface (i.e., the light-receiving surface). Therefore, it has a higher short-circuit current. At the same time, a relatively wide metal grid line can be allowed on the back to reduce the series resistance and thus increase the fill factor. Coupled with the open-circuit voltage gain brought by the front surface field of the cell and the good passivation effect, the photoelectric conversion efficiency of this cell without front surface occlusion is high.

[0003] Currently, N-type silicon wafers are used as raw materials for TBC cells. In the conventional process flow, the TOPcon structure is retained in the N+ region, and in the P region, the laser grooving method is used to retain the doping of the original N-type silicon wafer, without subsequent doping effects in the process flow, and silver-aluminum paste is printed in the P region to form an electrode structure. However, aluminum elements in the silver-aluminum paste are likely to form aluminum spines when the N-type silicon wafer cools from high temperature, damaging the PN junction on the N-type silicon wafer and forming a metal composite region, which easily affects the open-circuit voltage value and photoelectric conversion efficiency of the TBC cell. In addition, the single-piece wet weight of the paste in the single P region is 42 mg, and the unit price of the silver-aluminum paste is 8,500 yuan / kg. Then the cost of the paste in the single P region is approximately 0.357 yuan per piece, which accounts for a relatively large proportion in the overall cost of the TBC cell, seriously affecting the economic benefits of manufacturers. Summary of the Invention

[0004] Embodiments of the present invention provide a preparation method of a TBC cell and a TBC cell, which can effectively reduce the silver content required for preparing the electrode structure of the TBC cell, achieve cost reduction and efficiency improvement, and increase the open-circuit voltage value and photoelectric conversion efficiency of the TBC cell.

[0005] In a first aspect, embodiments of the present invention provide a preparation method of a TBC cell, including:

[0006] Provide a TBC cell process wafer; wherein, the TBC cell process wafer includes an N-type silicon substrate, a first region and a second region, the first region and the second region are arranged alternately in a finger-like manner on the same side surface of the N-type silicon substrate, the first region includes a first tunneling oxide layer, a phosphorus diffusion doping layer and a first passivation film layer sequentially stacked on the surface of the N-type silicon substrate, and the second region includes a second tunneling oxide layer, a boron diffusion doping layer and a second passivation film layer sequentially stacked on the surface of the N-type silicon substrate;

[0007] Use a first metal paste to perform screen printing and sintering treatment in a preset main grid line preparation sub-region corresponding to the first region to form a first main grid line, and perform screen printing and sintering treatment in a preset main grid line preparation sub-region corresponding to the second region to form a second main grid line;

[0008] Use a second metal paste to perform screen printing and sintering treatment in a preset fine grid line preparation sub-region corresponding to the first region to form a first fine grid line, and use a third metal paste to perform screen printing and sintering treatment in a preset fine grid line preparation sub-region corresponding to the second region to form a second fine grid line, thus obtaining the TBC cell; wherein, the silver content in the third metal paste is less than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is less than the silver content in the first metal paste.

[0009] Optionally, the first metal paste includes silver paste; and / or, the second metal paste includes at least any one of silver paste, copper paste and silver-coated copper paste; and / or, the third metal paste includes at least any one of copper paste and silver-coated copper paste.

[0010] Optionally, provide a TBC cell process wafer, including:

[0011] Provide the N-type silicon substrate;

[0012] Sequentially prepare the first tunneling oxide layer and the phosphorus diffusion doping layer on the surface of the N-type silicon substrate corresponding to the first region, and sequentially prepare the second tunneling oxide layer and the boron diffusion doping layer on the surface of the N-type silicon substrate corresponding to the second region;

[0013] Prepare the first passivation film layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer, and prepare the second passivation film layer on the side of the boron diffusion doping layer away from the second tunneling oxide layer.

[0014] Optionally, the first tunneling oxide layer and the phosphorus diffusion doping layer are sequentially formed on the surface of the N-type silicon substrate corresponding to the first region, and the second tunneling oxide layer and the boron diffusion doping layer are sequentially formed on the surface of the N-type silicon substrate corresponding to the second region, including:

[0015] The first tunneling oxide layer and the first intrinsic silicon layer are formed on the surface of the N-type silicon substrate corresponding to the first region and the second region;

[0016] Phosphorus diffusion doping treatment is performed on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form the phosphorus diffusion doping layer;

[0017] The phosphorus diffusion doping layer corresponding to the second region and the first tunneling oxide layer are removed, and the surface of the N-type silicon substrate corresponding to the second region is exposed;

[0018] The second tunneling oxide layer and the second intrinsic silicon layer are formed on the exposed surface of the N-type silicon substrate corresponding to the second region and on the surface of the phosphorus diffusion doping layer away from the first tunneling oxide layer;

[0019] Boron diffusion doping treatment is performed on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form the boron diffusion doping layer;

[0020] The boron diffusion doping layer corresponding to the first region and the second tunneling oxide layer are removed, and the phosphorus diffusion doping layer corresponding to the first region is exposed.

[0021] Optionally, before removing the phosphorus diffusion doping layer corresponding to the second region and the first tunneling oxide layer and exposing the surface of the N-type silicon substrate corresponding to the second region, it further includes:

[0022] A mask layer is formed on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer;

[0023] Removing the phosphorus diffusion doping layer corresponding to the second region and the first tunneling oxide layer and exposing the surface of the N-type silicon substrate corresponding to the second region includes:

[0024] In the second region, laser grooving is performed on the side of the mask layer away from the phosphorus diffusion doping layer until the surface of the N-type silicon substrate corresponding to the second region is exposed.

[0025] Optionally, the mask layer includes a first mask layer, a second mask layer, and a third mask layer;

[0026] Forming a mask layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer includes:

[0027] Perform a thermal oxidation treatment on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer to form the first mask layer;

[0028] Perform a coating treatment on the side of the first mask layer away from the phosphorus diffusion doping layer to form the second mask layer;

[0029] Perform a thermal oxidation treatment on the side of the second mask layer away from the first mask layer to form the third mask layer.

[0030] Optionally, the material of the first mask layer includes silicon oxide; and / or, the material of the second mask layer includes silicon nitride; and / or, the material of the third mask layer includes silicon oxide.

[0031] Optionally, after performing a boron diffusion doping treatment on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form the boron diffusion doping layer, it further includes:

[0032] Perform an oxidation degradation treatment on the N-type silicon substrate after the boron diffusion doping treatment.

[0033] Optionally, after providing the N-type silicon substrate, it further includes:

[0034] Prepare a third passivation film layer on the surface of the N-type silicon substrate on the side away from the first tunneling oxide layer and the second tunneling oxide layer.

[0035] In a second aspect, an embodiment of the present invention further provides a TBC battery, which is prepared by using the preparation method of the TBC battery according to any one of the first aspects.

[0036] An embodiment of the present invention provides a method for manufacturing a TBC battery and a TBC battery. The manufacturing method first provides a TBC battery process sheet. Among them, the TBC battery process sheet includes an N-type silicon substrate, a first region, and a second region. The first region and the second region are arranged alternately in a finger-like manner on the same side surface of the N-type silicon substrate. The first region includes a first tunneling oxide layer, a phosphorus diffusion doping layer, and a first passivation film layer sequentially stacked on the surface of the N-type silicon substrate. The second region includes a second tunneling oxide layer, a boron diffusion doping layer, and a second passivation film layer sequentially stacked on the surface of the N-type silicon substrate. Then, a first metal paste is used to perform screen printing and sintering treatment in a preset main grid line preparation sub-region corresponding to the first region to form a first main grid line, and screen printing and sintering treatment are performed in a preset main grid line preparation sub-region corresponding to the second region to form a second main grid line. Finally, a second metal paste is used to perform screen printing and sintering treatment in a preset fine grid line preparation sub-region corresponding to the first region to form a first fine grid line, and a third metal paste is used to perform screen printing and sintering treatment in a preset fine grid line preparation sub-region corresponding to the second region to form a second fine grid line, thereby manufacturing a TBC battery. Among them, the silver content in the third metal paste is less than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is less than the silver content in the first metal paste. Using the above method, the main grid line corresponding to the first region and the main grid line corresponding to the second region are prepared using the first metal paste. The fine grid line corresponding to the first region is prepared using the second metal paste, and the fine grid line corresponding to the second region is prepared using the third metal paste. In this embodiment, by reasonably setting the silver content in the first metal paste, the second metal paste, and the third metal paste, the silver content required for preparing the electrode structure of the TBC battery is effectively reduced, the metal recombination is reduced, the fill factor is improved, the overall cost of the TBC battery is reduced, the cost is reduced and the efficiency is increased, the open circuit voltage value and the photoelectric conversion efficiency of the TBC battery are improved, and the power stability of the TBC battery is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 is a schematic flow chart of a method for manufacturing a TBC battery provided by an embodiment of the present invention;

[0039] Figure 2 is a schematic flow chart of another method for manufacturing a TBC battery provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only the parts related to the present invention are shown in the drawings, rather than all the structures.

[0041] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the orientation terms such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described from the angles shown in the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also be indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes, and do not indicate any order, quantity, or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] The term "including" and its variations used in the present invention are open-ended, that is, "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0043] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or the interdependent relationship.

[0044] It should be noted that the modifications of "one" and "multiple" mentioned in the present invention are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly specified in the context, it should be understood as "one or more".

[0045] Figure 1 is a schematic flow chart of a method for preparing a TBC battery provided by an embodiment of the present invention. The method for preparing a TBC battery can be applied to the preparation process of a TBC battery, and the method for preparing a TBC battery can be used to prepare a TBC battery. As Figure 1 shown, the preparation method includes:

[0046] S110. Provide a TBC cell process wafer; wherein, the TBC cell process wafer includes an N-type silicon substrate, a first region, and a second region. The first region and the second region are arranged alternately in a finger-like pattern on the same side surface of the N-type silicon substrate. The first region includes a first tunneling oxide layer, a phosphorus diffusion doping layer, and a first passivation film layer sequentially stacked on the surface of the N-type silicon substrate. The second region includes a second tunneling oxide layer, a boron diffusion doping layer, and a second passivation film layer sequentially stacked on the surface of the N-type silicon substrate.

[0047] First of all, it should be noted that the TBC cell is a highly efficient and stable solar cell. The biggest difference between the TBC cell and other crystalline silicon solar cells is that the emitter, surface field, and metal electrodes are all made on the back of the cell and are distributed in a cross-finger pattern, and there are no grid lines blocking on the front of the cell. In other words, the TBC cell absorbs the tunneling oxide layer passivation contact technology of the TOPCon cell and the technology of preparing finger-like alternating P regions and N regions on the back of the BC cell. There are no electrodes on the front of the TBC cell, but charge collection and power transmission are achieved through ohmic contact on the back. And because there are no electrode blockages on the front of the TBC cell, the TBC cell can make the most of the incident light to reduce optical losses. That is to say, the TBC cell can reduce the blockage of sunlight, which is beneficial to obtaining more effective power generation area and improving the photoelectric conversion efficiency.

[0048] Specifically, the TBC cell process wafer includes an N-type silicon substrate, a first region, and a second region. The first region and the second region are located on the same side surface of the N-type silicon substrate, and the first region and the second region are arranged alternately in a finger-like manner. Exemplarily, both the first region and the second region can be located on the back surface of the N-type silicon substrate. Exemplarily, one of the first region and the second region can be a P region, and the other can be an N region. During the preparation process of the TBC cell, through doping, the P region can be made rich in holes and the N region can be made rich in electrons. When these two regions come into contact, a PN junction can be formed. When light irradiates the PN junction, the energy of photons will be absorbed by electrons, causing some electrons to transition from the valence band to the conduction band, and at the same time, holes will also be generated. Since the P region is rich in holes and the N region is rich in electrons, electrons and holes will diffuse in opposite directions, forming a photoinduced potential difference. The photoinduced potential difference prompts electrons and holes to move towards the P region and the N region respectively. Due to the existence of the electric field on the PN junction, electrons will be attracted to the N region, and holes will be attracted to the P region, that is, a potential gradient can be formed, prompting electrons to flow from the N region to the P region and holes to flow from the P region to the N region, that is, a photoinduced current can be formed. By means of an external circuit, the photoinduced current can be collected, and thus the conversion of light energy into electrical energy can be completed. In a specific embodiment, exemplarily, the first region can be an N region and the second region can be a P region. In a more understandable way, the first region can be used for preparing the negative electrode grid line subsequently, that is, to realize the conduction between the n+ doped region and the negative electrode grid line, and subsequently, a good ohmic contact between the negative electrode grid line and the N-type silicon substrate can be achieved. Also, the first region can be used for preparing the positive electrode grid line subsequently, that is, to realize the conduction between the p+ doped region and the positive electrode grid line, and subsequently, a good ohmic contact between the positive electrode grid line and the N-type silicon substrate can be achieved.

[0049] The first region includes a first tunneling oxide layer, a phosphorus diffusion doping layer, and a first passivation film layer that are sequentially stacked on the surface of the N-type silicon substrate. In other words, the first tunneling oxide layer, the phosphorus diffusion doping layer, and the first passivation film layer can be sequentially fabricated on the surface of the N-type silicon substrate corresponding to the first region. Among them, the first tunneling oxide layer is used to allow majority carriers (electrons) to pass through smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, increase the open-circuit voltage and fill factor of the TBC cell, thereby improving the photoelectric conversion efficiency of the TBC cell. The phosphorus diffusion doping layer is a phosphorus-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping phosphorus elements. The first passivation film layer can include an alumina film layer and / or a silicon nitride film layer. The first passivation film layer has passivation and anti-ultraviolet attenuation properties, which can effectively avoid the influence of ultraviolet and infrared on the entire TBC cell, and further ensure the operation reliability of the entire TBC cell. And, the second region includes a second tunneling oxide layer, a boron diffusion doping layer, and a second passivation film layer that are sequentially stacked on the surface of the N-type silicon substrate. In other words, the second tunneling oxide layer, the boron diffusion doping layer, and the second passivation film layer can be sequentially fabricated on the surface of the N-type silicon substrate corresponding to the second region. Among them, the second tunneling oxide layer is used to allow majority carriers (electrons) to pass through smoothly through the tunneling effect, while preventing the recombination of minority carriers (holes), so as to achieve selective collection of carriers, reduce surface recombination, increase the open-circuit voltage and fill factor of the TBC cell, thereby improving the photoelectric conversion efficiency of the TBC cell. The boron diffusion doping layer is a boron-doped polysilicon layer, which is a special semiconductor layer with a high doping concentration formed by doping boron elements. The second passivation film layer can include an alumina film layer and / or a silicon nitride film layer. The second passivation film layer has passivation and anti-ultraviolet attenuation properties, which can effectively avoid the influence of ultraviolet and infrared on the entire TBC cell, and further ensure the operation reliability of the entire TBC cell. In this embodiment, no specific requirements or special limitations are imposed on the film layer fabrication process of the TBC cell process wafer. For details, reference can be made to the subsequent embodiments.

[0050] S120. Use the first metal paste to perform screen printing and sintering treatment in the preset main grid line preparation sub-region corresponding to the first region to form the first main grid line, and perform screen printing and sintering treatment in the preset main grid line preparation sub-region corresponding to the second region to form the second main grid line.

[0051] Among them, the preset main grid line preparation sub-region corresponding to the first region can be understood as the region for forming the first main grid line subsequently, and the preset main grid line preparation sub-region corresponding to the second region can be understood as the region for forming the second main grid line subsequently. Specifically, this step is essentially to perform screen printing and sintering processes in the first region and the second region respectively to form the corresponding negative electrode main grid line and positive electrode main grid line, that is, to form the main grid line on the back of the N-type silicon substrate. Screen printing is one of the core processes in the manufacturing process of TBC batteries and is mainly used for forming the electrode structure of TBC batteries. This process uses the basic principle that the mesh holes in the graphic part of the screen allow the paste to pass through, while the mesh holes in the non-graphic part do not allow the paste to pass through for printing. During the printing process, the paste is precisely extruded onto the battery wafer through the mesh holes of the screen, and the paste is evenly distributed on the surface of the battery wafer in the form of a wire to form the required electrode pattern. Usually, the first metal paste used in screen printing can include but is not limited to silver paste. The pattern formed by screen printing includes electrodes for welding and metal grid lines for collecting current on the battery wafer, etc. After printing the first metal paste onto the back of the N-type silicon substrate, a paste pattern containing various metal components is formed on the surface of the N-type silicon substrate, and the first metal paste needs to be subjected to high-temperature sintering treatment. The high-temperature sintering treatment is used to process the first metal paste screen-printed on the surface of the N-type silicon substrate at high temperature, dry the first metal paste on the surface of the N-type silicon substrate, burn out the organic components of the first metal paste, and the first metal paste can corrode through the corresponding first passivation film layer or second passivation film layer and be connected to the PN junction, so that the formed main grid line forms a good ohmic contact with the N-type silicon substrate to achieve the purpose of collecting and conducting current. In addition, by way of example, the first metal paste can be silver paste.

[0052] S130. Use the second metal paste to perform screen printing and sintering processes in the preset fine grid line preparation sub-region corresponding to the first region to form the first fine grid line, and use the third metal paste to perform screen printing and sintering processes in the preset fine grid line preparation sub-region corresponding to the second region to form the second fine grid line, thereby manufacturing a TBC battery; wherein, the silver content in the third metal paste is less than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is less than the silver content in the first metal paste.

[0053] Among them, the preset fine grid line preparation sub-region corresponding to the first region can be understood as the region for forming the first fine grid line subsequently, and the preset fine grid line preparation sub-region corresponding to the second region can be understood as the region for forming the second fine grid line subsequently. Specifically, this step is essentially to perform screen printing and sintering processes in the first region and the second region respectively to form the corresponding negative electrode fine grid lines and positive electrode fine grid lines, that is, to form fine grid lines on the back of the N-type silicon substrate. Screen printing is one of the core processes in the manufacturing process of TBC batteries and is mainly used for forming the electrode structure of TBC batteries. This process uses the basic principle that the mesh holes in the graphic part of the screen allow the paste to pass through, while the mesh holes in the non-graphic part do not allow the paste to pass through for printing. During the printing process, the paste is precisely extruded onto the battery wafer through the mesh holes of the screen, and the paste is evenly distributed on the surface of the battery wafer in the form of a conductor to form the required electrode pattern. It should be noted that the second metal paste used in screen printing may include, but is not limited to, silver paste, copper paste, and silver-coated copper paste, and the third metal paste used in screen printing may include, but is not limited to, copper paste and silver-coated copper paste. The pattern formed by screen printing includes electrodes for welding and metal grid lines for collecting current on the battery wafer, etc. After printing the second metal paste onto the back of the N-type silicon substrate, a paste pattern containing various metal components is formed on the surface of the N-type silicon substrate, and the second metal paste also needs to be subjected to high-temperature sintering treatment. The high-temperature sintering treatment is used to process the second metal paste screen-printed on the surface of the N-type silicon substrate at high temperature, dry the second metal paste on the surface of the N-type silicon substrate, burn out the organic components of the second metal paste, and the second metal paste can corrode through the corresponding first passivation film layer and connect to the PN junction, so that the formed fine grid line forms a good ohmic contact with the N-type silicon substrate to achieve the purpose of collecting and conducting current. In addition, exemplarily, the second metal paste may be at least any one of silver paste, copper paste, and silver-coated copper paste. And, after printing the third metal paste onto the back of the N-type silicon substrate, a paste pattern containing various metal components is formed on the surface of the N-type silicon substrate, and the third metal paste also needs to be subjected to high-temperature sintering treatment. The high-temperature sintering treatment is used to process the third metal paste screen-printed on the surface of the N-type silicon substrate at high temperature, dry the third metal paste on the surface of the N-type silicon substrate, burn out the organic components of the third metal paste, and the third metal paste can corrode through the corresponding second passivation film layer and connect to the PN junction, so that the formed fine grid line forms a good ohmic contact with the N-type silicon substrate to achieve the purpose of collecting and conducting current. In addition, exemplarily, the third metal paste may be at least any one of copper paste and silver-coated copper paste.

[0054] Exemplarily, the first region can be an N region, and the second region can be a P region. Thus, the main gate lines corresponding to the first region and the second region are prepared using a first metal paste. The fine gate lines corresponding to the first region are prepared using a second metal paste, and the fine gate lines corresponding to the second region are prepared using a third metal paste. Among them, the silver content in the third metal paste is less than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is less than the silver content in the first metal paste. It can be understood that by reasonably setting the silver content in the first metal paste, the second metal paste, and the third metal paste, the cost required in the process of preparing the gate line electrode can be further reduced, and the overall production cost of the TBC battery can be reduced.

[0055] In addition, after the screen printing process, the TBC battery is sintered at a temperature of 742 °C, and then a light injection process is carried out. Exemplarily, the temperature of the light injection process can be 538 °C, and the light intensity can be 6500 W / m 2 . After the light injection, a laser-induced sintering process is carried out, which can trigger silver-silicon interdiffusion or copper-silicon interdiffusion, thereby significantly reducing the contact resistance, increasing the fill factor of the battery, and effectively improving the photoelectric conversion efficiency of the battery. Exemplarily, the laser power of the laser-induced sintering process can be 18 W, and the reverse voltage applied to the battery can be 28 V.

[0056] It should also be noted that through relevant experiments on the TBC battery prepared in this embodiment, it can be obtained that the open-circuit voltage value of the current-voltage characteristic curve test (IV test) of this TBC battery is 742.8 mV, the short-circuit current value is 16.175 A, the fill factor is 84.72%, and the photoelectric conversion efficiency is as high as 26.928%. Then, this TBC battery undergoes an aging experiment in a UV (ultraviolet light) chamber, with a UV irradiance of 165 W / m 2 and an accumulated irradiance of 60 kW / m 2 . Under the experimental conditions, the attenuation value before and after the IV test after accumulating 60 UV irradiations is measured. The open-circuit voltage value of this TBC battery decays by 0.85%, which is much lower than the open-circuit voltage decay value of UV60 of the control group (existing N-type crystalline silicon batteries), effectively improving the power stability of the TBC battery.

[0057] In the technical solution of the embodiment of the present invention, the main grid lines corresponding to the first region and the main grid lines corresponding to the second region are prepared by using a first metal paste, the fine grid lines corresponding to the first region are prepared by using a second metal paste, and the fine grid lines corresponding to the second region are prepared by using a third metal paste. In this embodiment, by reasonably setting the silver content in the first metal paste, the second metal paste, and the third metal paste, the silver content required for preparing the electrode structure of the TBC cell is effectively reduced, the metal recombination is reduced, the fill factor is improved, the overall cost of the TBC cell is reduced, the cost is reduced and the efficiency is increased, the open-circuit voltage value and the photoelectric conversion efficiency of the TBC cell are improved, and the power stability of the TBC cell is improved.

[0058] Optionally, the first metal paste includes silver paste; and / or, the second metal paste includes at least any one of silver paste, copper paste, and silver-coated copper paste; and / or, the third metal paste includes at least any one of copper paste and silver-coated copper paste.

[0059] Specifically, the first region may be an N region, and the second region may be a P region. Thus, the main grid lines corresponding to the first region and the second region are prepared by using the first metal paste, the fine grid lines corresponding to the first region are prepared by using the second metal paste, and the fine grid lines corresponding to the second region are prepared by using the third metal paste. It should be noted that the first metal paste, the second metal paste, and the third metal paste do not contain aluminum element, effectively avoiding problems such as the easy formation of aluminum spines when the N-type silicon substrate is cooled from high temperature, damaging the PN junction on the N-type silicon substrate, and forming a metal recombination region, and also avoiding the influence on the open-circuit voltage value and the photoelectric conversion efficiency of the TBC cell. And it can be understood that not all of the first metal paste, the second metal paste, and the third metal paste use expensive silver paste, and the second metal paste and the third metal paste use cheap copper paste or silver-coated copper paste, which is beneficial to further reducing the cost required in the preparation process of the grid electrode and reducing the overall production cost of the TBC cell. Exemplarily, in a specific embodiment, the first metal paste uses silver paste, and the second metal paste and the third metal paste use copper paste, then the overall production cost of the TBC cell can be reduced by approximately 0.21 yuan per wafer.

[0060] Figure 2 It is a schematic flow chart of another method for preparing a TBC cell provided by an embodiment of the present invention. This embodiment is optimized on the basis of the above embodiment. Optionally, providing a process wafer of a TBC cell includes:

[0061] Providing an N-type silicon substrate;

[0062] Successively preparing a first tunneling oxide layer and a phosphorus diffusion doping layer on the surface of the N-type silicon substrate corresponding to the first region, and successively preparing a second tunneling oxide layer and a boron diffusion doping layer on the surface of the N-type silicon substrate corresponding to the second region;

[0063] A first passivation film layer is prepared on one side of the phosphorus diffusion doping layer away from the first tunneling oxide layer, and a second passivation film layer is prepared on one side of the boron diffusion doping layer away from the second tunneling oxide layer.

[0064] For the content not elaborated in this embodiment, please refer to the above embodiments. As Figure 2 shown, the preparation method includes:

[0065] S210. Provide an N-type silicon substrate.

[0066] Specifically, an N-type silicon substrate is provided, and the N-type silicon substrate includes a first surface and a second surface facing away from each other. Exemplarily, the first surface can be understood as the back surface of the N-type silicon substrate, and the second surface can be understood as the front surface of the N-type silicon substrate. Exemplarily, the shapes of the first surface and the second surface of the N-type silicon substrate can be rectangular, the length of the long side of the rectangle can be 210 mm, and the length of the short side of the rectangle can be 182 mm.

[0067] The first surface of the N-type silicon substrate is a polished surface. Exemplarily, the first surface of the N-type silicon substrate can be subjected to alkaline polishing treatment to ensure that the first surface of the N-type silicon substrate is a polished surface, so that the N-type silicon substrate forms a polished surface with a high reflectivity, thereby improving the flatness of the battery surface, increasing the reflection of long-wavelength light, promoting the secondary absorption of light, increasing the short-circuit current and reducing the leakage current. Exemplarily, the alkaline polishing treatment can adopt a mixed solution of 32 L of concentrated potassium hydroxide (KOH) solution, 7.5 L of alkaline polishing additive, and 480 L of pure water. The alkaline polishing treatment time can be 280 s, and the alkaline polishing treatment temperature can be 70 °C. Exemplarily, the size of the square of the morphology of the polished surface tested under a microscope is 10 - 12 microns. In addition, exemparily, the effect of the alkaline polishing treatment is that both sides are polished, that is, the front and back surfaces of the N-type silicon substrate can be subjected to alkaline polishing treatment simultaneously.

[0068] The second surface of the N-type silicon substrate is a textured surface. Exemplarily, the second surface of the N-type silicon substrate can be subjected to texturing treatment to make the second surface of the N-type silicon substrate a textured surface. Exemplarily, the morphology of the textured surface tested under a microscope is a pyramid structure. The texturing treatment can remove the organic dirt and metal impurities on the surface of the N-type silicon substrate, remove the mechanical damage layer generated during the wire cutting process of the N-type silicon substrate, reduce the recombination centers, and can also form an uneven textured surface, so as to utilize the light trapping effect, increase the absorption rate of the N-type silicon substrate for sunlight, reduce the reflectivity, and at the same time increase the surface area of the N-type silicon substrate, and thus the area of the P-N junction formed on the surface also increases. Exemplarily, the texturing treatment can adopt a mixed solution of 42 L of concentrated potassium hydroxide (KOH) solution, 10 L of texturing additive, and 480 L of pure water. The texturing treatment time can be 340 s, and the texturing treatment temperature can be 68 °C.

[0069] In addition, it should be noted that in this embodiment, there are no specific requirements or special limitations on the sequence of the alkali polishing treatment and the texturing treatment. In fact, the alkali polishing treatment can be carried out first and then the texturing treatment, or the texturing treatment can be carried out first and then the alkali polishing treatment. This embodiment is only an example here and is not limited. Also, after the alkali polishing treatment and the texturing treatment, the N-type silicon substrate can be subjected to a chain acid cleaning treatment with a hydrochloric acid (HCl) solution to further ensure the cleanliness of both sides of the N-type silicon substrate.

[0070] S220. Sequentially prepare a first tunneling oxide layer and a phosphorus diffusion doping layer on the surface of the N-type silicon substrate corresponding to the first region, and sequentially prepare a second tunneling oxide layer and a boron diffusion doping layer on the surface of the N-type silicon substrate corresponding to the second region.

[0071] Optionally, step S220 may specifically include the following steps S2201-S2206.

[0072] S2201. Prepare a first tunneling oxide layer and a first intrinsic silicon layer on the surface of the N-type silicon substrate corresponding to the first region and the second region.

[0073] S2202. Perform a phosphorus diffusion doping treatment on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a phosphorus diffusion doping layer.

[0074] Specifically, for S2201 and S2202, the LP process (dual insertion, low-pressure chemical vapor deposition method) can be used to sequentially deposit and form a first tunneling oxide layer and a first intrinsic silicon layer in the first region and the second region. After forming the first intrinsic silicon layer, it is also necessary to dope the first intrinsic silicon layer with phosphorus elements so that the first intrinsic silicon layer forms a phosphorus diffusion doping layer after doping, and at the same time, a first associated layer is formed. Among them, the first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor characteristics. An intrinsic semiconductor refers to a semiconductor material that has neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and its conductivity mainly depends on the generation and recombination of electron-hole pairs in the material itself. Exemplarily, the deposition thickness range of the first tunneling oxide layer can be 1-2 nm, and the deposition thickness range of the first intrinsic silicon layer can be 90-130 nm. It can be understood that after forming the phosphorus diffusion doping layer by high-temperature doping, since the phosphorus in the doping process usually does not completely react and enter the first intrinsic silicon layer, but certain residual organic substances will be generated during the reaction. To prevent the residual organic substances from affecting the phosphorus diffusion doping layer, the generated residual organic substances can be post-oxidized. By introducing a certain flow rate of oxygen into the post-oxidation reaction chamber, the residual organic substances react with oxygen to form a first associated layer. Usually, the first associated layer is a phosphosilicate glass layer (PSG), and the thickness range of the first associated layer can be 90-100 nm. In addition, exemplarily, the sheet resistance after the phosphorus diffusion doping treatment is 42 Ω / sq, and the junction depth of ECV is 1.12 μm.

[0075] S2203. Remove the phosphorus diffusion doping layer and the first tunneling oxide layer corresponding to the second region, and expose the surface of the N-type silicon substrate corresponding to the second region.

[0076] Specifically, this step is essentially to sequentially remove the first associated layer, the phosphorus diffusion doping layer, and the first tunneling oxide layer corresponding to the second region. If the first associated layer is not generated in the actual process, only the phosphorus diffusion doping layer and the first tunneling oxide layer corresponding to the second region need to be sequentially removed until the surface of the N-type silicon substrate corresponding to the second region is exposed. Exemplarily, the laser grooving technology can be used to pattern the back surface of the N-type silicon substrate to remove the phosphorus diffusion doping layer and the first tunneling oxide layer corresponding to the second region. Exemplarily, the green picosecond laser can be used for the laser grooving technology. The laser marking speed of the laser grooving technology can be 42000 mm / min, the laser power of the laser grooving technology can be 26 W, the laser frequency of the laser grooving technology can be 1500 Hz, the width of the groove structure formed after laser grooving can be 280 microns, and the depth can be 1.8 microns.

[0077] Optionally, before removing the phosphorus diffusion doping layer corresponding to the second region and the first tunneling oxide layer and exposing the surface of the N-type silicon substrate corresponding to the second region, it further includes: preparing a mask layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer; removing the phosphorus diffusion doping layer corresponding to the second region and the first tunneling oxide layer and exposing the surface of the N-type silicon substrate corresponding to the second region, including: in the second region, performing laser grooving on the side of the mask layer away from the phosphorus diffusion doping layer until the surface of the N-type silicon substrate corresponding to the second region is exposed.

[0078] Specifically, preparing a mask layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer. Exemplarily, this mask layer can cover the first region and expose the second region, so as to facilitate subsequent precise laser grooving in the second region to form the second region corresponding to the grooved structure and the first region corresponding to the ungrooved structure, until the surface of the N-type silicon substrate corresponding to the second region is exposed to expose the second region, that is, to make the position difference between the first region and the second region more obvious. Exemplarily, processes such as thermal oxidation process, atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), coating, etc. can be used to achieve the formation of this mask layer. This embodiment is only for example here and is not limited.

[0079] In addition, after performing laser grooving on the side of the mask layer away from the phosphorus diffusion doping layer, the surface of the N-type silicon substrate after laser grooving can also be subjected to chain pickling and trough texturing treatment. Exemplarily, chain pickling treatment can be used to remove metal impurities such as Al, Fe, Zn, Ni, etc. on the silicon wafer surface, and to remove metal hydroxides attached to the natural oxide film. Exemplarily, the chain pickling treatment can use a 1.8% hydrochloric acid (HCl) solution. Exemplarily, trough texturing treatment can be used to effectively remove the impurity layer formed by laser grooving and effectively form a textured surface in the groove structure, reducing the surface reflectivity of the subsequently prepared TBC cell. Exemplarily, the trough texturing treatment can use a mixed solution of concentrated potassium hydroxide (KOH) solution and texturing additive.

[0080] Further, the mask layer includes a first mask layer, a second mask layer, and a third mask layer; preparing the mask layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer includes: performing thermal oxidation treatment on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer to form the first mask layer; performing coating treatment on the side of the first mask layer away from the phosphorus diffusion doping layer to form the second mask layer; performing thermal oxidation treatment on the side of the second mask layer away from the first mask layer to form the third mask layer.

[0081] Specifically, the mask layer includes a first mask layer, a second mask layer, and a third mask layer, that is, the mask layer is a multi-layer structure, which can effectively avoid damage or injury to the N-type silicon substrate during subsequent laser grooving treatment, etc., and the setting of the mask layer is also beneficial to distinguish the first region and the second region, forming the second region corresponding to the grooved structure and the first region corresponding to the ungrooved structure. Optionally, the material of the first mask layer includes silicon oxide; and / or, the material of the second mask layer includes silicon nitride; and / or, the material of the third mask layer includes silicon oxide. That is, using the backside thermal oxidation process, oxygen reacts with silicon atoms to form the corresponding silicon oxide layer, that is, the first mask layer. Using the second backside thermal oxidation process, oxygen reacts with silicon atoms to form the corresponding silicon oxide layer, that is, the third mask layer.

[0082] In addition, the TBC cell process sheet may further include a fourth mask layer, and the fourth mask layer is located on one side of the second surface of the N-type silicon substrate. The fourth mask layer can protect the second surface of the N-type silicon substrate and prevent damage or injury to the second surface of the N-type silicon substrate during subsequent etching, pickling, or alkaline polishing, etc. Optionally, the material of the fourth mask layer includes silicon oxide. That is, using the frontside thermal oxidation process, oxygen reacts with silicon atoms to form the corresponding silicon oxide layer, that is, the fourth mask layer.

[0083] S2204. Prepare a second tunneling oxide layer and a second intrinsic silicon layer on the surface of the N-type silicon substrate corresponding to the exposed second region and on the surface of the phosphorus diffusion doping layer away from the first tunneling oxide layer.

[0084] S2205. Perform boron diffusion doping treatment on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form a boron diffusion doping layer.

[0085] Specifically, for S2204 and S2205, the LP process (dual insertion, low-pressure chemical vapor deposition) can be utilized to sequentially deposit and form a second tunneling oxide layer and a second intrinsic silicon layer in the second region. After the formation of the second intrinsic silicon layer, boron element doping is also required for the second intrinsic silicon layer so that a boron diffusion doping layer is formed after doping the second intrinsic silicon layer, and a second associated layer is formed simultaneously. Among them, the second intrinsic silicon layer is a silicon material layer with intrinsic semiconductor characteristics. An intrinsic semiconductor refers to a semiconductor material that has neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and its conductivity mainly depends on the generation and recombination of electron-hole pairs in the material itself. Exemplarily, the deposition thickness range of the second tunneling oxide layer can be 1 - 2 nm, and the deposition thickness range of the second intrinsic silicon layer can be 90 - 130 nm. It can be understood that after the formation of the boron diffusion doping layer by high-temperature doping, since boron in the doping process usually does not fully react and enter the second intrinsic silicon layer, but certain residual organic substances will be generated during the reaction. To prevent the residual organic substances from affecting the boron diffusion doping layer, post-oxidation can be performed on the generated residual organic substances. By introducing a certain flow rate of oxygen into the reaction chamber for post-oxidation, the residual organic substances react with oxygen to form a second associated layer. Usually, the second associated layer is a borosilicate glass layer (BSG), and the thickness range of the second associated layer can be 90 - 100 nm.

[0086] Optionally, after performing boron diffusion doping treatment on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form a boron diffusion doping layer, it further includes: performing an oxidation degradation treatment on the N-type silicon substrate after the boron diffusion doping treatment.

[0087] Specifically, the oxidation degradation treatment can play a role of high-temperature promotion, redistributing the diffused boron, making the boron diffusion in the second region more uniform, and also acting like forming an oxide layer to play a protective role. Exemplarily, the sheet resistance after the oxidation degradation treatment is 60 Ω / sq.

[0088] In addition, exmplarily, after performing an oxidation degradation treatment on the N-type silicon substrate after the boron diffusion doping treatment, the N-type silicon substrate can also be subjected to chain pickling and buffered oxide etch treatment to ensure that both sides of the N-type silicon substrate are clean and impurity-free. Exemplarily, the chain pickling treatment can adopt a mixed solution of 1.5% hydrochloric acid (HCl) solution and 1.0% hydrofluoric acid (HF) solution. Exemplarily, the buffered oxide etch treatment can adopt a mixed solution of 32 L of concentrated potassium hydroxide (KOH) solution, 4 L of additive (BP62), and 460 L of pure water, the etch treatment time can be 300 s, and the etch treatment temperature can be 70 °C.

[0089] S2206. Remove the boron diffusion doping layer corresponding to the first region and the second tunneling oxide layer, and expose the phosphorus diffusion doping layer corresponding to the first region.

[0090] Specifically, this step is essentially to sequentially remove the second associated layer, the boron diffusion doping layer, and the second tunneling oxide layer corresponding to the first region. If the second associated layer is not formed in the actual process, only the boron diffusion doping layer and the second tunneling oxide layer corresponding to the first region need to be sequentially removed until the phosphorus diffusion doping layer corresponding to the first region is exposed. Exemplarily, the above-mentioned chain pickling and buffered oxide etch treatments can be used.

[0091] S230. Prepare a first passivation film layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer, and prepare a second passivation film layer on the side of the boron diffusion doping layer away from the second tunneling oxide layer.

[0092] Specifically, preparing a first passivation film layer on the side of the phosphorus diffusion doping layer away from the first tunneling oxide layer means forming the first passivation film layer in the first region. Exemplarily, processes such as atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and coating can be used to form the first passivation film layer on one side of the first surface of the N-type silicon substrate. And, preparing a second passivation film layer on the side of the boron diffusion doping layer away from the second tunneling oxide layer means forming the second passivation film layer in the second region. Exemplarily, processes such as atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and coating can be used to form the second passivation film layer on one side of the first surface of the N-type silicon substrate. It can be understood that the first passivation film layer and the second passivation film layer have passivation and anti-ultraviolet attenuation properties, which can effectively avoid the influence of ultraviolet and infrared on the entire TBC cell, and further ensure the operation reliability of the entire solar cell. And, the first passivation film layer and the second passivation film layer can essentially be understood as the same passivation film layer. The part of the passivation film layer located in the first region is defined as the first passivation film layer, and the part of the passivation film layer located in the second region is defined as the second passivation film layer. Optionally, the material of the first passivation film layer includes silicon nitride, and the material of the second passivation film layer includes silicon nitride.

[0093] Optionally, after providing the N-type silicon substrate, it further includes: preparing a third passivation film layer on a surface of the N-type silicon substrate away from the first tunneling oxide layer and the second tunneling oxide layer.

[0094] Specifically, preparing a third passivation film layer on a surface of the N-type silicon substrate away from the first tunneling oxide layer and the second tunneling oxide layer, that is, forming a third passivation film layer on one side of the second surface of the N-type silicon substrate. Exemplarily, processes such as atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), coating, etc. can be used to form a third passivation film layer on one side of the second surface of the N-type silicon substrate. It can be understood that the third passivation film layer has passivation and anti-ultraviolet attenuation properties, which can effectively avoid the influence of ultraviolet and infrared on the entire TBC cell, and further ensure the operation reliability of the entire solar cell. Optionally, the material of the third passivation film layer includes alumina and silicon nitride. Thus, an alumina film layer can be first formed on one side of the second surface of the N-type silicon substrate, and then a silicon nitride film layer can be formed on a side of the alumina film layer away from the second surface of the N-type silicon substrate. Exemplarily, the deposition thickness range of the alumina film layer can be 4 - 6 nm. Exemplarily, the deposition thickness of the alumina film layer can be 6 nm. Thus, by reasonably increasing the deposition thickness of the alumina film layer, the anti-UV (ultraviolet light) ability of the TBC cell can be effectively improved.

[0095] It should be noted that in this embodiment, there are no specific requirements and special limitations on the formation sequence of the first passivation film layer, the second passivation film layer, and the third passivation film layer. In fact, the first passivation film layer and the second passivation film layer can be formed simultaneously first, and then the third passivation film layer can be formed, or the third passivation film layer can be formed first, and then the first passivation film layer and the second passivation film layer can be formed simultaneously. In addition, regarding the silicon nitride film layers in the first passivation film layer, the second passivation film layer, and the third passivation film layer, it can be understood that they are prepared simultaneously, only the film layer positions are different, but other parameters and preparation methods can be the same.

[0096] S240: Use the first metal paste to perform screen printing and sintering treatment in the sub-region corresponding to the preset main grid line in the first region to form the first main grid line, and perform screen printing and sintering treatment in the sub-region corresponding to the preset main grid line in the second region to form the second main grid line.

[0097] S250. Use the second metal paste to perform screen printing and sintering in the preset fine grid line preparation sub-region corresponding to the first region to form the first fine grid line, and use the third metal paste to perform screen printing and sintering in the preset fine grid line preparation sub-region corresponding to the second region to form the second fine grid line, thereby manufacturing a TBC cell; wherein, the silver content in the third metal paste is less than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is less than the silver content in the first metal paste.

[0098] Based on the same inventive concept, an embodiment of the present invention further provides a TBC cell. The TBC cell is manufactured by using the manufacturing method of the TBC cell provided in any one of the embodiments of the present invention. Therefore, the TBC cell has the corresponding functional modules and beneficial effects of the manufacturing method of the TBC cell.

[0099] Note that the above is only a preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, combinations with each other, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the inventive concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a TBC battery, characterized in that: include: A TBC battery process sheet is provided; wherein the TBC battery process sheet comprises an N-type silicon substrate, a first region and a second region, the first region and the second region are alternately arranged in an interdigitated shape on the same side surface of the N-type silicon substrate, the first region comprises a first tunneling oxide layer, a phosphorus diffusion doping layer and a first passivation film layer stacked in sequence on the surface of the N-type silicon substrate, and the second region comprises a second tunneling oxide layer, a boron diffusion doping layer and a second passivation film layer stacked in sequence on the surface of the N-type silicon substrate; Using a first metal slurry, screen printing and sintering are performed in a preset busbar preparation sub-region corresponding to the first region to form a first busbar, and screen printing and sintering are performed in a preset busbar preparation sub-region corresponding to the second region to form a second busbar; The TBC battery is manufactured by using a second metal paste, performing screen printing and sintering in a preset fine grid line preparation sub-region corresponding to the first region to form a first fine grid line, and using a third metal paste, performing screen printing and sintering in a preset fine grid line preparation sub-region corresponding to the second region to form a second fine grid line; wherein the silver content in the third metal paste is less than or equal to the silver content in the second metal paste, and the silver content in the third metal paste is less than the silver content in the first metal paste.

2. The preparation method according to claim 1, characterized in that: The first metal paste includes silver paste; and / or the second metal paste includes at least any one of silver paste, copper paste and silver-coated copper paste; and / or the third metal paste includes at least any one of copper paste and silver-coated copper paste.

3. The preparation method according to claim 1, characterized in that: Provide TBC battery process sheet, including: Providing the N-type silicon substrate; The first tunneling oxide layer and the phosphorus diffusion doping layer are sequentially formed on the surface of the N-type silicon substrate corresponding to the first region, and the second tunneling oxide layer and the boron diffusion doping layer are sequentially formed on the surface of the N-type silicon substrate corresponding to the second region; The first passivation film layer is formed on a side of the phosphorus diffusion doped layer away from the first tunneling oxide layer, and the second passivation film layer is formed on a side of the boron diffusion doped layer away from the second tunneling oxide layer.

4. The preparation method according to claim 3, characterized in that: The first tunneling oxide layer and the phosphorus diffusion doping layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the first region, and the second tunneling oxide layer and the boron diffusion doping layer are sequentially prepared on the surface of the N-type silicon substrate corresponding to the second region, including: Preparing the first tunneling oxide layer and the first intrinsic silicon layer on the surface of the N-type silicon substrate corresponding to the first region and the second region; Performing a phosphorus diffusion doping process on a side of the first intrinsic silicon layer away from the first tunnel oxide layer to form the phosphorus diffusion doping layer; removing the phosphorus diffusion doping layer and the first tunneling oxide layer corresponding to the second region, and exposing the surface of the N-type silicon substrate corresponding to the second region; Forming the second tunneling oxide layer and the second intrinsic silicon layer on the surface of the N-type silicon substrate corresponding to the exposed second region and on the surface of the phosphorus diffusion doped layer on a side away from the first tunneling oxide layer; Performing a boron diffusion doping process on a side of the second intrinsic silicon layer away from the second tunnel oxide layer to form the boron diffusion doping layer; The boron diffusion doping layer and the second tunneling oxide layer corresponding to the first region are removed, and the phosphorus diffusion doping layer corresponding to the first region is exposed.

5. The preparation method according to claim 4, characterized in that: Before removing the phosphorus diffusion doping layer and the first tunneling oxide layer corresponding to the second region and exposing the surface of the N-type silicon substrate corresponding to the second region, the method further includes: Preparing a mask film layer on a side of the phosphorus diffusion doped layer away from the first tunnel oxide layer; Removing the phosphorus diffusion doping layer and the first tunneling oxide layer corresponding to the second region and exposing the surface of the N-type silicon substrate corresponding to the second region, comprising: In the second region, a laser groove process is performed on a side of the mask film layer away from the phosphorus diffusion doping layer until a surface of the N-type silicon substrate corresponding to the second region is exposed.

6. The preparation method according to claim 5, characterized in that: The mask film layer comprises a first mask layer, a second mask layer and a third mask layer; A mask film layer is prepared on a side of the phosphorus diffusion doped layer away from the first tunnel oxide layer, comprising: Performing thermal oxidation treatment on a side of the phosphorus diffusion doped layer away from the first tunneling oxide layer to form the first mask layer; Performing a coating process on a side of the first mask layer away from the phosphorus diffusion doping layer to form the second mask layer; A thermal oxidation treatment is performed on a side of the second mask layer away from the first mask layer to form the third mask layer.

7. The preparation method according to claim 6, characterized in that: The material of the first mask layer includes silicon oxide; and / or, the material of the second mask layer includes silicon nitride; and / or, the material of the third mask layer includes silicon oxide.

8. The preparation method according to claim 4, characterized in that: After performing a boron diffusion doping process on a side of the second intrinsic silicon layer away from the second tunnel oxide layer to form the boron diffusion doping layer, the method further includes: The N-type silicon substrate after the boron diffusion and doping treatment is subjected to oxidation degradation treatment.

9. The preparation method according to claim 3, characterized in that: After providing the N-type silicon substrate, the method further includes: A third passivation film layer is formed on a surface of the N-type silicon substrate which is away from the first tunneling oxide layer and the second tunneling oxide layer.

10. A TBC battery, characterized in that: The TBC battery is prepared by the preparation method of any one of claims 1 to 9.

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