LED epitaxial wafer with improved antistatic capability and preparation method thereof

Abstract

The invention relates to the technical field of LEDs, in particular to an LED epitaxial wafer with improved antistatic capability and a preparation method of the LED epitaxial wafer. The LED epitaxial wafer sequentially comprises a GaAs substrate, a secondary nucleating layer, a buffer layer, an N-type limiting layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type limiting layer, a P-type transition layer and a P-type window layer from bottom to top, and the secondary nucleation layer is a GaAs single crystal layer formed by in-situ secondary nucleation by combining Ga atoms left after the surface of the GaAs substrate is processed from the defect layer and As atoms in the external source gas AsH3. According to the method, the GaAs substrate is subjected to substrate surface self-defect layer treatment, and a method of secondary nucleation of the Ga fracture bonds and As atoms on the surface of the substrate is adopted, so that a complete defect-free GaAs surface layer is formed, the phenomenon that an electric leakage channel is formed due to proliferation of substrate crystal defects in the epitaxial growth process is effectively avoided, and the antistatic performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and particularly relates to an LED epitaxial wafer for improving antistatic ability and a preparation method thereof. Background Art

[0002] Light-emitting diodes (LEDs) have the advantages of high brightness, low power consumption, high reliability, etc., and have been widely used in markets such as solid-state lighting and display screens. LEDs prepared from quaternary AlGaInP materials are very widely used in fields such as backlights, scene lighting, and landscape lights. As the application scenarios of LED products become more and more diverse, antistatic performance has become a very important parameter index for LEDs. For conventional quaternary AlGaInP-based LEDs, the schematic structural diagram of its epitaxial wafer is as Figure 1 shown, which successively includes a GaAs substrate 100, a buffer layer 101, an N-type confinement layer 102, a multi-quantum well active layer 103, a P-type confinement layer 104, a P-type transition layer 105, and a P-type window layer 106 from bottom to top. However, due to the influence of unstable crystal nucleation between the surface of the GaAs substrate and the epitaxial layer, lattice defects are likely to occur, and as the crystal growth defects continue to extend upward, a leakage channel is formed, which is easily electrostatically broken down, resulting in a decrease in the antistatic ability of the LED; at the same time, the conventional LED epitaxial wafer structure generally uses a multi-quantum well active layer, and the width of the depletion region in the PN junction is relatively large, resulting in a decrease in the barrier capacitance and a weakening of the antistatic ability. Due to the above disadvantages, conventional quaternary AlGaInP-based LEDs cannot reach a high antistatic level. Therefore, it is of great significance to develop an LED with high antistatic performance. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention provides an LED epitaxial wafer for improving antistatic ability and a preparation method thereof, which can effectively improve the problem of poor antistatic ability of conventional quaternary AlGaInP-based LEDs.

[0004] The first object of the present invention is to provide an LED epitaxial wafer for improving antistatic ability, and the LED epitaxial wafer successively includes a GaAs substrate, a secondary nucleation layer, a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitance region, a multi-quantum well active layer, a P-type high-frequency barrier capacitance region, a P-type confinement layer, a P-type transition layer, and a P-type window layer from bottom to top; The secondary nucleation layer is a GaAs single crystal layer formed by in-situ secondary nucleation of the combination of Ga atoms left after surface defect layer treatment of the GaAs substrate and As atoms in the external source gas AsH3.

[0005] Further, the thickness of the secondary nucleation layer is 10 nm to 50 nm.

[0006] Further, the materials of the N-type high-frequency barrier capacitance region and the P-type high-frequency barrier capacitance region are both Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 P are alternately grown periodic structures, and the number of pairs of the periodic structures is 5 to 10 pairs. In each periodic structure, the thickness of the Al 0.5 In 0.5 P layer is 12 nm to 18 nm, and the thickness of the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer is 20 nm to 30 nm, where the value range of x1 is 0.1 to 0.3. In this technical solution, an N-type high-frequency barrier capacitance region is introduced between the N-type confinement layer and the multi-quantum well active layer, and a P-type high-frequency barrier capacitance region is introduced between the P-type confinement layer and the multi-quantum well active layer. Through the high-barrier Al 0.5 In 0.5 P material and the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material with high mobility and high dielectric constant are alternately grown to form a barrier capacitance region with high-frequency response and carrier injection, achieving the effect of balancing the depletion region width of the PN junction. It can not only solve the problem of weak electrostatic discharge resistance caused by the large depletion layer width in conventional LEDs, but also avoid potential hazards such as reverse leakage caused by too narrow depletion layer, effectively improving the electrostatic discharge performance and reliability of the LED chip.

[0007] Further, the doping concentrations of the Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials in the N-type high-frequency barrier capacitance region are both 2×10 18 cm -3 ~3×10 18 cm -3 , and SiH4 is used as the N-type dopant.

[0008] Further, the doping concentrations of the Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials in the P-type high-frequency barrier capacitance region are both 1×10 18 cm -3~2×10 18 cm -3 , and Cp2Mg is used as the P-type dopant in all cases.

[0009] In the present invention, by eliminating the self-defect layer on the surface of the GaAs substrate and adopting the secondary nucleation method of the GaAs single crystal layer formed by the combination of the broken Ga bonds on the substrate surface and As atoms, a complete defect-free GaAs surface layer is formed, which provides guarantee for subsequent epitaxial crystal growth, effectively avoids the formation of leakage channels due to the proliferation of substrate crystal defects during the epitaxial growth process, and improves the antistatic performance; at the same time, a high-frequency barrier capacitance region structure is introduced on both sides of the multi-quantum well active layer to balance the depletion region width of the PN junction and further improve the antistatic performance of the LED chip.

[0010] The second object of the present invention is to provide a method for preparing an LED epitaxial wafer with improved antistatic performance. Using an MOCVD device on a GaAs substrate, the surface of the GaAs substrate is treated with a self-defect layer in a gradual change manner, and then a secondary nucleation layer is formed by in-situ secondary nucleation, and then a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitance region, a multi-quantum well active layer, a P-type high-frequency barrier capacitance region, a P-type confinement layer, a P-type transition layer, and a P-type window layer are grown in sequence.

[0011] Furthermore, the method for treating the self-defect layer is as follows: the initial pressure of the reaction chamber is set to 10 mbar, the temperature of the reaction chamber is set to 780 °C to 800 °C, a mixed gas of H2 and N2 is introduced onto the substrate surface, the flow rate of H2 is set to 15000 sccm to 20000 sccm, the flow rate of N2 is set to 1500 sccm to 2000 sccm, the pressure of the reaction chamber starts from the introduction of the mixed gas and gradually changes from 10 mbar to 50 mbar, the rate of pressure change is 5 mbar / min to 10 mbar / min, and the time for pressure change is 5 min to 8 min. Due to the existence of an oxide layer and lattice defects on the surface of the GaAs substrate, in this technical solution, by means of the gradual change of high temperature and low pressure, the As on the GaAs substrate volatilizes under the action of unsaturated As pressure and high temperature, and the Ga atoms remain in-situ on the GaAs substrate in a liquid state. Under the mixed gas of high-speed and large-flow H2 and N2, it can be ensured that the H atoms in the carrier gas combine with the volatilized As atoms on the substrate and are pumped out of the reaction chamber under the action of N2 as the carrier gas, thereby leaving broken Ga bonds for subsequent secondary nucleation. This technology can remove the surface oxide layer and crystal defects of GaAs on the substrate surface by a non-chemical etching method, effectively avoiding the formation of leakage channels due to the proliferation of crystal defects during the epitaxial growth process and improving the antistatic performance.

[0012] Further, the in-situ secondary nucleation method is as follows: when the pressure in the reaction chamber after treating the self-defect layer reaches 50 mbar, the introduction of N2 is closed, and the pressure in the reaction chamber is maintained stable at 50 mbar. Meanwhile, AsH3 gas with a flow rate of 300 sccm to 500 sccm is introduced for 3 min to 5 min. After reaching a certain pressure, the newly introduced AsH3 is cracked and can recombine with the liquid Ga vacancies on the substrate surface to form a flat and ordered GaAs crystal layer, enabling the secondary nucleation of Ga and As left after the evaporation of As on the GaAs substrate surface, forming a complete defect-free GaAs surface layer, providing guarantee for subsequent epitaxial crystal growth, reducing the defect density, and improving the antistatic performance.

[0013] Further, the growth steps of the N-type high-frequency barrier capacitance region are as follows: set the reaction chamber temperature to 730 °C ± 20 °C, introduce TMAl, TMIn, and PH3 on the N-type confinement layer to grow an Al 0.5 In 0.5 P material with a thickness of 12 nm to 18 nm, and use SiH4 as a dopant. Then introduce TMGa to grow an (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material with a thickness of 20 nm to 30 nm, where the value range of x1 is 0.1 to 0.3, and use SiH4 as a dopant. The above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are alternately and periodically grown in a cycle to form the N-type high-frequency barrier capacitance region, and the number of cycle pairs is 5 to 10 pairs.

[0014] Further, the growth steps of the P-type high-frequency barrier capacitance region are as follows: set the reaction chamber temperature to 730 °C ± 20 °C, introduce TMAl, TMIn, and PH3 on the multi-quantum well active layer to grow an Al 0.5 In 0.5 P material with a thickness of 12 nm to 18 nm, and use Cp2Mg as a dopant. Then introduce TMGa to grow an (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material with a thickness of 20 nm to 30 nm, where the value range of x1 is 0.1 to 0.3, and use Cp2Mg as a dopant. The above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In0.5 The P material grows in an alternating periodic cycle to form a P-type high-frequency barrier capacitance region, and the logarithmic number of cycles is 5 to 10 pairs.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. In the epitaxial growth of a conventional quaternary AlGaInP-based LED, the GaAs substrate is treated with a self-defect layer on the substrate surface, and a method of secondary nucleation of Ga broken bonds on the substrate surface and As atoms is adopted to form a complete defect-free GaAs surface layer, effectively avoiding the formation of leakage channels due to the proliferation of substrate crystal defects during the epitaxial growth process, and improving the antistatic performance.

[0016] 2. The present invention introduces an N-type high-frequency barrier capacitance region between the N-type confinement layer and the multi-quantum well active layer, and a P-type high-frequency barrier capacitance region structure between the P-type confinement layer and the multi-quantum well active layer. Through the high-barrier Al 0.5 In 0.5 P material and the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials grow alternately to form a barrier capacitance region with high-frequency response and carrier injection, which can balance the width of the PN junction depletion region, effectively solve the problem of weak antistatic ability caused by the too large depletion layer width in conventional LEDs, and at the same time avoid potential hazards such as reverse leakage caused by too narrow depletion layers, improving the antistatic performance and reliability of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of a conventional quaternary AlGaInP-based LED epitaxial wafer; Figure 2 It is a schematic diagram of the structure of the LED epitaxial wafer of the present invention; Figure 3 It is an SEM image of a conventional quaternary AlGaInP-based LED epitaxial wafer; Figure 4 It is an SEM image of the LED epitaxial wafer of the present invention.

[0018] Explanation of the reference numerals in the schematic diagram: 100, GaAs substrate; 101, buffer layer; 102, N-type confinement layer; 103, multi-quantum well active layer; 104, P-type confinement layer; 105, P-type transition layer; 106, P-type window layer; 107, secondary nucleation layer; 108, N-type high-frequency barrier capacitance region; 109, P-type high-frequency barrier capacitance region. DETAILED DESCRIPTION OF THE INVENTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present application and its application or use. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0020] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Without further statement, these terms have no special meaning, so they cannot be construed as limiting the scope of protection of the present application.

[0021] In the description of the present application, it should be understood that the orientation or positional relationships indicated by orientation words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationships shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description. Without contrary description, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, so they cannot be construed as limiting the scope of protection of the present application; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0022] Please refer to Figures 1 to 4 , it should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0023] In one embodiment of the present invention, an LED epitaxial wafer with improved antistatic ability is provided. The schematic structural diagram is as Figure 2 shown. The LED epitaxial wafer sequentially includes a GaAs substrate 100, a secondary nucleation layer 107, a buffer layer 101, an N-type confinement layer 102, an N-type high-frequency barrier capacitance region 108, a multi-quantum well active layer 103, a P-type high-frequency barrier capacitance region 109, a P-type confinement layer 104, a P-type transition layer 105, and a P-type window layer 106 from bottom to top.

[0024] In some embodiments, the material of the secondary nucleation layer is GaAs, which is a single crystal GaAs layer formed by the in-situ secondary nucleation of the combination of Ga left after the treatment of the surface self-defect layer of the GaAs substrate and As in the external source gas AsH3. Among them, the flow rate of AsH3 is 300 sccm to 500 sccm, the time of secondary nucleation is 3 min to 5 min, and the thickness is 10 nm to 50 nm. The newly introduced AsH3 can be cracked and recombined with the liquid Ga vacancies on the substrate surface to form a flat and orderly GaAs crystal layer, enabling the secondary nucleation of Ga and As after the evaporation of As on the GaAs substrate surface, forming a complete and defect-free GaAs surface layer, providing guarantee for the subsequent epitaxial crystal growth and reducing the defect density.

[0025] In some embodiments, the material of the buffer layer is GaAs, the doping material is SiH4, and the doping concentration is 3.0×10 18 cm -3 ~5.0×10 18 cm -3 , and the thickness is 100 nm to 300 nm.

[0026] In some embodiments, the material of the N-type confinement layer is Al 0.5 In 0.5 P, the doping concentration is 1×10 18 cm -3 ~2×10 18 cm -3 , using SiH4 as the dopant, and the thickness is 200 nm to 500 nm.

[0027] In some embodiments, the material of the N-type high-frequency barrier capacitance region is a periodic structure of alternating growth of Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 P. The number of cycle logarithms is 5 to 10 pairs, the value range of x1 is 0.1 to 0.3. In each cycle, the thickness of the Al 0.5 In 0.5 P layer is 12 nm to 18 nm, and the thickness of the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer is 20 nm to 30 nm. The doping concentrations of both the Al 0.5 In 0.5 P and the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are both 2×10 18 cm-3 ~3×10 18 cm -3 , SiH4 is used as the N-type dopant for all, and a barrier capacitance region with high-frequency response and carrier injection is formed by alternating growth, achieving the effect of balancing the width of the PN junction depletion region.

[0028] In some embodiments, the multi-quantum well active layer has a quantum well / quantum barrier structure of 15 to 20 pairs, where the materials of the quantum well layer / quantum barrier layer are both AlGaInP; specifically, the material of the quantum well layer is (Al y1 Ga 1-y1 ) 0.5 In 0.5 P, the thickness of a single quantum well is 5 nm to 7 nm, and the value range of y1 is 0.04 to 0.08; the material of the quantum barrier layer is (Al y2 Ga 1-y2 ) 0.5 In 0.5 P, the thickness of a single barrier is 9 nm to 12 nm, the value range of y2 is 0.6 to 0.8, and both the quantum well / quantum barrier are undoped.

[0029] In some embodiments, the material of the P-type high-frequency barrier capacitance region is an alternating periodic structure of Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 P, the number of cycle pairs is 5 to 10 pairs, the value range of x1 is 0.1 to 0.3, the thickness of the Al 0.5 In 0.5 P layer in each cycle is 12 nm to 18 nm, and the thickness of the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer in each cycle is 20 nm to 30 nm. The doping concentrations of both Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are 1×10 18 cm -3 ~2×10 18 cm -3 , and Cp2Mg is used as the P-type dopant for all. An alternating growth forms a barrier capacitance region with high-frequency response and carrier injection, achieving the effect of balancing the width of the PN junction depletion region.

[0030] In some embodiments, the material of the P-type confinement layer is Al0.5 In 0.5 P, with a doping concentration of 0.5×10 18 cm -3 ~1×10 18 cm -3 , using Cp2Mg as the dopant, with a thickness of 500 nm to 1000 nm.

[0031] In some embodiments, the material of the P-type transition layer is (Al y3 Ga 1-y3 ) 0.5 In 0.5 P, with a thickness of 10 nm to 30 nm, the dopant is Cp2Mg, and the doping concentration is 2×10 18 cm -3 ~3×10 18 cm -3 , and the value range of y3 is 0.15 to 0.35.

[0032] In some embodiments, the material of the P-type window layer is GaP, with a thickness of 3000 nm to 5000 nm, the dopant is CP2Mg, and the doping concentration is 2×10 18 cm -3 ~5×10 18 cm -3 .

[0033] In yet another embodiment, the present invention further provides a method for preparing an LED epitaxial wafer for improving antistatic ability. Using an MOCVD device on a GaAs substrate, the surface of the GaAs substrate is treated with self-defect layers in a gradient manner, and then in-situ secondary nucleation is performed to form a secondary nucleation layer, and then a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitance region, a multi-quantum well active region, a P-type high-frequency barrier capacitance region, a P-type confinement layer, a P-type transition layer, and a P-type window layer are sequentially grown. Specifically, it includes the following steps: (1)Substrate surface self-defect layer treatment: The MOCVD is evacuated to a low pressure of 50 mbar in a pure H2 atmosphere, and the reaction chamber is set at a temperature of 400 °C. Subsequently, the GaAs substrate is transferred to the reaction chamber through the transfer chamber of the manipulator. Then, a mixed gas of H2 and N2 is introduced into the MOCVD reaction chamber. The reaction chamber is set at a temperature of 780 °C to 800 °C. Starting from the introduction of the mixed gas, the pressure in the reaction chamber gradually rises from 10 mbar to 50 mbar, and the rate of pressure change is 5 mbar / min to 10 mbar / min. The flow rate of H2 is set at 15000 sccm to 20000 sccm, and the flow rate of N2 is set at 1500 sccm to 2000 sccm. The time for pressure change is 5 min to 8 min. By adopting the method of gradually changing the temperature and pressure from high temperature to low pressure, the As on the GaAs substrate volatilizes under the action of unsaturated As pressure and high temperature, and the Ga atoms remain in situ on the GaAs substrate in a liquid state. The mixed gas of high-speed and large-flow H2 and N2 can ensure that H atoms combine with the volatilized As atoms and are evacuated from the reaction chamber under the action of N2 as a carrier gas. Finally, the surface oxide layer and crystal defects of GaAs are removed on the substrate surface by a non-chemical etching method, effectively avoiding the formation of leakage channels due to the proliferation of crystal defects during the epitaxial growth process and improving the antistatic performance; (2)Substrate secondary nucleation: After the pressure in the reaction chamber during the substrate self-defect layer treatment rises to 50 mbar, the introduction of N2 is closed, and the pressure in the reaction chamber is maintained stable at 50 mbar. At the same time, AsH3 gas with a flow rate of 300 sccm to 500 sccm is introduced for 3 min to 5 min. The newly introduced AsH3 can be cracked and recombined with the liquid Ga vacancies on the substrate surface to form a flat and orderly GaAs crystal layer, enabling the Ga and As on the GaAs substrate surface to undergo secondary nucleation after As volatilization, forming a complete and defect-free GaAs surface layer, providing a guarantee for subsequent epitaxial crystal growth and reducing the defect density; (3)Growth of buffer layer: The reaction chamber is set at a temperature of 730 °C ± 20 °C, and TMGa and AsH3 are introduced to grow a GaAs buffer layer material with a thickness of 100 nm to 300 nm. SiH4 is used as an N-type dopant with a doping concentration of 3×10 18 cm -3 ~5×10 18 cm -3 ; (4)Growth of N-type confinement layer: The reaction chamber is set at a temperature of 730 °C ± 20 °C, and TMAl, TMIn, and PH3 are introduced to grow an Al 0.5 In 0.5 P material with a thickness of 200 nm to 500 nm. The doping concentration is 1×10 18 cm -3 ~2×10 18cm -3 , the N-type dopant is SiH4; (5) Growing the N-type high-frequency barrier capacitance region: Set the reaction chamber temperature to 730 °C ± 20 °C. Introduce TMAl, TMIn, and PH3 onto the N-type confinement layer to grow an Al 0.5 In 0.5 P material with a thickness of 12 nm to 18 nm, and use SiH4 as the dopant with a doping concentration of 2×10 18 cm -3 ~3×10 18 cm -3 ; Then introduce TMGa to grow an (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material with a thickness of 20 nm to 30 nm, where the value range of x1 is 0.1 to 0.3, and use SiH4 as the dopant with a doping concentration of 2×10 18 cm -3 ~3×10 18 cm -3 , and the above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are alternately and periodically grown in a cycle to form the N-type high-frequency barrier capacitance region, and the number of cycle pairs is 5 to 10 pairs; (6) Growing the multi-quantum well active layer: Set the reaction chamber temperature to 710 °C ± 20 °C. Introduce TMGa, TMAl, TMIn, and PH3 to grow quantum well layers and quantum barrier layers of (Al y1 Ga 1-y1 ) 0.5 In 0.5 P and (Al y2 Ga 1-y2 ) 0.5 In 0.5 P materials, where the thickness of a single quantum well is 5 nm to 7 nm, the value range of y1 is 0.04 to 0.08, the thickness of a single quantum barrier is 9 nm to 12 nm, the value range of y2 is 0.6 to 0.8, the number of periods is 15 to 20 pairs, and the quantum well / quantum barrier is undoped; (7) Growing the P-type high-frequency barrier capacitance region: Set the reaction chamber temperature to 730 °C ± 20 °C. Introduce TMAl, TMIn, and PH3 onto the multi-quantum well active layer to grow an Al 0.5 In 0.5 P material with a thickness of 12 nm to 18 nm, and use Cp2Mg as the dopant with a doping concentration of 1×10 18cm -3 ~2×10 18 cm -3 , and then introduce TMGa to grow an (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material with a growth thickness of 20 nm to 30 nm. The value range of x1 is 0.1 to 0.3, and Cp2Mg is used as a dopant with a doping concentration of 1×10 18 cm -3 ~2×10 18 cm -3 . The above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are alternately and periodically grown in a cycle to form a P-type high-frequency barrier capacitance region, and the number of cycle logarithms is 5 to 10 pairs; (8) Grow a P-type confinement layer: Set the temperature of the reaction chamber to 730 °C ± 20 °C, introduce TMAl, TMIn, and PH3, and grow an Al 0.5 In 0.5 P material with a growth thickness of 500 nm to 1000 nm and a doping concentration of 0.5×10 18 cm -3 ~1×10 18 cm -3 . The P-type dopant is Cp2Mg; (9) Grow a P-type transition layer: Set the temperature of the reaction chamber to 730 °C ± 20 °C, introduce TMGa, TMAl, TMIn, and PH3, and grow an (Al y3 Ga 1-y3 ) 0.5 In 0.5 P material with a growth thickness of 10 nm to 30 nm. The dopant is Cp2Mg with a doping concentration of 2×10 18 cm -3 ~3×10 18 cm -3 . The value range of y3 is 0.15 to 0.35; (10) Grow a P-type window layer: Set the temperature of the reaction chamber to 660 °C ± 20 °C, introduce TMGa and PH3, and grow a GaP material with a growth thickness of 3000 nm to 5000 nm. Use CP2Mg as the P-type dopant with a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 ; (11)Wafer picking: After the growth is completed, the temperature of the MOCVD reaction chamber is reduced to 110 °C, then the pressure is adjusted to 1000 mbar, the reaction chamber is opened, and the epitaxial wafer is taken out.

[0034] To further illustrate the present invention, the present invention will be described in detail below in conjunction with specific embodiments.

[0035] Embodiment 1 A method for preparing an LED epitaxial wafer with improved antistatic ability specifically includes the following steps: (1)Substrate surface self-defect layer treatment: The MOCVD is evacuated to a low pressure of 50 mbar in a pure H2 atmosphere, the set temperature of the reaction chamber is 400 °C, then the GaAs substrate is transferred to the reaction chamber through the transfer chamber of the manipulator, and then a mixed gas of H2 and N2 is introduced into the MOCVD reaction chamber. The set temperature of the reaction chamber is 780 °C. Starting from the introduction of the mixed gas, the pressure of the reaction chamber gradually rises from 10 mbar to 50 mbar, and the rate of pressure change is 5 mbar / min. The flow rate of H2 is set to 20000 sccm, and the flow rate of N2 is set to 2000 sccm. The time for pressure change is 8 min; (2)Substrate secondary nucleation: After the pressure in the reaction chamber during the substrate self-defect layer treatment rises to 50 mbar, the introduction of N2 is closed, the pressure in the reaction chamber is maintained stable at 50 mbar, and at the same time, AsH3 gas with a flow rate of 500 sccm is introduced for 5 min; (3)Growth of buffer layer: The set temperature of the reaction chamber is 730 °C, TMGa and AsH3 are introduced, and a GaAs buffer layer material with a thickness of 300 nm is grown. SiH4 is used as the N-type dopant, and the doping concentration is 3×10 18 cm -3 ; (4)Growth of N-type confinement layer: The set temperature of the reaction chamber is 730 °C, TMAl, TMIn, and PH3 are introduced, and an Al 0.5 In 0.5 P material with a thickness of 500 nm is grown, and the doping concentration is 2×10 18 cm -3 , and the N-type dopant is SiH4; (5)Growth of N-type high-frequency barrier capacitance region: The set temperature of the reaction chamber is 730 °C, TMAl, TMIn, and PH3 are introduced on the N-type confinement layer, and an Al 0.5 In 0.5 P material with a thickness of 12 nm is grown, and SiH4 is used as the dopant with a doping concentration of 2×10 18 cm -3 ; Then TMGa is introduced, and an (Al 0.3 Ga0.7 ) 0.5 In 0.5 P material, and using SiH4 as a dopant with a doping concentration of 2×10 18 cm -3 , the above-mentioned Al 0.5 In 0.5 P and (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P materials are alternately and periodically grown in a cycle to form an N-type high-frequency barrier capacitance region, and the number of cycle logarithms is 10 pairs; (6) Growing a multi-quantum well active layer: Set the temperature of the reaction chamber to 700 °C, and introduce TMGa, TMAl, TMIn, and PH3. The quantum well layer and the quantum barrier layer are respectively (Al 0.06 Ga 0.94 ) 0.5 In 0.5 P, (Al 0.8 Ga 0.2 ) 0.5 In 0.5 P materials, where the thickness of a single quantum well is 5 nm to 7 nm, the thickness of a single quantum barrier is 12 nm, the number of periods is 15 pairs, and the quantum well / quantum barrier is undoped; (7) Growing a P-type high-frequency barrier capacitance region: Set the temperature of the reaction chamber to 730 °C, introduce TMAl, TMIn, and PH3 on the multi-quantum well active layer, and grow an Al 0.5 In 0.5 P material with a thickness of 12 nm, and use Cp2Mg as a dopant with a doping concentration of 1×10 18 cm -3 , then introduce TMGa and grow a (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P material with a thickness of 20 nm, and use Cp2Mg as a dopant with a doping concentration of 1×10 18 cm -3 , the above-mentioned Al 0.5 In 0.5 P and (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P materials are alternately and periodically grown in a cycle to form a P-type high-frequency barrier capacitance region, and the number of cycle logarithms is 10 pairs; (8) Growing a P-type confinement layer: Set the temperature of the reaction chamber to 730 °C, introduce TMAl, TMIn, and PH3, and grow an Al 0.5 In 0.5P material, with a doping concentration of 0.5×10 18 cm -3 , and the P-type dopant is Cp2Mg; (9) Growing a P-type transition layer: Set the temperature of the reaction chamber to 730 °C, introduce TMGa, TMAl, TMIn, and PH3, and grow a (Al 0.15 Ga 0.85 ) 0.5 In 0.5 P material with a dopant of Cp2Mg and a doping concentration of 3×10 18 cm -3 ; (10) Growing a P-type window layer: Set the temperature of the reaction chamber to 680 °C, introduce TMGa and PH3, and grow a GaP material with a thickness of 5000 nm. Use CP2Mg as the P-type dopant with a doping concentration of 5×10 18 cm -3 .

[0036] (11) Taking the wafer: After the growth is completed, lower the temperature of the MOCVD reaction chamber to 110 °C, then adjust the pressure to 1000 mbar, open the reaction chamber, and take out the epitaxial wafer.

[0037] Comparative Example 1 A conventional quaternary AlGaInP-based LED epitaxial wafer is prepared by a conventional method, and its structural schematic diagram is as Figure 1 shown.

[0038] Test Example 1. Observe the LED epitaxial wafers obtained in Comparative Example 1 and Example 1 under a scanning electron microscope (magnification: 10000 times), and the results are as Figure 3 and Figure 4 shown. It can be seen from Figure 3 that there are lattice defects on the surface of the substrate of the conventional quaternary AlGaInP-based LED epitaxial wafer (the positions marked by the red dotted line). As the epitaxial growth proceeds, the defects continue to extend upward, forming a leakage channel, which is easily electrostatically broken down, resulting in a decrease in the antistatic ability of the LED; while Figure 4 in the LED epitaxial layer obtained in Example 1 of the present invention, the crystal growth quality is improved, and the epitaxial layer is clear and complete without defects causing leakage channels.

[0039] 2. For the LEDs obtained in Comparative Example 1 and Example 1, in different high-voltage electrostatic discharge ESD tests, the passing rate of chip testing, where the test conditions and results are shown in Table 1.

[0040] Table 1

[0041] As can be seen from the results in Table 1, the LED prepared in Example 1 of the present invention can still maintain a 95% ESD passing rate in the 5000V test, while the passing rate of the conventional quaternary AlGaInP-based LED in the 2000V test is only 64%, indicating that the antistatic performance of the LED prepared by the method of the present invention has been greatly improved.

[0042] Finally, it should be emphasized that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An LED epitaxial wafer for improving antistatic ability, characterized in that, The LED epitaxial wafer sequentially includes a GaAs substrate, a secondary nucleation layer, a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitance region, a multi-quantum well active layer, a P-type high-frequency barrier capacitance region, a P-type confinement layer, a P-type transition layer, and a P-type window layer from bottom to top; The secondary nucleation layer is a GaAs single crystal layer formed by in-situ secondary nucleation of the combination of Ga atoms remaining after surface self-defect layer treatment of the GaAs substrate and As atoms in the external source gas AsH3.

2. The LED epitaxial wafer for improving antistatic ability according to claim 1, characterized in that, The thickness of the secondary nucleation layer is 10 nm to 50 nm.

3. The LED epitaxial wafer for improving antistatic ability according to claim 1, characterized in that, The materials of the N-type high-frequency barrier capacitance region and the P-type high-frequency barrier capacitance region are both Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 P is a periodically grown structure with 5 to 10 pairs of periodic structures. In each periodic structure, the thickness of the Al 0.5 In 0.5 P layer is 12 nm to 18 nm, and the thickness of the (Al x1 Ga 1-x1 ) 0.5 In 0.5 P layer is 20 nm to 30 nm, where the value range of x1 is 0.1 to 0.

3.

4. The LED epitaxial wafer for improving antistatic ability according to claim 3, characterized in that, In the N-type high-frequency barrier capacitance region, Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials have a doping concentration of 2×10 18 cm -3 ~3×10 18 cm -3 , and SiH4 is used as the N-type dopant for all of them.

5. The LED epitaxial wafer for improving antistatic ability according to claim 3, characterized in that, In the P-type high-frequency barrier capacitance region, Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials have a doping concentration of 1×10 18 cm -3 ~2×10 18 cm -3 , and Cp2Mg is used as the P-type dopant for all of them.

6. A method for preparing an LED epitaxial wafer for improving antistatic ability according to any one of claims 1 to 5, characterized in that, Using an MOCVD device on a GaAs substrate, the surface of the GaAs substrate is subjected to self-defect layer treatment in a gradient manner, and then a secondary nucleation layer is formed by in-situ secondary nucleation, and then a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitance region, a multi-quantum well active layer, a P-type high-frequency barrier capacitance region, a P-type confinement layer, a P-type transition layer, and a P-type window layer are sequentially grown.

7. The method for preparing an LED epitaxial wafer for improving antistatic ability according to claim 6, characterized in that, The method of self-defect layer treatment is: set the initial pressure of the reaction chamber to 10 mbar, set the reaction chamber temperature to 780 °C to 800 °C, introduce a mixed gas of H2 and N2 on the surface of the GaAs substrate, set the flow rate of H2 to 15000 sccm to 20000 sccm, set the flow rate of N2 to 1500 sccm to 2000 sccm, the pressure of the reaction chamber starts from the introduction of the mixed gas and gradually changes from 10 mbar to 50 mbar, the rate of pressure gradient is 5 mbar / min to 10 mbar / min, and the time of pressure change is 5 min to 8 min.

8. The method for preparing an LED epitaxial wafer for improving antistatic ability according to claim 6, characterized in that, The method of in-situ secondary nucleation is: when the pressure of the reaction chamber for self-defect layer treatment reaches 50 mbar, the introduction of N2 is closed, the pressure of the reaction chamber is maintained stable at 50 mbar, and at the same time, AsH3 gas with a flow rate of 300 sccm to 500 sccm is introduced, and the introduction time is 3 min to 5 min.

9. The method for preparing an LED epitaxial wafer for improving antistatic ability according to claim 6, characterized in that, The growth steps of the N-type high-frequency barrier capacitance region are as follows: set the reaction chamber temperature to 730 °C ± 20 °C, introduce TMAl, TMIn, and PH3 onto the N-type confinement layer to grow an Al 0.5 In 0.5 P material with a thickness of 12 nm to 18 nm, and use SiH4 as a dopant, then introduce TMGa to grow an (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material with a thickness of 20 nm to 30 nm, where the value range of x1 is 0.1 to 0.3, and use SiH4 as a dopant. The above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are alternately and periodically grown in cycles to form the N-type high-frequency barrier capacitance region, and the number of cycle pairs is 5 to 10 pairs.

10. The method for preparing an LED epitaxial wafer for improving antistatic ability according to claim 6, characterized in that, The growth steps of the P-type high-frequency barrier capacitance region are as follows: Set the reaction chamber temperature to 730°C ± 20°C, introduce TMAl, TMIn, and PH3 onto the multi-quantum well active layer to grow an Al 0.5 In 0.5 P material, and use Cp2Mg as a dopant, then introduce TMGa to grow an (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, where the value range of x1 is 0.1 to 0.3, and use Cp2Mg as a dopant. The above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 P materials are alternately and periodically grown in cycles to form the P-type high-frequency barrier capacitance region, and the number of cycle pairs is 5 to 10 pairs.

Images