An LED epitaxial wafer with improved antistatic ability and preparation method thereof

Abstract

The present invention relates to the field of LED technology, and more specifically to an LED epitaxial wafer with improved antistatic capabilities and a method for preparing the same. The LED epitaxial wafer comprises, from bottom to top, a GaAs substrate, a secondary nucleation layer, a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type confinement layer, a P-type transition layer, and a P-type window layer; the secondary nucleation layer is a GaAs single crystal layer formed by in-situ secondary nucleation of Ga atoms remaining after surface self-defect layer treatment of the GaAs substrate and As atoms in an exogenous gas, AsH3. The present invention forms a complete and defect-free GaAs surface layer by performing a substrate surface self-defect layer treatment on the GaAs substrate and adopting a method of secondary nucleation of Ga broken bonds on the substrate surface and As atoms, thereby effectively avoiding the formation of leakage channels due to the proliferation of substrate crystal defects during epitaxial growth and improving antistatic performance.

Description

Technical Field

[0001] The present invention relates to the technical field of LEDs, and in particular to an LED epitaxial wafer with improved antistatic capability and a preparation method thereof. Background Art

[0002] Light-emitting diodes (LEDs) have the advantages of high brightness, low power consumption, and high reliability, and have been widely used in solid-state lighting and display markets. LEDs made of quaternary AlGaInP materials are widely used in backlight sources, scene lighting, landscape lighting, and other fields. As the application scenarios of LED products become more and more diverse, antistatic performance has become a very important parameter indicator of LEDs. The schematic diagram of the epitaxial wafer structure of a conventional quaternary AlGaInP LED is as follows: Figure 1 As shown, from bottom to top, it includes a GaAs substrate 100, a buffer layer 101, an N-type confinement layer 102, a multi-quantum well active layer 103, a P-type confinement layer 104, a P-type transition layer 105, and a P-type window layer 106. However, due to the influence of unstable crystal nucleation between the GaAs substrate surface and the epitaxial layer, lattice defects are easily generated. As the crystal grows, the defects continue to extend upward, forming leakage channels that are easily broken down by static electricity, resulting in a decrease in the anti-static ability of the LED. At the same time, conventional LED epitaxial wafer structures generally use a multi-quantum well active layer, and the width of the depletion region in the PN junction is large, resulting in a decrease in barrier capacitance and a weakening of the anti-static ability. Due to the above shortcomings, conventional quaternary AlGaInP-based LEDs cannot achieve a high level of anti-static performance. Therefore, it is of great significance to develop an LED with high anti-static performance. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the present invention provides an LED epitaxial wafer with improved antistatic capability and a preparation method thereof, which can effectively improve the problem of poor antistatic capability of conventional quaternary AlGaInP-based LEDs.

[0004] The first object of the present invention is to provide an LED epitaxial wafer with improved antistatic capability, wherein the LED epitaxial wafer comprises, from bottom to top, a GaAs substrate, a secondary nucleation layer, a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type confinement layer, a P-type transition layer, and a P-type window layer;

[0005] The secondary nucleation layer is a GaAs single crystal layer formed by in-situ secondary nucleation of Ga atoms remaining after the surface defect layer of the GaAs substrate is treated and combined with As atoms in the external gas AsH3.

[0006] Furthermore, the thickness of the secondary nucleation layer is 10 nm to 50 nm.

[0007] Furthermore, the materials of the N-type high-frequency barrier capacitor region and the P-type high-frequency barrier capacitor region are both Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 P alternately grows in a periodic structure, the number of pairs of periodic structures is 5 to 10 pairs, in each periodic structure, Al 0.5 In 0.5 The thickness of the P layer is 12nm to 18nm. x1 Ga 1-x1 ) 0.5 In 0.5 The thickness of the P layer is 20nm to 30nm, and the value range of x1 is 0.1 to 0.3. In this technical solution, an N-type high-frequency barrier capacitor region is introduced between the N-type confinement layer and the multi-quantum well active layer, and a P-type high-frequency barrier capacitor region is introduced between the P-type confinement layer and the multi-quantum well active layer. 0.5 In 0.5 P materials with high mobility and high dielectric constant (Al x1 Ga 1-x1 ) 0.5 In 0.5 The P material grows alternately to form a barrier capacitance region with high-frequency response and carrier injection, achieving the effect of balancing the width of the PN junction depletion region. This not only solves the problem of weak antistatic ability caused by the large depletion layer width in conventional LEDs, but also avoids hidden dangers such as reverse leakage caused by the depletion layer being too narrow, effectively improving the antistatic performance and reliability of the LED chip.

[0008] Furthermore, the Al in the N-type high-frequency barrier capacitor region 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The doping concentration of P materials is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

[0009] Furthermore, the Al in the P-type high-frequency barrier capacitor region 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The doping concentration of P materials is 1×10 18 cm -3~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

[0010] The present invention forms a complete and defect-free GaAs surface layer by performing a treatment on the surface of a GaAs substrate to eliminate the self-defect layer on the substrate and adopting a secondary nucleation method for a GaAs single crystal layer formed by the combination of broken Ga bonds on the substrate surface and As atoms. This provides a guarantee for subsequent epitaxial crystal growth, effectively avoids the formation of leakage channels due to the proliferation of substrate crystal defects during the epitaxial growth process, and improves the antistatic performance. At the same time, a high-frequency barrier capacitor region structure is introduced on both sides of the multi-quantum well active layer to balance the width of the PN junction depletion region, further improving the antistatic performance of the LED chip.

[0011] The second object of the present invention is to provide a method for preparing an LED epitaxial wafer with improved antistatic properties, using MOCVD equipment on a GaAs substrate to perform a self-defect layer treatment on the surface of the GaAs substrate in a gradual manner, then performing in-situ secondary nucleation to form a secondary nucleation layer, and then sequentially growing a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type confinement layer, a P-type transition layer, and a P-type window layer.

[0012] Furthermore, the method for treating the self-defect layer is as follows: setting the starting pressure of the reaction chamber to 10 mbar, the temperature of the reaction chamber to 780°C~800°C, introducing a mixed gas of H2 and N2 on the surface of the substrate, the flow rate of H2 is set to 15000 sccm~20000 sccm, the flow rate of N2 is set to 1500 sccm~2000 sccm, the pressure of the reaction chamber gradually changes from 10 mbar to 50 mbar starting from the introduction of the mixed gas, the pressure gradient rate is 5 mbar / min~10 mbar / min, and the pressure change time is 5 min~8 min. Due to the presence of oxide layers and lattice defects on the surface of the GaAs substrate, this technical solution uses a high-temperature, low-pressure gradient method to volatilize the As in the GaAs substrate under the action of unsaturated As pressure and high temperature, and the Ga atoms remain in the original position of the GaAs substrate in liquid form. Under the high-speed, large-flow mixed gas of H2 and N2, it can ensure that the H atoms in the carrier gas combine with the As atoms volatilized from the substrate and are extracted from the reaction chamber under the action of N2 as a carrier gas, thereby leaving the Ga atoms with broken bonds to prepare for subsequent secondary nucleation. This technology can remove the surface oxide layer and crystal defects of GaAs on the substrate surface by non-chemical etching methods, effectively avoiding the formation of leakage channels due to the proliferation of crystal defects during epitaxial growth, and improving the antistatic performance.

[0013] Furthermore, the in-situ secondary nucleation method is as follows: when the pressure of the reaction chamber treated from the defect layer reaches 50mbar, the N2 is turned off to maintain the reaction chamber pressure stable at 50mbar, and AsH3 gas is introduced at a flow rate of 300sccm to 500sccm for 3min to 5min. After reaching a certain pressure, the newly introduced AsH3 is cracked and can be recombined with the liquid Ga vacancies on the substrate surface to form a flat and orderly GaAs crystal layer, so that the Ga and As left after the As volatilization on the GaAs substrate surface are secondary nucleated to form a complete and defect-free GaAs surface layer, which provides a guarantee for subsequent epitaxial crystal growth, reduces defect density, and improves antistatic performance.

[0014] Furthermore, the growth step of the N-type high frequency barrier capacitor region is as follows: setting the reaction chamber temperature to 730°C ± 20°C, introducing TMAl, TMIn, and PH3 on the N-type confinement layer, and growing Al with a thickness of 12nm to 18nm. 0.5 In 0.5 P material, and SiH4 is used as a dopant, and then TMGa is introduced to grow (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, the value range of x1 is 0.1~0.3, and SiH4 is used as dopant. 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The P material is grown alternately and periodically to form an N-type high-frequency barrier capacitor region, and the number of cycle pairs is 5 to 10 pairs.

[0015] Furthermore, the growth step of the P-type high-frequency barrier capacitor region is as follows: setting the reaction chamber temperature to 730°C ± 20°C, introducing TMAl, TMIn, and PH3 into the multi-quantum well active layer, and growing Al with a thickness of 12nm to 18nm. 0.5 In 0.5 P material, and use Cp2Mg as dopant, then introduce TMGa, grow (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, the value range of x1 is 0.1~0.3, and Cp2Mg is used as dopant. 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In0.5 The P material grows alternately and periodically to form a P-type high-frequency barrier capacitor region, and the number of cycle pairs is 5 to 10 pairs.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. In the epitaxial growth of conventional quaternary AlGaInP-based LEDs, the present invention performs a substrate surface self-defect layer treatment on the GaAs substrate and adopts a method of secondary nucleation of Ga bonds on the substrate surface and As atoms to form a complete and defect-free GaAs surface layer. This effectively avoids the formation of leakage channels due to the proliferation of substrate crystal defects during the epitaxial growth process, thereby improving the antistatic performance.

[0018] 2. The present invention introduces an N-type high-frequency barrier capacitor region between the N-type confinement layer and the multi-quantum well active layer, and introduces a P-type high-frequency barrier capacitor region structure between the P-type confinement layer and the multi-quantum well active layer, through the high-potential barrier Al 0.5 In 0.5 P materials with high mobility and high dielectric constant (Al x1 Ga 1-x1 ) 0.5 In 0.5 The alternating growth of P materials forms a barrier capacitance region with high-frequency response and carrier injection, which can balance the width of the PN junction depletion region, effectively solving the problem of weak anti-static ability caused by the large depletion layer width in conventional LEDs. At the same time, it also avoids hidden dangers such as reverse leakage caused by the depletion layer being too narrow, thereby improving the anti-static performance and reliability of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the structure of a conventional quaternary AlGaInP LED epitaxial wafer;

[0020] Figure 2 This is a schematic diagram of the LED epitaxial wafer structure of the present invention;

[0021] Figure 3 This is the SEM image of a conventional quaternary AlGaInP LED epitaxial wafer;

[0022] Figure 4 This is a SEM image of the LED epitaxial wafer of the present invention.

[0023] Description of the numbers in the schematic diagram:

[0024] 100. GaAs substrate; 101. buffer layer; 102. N-type confinement layer; 103. multi-quantum well active layer; 104. P-type confinement layer; 105. P-type transition layer; 106. P-type window layer; 107. secondary nucleation layer; 108. N-type high-frequency barrier capacitor region; 109. P-type high-frequency barrier capacitor region. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0026] In the description of this application, it should be understood that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0027] In the description of this application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of this application; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0028] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component can be changed at will, and the component layout may also be more complicated.

[0029] In one embodiment of the present invention, an LED epitaxial wafer with improved antistatic capability is provided, and its structural schematic diagram is shown as follows: Figure 2 As shown, the LED epitaxial wafer includes, from bottom to top, a GaAs substrate 100, a secondary nucleation layer 107, a buffer layer 101, an N-type confinement layer 102, an N-type high-frequency barrier capacitor region 108, a multi-quantum well active layer 103, a P-type high-frequency barrier capacitor region 109, a P-type confinement layer 104, a P-type transition layer 105, and a P-type window layer 106.

[0030] In some embodiments, the material of the secondary nucleation layer is GaAs, which is a GaAs single crystal layer formed by in-situ secondary nucleation of Ga left after the surface defect layer of the GaAs substrate is treated and As in the exogenous gas AsH3. The flow rate of AsH3 is 300sccm to 500sccm, the time of secondary nucleation is 3min to 5min, and the thickness is 10nm to 50nm. The newly introduced AsH3 can be decomposed and recombined with the liquid Ga vacancies on the surface of the substrate to form a flat and orderly GaAs crystal layer, so that the Ga and As after the volatilization of As on the surface of the GaAs substrate are secondary nucleated to form a complete and defect-free GaAs surface layer, which provides a guarantee for subsequent epitaxial crystal growth and reduces the defect density.

[0031] In some embodiments, the buffer layer is made of GaAs, the doping material is SiH4, and the doping concentration is 3.0×10 18 cm -3 ~5.0×10 18 cm -3 , with a thickness of 100nm to 300nm.

[0032] In some embodiments, the material of the N-type confinement layer is Al 0.5 In 0.5 P, doping concentration is 1×10 18 cm -3 ~2×10 18 cm -3 , SiH4 is used as the dopant, and the thickness is 200nm~500nm.

[0033] In some embodiments, the material of the N-type high frequency barrier capacitor region is Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 The periodic structure of P alternating growth has a cycle number of 5 to 10 pairs, and the value range of x1 is 0.1 to 0.3. In each cycle, Al 0.5 In 0.5 The thickness of the P layer is 12nm to 18nm. x1 Ga 1-x1 ) 0.5 In 0.5 The thickness of the P layer is 20nm to 30nm. 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The doping concentration of P materials is 2×10 18 cm-3 ~3×10 18 cm -3 , both use SiH4 as N-type dopant, and through alternating growth, a barrier capacitance region with high-frequency response and carrier injection is formed to achieve the effect of balancing the width of the PN junction depletion region.

[0034] In some embodiments, the multi-quantum well active layer has 15 to 20 pairs of quantum well / quantum barrier structures, wherein the materials of the quantum well layer / quantum barrier layer are AlGaInP; specifically, the material of the quantum well layer is (Al y1 Ga 1-y1 ) 0.5 In 0.5 The thickness of the single-layer well is 5nm to 7nm, and the value range of y1 is 0.04 to 0.08; the material of the quantum barrier layer is (Al y2 Ga 1-y2 ) 0.5 In 0.5 P, the thickness of the single-layer barrier is 9nm~12nm, the value range of y2 is 0.6~0.8, and the quantum wells / quantum barriers are all non-doped.

[0035] In some embodiments, the material of the P-type high frequency barrier capacitor region is Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 The periodic structure of P alternating growth has a cycle number of 5 to 10 pairs, and the value range of x1 is 0.1 to 0.3. In each cycle, Al 0.5 In 0.5 The thickness of the P layer is 12nm to 18nm. x1 Ga 1-x1 ) 0.5 In 0.5 The thickness of the P layer is 20nm to 30nm. 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The doping concentration of P materials is 1×10 18 cm -3 ~2×10 18 cm -3 , both use Cp2Mg as P-type dopant, and through alternating growth, a barrier capacitance region with high-frequency response and carrier injection is formed to achieve the effect of balancing the width of the PN junction depletion region.

[0036] In some embodiments, the material of the P-type confinement layer is Al0.5 In 0.5 P, doping concentration is 0.5×10 18 cm -3 ~1×10 18 cm -3 , Cp2Mg is used as the dopant, and the thickness is 500nm~1000nm.

[0037] In some embodiments, the material of the P-type transition layer is (Al y3 Ga 1-y3 ) 0.5 In 0.5 P, thickness is 10nm~30nm, dopant is Cp2Mg, doping concentration is 2×10 18 cm -3 ~3×10 18 cm -3 , the value range of y3 is 0.15~0.35.

[0038] In some embodiments, the material of the P-type window layer is GaP, the thickness is 3000nm to 5000nm, the dopant is CP2Mg, and the doping concentration is 2×10 18 cm -3 ~5×10 18 cm -3 .

[0039] In another embodiment, the present invention also provides a method for preparing an LED epitaxial wafer with improved antistatic capability, using MOCVD equipment on a GaAs substrate to perform a self-defect layer treatment on the surface of the GaAs substrate in a gradual manner, then performing in-situ secondary nucleation to form a secondary nucleation layer, and then sequentially growing a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type confinement layer, a P-type transition layer, and a P-type window layer. Specifically, the method comprises the following steps:

[0040] (1) Treatment of self-defect layer on substrate surface: The MOCVD is evacuated to 50 mbar in a pure H2 atmosphere, and the reaction chamber temperature is set at 400°C. The GaAs substrate is then transferred to the reaction chamber through a robot transfer bin, and a mixed gas of H2 and N2 is introduced into the MOCVD reaction chamber. The reaction chamber temperature is set at 780°C to 800°C. The pressure of the reaction chamber gradually increases from 10 mbar to 50 mbar starting from the introduction of the mixed gas, and the pressure gradient rate is 5 mbar / min to 10 mbar / min. The flow rate of H2 is set to 15000 sccm to 20000 sccm, and the flow rate of N2 is set to 1500 sccm to 2000 sccm. The pressure change time is 5 min to 8 min. The high-temperature and low-pressure gradient method is used to make the As in the GaAs substrate volatilize under the action of unsaturated As pressure and high temperature, and the Ga atoms remain in the original position of the GaAs substrate in liquid form. The high-speed, high-flow mixture of H2 and N2 ensures that H atoms combine with volatile As atoms and are extracted from the reaction chamber under the action of N2 as a carrier gas. Finally, a non-chemical etching method is used on the substrate surface to remove the surface oxide layer and crystal defects of GaAs, effectively avoiding the formation of leakage channels due to the proliferation of crystal defects during the epitaxial growth process and improving the antistatic performance.

[0041] (2) Secondary nucleation of substrate: When the pressure of the reaction chamber rises to 50 mbar during the process of treating the defect layer of the substrate, the N2 is turned off to maintain the pressure of the reaction chamber stable at 50 mbar. At the same time, AsH3 gas is introduced at a flow rate of 300 sccm to 500 sccm for 3 min to 5 min. The newly introduced AsH3 can be decomposed and recombined with the liquid Ga vacancies on the surface of the substrate to form a flat and orderly GaAs crystal layer, so that the Ga and As after the volatilization of As on the surface of the GaAs substrate are secondary nucleated to form a complete and defect-free GaAs surface layer, which provides a guarantee for the subsequent epitaxial crystal growth and reduces the defect density.

[0042] (3) Growth of buffer layer: The reaction chamber temperature was set to 730℃±20℃, TMGa and AsH3 were introduced, and GaAs buffer layer material with a thickness of 100nm to 300nm was grown. SiH4 was used as the N-type dopant with a doping concentration of 3×10 18 cm -3 ~5×10 18 cm -3 ;

[0043] (4) Growth of N-type confinement layer: Set the reaction chamber temperature to 730℃±20℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 200nm~500nm. 0.5 In 0.5 P material, doping concentration is 1×1018 cm -3 ~2×10 18 cm -3 , N-type dopant is SiH4;

[0044] (5) Growth of N-type high-frequency barrier capacitor region: Set the reaction chamber temperature to 730℃±20℃, introduce TMAl, TMIn, and PH3 into the N-type confinement layer, and grow Al with a thickness of 12nm~18nm. 0.5 In 0.5 P material, and SiH4 is used as the dopant with a doping concentration of 2×10 18 cm -3 ~3×10 18 cm -3 Then TMGa is introduced to grow (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, the value range of x1 is 0.1~0.3, and SiH4 is used as dopant with a doping concentration of 2×10 18 cm -3 ~3×10 18 cm -3 , the above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The P material grows alternately and periodically to form an N-type high-frequency barrier capacitor region, with the number of cycle pairs being 5 to 10 pairs.

[0045] (6) Growth of multi-quantum well active layer: Set the temperature of the reaction chamber to 710℃±20℃, introduce TMGa, TMAl, TMIn, and PH3, and grow quantum well layer and quantum barrier layer respectively (Al y1 Ga 1-y1 ) 0.5 In 0.5 P、(Al y2 Ga 1-y2 ) 0.5 In 0.5 P material, wherein the thickness of the single-layer well is 5nm to 7nm, the value range of y1 is 0.04 to 0.08, the thickness of the single-layer barrier is 9nm to 12nm, the value range of y2 is 0.6 to 0.8, the number of periods is 15 pairs to 20 pairs, and the quantum wells / quantum barriers are non-doped;

[0046] (7) Growth of P-type high-frequency barrier capacitor region: Set the reaction chamber temperature to 730℃±20℃, introduce TMAl, TMIn, and PH3 into the multi-quantum well active layer, and grow Al with a thickness of 12nm~18nm. 0.5 In 0.5 P material, and Cp2Mg is used as the dopant with a doping concentration of 1×10 18 cm -3 ~2×10 18 cm -3 , then introduce TMGa to grow (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, the value range of x1 is 0.1~0.3, and Cp2Mg is used as dopant with a doping concentration of 1×10 18 cm -3 ~2×10 18 cm -3 , the above Al 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The P material grows alternately and periodically to form a P-type high-frequency barrier capacitor region, with the number of cycle pairs being 5 to 10 pairs.

[0047] (8) Growth of P-type confinement layer: Set the reaction chamber temperature to 730℃±20℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 500nm~1000nm. 0.5 In 0.5 P material, doping concentration is 0.5×10 18 cm -3 ~1×10 18 cm -3 , the P-type dopant is Cp2Mg;

[0048] (9) Growth of P-type transition layer: Set the temperature of the reaction chamber to 730℃±20℃, introduce TMGa, TMAl, TMIn, and PH3, and grow (Al y3 Ga 1-y3 ) 0.5 In 0.5 P material, dopant is Cp2Mg, doping concentration is 2×10 18 cm -3 ~3×10 18 cm -3 , the value range of y3 is 0.15~0.35;

[0049] (10) Growth of P-type window layer: The reaction chamber temperature was set to 660℃±20℃, TMGa and PH3 were introduced, and GaP material with a thickness of 3000nm~5000nm was grown. CP2Mg was used as the P-type dopant with a doping concentration of 2×10 18 cm -3 ~5×10 18 cm -3 ;

[0050] (11) Taking out the wafer: After the growth is completed, the temperature of the MOCVD reaction chamber is lowered to 110℃, and then the pressure is adjusted to 1000mbar. The reaction chamber is opened and the epitaxial wafer is taken out.

[0051] In order to further illustrate the present invention, the present invention is described in detail below with reference to specific embodiments.

[0052] Example 1

[0053] A method for preparing an LED epitaxial wafer with improved antistatic capability comprises the following steps:

[0054] (1) Treatment of self-defect layer on substrate surface: The MOCVD was pumped down to 50 mbar in a pure H2 atmosphere, and the reaction chamber temperature was set at 400 °C. The GaAs substrate was then transferred to the reaction chamber through a robot transfer bin, and then a mixed gas of H2 and N2 was introduced into the MOCVD reaction chamber. The reaction chamber temperature was set at 780 °C. The pressure in the reaction chamber gradually increased from 10 mbar to 50 mbar from the time the mixed gas was introduced. The pressure gradient rate was 5 mbar / min, with the H2 flow rate set at 20,000 sccm and the N2 flow rate set at 2,000 sccm. The pressure change time was 8 min.

[0055] (2) Substrate secondary nucleation: When the reaction chamber pressure rises to 50 mbar during the process of substrate self-defect layer treatment, the N2 flow is turned off to maintain the reaction chamber pressure stable at 50 mbar, and AsH3 gas is introduced at a flow rate of 500 sccm for 5 min.

[0056] (3) Growth of buffer layer: The reaction chamber temperature was set to 730°C, TMGa and AsH3 were introduced, and a GaAs buffer layer material with a thickness of 300 nm was grown. SiH4 was used as an N-type dopant with a doping concentration of 3×10 18 cm -3 ;

[0057] (4) Growth of N-type confinement layer: Set the reaction chamber temperature to 730℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 500nm. 0.5 In 0.5 P material, doping concentration is 2×1018 cm -3 , N-type dopant is SiH4;

[0058] (5) Growth of N-type high-frequency barrier capacitor region: Set the reaction chamber temperature to 730℃, introduce TMAl, TMIn, and PH3 into the N-type confinement layer, and grow Al with a thickness of 12nm. 0.5 In 0.5 P material, and SiH4 is used as the dopant with a doping concentration of 2×10 18 cm -3 ; Then TMGa is introduced to grow a 20nm thick (Al 0.3 Ga 0.7 ) 0.5 In 0.5 P material, and SiH4 is used as the dopant with a doping concentration of 2×10 18 cm -3 , the above Al 0.5 In 0.5 P and (Al 0.3 Ga 0.7 ) 0.5 In 0.5 The P material grows alternately and periodically to form an N-type high-frequency barrier capacitor region, with the number of cycle pairs being 10.

[0059] (6) Growth of multi-quantum well active layer: Set the temperature of the reaction chamber to 700℃, introduce TMGa, TMAl, TMIn, and PH3, and grow quantum well layer and quantum barrier layer respectively (Al 0.06 Ga 0.94 ) 0.5 In 0.5 P、(Al 0.8 Ga 0.2 ) 0.5 In 0.5 P material, wherein the thickness of a single well layer is 5nm to 7nm, the thickness of a single barrier layer is 12nm, the number of periods is 15 pairs, and the quantum wells / quantum barriers are non-doped;

[0060] (7) Growth of P-type high-frequency barrier capacitor region: Set the reaction chamber temperature to 730℃, introduce TMAl, TMIn, and PH3 into the multi-quantum well active layer, and grow Al with a thickness of 12nm. 0.5 In 0.5 P material, and Cp2Mg is used as the dopant with a doping concentration of 1×10 18 cm -3 , then TMGa is introduced to grow a 20nm thick (Al 0.3 Ga 0.7 ) 0.5 In 0.5P material, and Cp2Mg is used as the dopant with a doping concentration of 1×10 18 cm -3 , the above Al 0.5 In 0.5 P and (Al 0.3 Ga 0.7 ) 0.5 In 0.5 The P material grows alternately and periodically to form a P-type high-frequency barrier capacitor region, and the number of cycle pairs is 10;

[0061] (8) Growth of P-type confinement layer: Set the reaction chamber temperature to 730℃, introduce TMAl, TMIn, and PH3, and grow Al with a thickness of 800nm. 0.5 In 0.5 P material, doping concentration is 0.5×10 18 cm -3 , the P-type dopant is Cp2Mg;

[0062] (9) Growth of P-type transition layer: Set the temperature of the reaction chamber to 730℃, introduce TMGa, TMAl, TMIn, and PH3, and grow a 30nm thick (Al 0.15 Ga 0.85 ) 0.5 In 0.5 P material, dopant is Cp2Mg, doping concentration is 3×10 18 cm -3 ;

[0063] (10) Growth of P-type window layer: The reaction chamber temperature was set to 680°C, TMGa and PH3 were introduced, and GaP material with a thickness of 5000 nm was grown. CP2Mg was used as the P-type dopant with a doping concentration of 5×10 18 cm -3 .

[0064] (11) Taking out the wafer: After the growth is completed, the temperature of the MOCVD reaction chamber is lowered to 110℃, and then the pressure is adjusted to 1000mbar. The reaction chamber is opened and the epitaxial wafer is taken out.

[0065] Comparative Example 1

[0066] A conventional quaternary AlGaInP LED epitaxial wafer is prepared using conventional methods, and its structural diagram is shown in FIG. Figure 1 shown.

[0067] Test example

[0068] 1. The LED epitaxial wafer obtained in Comparative Example 1 and the LED epitaxial wafer obtained in Example 1 were observed under a scanning electron microscope (magnification of 10,000 times). The results were as follows: Figure 3 and Figure 4 As shown. Figure 3 It can be seen that conventional quaternary AlGaInP LED epitaxial wafers have lattice defects on the substrate surface (marked by the red dotted line). As the epitaxial growth defects continue to extend upward, leakage channels are formed, which are easily broken down by static electricity, resulting in a decrease in the anti-static ability of the LED. Figure 4 The crystal growth quality of the LED epitaxial layer obtained in Example 1 of the present invention is improved, and the epitaxial layer is clear and complete without defects that may cause leakage channels.

[0069] 2. The LED obtained in Comparative Example 1 and the LED obtained in Example 1 were subjected to different high-voltage electrostatic discharge (ESD) tests to determine the pass rate of the chip test. The test conditions and results are shown in Table 1.

[0070] Table 1

[0071]

[0072] From the results in Table 1, it can be seen that the LED prepared in Example 1 of the present invention can still maintain an ESD pass rate of 95% in the 5000V test, while the pass rate of the conventional quaternary AlGaInP series LED in the 2000V test is only 64%, indicating that the antistatic performance of the LED prepared by the method of the present invention is greatly improved.

[0073] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An LED epitaxial wafer with improved antistatic capability, characterized in that: The LED epitaxial wafer includes, from bottom to top, a GaAs substrate, a secondary nucleation layer, a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type confinement layer, a P-type transition layer, and a P-type window layer; The secondary nucleation layer is a GaAs single crystal layer formed by in-situ secondary nucleation of Ga atoms remaining after the surface defect layer of the GaAs substrate is treated and As atoms in the exogenous gas AsH3; The self-defect layer treatment method is as follows: the initial pressure of the reaction chamber is set to 10 mbar, the temperature of the reaction chamber is set to 780° C. to 800° C., a mixed gas of H2 and N2 is introduced onto the surface of the GaAs substrate, the flow rate of H2 is set to 15000 sccm to 20000 sccm, and the flow rate of N2 is set to 1500 sccm to 2000 sccm. The pressure of the reaction chamber is gradually changed from 10 mbar to 50 mbar from the time the mixed gas is introduced, the pressure gradient rate is 5 mbar / min to 10 mbar / min, and the pressure change time is 5 min to 8 min. The in-situ secondary nucleation method is as follows: when the pressure of the reaction chamber treated from the defect layer reaches 50 mbar, the N2 flow is turned off to maintain the reaction chamber pressure stable at 50 mbar, and AsH3 gas is introduced at a flow rate of 300 sccm to 500 sccm for 3 minutes to 5 minutes; The materials of the N-type high-frequency barrier capacitor region and the P-type high-frequency barrier capacitor region are both Al 0.5 In 0.5 P / (Al x1 Ga 1-x1 ) 0.5 In 0.5 P alternately grows in a periodic structure, the number of pairs of periodic structures is 5 to 10 pairs, in each periodic structure, Al 0.5 In 0.5 The thickness of the P layer is 12nm to 18nm. x1 Ga 1-x1 ) 0.5 In 0.5 The thickness of the P layer is 20 nm to 30 nm, where the value of x1 ranges from 0.1 to 0.

3.

2. The LED epitaxial wafer with improved antistatic capability according to claim 1, characterized in that: The thickness of the secondary nucleation layer is 10 nm to 50 nm.

3. The LED epitaxial wafer with improved antistatic capability according to claim 1, characterized in that: The Al in the N-type high-frequency barrier capacitor region 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The doping concentration of P materials is 2×10 18 cm -3 ~3×10 18 cm -3 , and both use SiH4 as the N-type dopant.

4. The LED epitaxial wafer with improved antistatic capability according to claim 1, characterized in that: The Al in the P-type high-frequency barrier capacitor region 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The doping concentration of P materials is 1×10 18 cm -3 ~2×10 18 cm -3 , and both use Cp2Mg as the P-type dopant.

5. The method for preparing an LED epitaxial wafer with improved antistatic capability according to any one of claims 1 to 4, characterized in that: Using MOCVD equipment, the surface of the GaAs substrate is treated with a self-defect layer in a gradual manner, and then in-situ secondary nucleation is performed to form a secondary nucleation layer. Then, a buffer layer, an N-type confinement layer, an N-type high-frequency barrier capacitor region, a multi-quantum well active layer, a P-type high-frequency barrier capacitor region, a P-type confinement layer, a P-type transition layer, and a P-type window layer are grown in sequence.

6. The method for preparing an LED epitaxial wafer with improved antistatic capability according to claim 5, wherein: The growth steps of the N-type high-frequency barrier capacitor region are as follows: setting the reaction chamber temperature to 730°C ± 20°C, introducing TMAl, TMIn, and PH3 into the N-type confinement layer, and growing Al with a thickness of 12nm to 18nm. 0.5 In 0.5 P material, and SiH4 is used as a dopant, and then TMGa is introduced to grow (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, the value range of x1 is 0.1~0.3, and SiH4 is used as dopant. 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The P material is grown alternately and periodically to form an N-type high-frequency barrier capacitor region, and the number of cycle pairs is 5 to 10 pairs.

7. The method for preparing an LED epitaxial wafer with improved antistatic capability according to claim 5, characterized in that: The growth steps of the P-type high-frequency barrier capacitor region are as follows: setting the reaction chamber temperature to 730°C ± 20°C, introducing TMAl, TMIn, and PH3 into the multi-quantum well active layer, and growing Al with a thickness of 12nm to 18nm. 0.5 In 0.5 P material, and use Cp2Mg as dopant, then introduce TMGa, grow (Al x1 Ga 1-x1 ) 0.5 In 0.5 P material, the value range of x1 is 0.1~0.3, and Cp2Mg is used as dopant. 0.5 In 0.5 P and (Al x1 Ga 1-x1 ) 0.5 In 0.5 The P material grows alternately and periodically to form a P-type high-frequency barrier capacitor region, and the number of cycle pairs is 5 to 10 pairs.

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