Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes an upper substrate controlling a viewing angle of light emitted from a lower substrate and bonded to the lower substrate, the upper substrate being divided into a viewing angle control region and a packaging region, the upper substrate including a packaging substrate and a viewing angle control layer, the package substrate includes a base layer, a cavity defined in the viewing angle control region, and a protrusion protruding from the base layer toward the lower substrate in the package region, the viewing angle control layer is disposed in the cavity, and the viewing angle control layer includes transparent patterns and light absorbing patterns alternately arranged.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a display device and a method of manufacturing the display device. Background Art

[0002] Generally, a display device displays an image with a wide viewing angle, but for safety reasons or to improve image reflection, the viewing angle of the image displayed on the display device may be restricted. Summary of the Invention

[0003] An embodiment provides a display device.

[0004] An embodiment provides a method of manufacturing the display device.

[0005] A display device according to an embodiment may include: a lower substrate; and an upper substrate disposed on the lower substrate, controlling a viewing angle of light emitted from the lower substrate, and being bonded to the lower substrate. The upper substrate may include: a package substrate divided into a viewing angle control region and a package region surrounding the viewing angle control region, and the package substrate includes a base layer, a cavity defined in the viewing angle control region, and a protrusion protruding from the base layer toward the lower substrate in the package region; and a viewing angle control layer disposed in the cavity and including alternately arranged transparent patterns and light absorption patterns.

[0006] In an embodiment, the viewing angle control layer may be surrounded by the protrusion.

[0007] In an embodiment, the thickness of the protrusion may be greater than the thickness of the viewing angle control layer.

[0008] In an embodiment, the thickness of the protrusion may be greater than about 100 μm, and the thickness of the viewing angle control layer may be in the range of about 20 μm to about 100 μm.

[0009] In an embodiment, the upper substrate may further include: a sealing member disposed under the protrusion.

[0010] In an embodiment, the thickness of the sealing member may be less than the thickness of the protrusion and the thickness of the viewing angle control layer.

[0011] In an embodiment, the thickness of the sealing member may be in the range of about 3 μm to about 5 μm.

[0012] In an embodiment, the upper substrate may further include: a protective layer covering the viewing angle control layer.

[0013] In an embodiment, the upper substrate may further include: a moisture absorption layer covering the protective layer.

[0014] In an embodiment, the aspect ratio of each of the light absorption patterns may be greater than about 5, and the period in which the light absorption patterns are arranged may be in the range of about 2 times to about 4 times the width of each of the light absorption patterns.

[0015] In an embodiment, the light absorption patterns may be disposed between the transparent patterns, and the thickness of each of the light absorption patterns may be substantially equal to the thickness of each of the transparent patterns.

[0016] In an embodiment, the encapsulation substrate may include glass.

[0017] In an embodiment, the protrusion may be integral with the base layer.

[0018] In an embodiment, the lower substrate may include an emission layer, and the emission layer may include a pixel electrode, an organic emission layer, and a common electrode, and may completely overlap with the viewing angle control layer.

[0019] In an embodiment, the emission layer may be spaced apart from the viewing angle control layer.

[0020] In an embodiment, the emission layer may not contact the viewing angle control layer.

[0021] A method of manufacturing a display device according to an embodiment may include: preparing a substrate member divided into a viewing angle control region and an encapsulation region surrounding the viewing angle control region; etching the substrate member to form an encapsulation substrate including a base layer, a cavity defined in the viewing angle control region, and a protrusion protruding from the base layer toward the lower substrate in the encapsulation region; forming a transparent pattern in the cavity; and forming a light absorption pattern between the transparent patterns.

[0022] In an embodiment, the formation of the transparent pattern may include: forming a transparent layer in the cavity; and patterning the transparent layer to form the transparent pattern.

[0023] In an embodiment, the method may further include: forming a sealing member on the protrusion before the formation of the transparent pattern.

[0024] In an embodiment, the method may further include: forming a protective layer covering the transparent pattern and the light absorption pattern; and forming a moisture absorption layer covering the protective layer.

[0025] Accordingly, a display device according to an embodiment of the present disclosure may include an upper substrate in which a viewing angle control layer is embedded. Specifically, the upper substrate may include an encapsulation substrate having a cavity defined by the protrusion and a viewing angle control layer disposed in the cavity.

[0026] Since the viewing angle control layer is internalized in the upper substrate, the cost of manufacturing the display device can be reduced. For example, the cost of purchasing a conventional viewing angle control layer, the cost of an adhesive for attaching the conventional viewing angle control layer to the display device, the process cost for attaching the conventional viewing angle control layer to the display device, etc. can be reduced.

[0027] Since the viewing angle control layer is internalized in the upper substrate, the durability of the display device can be improved. For example, since the viewing angle control layer is directly formed on the encapsulation substrate, deformation defects caused by external impacts can be prevented from occurring.

[0028] The technical objectives to be achieved by the present disclosure are not limited to the technical objectives described herein, and those skilled in the art will clearly understand other technical objectives not mentioned herein through the description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings included to provide a further understanding of the present disclosure and incorporated into and constituting a part of this specification illustrate embodiments of the present disclosure together with the description.

[0030] Figure 1 is a schematic perspective view illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is illustrative of Figure 1 a schematic cross-sectional view of the display device.

[0032] Figure 3 is illustrative of Figure 2 a schematic block diagram of a lower substrate included in the display device.

[0033] Figure 4 is illustrative of Figure 3 a schematic diagram of an equivalent circuit of a pixel included in the lower substrate.

[0034] Figure 5 is illustrative of Figure 2 a schematic cross-sectional view of a lower substrate included in the display device.

[0035] Figures 6 to 19 is illustrative of a method for manufacturing Figure 2 the display device. DETAILED DESCRIPTION

[0036] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0037] When an element is referred to as being "on," "connected to," or "coupled to" another element, the element can be directly on, directly connected to, or directly coupled to the other element, or there can be intervening elements or layers. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements.

[0038] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, the terms "about" or "approximate" include the stated value and mean within an acceptable deviation of the particular value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0039] The term "and / or" includes all combinations that can define one or more of the related configurations. For example, "A and / or B" can be understood to mean "A, B, or A and B."

[0040] For the purposes of the present disclosure, the phrase "at least one of A and B" can be interpreted to mean only A, only B, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0041] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0042] Figure 1 is a schematic perspective view illustrating a display device according to an embodiment of the present disclosure.

[0043] Reference Figure 1 , a display device 1000 according to an embodiment of the present disclosure can include a lower substrate 10 and an upper substrate 20.

[0044] The lower substrate 10 can be divided into a display area EA and a non-display area NEA surrounding the display area EA, and can emit light.

[0045] The upper substrate 20 may be disposed on the lower substrate 10 and may encapsulate the lower substrate 10 or may be bonded to the lower substrate 10. In an embodiment, the upper substrate 20 may control or adjust the viewing angle of light emitted from the lower substrate 10. For example, the upper substrate 20 may be divided into a viewing angle control region VCA and an encapsulation region ECA surrounding the viewing angle control region VCA.

[0046] In an embodiment, as Figure 1 shown, the display region EA may completely overlap with the viewing angle control region VCA. In other words, the viewing angle control region VCA may cover the display region EA (or overlap with the display region EA), and the area of the viewing angle control region VCA may be larger than the area of the display region EA.

[0047] Figure 2 is a schematic cross-sectional view of the Figure 1 display device illustrated. Figure 3 is a schematic block diagram of the Figure 2 lower substrate included in the display device illustrated. Figure 4 is a schematic diagram of the Figure 3 equivalent circuit of the pixel included in the lower substrate illustrated. Figure 5 is a schematic cross-sectional view of the Figure 2 lower substrate included in the display device illustrated.

[0048] Referring to Figure 2 , the lower substrate 10 may include a base substrate SUB, a transistor layer TL, and an emission layer EL. The transistor layer TL may be disposed on the base substrate SUB and may generate a driving current. The emission layer EL may be disposed on the transistor layer TL and may overlap with the display region EA. The emission layer EL may generate light based on the driving current.

[0049] Referring to Figure 3 , the lower substrate 10 may include a pixel portion PXP, a gate driver GDV, a data driver DDV, an emission driver EDV, and a controller CON.

[0050] The pixel portion PXP may include at least one pixel PX and may be supplied with voltages (e.g., a power voltage and / or a data voltage) for driving the pixel PX. The pixel portion PXP may include a data line DL connected to the pixel PX, a gate line GL connected to the pixel PX, and an emission control line EML connected to the pixel PX.

[0051] The gate driver GDV may generate gate signals GW, GC, GI, and GB based on a gate control signal GCTRL. For example, the gate signals GW, GC, GI, and GB may include a gate-on voltage for turning on a transistor and a gate-off voltage for turning off a transistor. The gate control signal GCTRL may include a vertical start signal, a clock signal, etc.

[0052] The data driver DDV can generate a data voltage DATA based on the output image data ODAT and the data control signal DCTRL. For example, the data driver DDV can generate a data voltage DATA corresponding to the output image data ODAT and output the data voltage DATA in response to the data control signal DCTRL. The data control signal DCTRL can include an output data enable signal, a horizontal start signal, and / or a load signal.

[0053] The emission driver EDV can generate an emission control signal EM based on the emission drive signal ECTRL. For example, the emission drive signal ECTRL can include a vertical start signal, a clock signal, etc., and the emission control signal EM can include a gate-on voltage for a conducting transistor and a gate-off voltage for a non-conducting transistor.

[0054] The controller CON (e.g., a timing controller (T-CON)) can receive the input image data IDAT and the control signal CTRL from an external host processor (e.g., a GPU). For example, the input image data IDAT can be RGB data including red image data, green image data, and blue image data. The control signal CTRL can include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and / or a main clock signal. The controller CON can generate a gate control signal GCTRL, an emission drive signal ECTRL, a data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the control signal CTRL.

[0055] Reference Figure 4 , the pixel PX can include a pixel circuit PC and a light-emitting diode LED. The pixel circuit PC can supply a drive current to the light-emitting diode LED, and the light-emitting diode LED can generate light based on the drive current. Examples of the light-emitting diode LED can include an organic light-emitting diode, an inorganic light-emitting diode, a nano light-emitting diode, etc.

[0056] The pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

[0057] The light-emitting diode LED can include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal). The first terminal of the light-emitting diode LED can be connected to the sixth transistor T6 and the seventh transistor T7, and the second terminal can be supplied with a second power voltage ELVSS. The light-emitting diode LED can generate light having a brightness corresponding to the drive current.

[0058] The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive the first power voltage ELVDD. During the deactivation period of the first gate signal GW, the storage capacitor CST may hold the voltage level of the gate terminal of the first transistor T1.

[0059] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the first transistor T1 may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1 may be connected to the second transistor T2 and may receive the data voltage DATA. The second terminal of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may generate a driving current based on the voltage difference between the gate terminal and the first terminal. For example, the first transistor T1 may be referred to as a driving transistor.

[0060] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 may receive the first gate signal GW through the gate line GL.

[0061] The second transistor T2 may be turned on or off in response to the first gate signal GW. For example, in the case where the second transistor T2 is a PMOS transistor, the second transistor T2 may be turned off when the first gate signal GW has a positive voltage level, and the second transistor T2 may be turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2 may receive the data voltage DATA through the data line DL. During the period when the second transistor T2 is turned on, the second terminal of the second transistor T2 may supply the data voltage DATA to the first terminal of the first transistor T1. For example, the second transistor T2 may be referred to as a switching transistor.

[0062] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor T3 may receive the second gate signal GC. The first terminal of the third transistor T3 may be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 may be connected to the gate terminal of the first transistor T1.

[0063] The third transistor T3 may be turned on or off in response to the second gate signal GC. For example, in the case where the third transistor T3 is a PMOS transistor, the third transistor T3 may be turned off when the second gate signal GC has a positive voltage level, and the third transistor T3 may be turned on when the second gate signal GC has a negative voltage level.

[0064] During a period when the third transistor T3 is turned on in response to the second gate signal GC, the third transistor T3 may diode-connect the first transistor T1. Accordingly, the third transistor T3 may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be referred to as a compensation transistor.

[0065] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor T4 may receive the third gate signal GI. The first terminal of the fourth transistor T4 may be connected to the gate terminal of the first transistor T1. The second terminal of the fourth transistor T4 may receive the initialization voltage VINT.

[0066] The fourth transistor T4 may be turned on or off in response to the third gate signal GI. For example, in the case where the fourth transistor T4 is a PMOS transistor, the fourth transistor T4 may be turned off when the third gate signal GI has a positive voltage level, and the fourth transistor T4 may be turned on when the third gate signal GI has a negative voltage level.

[0067] During a period when the fourth transistor T4 is turned on by the third gate signal GI, the initialization voltage VINT may be provided to the gate terminal of the first transistor T1. Accordingly, the fourth transistor T4 may initialize the gate terminal of the first transistor T1 to the initialization voltage VINT. For example, the fourth transistor T4 may be referred to as a gate initialization transistor.

[0068] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fifth transistor T5 may receive the emission control signal EM. The first terminal of the fifth transistor T5 may receive the first power voltage ELVDD. The second terminal of the fifth transistor T5 may be connected to the first transistor T1. When the fifth transistor T5 is turned on in response to the emission control signal EM, the fifth transistor T5 may provide the first power voltage ELVDD to the first transistor T1.

[0069] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the sixth transistor T6 may receive the emission control signal EM. The first terminal of the sixth transistor T6 may be connected to the first transistor T1. The second terminal of the sixth transistor T6 may be connected to the light-emitting diode LED. When the sixth transistor T6 is turned on in response to the emission control signal EM, the sixth transistor T6 may provide a drive current to the light-emitting diode LED.

[0070] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the seventh transistor T7 may receive the fourth gate signal GB. The first terminal of the seventh transistor T7 may be connected to the light-emitting diode LED. The second terminal of the seventh transistor T7 may receive the initialization voltage VINT.

[0071] When the seventh transistor T7 is turned on in response to the fourth gate signal GB, the seventh transistor T7 can supply the initialization voltage VINT to the light-emitting diode LED. Accordingly, the seventh transistor T7 can initialize the first terminal of the light-emitting diode LED to the initialization voltage VINT. For example, the seventh transistor T7 can be referred to as an anode initialization transistor.

[0072] However, the structure of the pixel circuit PC is not limited to the structure described above. For example, the number of transistors, the number of capacitors, and the type of transistors (PMOS, NMOS, etc.) included in the pixel circuit PC can be appropriately set as needed.

[0073] Reference Figure 5 , the transistor layer TL may include a buffer layer BFR, an active pattern ACT, a first insulating layer ISL1, a gate electrode GAT, a second insulating layer ISL2, a first connection electrode CE1, a second connection electrode CE2, and / or a third insulating layer ISL3. The first connection electrode CE1, the gate electrode GAT, the active pattern ACT, and the second connection electrode CE2 may form a transistor TFT. The emission layer EL may include a pixel electrode ED1, a pixel defining layer PDL, an organic emission layer OL, and a common electrode ED2.

[0074] The substrate substrate SUB may be formed of glass, quartz, plastic, etc. In an embodiment, when the display device 1000 is a rigid display device, the substrate substrate SUB may be made of glass (or include glass). In another embodiment, when the display device 1000 is a flexible display device, the substrate substrate SUB may be made of plastic. Examples of plastics that can be used in the substrate substrate SUB may include polyimide (PI), polyethylene terephthalate (PET), etc. These may be used alone or in combination with each other.

[0075] The buffer layer BFR may be disposed on the substrate substrate SUB. In an embodiment, the buffer layer BFR may be formed of an insulating material (or include an insulating material). Examples of materials that can be used in the buffer layer BFR may include silicon oxide, silicon nitride, and silicon oxynitride. These may be used alone or in combination with each other.

[0076] The active pattern ACT may be disposed on the buffer layer BFR. In an embodiment, the active pattern ACT may be formed of an oxide semiconductor or a silicon semiconductor, etc.

[0077] The first insulating layer ISL1 can be disposed on the buffer layer BFR and can cover the active pattern ACT (or overlap with the active pattern ACT). In an embodiment, the first insulating layer ISL1 can be formed of an insulating material. Examples of materials that can be used as the first insulating layer ISL1 can include silicon oxide, silicon nitride, and silicon oxynitride. These can be used alone or in combination with each other.

[0078] The gate electrode GAT can be disposed on the first insulating layer ISL1 and can overlap with the active pattern ACT. In an embodiment, the gate electrode GAT can be formed of, for example, metal, alloy, conductive metal oxide, transparent conductive material, etc. Examples of materials that can be used as the gate electrode GAT can include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0079] The second insulating layer ISL2 can be disposed on the first insulating layer ISL1 and can cover the gate electrode GAT. In an embodiment, the second insulating layer ISL2 can be formed of an insulating material. Examples of materials that can be used as the second insulating layer ISL2 can include silicon oxide, silicon nitride, and silicon oxynitride. These can be used alone or in combination with each other.

[0080] The first connection electrode CE1 and the second connection electrode CE2 can be disposed on the second insulating layer ISL2 and can contact the active pattern ACT. In an embodiment, the first connection electrode CE1 and the second connection electrode CE2 can be formed of, for example, metal, alloy, conductive metal oxide, transparent conductive material, etc. Examples of materials that can be used as the first connection electrode CE1 and the second connection electrode CE2 can include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), and indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0081] The third insulating layer ISL3 may be disposed on the second insulating layer ISL2 and may cover the first connection electrode CE1 and the second connection electrode CE2. In an embodiment, the third insulating layer ISL3 may be formed of an insulating material. Examples of materials that may be used as the third insulating layer ISL3 may include photoresist, polyacrylic resin, polyimide resin, and acrylic resin. These may be used alone or in combination with each other.

[0082] The pixel electrode ED1 may be disposed on the third insulating layer ISL3 and may contact the second connection electrode CE2. The pixel defining layer PDL may be disposed on the third insulating layer ISL3 and may include an opening exposing the pixel electrode ED1. The organic emission layer OL may be disposed on the pixel electrode ED1. The common electrode ED2 may be disposed on the organic emission layer OL.

[0083] In an embodiment, since the upper substrate 20 encapsulates the lower substrate 10, the lower substrate 10 may not include an additional thin film encapsulation (TFE) layer.

[0084] Refer again to Figure 2 , the upper substrate 20 may include a package substrate ECS, a viewing angle control layer VCL, a protective layer PL, a moisture absorption layer AL, and / or a sealing member SM.

[0085] In an embodiment, the package substrate ECS may include a base layer BL, a cavity CV, and a protrusion PP.

[0086] In an embodiment, the base layer BL may be parallel to a plane formed by a first direction D1 and a second direction D2 and may have a thickness in a third direction D3. In an embodiment, the base layer BL may be made of, for example, glass and may protect the components of the lower layer.

[0087] In an embodiment, the cavity CV may be defined in the viewing angle control area VCA and may face the lower substrate 10. The cavity CV may be defined as a void formed in the package substrate ECS, and the boundary of the cavity CV may be set by the protrusion PP.

[0088] In an embodiment, in the encapsulation area ECA, the protrusion PP may protrude from the base layer BL toward the lower substrate 10, and the protrusion PP may define the boundary of the cavity CV. The protrusion PP may be integral with the base layer BL and may be made of, for example, glass.

[0089] In an embodiment, the viewing angle control layer VCL may be internalized in the package substrate ECS and may be directly formed on the package substrate ECS. For example, the viewing angle control layer VCL may be disposed within the cavity CV and may be surrounded by the protrusion PP.

[0090] In an embodiment, the emission layer EL may completely overlap with the viewing angle control layer VCL. In other words, the planar area of the viewing angle control layer VCL may be larger than the planar area of the emission layer EL.

[0091] In an embodiment, the emission layer EL may be spaced apart from the viewing angle control layer VCL. For example, the emission layer EL may not contact the viewing angle control layer VCL.

[0092] In an embodiment, the viewing angle control layer VCL may include a transparent pattern 100 and a light absorption pattern 200. The transparent pattern 100 and the light absorption pattern 200 may be arranged side by side, alternating with each other along a first direction D1 and a second direction D2. In other words, the transparent pattern 100 may serve as a mold for fixing the light absorption pattern 200.

[0093] For example, each of the light absorption patterns 200 may have a thickness in a third direction D3 and a width in the first direction D1. In this case, the aspect ratio of each of the light absorption patterns 200 may be greater than about 5.

[0094] Wherein the period in which the light absorption patterns 200 are arranged in the first direction D1 may be in the range of about 2 times to about 4 times the width of each of the light absorption patterns 200.

[0095] The thickness of each of the light absorption patterns 200 may be substantially equal to the thickness of each of the transparent patterns 100.

[0096] In an embodiment, the transparent pattern 100 may include a material having a relatively high light transmittance. For example, the transparent pattern 100 may be made of a photoresist, a polypropylene resin, a polyimide resin, a polyamide resin, a silicone resin, an acrylic resin, an epoxy resin, etc. These may be used alone or in combination with each other. The transparent pattern 100 may transmit the light emitted from the emission layer EL.

[0097] In an embodiment, the light absorption pattern 200 may include a material having a relatively low light transmittance. For example, the light absorption pattern 200 may include a black dye, a black pigment, carbon black, chromium, etc. These may be used alone or in combination with each other. The light absorption pattern 200 may absorb or block the light emitted from the emission layer EL.

[0098] In an embodiment, the protective layer PL may be disposed below the viewing angle control layer VCL and may cover the viewing angle control layer VCL. The protective layer PL may maintain the shape of the viewing angle control layer VCL and may protect the viewing angle control layer VCL. In an embodiment, the protective layer PL may include a transparent inorganic material or a transparent metal oxide. Examples of the inorganic material that may be used as the protective layer PL may include silicon oxide, silicon nitride, and silicon oxynitride. Examples of the metal oxide that may be used as the protective layer PL may include indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO).

[0099] In an embodiment, the moisture absorption layer AL may be disposed below the protective layer PL and may cover the protective layer PL. The moisture absorption layer AL may include a moisture-absorbing material and may absorb moisture and / or oxygen.

[0100] In an embodiment, the sealing member SM may overlap with the encapsulation area ECA and the non-display area NEA and may be disposed between the protrusion PP and the transistor layer TL. The sealing member SM may be located between the encapsulation substrate ECS and the lower substrate 10 to seal the internal space. For example, a glass frit may be used as the sealing member SM. Thus, after the glass frit is applied to the lower portion of the protrusion PP and covers the encapsulation substrate ECS, when laser or heat is applied to the glass frit, the glass frit may be hardened and may seal the encapsulation substrate ECS and the lower substrate 10. In this case, the internal space may be filled with a filler, a moisture absorbent, etc.

[0101] In an embodiment, the protrusion PP may have a first thickness TH1 in the third direction D3, the viewing angle control layer VCL may have a second thickness TH2 in the third direction D3, and the sealing member SM may have a third thickness TH3 in the third direction D3.

[0102] In an embodiment, the first thickness TH1 of the protrusion PP may be greater than the second thickness TH2 of the viewing angle control layer VCL. For example, the first thickness TH1 may be greater than about 100 μm, and the second thickness TH2 may be about 20 μm to about 100 μm. Accordingly, the viewing angle control layer VCL may be protected by the protrusion PP and may be internalized in the encapsulation substrate ECS.

[0103] In an embodiment, the third thickness TH3 of the sealing member SM may be less than the first thickness TH1 of the protrusion PP and the second thickness TH2 of the viewing angle control layer VCL. For example, the third thickness TH3 may be in the range of about 3 μm to about 5 μm.

[0104] The display device 1000 according to an embodiment of the present disclosure may include an upper substrate 20 in which a viewing angle control layer VCL is embedded. Specifically, the upper substrate 20 may include a package substrate ECS having a cavity CV defined by protrusions PP and a viewing angle control layer VCL disposed within the cavity CV.

[0105] Since the viewing angle control layer VCL is internalized in the upper substrate 20, the cost of manufacturing the display device 1000 can be reduced. For example, the cost of purchasing a conventional viewing angle control layer, the cost of an adhesive for attaching the conventional viewing angle control layer to the display device, the process cost for attaching the conventional viewing angle control layer to the display device, etc. can be reduced.

[0106] Since the viewing angle control layer VCL is internalized in the upper substrate 20, the durability of the display device 1000 can be improved. For example, since the viewing angle control layer VCL is directly formed on the package substrate ECS, deformation defects caused by external shocks may not occur.

[0107] Figures 6 to 19 is a schematic cross-sectional view of a method of manufacturing Figure 2 the display device shown.

[0108] Referring to Figure 6 , a base member BL' divided into a viewing angle control region VCA and a package region ECA surrounding the viewing angle control region VCA may be prepared. For example, the base member BL' may be made of glass (or include glass).

[0109] Referring to Figure 7 , the package substrate ECS may be formed by etching the base member BL'. Specifically, the base member BL' corresponding to the viewing angle control region VCA may be etched. Accordingly, a cavity CV defined in the viewing angle control region VCA and protrusions PP protruding from the package region ECA may be formed.

[0110] Referring to Figure 8 , a sealing member SM may be formed on the protrusions PP. In an embodiment, the sealing member SM may be plasticized. Since the plasticization process is performed before the viewing angle control layer VCL is formed, the reliability of the viewing angle control layer VCL can be improved.

[0111] Referring to Figure 9 , a transparent layer TPL may be formed within the cavity CV. In an embodiment, the transparent layer TPL may be printed by an inkjet process. The transparent layer TPL may include a material having a relatively high light transmittance.

[0112] Referring to Figure 10, an inorganic layer IL may be formed on the transparent layer TPL. The inorganic layer IL may include an inorganic material or a metal oxide and may be formed using, for example, a chemical vapor deposition (CVD) process, a sputtering process, or the like.

[0113] Reference Figure 11 , a photoresist pattern PR may be formed on the inorganic layer IL. The photoresist pattern PR may include a photoresist and may be patterned to correspond to the grooves formed in the transparent pattern 100.

[0114] Reference Figure 12 , a mask ILM may be formed. For example, the inorganic layer IL may be etched corresponding to the photoresist pattern PR, and the remaining inorganic layer IL may serve as the mask ILM.

[0115] Reference Figure 13 , a transparent pattern 100 may be formed. For example, the transparent layer TPL may be patterned to correspond to the pattern of the mask ILM, and the remaining transparent layer TPL may serve as the transparent pattern 100.

[0116] Reference Figure 14 , a preliminary light absorption pattern 200' may be formed between the transparent patterns 100. The preliminary light absorption pattern 200' may be fully applied or printed on the transparent pattern 100 and may fill the grooves defined between the transparent patterns 100.

[0117] Reference Figure 15 , a light absorption pattern 200 may be formed by curing the preliminary light absorption pattern 200'. For example, the preliminary light absorption pattern 200' may be cured at about 230°C in a nitrogen atmosphere or a vacuum atmosphere.

[0118] Reference Figure 16 , a protective layer PL may be formed on the transparent pattern 100 and the light absorption pattern 200. For example, an inorganic material or a metal oxide may be deposited using an opening mask or the like.

[0119] Reference Figure 17 , a moisture absorption layer AL may be formed on the protective layer PL. In an embodiment, the protective layer PL and the moisture absorption layer AL may be formed in a nitrogen atmosphere or a vacuum atmosphere. In another embodiment, the protective layer PL and the moisture absorption layer AL may be omitted.

[0120] Reference Figure 18 , the formed upper substrate 20 may be bonded to the prepared lower substrate 10.

[0121] Reference Figure 19 , the display device 1000 may be manufactured by cutting each unit along the cutting line.

[0122] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0123] The embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be understood by the claims, and it should be understood that all technical spirits within the equivalent scope are included within the scope of the present disclosure.

Claims

1. A display device, comprising: lower base plate; as well as an upper substrate disposed on the lower substrate, controlling a viewing angle of light emitted from the lower substrate, and bonded to the lower substrate, The upper substrate comprises: a packaging substrate divided into a viewing angle control area and a packaging area surrounding the viewing angle control area, and comprising: a base layer, a cavity defined in the viewing angle control area, and a protrusion protruding from the base layer toward the lower substrate in the packaging area; and The viewing angle control layer is disposed in the cavity and includes transparent patterns and light absorption patterns that are alternately arranged.

2. The display device according to claim 1, wherein: The viewing angle control layer is surrounded by the protrusion.

3. The display device according to claim 1, wherein: The thickness of the protrusion is greater than the thickness of the viewing angle control layer.

4. The display device according to claim 3, wherein: The thickness of the protrusion is greater than 100 μm, and The thickness of the viewing angle control layer is in a range of 20 μm to 100 μm.

5. The display device according to claim 1, wherein: The upper substrate further comprises: The sealing member is disposed below the protrusion.

6. The display device according to claim 5, wherein: The sealing member has a thickness smaller than a thickness of the protrusion and a thickness of the viewing angle control layer.

7. The display device according to claim 6, wherein: The thickness of the sealing member is in the range of 3 μm to 5 μm.

8. The display device according to claim 1, wherein: The upper substrate further comprises: A protective layer covers the viewing angle control layer.

9. The display device according to claim 8, wherein: The upper substrate further comprises: A moisture absorbing layer covers the protective layer.

10. The display device according to claim 1, wherein: The thickness-to-width ratio of each of the light absorption patterns is greater than 5, and A period in which the light absorption patterns are arranged is in the range of 2 to 4 times a width of each of the light absorption patterns.

11. The display device according to claim 1, wherein: The light absorption pattern is disposed between the transparent patterns, and A thickness of each of the light absorption patterns is equal to a thickness of each of the transparent patterns.

12. The display device according to claim 1, wherein: The packaging substrate includes glass.

13. The display device according to claim 12, wherein: The protrusions are integral with the base layer.

14. The display device according to any one of claims 1 to 13, wherein: The lower substrate includes an emission layer, and The emission layer includes a pixel electrode, an organic emission layer and a common electrode, and completely overlaps with the viewing angle control layer.

15. The display device according to claim 14, wherein: The emission layer is spaced apart from the viewing angle control layer.

16. The display device according to claim 14, wherein: The emission layer does not contact the viewing angle control layer.

17. A method for manufacturing a display device, the method comprising: preparing a substrate member divided into a viewing angle control area and a packaging area surrounding the viewing angle control area; etching the base member to form a packaging substrate, the packaging substrate comprising a base layer, a cavity defined in the viewing angle control region, and a protrusion protruding from the base layer toward a lower substrate in the packaging region; forming a transparent pattern in the cavity; and A light absorption pattern is formed between the transparent patterns.

18. The method according to claim 17, wherein: The forming of the transparent pattern comprises: forming a transparent layer in the cavity; and The transparent layer is patterned to form the transparent pattern.

19. The method according to claim 17, further comprising: Prior to the forming of the transparent pattern, a sealing member is formed on the protrusion.

20. The method of claim 17, further comprising: forming a protective layer covering the transparent pattern and the light absorbing pattern; and A moisture absorbing layer is formed covering the protective layer.

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