Preparation method of nonvolatile two-end storage unit and product thereof

Abstract

The invention discloses a preparation method of a nonvolatile two-end storage unit and a product thereof. The preparation method comprises the following steps: providing a lower dielectric layer surrounding a first region lower electrode metal connecting layer; forming an isolation stack layer covering the first region lower electrode metal connection layer; forming a first region lower electrode interconnecting through hole based on the patterned photomask layer, wherein the first region lower electrode interconnecting through hole is in contact with the first region lower electrode metal connecting layer; forming a layered structure in the first region lower electrode interconnection through hole; and removing the layered structure outside the first region lower electrode interconnection through hole region, forming a first stacking layer in the first region lower electrode interconnection through hole, and enabling the first stacking layer to be flush with the isolation stacking layer. According to the preparation method, the first stack layer is formed in the first region lower electrode interconnection through hole, and only one patterned photomask layer is used, so that the preparation of the first lower electrode metal layer and the first upper electrode metal layer is realized, the production cost is reduced, the preparation process is simplified, the problem of mutual alignment of the upper electrode and the lower electrode is avoided, and the preparation difficulty is reduced.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a method for manufacturing a non-volatile two-terminal memory cell and its product. Background Art

[0002] A resistive random access memory (RRAM) is a non-volatile two-terminal memory cell that stores information based on the change in the resistance of a material, and is typically composed of a lower electrode, a switching layer, and an upper electrode. In the prior art, during the manufacturing process of a resistive random access memory, two lithography processes are required to separately fabricate the lower electrode and the upper electrode. Due to the manufacturing steps, generally, the fabrication of the lower electrode and the upper electrode of a resistive random access memory each requires a different patterned photomask layer, which significantly increases the production cost and the manufacturing process is also relatively complex. At the same time, such a manufacturing method also involves the problem of alignment between the lower electrode and the upper electrode during the fabrication of the lower electrode and the upper electrode, which makes the fabrication of the resistive random access memory difficult.

[0003] In view of this, there is an urgent need to provide a method for manufacturing a non-volatile two-terminal memory cell, which can reduce the number of patterned photomask layers used while realizing the fabrication of the lower electrode and the upper electrode of the non-volatile two-terminal memory cell, thereby reducing the production cost of the non-volatile two-terminal memory cell, simplifying the manufacturing process, and avoiding the problem of alignment between the lower electrode and the upper electrode, and reducing the fabrication difficulty of the non-volatile two-terminal memory cell. Summary of the Invention

[0004] To at least solve one or more of the above-mentioned technical problems, this disclosure proposes solutions for a method for manufacturing a non-volatile two-terminal memory cell and its product in multiple aspects.

[0005] In a first aspect, the present disclosure provides a method for fabricating a non-volatile two-terminal memory cell. The fabrication method includes: providing a lower dielectric layer 120 that surrounds a first-region lower electrode metal connection layer 111 and has its upper surface exposed; forming an isolation stack layer 130 that at least covers the first-region lower electrode metal connection layer 111; forming a first-region lower electrode interconnect via 141 in the isolation stack layer 130 based on a patterned photomask layer, with the bottom of the first-region lower electrode interconnect via 141 at least partially contacting the first-region lower electrode metal connection layer 111; sequentially forming a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253; removing the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 outside the region of the first-region lower electrode interconnect via 141, and forming a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in the first-region lower electrode interconnect via 141, such that the upper surface of the first stack layer 250 is flush with the upper surface of the isolation stack layer 130.

[0006] In some embodiments, forming the first stack layer 250 flush with the upper surface of the isolation stack layer 130 in the first-region lower electrode interconnect via 141 includes: depositing at least the first lower electrode metal layer 251 on the inner wall and bottom of the first-region lower electrode interconnect via 141, the first switching layer 252 covering the first lower electrode metal layer 251, and the first upper electrode metal layer 253 covering the first switching layer 252.

[0007] In some embodiments, after forming the first stack layer 250, a blocking layer 230 is formed that at least covers the upper surface of the first stack layer 250.

[0008] In some embodiments, after forming the blocking layer 230, a first-region upper electrode metal connection layer 191 is formed that penetrates the blocking layer 230 and has its bottom contacting the upper surface of the first upper electrode metal layer 253.

[0009] In some embodiments, after forming the first stack layer 250, a first-region upper electrode metal connection layer 191 is formed that has its bottom contacting the upper surface of the first upper electrode metal layer 253.

[0010] In a second aspect, the present disclosure provides a non-volatile two-terminal memory cell, the non-volatile two-terminal memory cell comprising: a lower dielectric layer 120 that surrounds and exposes the upper surface of a first-region lower electrode metal connection layer 111; an isolation stack layer 130 that at least covers the first-region lower electrode metal connection layer 111; a first-region lower electrode interconnection via 141 that is formed in the isolation stack layer 130 and the bottom of which at least partially contacts the first-region lower electrode metal connection layer 111; a first stack layer 250 having an upper surface flush with the upper surface of the isolation stack layer 130, the first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 in the first-region lower electrode interconnection via 141.

[0011] In some embodiments, the non-volatile two-terminal memory cell further comprises: a blocking layer 230 that at least covers the upper surface of the first stack layer 250, and a first-region upper electrode metal connection layer 191 that penetrates the blocking layer 230 and the bottom of which contacts the upper surface of the first upper electrode metal layer 253.

[0012] In some embodiments, the non-volatile two-terminal memory cell further comprises: a first-region upper electrode metal connection layer 191, the bottom of which contacts the upper surface of the first upper electrode metal layer 253.

[0013] In a third aspect, the present disclosure provides a memory that includes one or more non-volatile two-terminal memory cells according to embodiments of the present disclosure.

[0014] In a fourth aspect, the present disclosure provides an electronic device that includes the memory according to embodiments of the present disclosure.

[0015] By means of the preparation scheme of the non-volatile two-terminal memory cell provided above, embodiments of the present disclosure form a first stack layer in a first-region lower electrode interconnection via, so as to implement the preparation of the first lower electrode metal layer and the first upper electrode metal layer of the non-volatile two-terminal memory cell by using only one patterning photomask layer, reduce production costs, simplify the preparation process, avoid the problem of mutual alignment between the lower electrode and the upper electrode, and reduce the preparation difficulty. Description of the Drawings

[0016] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understandable. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, where:

[0017] Figures 1A - 1F A schematic cross-sectional structure diagram of a semiconductor for preparing a non-volatile two-terminal storage cell in the prior art is shown;

[0018] Figure 2 An exemplary structural block diagram of a method for preparing a non-volatile two-terminal storage cell according to some embodiments of the present application is shown;

[0019] Figures 3A - 3H A schematic cross-sectional structure diagram of a semiconductor for a method for preparing a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown;

[0020] Figures 4A - 4I A schematic cross-sectional structure diagram of a semiconductor for a method for preparing a non-volatile two-terminal storage cell according to some other embodiments of the present disclosure is shown.

[0021] Names of reference numerals:

[0022] 111 - First region lower electrode metal connection layer, 112 - Second region lower electrode metal connection layer, 120 - Lower dielectric layer, 130 - Isolation stack layer, 131 - First sub-layer of the isolation stack, 132 - Second sub-layer of the isolation stack, 141 - First region lower electrode interconnection via, 1511 - First sub-layer of the second lower electrode metal, 1512 - Second sub-layer of the second lower electrode metal, 152 - Second switching layer, 153 - Second upper electrode metal layer, 154 - Upper electrode hard mask layer, 159 - Sidewall, 170 - Upper dielectric layer, 191 - First region upper electrode metal connection layer, 192 - Second region upper electrode metal connection layer;

[0023] 230 - Blocking layer, 250 - First stack layer, 251 - First lower electrode metal layer, 2511 - First sub-layer of the first lower electrode metal, 2512 - Second sub-layer of the first lower electrode metal, 252 - First switching layer, 253 - First upper electrode metal layer, 2531 - First sub-layer of the first upper electrode metal, 2532 - Second sub-layer of the first upper electrode metal. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0025] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0026] It should also be understood that the terms used in this disclosure specification are for the purpose of describing particular embodiments only and are not intended to limit this disclosure. As used in this disclosure specification and claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should further be understood that the term "and / or" as used in this disclosure specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0027] As used in this specification and claims, the term "if" can be interpreted, depending on the context, as "when", "once", "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" can be interpreted, depending on the context, as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0028] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0029] Figures 1A - 1F A schematic semiconductor cross-sectional structure diagram of preparing a non-volatile two-terminal storage cell in the prior art is shown.

[0030] Figure 1A A schematic semiconductor cross-sectional structure diagram of forming the second lower electrode metal sub-layer 1511 in the prior art is shown.

[0031] As Figure 1AAs shown, a lower dielectric layer 120 is provided to surround the first-zone lower electrode metal connection layer 111 and expose its upper surface. Through a thin-film deposition process, an isolation stack layer 130 is deposited on the upper surface of the first-zone lower electrode metal connection layer 111 and the upper surface of the lower dielectric layer 120. Among them, the isolation stack layer 130 may include an isolation stack first sub-layer 131 and an isolation stack second sub-layer 132, and the isolation stack second sub-layer 132 covers the upper surface of the isolation stack first sub-layer 131. Through a photolithography process and an etching process, a first-zone lower electrode interconnection via 141 is formed in the isolation stack layer 130. Through processes such as thin-film deposition and chemical mechanical polishing, a second lower electrode metal first sub-layer 1511 is formed within the first-zone lower electrode interconnection via 141.

[0032] Figure 1B The schematic semiconductor cross-sectional structure diagram showing the deposition of the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 in the prior art is shown.

[0033] As Figure 1B shown, through a thin-film deposition process, the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 are sequentially deposited above the isolation stack layer 130 and the second lower electrode metal first sub-layer 1511. The second lower electrode metal first sub-layer 1511 and the second lower electrode metal second sub-layer 1512 covering the second lower electrode metal first sub-layer 1511 form the second lower electrode metal layer 151. The upper electrode hard mask layer 154 can be a conductive hard mask layer or a non-conductive hard mask layer.

[0034] Figure 1C The schematic semiconductor cross-sectional structure diagram showing the etching of the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 in the prior art is shown.

[0035] As Figure 1C shown, through a photolithography process and an etching process, a part of the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 are etched to form a stacked structure.

[0036] Figure 1D The schematic semiconductor cross-sectional structure diagram showing the deposition of the sidewall 159 in the prior art is shown.

[0037] As Figure 1DAs shown, a sidewall 159 is deposited on the exposed areas of the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 after etching. The sidewall 159 can be a single layer or multiple layers, and covers all sides of the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154, as well as at least a part of the sides of the second lower electrode metal bilayer 1512.

[0038] Figure 1E FIG. shows a schematic cross-sectional structure of a semiconductor in the prior art for etching the sidewall 159 and the second lower electrode metal bilayer 1512.

[0039] As Figure 1E shown, the deposited sidewall 159 and the second lower electrode metal bilayer 1512 are etched, and the etching stops at the upper surface of the isolation stack layer 130, so that the sidewall 159 wraps all sides of the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154.

[0040] Figure 1F FIG. shows a schematic cross-sectional structure of a semiconductor in the prior art for forming the first region upper electrode metal connection layer 191.

[0041] As Figure 1F shown, an upper dielectric layer 170 is deposited on the exposed areas of the above-formed structure, and a first region upper electrode interconnect via is formed in the upper dielectric layer 170 through a photolithography process and an etching process, and a first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnect via. When the upper electrode hard mask layer 154 is a conductive hard mask layer, the first region upper electrode interconnect via can partially penetrate into the upper electrode hard mask layer 154 to conduct the first region upper electrode metal connection layer 191, the upper electrode hard mask layer 154, and the second upper electrode metal layer 153. When the upper electrode hard mask layer 154 is a non-conductive hard mask layer, the first region upper electrode interconnect via can penetrate through the upper electrode hard mask layer 154 to conduct the first region upper electrode metal connection layer 191 and the second upper electrode metal layer 153. The first lower electrode metal sublayer 1511 and the second lower electrode metal bilayer 1512 of the second lower electrode metal layer 151 are in contact with each other. The second lower electrode metal layer 151 is in contact with the first region lower electrode metal connection layer 111 to conduct the second lower electrode metal layer 151 and the first region lower electrode metal connection layer 111.

[0042] In the process of fabricating a non-volatile two-terminal memory cell in the prior art, when forming the second lower electrode metal sub-layer 1511, a first region lower electrode interconnect via 141 is formed in the isolation stack layer 130 through a photolithography process and an etching process, and the second lower electrode metal sub-layer 1511 is deposited in the first region lower electrode interconnect via 141; when forming the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154, photolithography and etching processes are required to etch the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Thus, forming the second lower electrode metal sub-layer 1511 and forming the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 both require a patterned photomask layer formed by a corresponding mask plate. Due to the manufacturing steps, generally, the fabrication of the lower electrode and the upper electrode of the non-volatile two-terminal memory cell each requires a different patterned photomask layer, which greatly increases the production cost and the fabrication process is also relatively complex. At the same time, such a fabrication method also involves the problem of alignment between the lower electrode and the upper electrode during the fabrication of the lower electrode and the upper electrode, which makes the fabrication of the non-volatile two-terminal memory cell difficult.

[0043] In view of this, the embodiments of the present disclosure provide a fabrication solution for a non-volatile two-terminal memory cell, which forms a first stack layer 250 in the first region lower electrode interconnect via 141 to achieve the formation of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 of the non-volatile two-terminal memory cell using only one patterned photomask layer, reducing the fabrication cost, shortening the fabrication process flow of the non-volatile two-terminal memory cell, and reducing the fabrication difficulty.

[0044] Figure 2 The exemplary structural block diagram of the fabrication method 200 of the non-volatile two-terminal memory cell according to some embodiments of the present application is shown.

[0045] As Figure 2As shown, in step S210, a lower dielectric layer 120 is provided to surround the first-zone lower electrode metal connection layer 111 and expose its upper surface. In step S220, an isolation stack layer 130 is formed to at least cover the first-zone lower electrode metal connection layer 111. In step S230, a first-zone lower electrode interconnection via 141 is etched in the isolation stack layer 130 based on a patterned mask layer, and the bottom of the first-zone lower electrode interconnection via 141 at least partially contacts the first-zone lower electrode metal connection layer 111. In step S240, a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 are sequentially formed. In step S250, the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 outside the area of the first-zone lower electrode interconnection via 141 are removed, and a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 is formed in the first-zone lower electrode interconnection via 141, making the upper surface of the first stack layer 250 flush with the upper surface of the isolation stack layer 130.

[0046] The following is based on Figure 2 the preparation process of the non-volatile two-terminal memory cell, and in combination with Figures 3A - 3H the schematic cross-sectional semiconductor structure diagram shown, the exemplary process flow of the preparation method 200 of the non-volatile two-terminal memory cell using the embodiments of the present application is described in detail.

[0047] Figure 3A The schematic cross-sectional semiconductor structure diagram of the lower dielectric layer 120 of the embodiment of the present application is shown.

[0048] As Figure 3A shown, a lower dielectric layer 120 is provided to surround the first-zone lower electrode metal connection layer 111 in the array region and expose its upper surface.

[0049] Specifically, the material used for the first-zone lower electrode metal connection layer 111 can be copper metal. The main advantages of copper metal compared with other metals are high electrical conductivity, high thermal conductivity, corrosion resistance, appropriate strength, easy processability, etc. In the embodiments of the present application, the first-zone lower electrode metal connection layer 111 can also use other metals according to needs, which is not limited herein.

[0050] The material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, low dielectric constant (Low-k) material, etc. More specifically, the low dielectric constant (Low-k) material can be porous silicon dioxide, fluorinated silicon glass, etc. In the embodiments of the present application, the lower dielectric layer 120 can also select other materials according to the actual application scenario and process requirements, which is not limited herein.

[0051] In the process of providing the lower dielectric layer 120 that surrounds the first-zone lower electrode metal connection layer 111 and exposes its upper surface, it can be formed by various known processes, and the embodiments of the present application have no limitations in this regard. For example, the process of providing the lower dielectric layer 120 that surrounds the first-zone lower electrode metal connection layer 111 and exposes its upper surface includes: First, provide the lower dielectric layer 120, form a layer of photoresist on the lower dielectric layer 120, selectively expose the photoresist through an exposure machine, develop and remove the exposed or unexposed portions of the photoresist, etch or deposit to form a pattern in the exposed area, remove the remaining photoresist, continue to form the required grooves by dry etching or wet etching, and form the remaining portion after etching into the lower dielectric layer 120. Then, deposit a metal material in the grooves. Finally, perform a planarization process on the metal material to form the first-zone lower electrode metal connection layer 111, such that the upper surface of the first-zone lower electrode metal connection layer 111 is flush with the upper surface of the lower dielectric layer 120. Thus, the lower dielectric layer 120 that surrounds the first-zone lower electrode metal connection layer 111 and exposes its upper surface is obtained.

[0052] By providing the lower dielectric layer 120 that surrounds the first-zone lower electrode metal connection layer 111 and exposes its upper surface, it is convenient to isolate the first-zone lower electrode metal connection layer 111 and the subsequently formed first lower electrode metal layer 251 from other irrelevant parts in the multi-layer metal interconnection structure. Thus, it prevents current from flowing on unnecessary paths and avoids the occurrence of short circuits and leakage.

[0053] Figure 3B The semiconductor cross-sectional structure diagram of the deposited isolation stack layer 130 according to the embodiment of the present application is shown.

[0054] As Figure 3B shown, through a thin film deposition process, the isolation stack layer 130 is deposited on the upper surface of the first-zone lower electrode metal connection layer 111 and the upper surface of the lower dielectric layer 120. Among them, the isolation stack layer 130 may include an isolation stack first sub-layer 131 and an isolation stack second sub-layer 132, and the isolation stack second sub-layer 132 covers the upper surface of the isolation stack first sub-layer 131.

[0055] In some embodiments of the present application, during the process of forming the isolation stack layer 130, at least the deposited isolation stack layer 130 should cover the first-zone lower electrode metal connection layer 111.

[0056] Specifically, the first isolation stack layer 131 can be made of a silicon nitride (SiN) thin film or a nitride-doped silicon carbide (NDC) thin film, and the second isolation stack layer 132 can be made of a low-temperature oxide (LTO), a silicon dioxide layer (SiO2), a silicon-rich oxide layer (SRO), etc. In the embodiments of the present application, the first isolation stack layer 131 and the second isolation stack layer 132 can also be selected according to actual application scenarios and process requirements, and other materials are not limited herein.

[0057] By depositing the first isolation stack layer 131 and the second isolation stack layer 132, the first region lower electrode metal connection layer 111 can be protected to prevent damage to the first region lower electrode metal connection layer 111 in subsequent steps.

[0058] Figure 3C The semiconductor cross-sectional structure diagram of forming the first region lower electrode interconnection via hole 141 in the embodiment of the present application is shown.

[0059] As Figure 3C shown, the first region lower electrode interconnection via hole 141 is etched in the isolation stack layer 130.

[0060] In the embodiments of the present application, the first region lower electrode interconnection via hole 141 is mainly formed by photolithography technology and can be formed by various known processes. The embodiments of the present application are not limited in this regard. For example, the preparation process of the first region lower electrode interconnection via hole 141 includes: forming a photoresist on the upper surface of the isolation stack layer 130, selectively exposing the photoresist through an exposure machine, developing and removing the exposed or unexposed part of the photoresist to form a patterned mask layer. Then, the isolation stack layer 130 not covered by the patterned mask layer is etched by dry etching or wet etching to form the first region lower electrode interconnection via hole 141, and the bottom of the first region lower electrode interconnection via hole 141 is at least partially in contact with the first region lower electrode metal connection layer 111. After the first region lower electrode interconnection via hole 141 is formed, the patterned mask layer is removed.

[0061] In the embodiments of the present application, the first region lower electrode interconnection via hole 141 can be designed as a trapezoidal structure with a large upper end and a small lower end, for example, a frustum of a cone structure or a trapezoidal frustum structure, etc. Designing the first region lower electrode interconnection via hole 141 as a trapezoidal structure determines the cross-sectional shape of each layer of the stack layer deposited in the first region lower electrode interconnection via hole 141, which can not only ensure the required contact area between each layer of the stack layer deposited in the first region lower electrode interconnection via hole 141, but also effectively reduce the overall volume of the stack layer.

[0062] In an embodiment of the present application, the first-region lower electrode interconnection via 141 may also be selected to have other structural shapes according to actual application scenarios and process requirements, and no limitation is made herein.

[0063] In an embodiment of the present application, the cross-sectional shape of the first-region lower electrode interconnection via 141 is an inverted trapezoid.

[0064] In an embodiment of the present application, the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid, and the upper base width of the inverted trapezoid is greater than The lower base width of the inverted trapezoid is greater than

[0065] In an embodiment of the present application, the angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

[0066] In other embodiments of the present application, the size of the first-region lower electrode interconnection via 141 may also be set based on the size of the first stacked layer 250 to be formed in the first-region lower electrode interconnection via 141 and the process adopted during the deposition of the first stacked layer 250 as required later.

[0067] Figure 3D A semiconductor cross-sectional structure diagram showing the deposition of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in an embodiment of the present application is shown.

[0068] As Figure 3D shown, the first lower electrode metal layer 251, the first switching layer 252 covering the first lower electrode metal layer 251, and the first upper electrode metal layer 253 covering the first switching layer 252 are sequentially deposited on the upper surface of the isolation stacked layer 130, the inner wall and bottom of the first-region lower electrode interconnection via 141. During the deposition of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253, at least the inner wall and bottom of the first-region lower electrode interconnection via 141 should be covered by the deposition.

[0069] When depositing multiple layers of materials, due to reasons such as uneven deposition rates in different regions, the deposition amount of materials in some regions may be insufficient, forming depressions. As Figure 3D shown, above the first-region lower electrode interconnection via 141, the first upper electrode metal layer 253 has a depression towards the first-region lower electrode interconnection via 141.

[0070] In an embodiment of the present application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure, and the materials used may be one of TiN (titanium nitride), Ti (titanium), Ta (tantalum), W (tungsten), etc. The same metal material may also be used for the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111, so that the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 are in close contact, avoiding the appearance of holes.

[0071] Figure 3E FIG. shows a schematic cross-sectional semiconductor structure of removing partial materials of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in an embodiment of the present application.

[0072] As Figure 3E shown, by using planarization processing, partial materials of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 are removed, so that the exposed part of the first lower electrode metal layer 251, the exposed part of the first switching layer 252, and the upper surface of the first upper electrode metal layer 253 are flush with the upper surface of the isolation stack layer 130, thereby forming a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in the first region lower electrode interconnection via 141.

[0073] Specifically, during the planarization process, chemical mechanical planarization technology (CMP, Chemical Mechanical Polishing) may be used.

[0074] In the case where a part is deposited with a downward depression, planarization processing is generally adopted because if etching is used, it is difficult to control the etching progress and it is easy to etch off other useful parts. Etching may also be performed based on a specific patterned mask layer.

[0075] In summary, in an embodiment of the present application, after depositing the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253, planarization processing is adopted to make the upper surface of the first stack layer 250 flush with the upper surface of the isolation stack layer 130.

[0076] Figure 3F FIG. shows a schematic cross-sectional semiconductor structure of forming the first region upper electrode metal connection layer 191 in an embodiment of the present application.

[0077] As Figure 3FAs shown, during the process of forming the first-region upper electrode metal connection layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130. A first-region upper electrode interconnect via hole is formed in the upper dielectric layer 170 through a photolithography process and an etching process, and the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode interconnect via hole. That is, the bottom of the formed first-region upper electrode metal connection layer 191 contacts the first upper electrode metal layer 253. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, enabling the first-region upper electrode metal connection layer 191 to be in full contact with the first upper electrode metal layer 253 and preventing partial lower surfaces of the bottom of the first-region upper electrode metal connection layer 191 from contacting the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0078] Specifically, the material used for the upper dielectric layer 170 may be silicon nitride (Si3N4). In the embodiments of the present application, the upper dielectric layer 170 may also be selected according to actual application scenarios and process requirements to use other materials, which are not limited herein.

[0079] The upper dielectric layer 170 can isolate the first upper electrode metal layer 253 and the first-region upper electrode metal connection layer 191 from other parts, thereby preventing current from flowing on unnecessary paths and avoiding the occurrence of short circuits and leakage phenomena.

[0080] Specifically, the first-region upper electrode metal connection layer 191 may be made of copper metal. In the embodiments of the present application, the first-region upper electrode metal connection layer 191 may also be made of other metals according to needs, which are not limited herein.

[0081] In the embodiments of the present application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure.

[0082] In the preferred embodiments of the present application, the first lower electrode metal layer 251 adopts a two-layer structure.

[0083] In some embodiments of the present application, the first lower electrode metal layer 251 includes a first lower electrode metal first sub-layer 2511 and a first lower electrode metal second sub-layer 2512 covering the upper surface of the first lower electrode metal first sub-layer 2511.

[0084] Specifically, the material used for the first lower electrode metal first layer 2511 can be TiN (titanium nitride), and the material used for the first lower electrode metal second layer 2512 can be W (tungsten). The first lower electrode metal second layer 2512 can serve as a connection layer between the first lower electrode metal first layer 2511 and the first switching layer 252. By setting the material of the first lower electrode metal second layer 2512 to be W (tungsten), not only can the better thermal conductivity of the first lower electrode metal second layer 2512 be ensured, the resistance of the first lower electrode metal second layer 2512 can be guaranteed to be small, so that heat can be quickly conducted, heat dissipation can be promoted, and heat generation can be reduced, thereby reducing the thermal damage to the prepared non-volatile two-terminal storage unit. By setting the material of the first lower electrode metal second layer 2512 to be W (tungsten), the higher inertness of the first lower electrode metal second layer 2512 can also be guaranteed, so that a chemical reaction between the first lower electrode metal second layer 2512 and the first switching layer 252 can be avoided, and the thermal stability of the prepared non-volatile two-terminal storage unit can be ensured.

[0085] In an embodiment of the present application, the material of the foregoing first switching layer 252 can be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), etc., which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 can also be selected for other materials according to actual application scenarios and process requirements, which are not limited herein.

[0086] In an embodiment of the present application, the foregoing first upper electrode metal layer 253 can be a single-layer or multi-layer structure.

[0087] In a preferred embodiment of the present application, the first upper electrode metal layer 253 adopts a two-layer structure.

[0088] In some embodiments of the present application, the first upper electrode metal layer 253 includes a first upper electrode metal first layer 2531 and a first upper electrode metal second layer 2532 covering the surface of the first upper electrode metal first layer 2531, and the material used for the first upper electrode metal first layer 2531 is more easily oxidized than the material used for the first upper electrode metal second layer 2532. That is, the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal second layer 2532.

[0089] Figure 3G The semiconductor cross-sectional structure diagram of forming the first region upper electrode metal connection layer 191 in the embodiment of the present application is shown.

[0090] As Figure 3GAs shown, during the process of forming the first-region upper electrode metal connection layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130. A first-region upper electrode via is formed in the upper dielectric layer 170 through a photolithography process and an etching process, and the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode via, such that the bottom of the formed first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal two-layer 2532. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal two-layer 2532, enabling the first-region upper electrode metal connection layer 191 to be in full contact with the first upper electrode metal two-layer 2532 and preventing partial lower surfaces of the bottom of the first-region upper electrode metal connection layer 191 from contacting the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0091] By the bottom of the aforementioned first-region upper electrode metal connection layer 191 contacting the upper surface of the first upper electrode metal two-layer 2532, when the first-region upper electrode metal connection layer 191 contacts the first upper electrode metal one-layer 2531, it can prevent the first upper electrode metal one-layer 2531 from being easily oxidized to generate high-threshold oxides, which affects the conduction between the first-region upper electrode metal connection layer 191 and the first upper electrode metal layer 253.

[0092] Figure 3H The semiconductor cross-sectional structure diagram of forming the second-region upper electrode metal connection layer 192 according to an embodiment of the present application is shown.

[0093] As Figure 3H shown, during the preparation process of the non-volatile two-terminal memory cell of the embodiment of the present application, a second-region lower electrode metal connection layer 112 in the peripheral circuit region and a second-region upper electrode metal connection layer 192 in the peripheral circuit region can also be generated.

[0094] Specifically, during the process of providing the lower dielectric layer 120 that surrounds the first-region lower electrode metal connection layer 111 and exposes its upper surface, a second-region lower electrode metal connection layer 112 in the peripheral circuit region is also provided. Among them, the second-region lower electrode metal connection layer 112 under the peripheral circuit region is also surrounded by the lower dielectric layer 120, and the upper surface of the second-region lower electrode metal connection layer 112 in the peripheral circuit region is exposed.

[0095] The structure, materials used, and preparation process of the second-region lower electrode metal connection layer 112 in the peripheral circuit region can be the same as those of the first-region lower electrode metal connection layer 111, and will not be elaborated here.

[0096] Specifically, the isolation stack layer 130 and the upper dielectric layer 170 can be etched in the peripheral circuit region, and the etching is stopped at the upper surface of the second-region lower electrode metal connection layer 112 in the peripheral circuit region, so as to form the second-region upper electrode via interconnecting holes in the peripheral circuit region. Then, a second-region upper electrode metal connection layer 192 is formed in the second-region upper electrode via interconnecting holes in the peripheral circuit region, so that the second-region upper electrode metal connection layer 192 is connected to the second-region lower electrode metal connection layer 112. Thus, the preparation of the semiconductor structure in the peripheral circuit region is completed.

[0097] The structure, the materials used, and the preparation process of the second-region upper electrode metal connection layer 192 in the peripheral circuit region can be the same as those of the first-region upper electrode metal connection layer 191, and will not be elaborated here.

[0098] Next, based on Figure 2 the preparation process of the non-volatile two-terminal memory cell preparation method, combined with Figures 4A - 4I the schematic cross-sectional structure diagram of the semiconductor shown, the exemplary process flow of the non-volatile two-terminal memory cell preparation method 200 using some other embodiments of the present application will be described in detail.

[0099] Among them, the preparation steps of the non-volatile two-terminal memory cell combined with Figures 4A - 4E are the same as those of the non-volatile two-terminal memory cell combined with Figures 3A - 3E shown, so they will not be described in detail here.

[0100] In an embodiment of the present application, after the formed first stack layer 250 and before the first-region upper electrode metal connection layer 191 is formed above the first stack layer 250, a blocking layer 230 is formed on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130.

[0101] Figure 4F shows the schematic cross-sectional structure diagram of the semiconductor for forming the blocking layer 230 in the embodiment of the present application.

[0102] As Figure 4F shown, the blocking layer 230 is formed on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130.

[0103] Specifically, the blocking layer can also be formed only on the upper surface of the first stack layer 250, or the blocking layer 230 can be formed on the upper surface of the first stack layer 250 and a partial upper surface of the isolation stack layer 130. The blocking layer 230 can be a single-layer structure or a multi-layer structure, and the blocking layer 230 can be formed by a thin film deposition process.

[0104] The blocking layer 230 can be made of at least one material among amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, carbon oxide silicon, and carbon nitride silicon.

[0105] When planarizing the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 as described above, it is easy for atoms of each layer to be freed, so there is a risk of contacting other materials in subsequent steps, resulting in short circuits or leakage. By performing the operation of forming the barrier layer 230 as described above, such risks can be effectively avoided.

[0106] Figure 4G Fig. shows a schematic cross-sectional structure of a semiconductor in which a first region upper electrode metal connection layer 191 is formed after forming the barrier layer 230 according to an embodiment of the present application.

[0107] As Figure 4G shown, after forming the barrier layer 230, during the process of forming the first region upper electrode metal connection layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130, and a first region upper electrode via is formed in the upper dielectric layer 170 and the barrier layer 230 through a photolithography process and an etching process, and the first region upper electrode metal connection layer 191 is filled in the first region upper electrode via. That is, the formed first region upper electrode metal connection layer 191 penetrates the barrier layer 230 and contacts the first upper electrode metal layer 253 at the bottom. The entire lower surface of the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, so that the first region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal layer 253, and it is prevented that partial lower surfaces of the bottom of the first region upper electrode metal connection layer 191 contact the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0108] Specifically, the material of the upper dielectric layer 170 may be silicon nitride (Si3N4). In the embodiment of the present application, the upper dielectric layer 170 may also be selected from other materials according to actual application scenarios and process requirements, and is not limited herein.

[0109] The upper dielectric layer 170 can isolate the first upper electrode metal layer 253 and the first region upper electrode metal connection layer 191 from other parts, thereby preventing current from flowing in an unnecessary path and avoiding short circuits and leakage.

[0110] Specifically, the first region upper electrode metal connection layer 191 may be made of copper metal. In the embodiment of the present application, the first region upper electrode metal connection layer 191 may also be made of other metals according to needs, and is not limited herein.

[0111] In the embodiment of the present application, the first lower electrode metal layer 251 may be a single-layer or multi-layer structure.

[0112] In a preferred embodiment of the present application, the first lower electrode metal layer 251 adopts a two-layer structure.

[0113] In some embodiments of the present application, the first lower electrode metal layer 251 includes a first lower electrode metal first sub-layer 2511 and a first lower electrode metal second sub-layer 2512 covering the upper surface of the first lower electrode metal first sub-layer 2511.

[0114] Specifically, the material used for the first lower electrode metal first sub-layer 2511 may be TiN (titanium nitride), and the material used for the first lower electrode metal second sub-layer 2512 may be W (tungsten). The first lower electrode metal second sub-layer 2512 can serve as a connection layer between the first lower electrode metal first sub-layer 2511 and the first switching layer 252. By setting the material used for the first lower electrode metal second sub-layer 2512 to be W (tungsten), not only can the better thermal conductivity of the first lower electrode metal second sub-layer 2512 be ensured, the resistance of the first lower electrode metal second sub-layer 2512 can be guaranteed to be small, so that heat can be quickly conducted, heat dissipation can be promoted, and heat generation can be reduced, thereby reducing the thermal damage to the prepared non-volatile two-terminal storage unit. By setting the material used for the first lower electrode metal second sub-layer 2512 to be W (tungsten), the higher inertness of the first lower electrode metal second sub-layer 2512 can also be guaranteed, so that a chemical reaction between the first lower electrode metal second sub-layer 2512 and the first switching layer 252 can be avoided, and the thermal stability of the prepared non-volatile two-terminal storage unit can be ensured.

[0115] In an embodiment of the present application, the material of the aforementioned first switching layer 252 may be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), etc., which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 can also be selected from other materials according to the actual application scenario and process requirements, which are not limited herein.

[0116] In an embodiment of the present application, the aforementioned first upper electrode metal layer 253 may be a single-layer or multi-layer structure.

[0117] In a preferred embodiment of the present application, the first upper electrode metal layer 253 adopts a two-layer structure.

[0118] In some embodiments of the present application, the first upper electrode metal layer 253 includes a first upper electrode metal first sub-layer 2531 and a first upper electrode metal second sub-layer 2532 covering the surface of the first upper electrode metal first sub-layer 2531, and the material used for the first upper electrode metal first sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532. After the barrier layer 230 is formed, that is, the first region upper electrode metal connection layer 191 penetrates the barrier layer 230, and its bottom contacts the upper surface of the first upper electrode metal second sub-layer 2532.

[0119] Figure 4H The schematic cross-sectional structure diagram of the semiconductor shows the formation of the first-region upper electrode metal connection layer 191 after the formation of the blocking layer 230 in the embodiment of the present application.

[0120] As Figure 4H shown, after the formation of the blocking layer 230, during the process of forming the first-region upper electrode metal connection layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130, and a first-region upper electrode via hole is formed in the upper dielectric layer 170 and the blocking layer 230 through a photolithography process and an etching process, and the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode via hole, so that the formed first-region upper electrode metal connection layer 191 penetrates through the blocking layer 230, and its bottom contacts the upper surface of the first upper electrode metal dichotomous layer 2532. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal dichotomous layer 2532, so that the first-region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal dichotomous layer 2532, and it is prevented that a partial lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0121] By the contact between the bottom of the aforementioned first-region upper electrode metal connection layer 191 and the upper surface of the first upper electrode metal dichotomous layer 2532, it can be prevented that when the first-region upper electrode metal connection layer 191 contacts the first upper electrode metal monolithic layer 2531, the first upper electrode metal monolithic layer 2531 is easily oxidized to generate a high-limited state oxide, which affects the conduction between the first-region upper electrode metal connection layer 191 and the first upper electrode metal layer 253.

[0122] Figure 4I The schematic cross-sectional structure diagram of the semiconductor shows the formation of the first-region upper electrode metal connection layer 191 after the formation of the blocking layer 230 in the embodiment of the present application.

[0123] As Figure 4I shown, during the preparation process of the non-volatile two-terminal storage unit in the embodiment of the present application, the second-region lower electrode metal connection layer 112 in the peripheral circuit region and the second-region upper electrode metal connection layer 192 in the peripheral circuit region can also be generated.

[0124] Specifically, during the process of providing the lower dielectric layer 120 that surrounds the first-region lower electrode metal connection layer 111 and exposes its upper surface, the second-region lower electrode metal connection layer 112 in the peripheral circuit region is also provided. Among them, the second-region lower electrode metal connection layer 112 under the peripheral circuit region is also surrounded by the lower dielectric layer 120, and the upper surface of the second-region lower electrode metal connection layer 112 in the peripheral circuit region is exposed.

[0125] The structure, materials used, and preparation process of the second-zone lower electrode metal connection layer 112 in the peripheral circuit region can be the same as those of the first-zone lower electrode metal connection layer 111, and will not be elaborated here.

[0126] Specifically, the isolation stack layer 130, the blocking layer 230, and the upper dielectric layer 170 in the peripheral circuit region can be etched through the blocking layer 230, and the etching is stopped at the upper surface of the second-zone lower electrode metal connection layer 112 in the peripheral circuit region to form the second-zone upper electrode interconnection via in the peripheral circuit region. Then, the second-zone upper electrode metal connection layer 192 is formed in the second-zone upper electrode interconnection via in the peripheral circuit region to connect the second-zone upper electrode metal connection layer 192 and the second-zone lower electrode metal connection layer 112. Thus, the semiconductor structure preparation in the peripheral circuit region is completed.

[0127] The structure, materials used, and preparation process of the second-zone upper electrode metal connection layer 192 in the peripheral circuit region can be the same as those of the first-zone upper electrode metal connection layer 191, and will not be elaborated here.

[0128] In summary, by means of the preparation scheme of the non-volatile two-terminal memory cell provided above, in the embodiment of the present disclosure, by forming the first stack layer 250 in the first-zone lower electrode interconnection via 141, the preparation of the first lower electrode metal layer 251 and the first upper electrode metal layer 253 of the non-volatile two-terminal memory cell can be achieved by only using one patterned photomask layer, thereby shortening the preparation cost of the non-volatile two-terminal memory cell and simplifying the process flow. At the same time, since only one patterned photomask layer is used, that is, alignment is only performed when forming the first-zone lower electrode interconnection via 141, and alignment is not required when forming the second stack layer (i.e., the stack of the second lower electrode metal first sub-layer 1511, the second lower electrode metal second sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154), the complexity of the process is reduced, and problems such as contact resistance change caused by poor alignment are avoided, improving the stability and reliability of the prepared non-volatile two-terminal memory cell. In addition, in the present application, by forming the first stack layer 250 in the first-zone lower electrode interconnection via 141, the height of the formed first stack layer 250 is reduced compared with the second stack layer in the prior art, so that the formed first stack layer 250 is more easily embedded between the first-zone lower electrode metal connection layer 111 and the first-zone upper electrode metal connection layer 191. Thus, the integration degree of the formed non-volatile two-terminal memory cell can be improved, the current path can be shortened, the resistance can be reduced, and the performance of the formed non-volatile two-terminal memory cell can be improved.

[0129] In this embodiment, a non-volatile two-terminal memory cell is provided, and the non-volatile two-terminal memory cell includes:

[0130] The lower dielectric layer 120 surrounds the first-region lower electrode metal connection layer 111 and exposes its upper surface; the isolation stack layer 130 at least covers the first-region lower electrode metal connection layer 111; the first-region lower electrode interconnection via hole 141 is formed in the isolation stack layer 130, and the bottom of the first-region lower electrode interconnection via hole 141 at least partially contacts the first-region lower electrode metal connection layer 111; the first stack layer 250 includes a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 in the first-region lower electrode interconnection via hole 141, and the upper surface of the first stack layer 250 is flush with the upper surface of the isolation stack layer 130.

[0131] In this embodiment, a non-volatile two-terminal storage cell is further provided. In the first-region lower electrode interconnection via hole 141 of the non-volatile two-terminal storage cell, the first switching layer 252 covers the first lower electrode metal layer 251, and the first upper electrode metal layer 253 covers the first switching layer 252.

[0132] In this embodiment, a non-volatile two-terminal storage cell is further provided. The non-volatile two-terminal storage cell further includes: a blocking layer 230 that at least covers the upper surface of the first stack layer 250, and a first-region upper electrode metal connection layer 191 that penetrates the blocking layer 230, and the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253; the entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, so that the first-region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal layer 253, and prevents partial lower surface of the bottom of the first-region upper electrode metal connection layer 191 from contacting the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0133] In this embodiment, a non-volatile two-terminal storage cell is further provided. The non-volatile two-terminal storage cell further includes: a first-region upper electrode metal connection layer 191. At this time, the non-volatile two-terminal storage cell does not include the blocking layer 230, and the bottom of the first-region upper electrode metal connection layer 191 directly contacts the upper surface of the first upper electrode metal layer 253. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, so that the first-region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal layer 253, and prevents partial lower surface of the bottom of the first-region upper electrode metal connection layer 191 from contacting the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0134] In an embodiment of the present application, the foregoing non-volatile two-terminal storage cell can be prepared by using the preparation method 200 of the non-volatile two-terminal storage cell in any of the foregoing embodiments.

[0135] After obtaining the non-volatile two-terminal memory cell, a second-region lower electrode metal connection layer 112 in the peripheral circuit region and a second-region upper electrode metal connection layer 192 in the peripheral circuit region can also be fabricated, thereby obtaining a further semiconductor device.

[0136] For a specific structural diagram, reference can be made to Figures 3A - 3H and Figures 4A - 4I , which will not be described herein again.

[0137] In this embodiment, a memory is provided. The memory includes one or more non-volatile two-terminal memory cells of any of the foregoing embodiments. These non-volatile two-terminal memory cells can be arranged in a specific manner for storing instructions or data. Since the memory employs the above-mentioned non-volatile two-terminal memory cells, the yield rate of the memory can be improved.

[0138] In this embodiment, an electronic device is provided. The electronic device includes the memory of the embodiments of the present application. The electronic device may further include a processor. Among them, the processor is configured to execute program instructions, and the memory is configured to store program instructions. When the program instructions are loaded and executed by the processor, the electronic device executes according to a specific method. Since the electronic device employs the above-mentioned memory, the possibility of quality problems occurring in the memory of the electronic device can be reduced.

[0139] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many variations, changes, and alternative ways may occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the present disclosure described herein may be employed in practicing the present disclosure. The appended claims are intended to define the scope of protection of the present disclosure and thus cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a non-volatile two-terminal storage unit, characterized in that: The preparation method comprises: Providing a lower dielectric layer (120) surrounding the first region lower electrode metal connection layer (111) and exposing its upper surface; forming an isolation stacking layer (130) that at least covers the lower electrode metal connection layer (111) of the first region; Based on the patterned mask layer, a first region lower electrode interconnection through hole (141) is formed in the isolation stack layer (130), wherein the bottom of the first region lower electrode interconnection through hole (141) at least partially contacts the first region lower electrode metal connection layer (111); sequentially forming a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253); The first lower electrode metal layer (251), the first switching layer (252) and the first upper electrode metal layer (253) outside the region of the lower electrode interconnection through hole (141) of the first zone are removed, and a first stacking layer (250) including the first lower electrode metal layer (251), the first switching layer (252) and the first upper electrode metal layer (253) is formed in the lower electrode interconnection through hole (141) of the first zone, so that the upper surface of the first stacking layer (250) is flush with the upper surface of the isolation stacking layer (130).

2. The preparation method according to claim 1, characterized in that: Forming a first stacked layer (250) flush with the upper surface of the isolation stacked layer (130) in the first region lower electrode interconnection through hole (141) comprises: A first lower electrode metal layer (251), the first switching layer (252) covering the first lower electrode metal layer (251), and the first upper electrode metal layer (253) covering the first switching layer (252) are deposited at least on the inner wall and bottom of the lower electrode interconnection through hole (141) in the first region.

3. The preparation method according to claim 1, characterized in that: After forming the first stacked layer (250), a blocking layer (230) is formed to cover at least the upper surface of the first stacked layer (250).

4. The preparation method according to claim 3, characterized in that: After the blocking layer (230) is formed, a first region upper electrode metal connection layer (191) is formed which penetrates the blocking layer (230) and whose bottom contacts the upper surface of the first upper electrode metal layer (253).

5. The preparation method according to claim 1, characterized in that: After forming the first stacked layer (250), a first region upper electrode metal connection layer (191) is formed, the bottom of which contacts the upper surface of the first upper electrode metal layer (253).

6. The preparation method according to claim 1, characterized in that: In the process of removing the first lower electrode metal layer (251), the first switching layer (252) and the first upper electrode metal layer (253) outside the region of the lower electrode interconnection through hole (141) in the first region, an etching process or a CMP process is used.

7. The preparation method according to claim 1, characterized in that: The first upper electrode metal layer (253) includes a first upper electrode metal layer (2531) and a first upper electrode metal layer (2532) covering the surface of the first upper electrode metal layer (2531), wherein the material used for the first upper electrode metal layer (2531) is more easily oxidized than the material used for the first upper electrode metal layer (2532).

8. The preparation method according to claim 1, characterized in that: The first lower electrode metal layer (251) comprises a first lower electrode metal first layer (2511) and a first lower electrode metal second layer (2512) covering the surface of the first lower electrode metal first layer (2511).

9. The preparation method according to claim 1, characterized in that: The cross-sectional shape of the lower electrode interconnection through hole (141) in the first region is an inverted trapezoid.

10. The preparation method according to claim 9, characterized in that: The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than The lower base width of the inverted trapezoid is greater than 11. The preparation method according to claim 9, characterized in that: The angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

12. A non-volatile two-terminal storage unit, characterized in that: The non-volatile two-terminal storage unit is prepared by the preparation method according to any one of claims 1 to 11, and comprises: A lower dielectric layer (120), the lower dielectric layer (120) surrounds the first region lower electrode metal connection layer (111) and leaves its upper surface exposed; An isolation stacked layer (130), the isolation stacked layer (130) at least covering the first region lower electrode metal connection layer (111); A first region lower electrode interconnection through hole (141), wherein the first region lower electrode interconnection through hole (141) is formed in the isolation stack layer (130), and the bottom of the first region lower electrode interconnection through hole (141) at least partially contacts the first region lower electrode metal connection layer (111); A first stacked layer (250) whose upper surface is flush with the upper surface of the isolation stacked layer (130), the first stacked layer (250) comprising a first lower electrode metal layer (251) in the first region lower electrode interconnection through hole (141), a first switching layer (252) and a first upper electrode metal layer (253).

13. The non-volatile two-terminal memory cell according to claim 12, characterized in that: The non-volatile two-terminal storage unit also includes: a blocking layer (230), the blocking layer (230) at least covering the upper surface of the first stacked layer (250), and The first region upper electrode metal connection layer (191) penetrates the blocking layer (230), and the bottom of the first region upper electrode metal connection layer (191) contacts the upper surface of the first upper electrode metal layer (253).

14. The non-volatile two-terminal memory cell according to claim 12, characterized in that: The non-volatile two-terminal storage unit also includes: A first region upper electrode metal connection layer (191), wherein the bottom of the first region upper electrode metal connection layer (191) contacts the upper surface of the first upper electrode metal layer (253).

15. A memory, characterized in that: The memory comprises one or more non-volatile two-terminal memory cells as claimed in any one of claims 12-14.

16. An electronic device, characterized in that: The electronic device comprises the memory according to claim 15.

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