Ac coupling circuit and transimpedance amplifier

Abstract

Provided is a transimpedance amplifier that obtains a stable output voltage in a short time regardless of the timing of a control signal. A transimpedance amplifier is provided with: a transimpedance amplifier core circuit that amplifies a current input to an input terminal by a desired gain and outputs the amplified current as a voltage signal; one or more buffer circuits for differentially amplifying and outputting the output signal from the transimpedance amplifier core circuit; and an AC coupling circuit inserted between the transimpedance amplifier core circuit and the buffer circuit or between the plurality of buffer circuits, and switching two different time constants according to the amplitude of the output signal, the switching time of time constants of the AC coupling circuit from small to large is longer than the switching time of time constants from large to small.

Description

Technical Field

[0001] The present invention relates to an AC coupling circuit for inputting and outputting signals with different amplitudes and a transimpedance amplifier using the AC coupling circuit. Background Art

[0002] In optical transmission devices such as optical transmission systems capable of high-speed data transmission and passive optical network (PON) systems, a transimpedance amplifier (TIA) is used in an optical receiving circuit that converts an optical signal into an electrical signal. The TIA is input with a photocurrent obtained by performing optical / electrical conversion on a received optical signal by a light-receiving element such as a photodiode (PD). The input current is subjected to current-voltage conversion with an impedance conversion gain proportional to the value of a feedback resistor, and a converted voltage is output.

[0003] In a PON system, upstream packet data from each of a plurality of user-side devices (optical network unit: ONU) to a central office-side device (optical line terminal: OLT) is sent in a burst manner by time-division multiplexing. Since the paths and distances between each ONU and the OLT are different, the optical signals reaching the OLT have different optical powers for each packet. Therefore, in the light-receiving element of the optical receiving circuit of the OLT, the electrical signals of the photocurrents obtained by performing optical / electrical conversion have different signal amplitudes for each packet.

[0004] Generally, upstream packet data is composed of a specific pattern section (preamble pattern) for signal reproduction located at the beginning part of the packet and a subsequent data section (payload). As the preamble pattern, an alternating (repeating) signal of 1 / 0 (Hi / Lo) is often used.

[0005] Figure 1 FIG. is a diagram showing the structure of a conventional TIA. The TIA10 connected to the PD is composed of a TIA core circuit 11 and a buffer (amplifier) circuit 12. The TIA core circuit 11 amplifies the photocurrent input to the input terminal with a desired gain and outputs it as a voltage signal. The buffer circuit 12 differentially amplifies and outputs the output signal from the core circuit. Moreover, between the core circuit 11 and the buffer circuit 12, an AC coupling circuit (i.e., a high-pass filter: HPF) composed of a capacitor C, resistors R1, and R2 is used for connection. The output of the AC coupling circuit is connected to one input of the buffer circuit 12, and a reference voltage VREF (voltage reference) is input to the other input.

[0006] The core circuit 11 converts the photocurrent of the PD and outputs a voltage in a single-ended form. The buffer circuit 12 outputs an electrical signal corresponding to the received optical signal in a differential form centered on VREF to the stage behind the TIA.

[0007] Figure 2 It is a diagram showing the time constant dependence of the output voltage in the existing TIA. Figure 2 Each of the diagrams schematically depicts the vicinity of the boundary of packets from different ONUs, and there is a guard time without data between two packets. As Figure 2 As shown by the output voltage of the core circuit 11 in the upper diagram of , packets 1 and 2 from ONUs at different distances have different amplitudes. Since the output voltage of the TIA core circuit 11 is a single-ended output, the DC components of packets 1 and 2 are also different. Ideally, the AC coupling circuit in the TIA 10 should have the following characteristics: removing only the DC component of the input signal and supplying only the AC component of the data signal to the buffer circuit 12. However, in a TIA using an AC coupling circuit, when packets with different signal amplitudes are input, the time until the normal packet signal is output is affected by the time constant of the AC coupling circuit.

[0008] As described above, when an optical signal is received from an ONU close to the OLT, the signal amplitude of the output voltage of the TIA core circuit 11 is large (packet 1), and when an optical signal is received from an ONU far from the OLT, the signal amplitude of the output voltage of the TIA core circuit 11 is small (packet 2). For each packet, the DC component of the output voltage of the TIA core circuit 11 also changes and changes stepwise near the boundary of the packet. When the time constant of the HPF is relatively large and the cut-off frequency is low, as Figure 2 shown, a slow stepwise change caused by the transmitted low-frequency component appears in the output of the buffer circuit 12. On the contrary, when the time constant of the HPF is relatively small and the cut-off frequency is too high, as Figure 2 shown, drooping occurs in the pulse waveform of the output of the buffer circuit 12 and the data waveform itself is distorted. There is a trade-off relationship between blocking the DC component of the packet and maintaining the pulse waveform.

[0009] In the case where the time constant of the AC coupling circuit is small, it responds quickly to the DC component variation near the boundary of the data packet, and the time until a normal data packet signal is output from the buffer circuit 12 becomes shorter. However, if the payload in the data packet contains a long run of the same symbol, it is impossible to maintain VREF of the output voltage of the buffer circuit 12 during the time required to discriminate these symbols, resulting in misjudgment. On the contrary, if the time constant is increased to maintain VREF during the run of the same symbol included in the payload, the time until a normal data packet signal is output becomes longer. There is also a trade-off relationship between accurate data discrimination for a run of the same symbol and quick adaptation to the DC component variation near the boundary of the data packet. Therefore, a structure is known in which the capacitance value and resistance value of the AC coupling circuit are changed by using an external control signal to switch the time constant.

[0010] Figure 24 FIG. is a diagram showing the structure of a conventional TIA for switching the time constant (Patent Document 1). The TIA 11-1 has an automatic gain control (AGC) circuit 13 of the TIA core circuit 11 and an automatic offset control (AOC) circuit 14 for the DC offset of the differential output from the buffer circuit 12. The TIA 11-1 has a structure for switching between a state with a small time constant and a state with a large time constant in the AGC circuit 13 and the AOC circuit 14. The state with a small time constant is a state where the time until a normal data packet signal is output is fast, and the state with a large time constant corresponds to a state with a high holding power for a run of the same symbol included in the data packet signal. The switching of the time constant of the AC coupling circuit 15 is performed by a reset control signal (RESET).

[0011] Prior Art Documents

[0012] Patent Documents

[0013] Patent Document 1: Japanese Patent No. 5731615 Summary of the Invention

[0014] Problems to be Solved by the Invention

[0015] In order to obtain a data packet signal output in a short time and also maintain a required run of the same symbol, the following structure is considered: the time constant is reduced in the preamble at the beginning of the data packet to obtain a normal signal output, and then the time constant is increased. However, in the circuit described in Patent Document 1, if a structure in which the time constant is reduced in the preamble at the beginning of the data packet to obtain a normal signal output and then the time constant is increased is used, the following problem occurs: the time until a normal output voltage is obtained largely depends on the timing of the control signal.

[0016] Figure 3 This is a diagram showing the output voltage of the AC coupling circuit when the time constant changes from small to large in a short period in the existing TIA. It shows that in Figure 24 the TIA11-1 shown, when the reset control signal (RESET) externally provided to reset the AOC circuit 14 is applied with a timing offset relative to the input voltage to the AC coupling circuit 15, the output voltage of the AC coupling circuit. The reset period is a period including the guard time for switching packets from different ONUs.

[0017] Figure 4 This is an enlarged view showing Figure 3 the reset period in Figure 4 Specifically, in (A) of Figure 4 the reset control signals (Hi-Lo-Hi) 1-0 to 1-9 that are sequentially offset at intervals of 1 / 10 of a cycle of the AC-coupled input voltage are shown. For example, between the reset control signal 1-0 that becomes Lo at the timing of point a (110 ns) and the next reset control signal 1-1, the 1 / 10 cycle of the AC-coupled input voltage, i.e., a phase of 36°, is offset. Between the reset control signal 1-0 and the reset control signal 1-5, the 5 / 10 cycle of the AC-coupled input voltage, i.e., a phase of 180°, is offset. Figure 4 Shown in (B) of Figure 4 is the change in the time constant τ of the AC coupling circuit obtained indirectly by monitoring the potential difference between certain nodes in the TIA11-1. The Hi period of the reset control signal and the state with a large time constant, and the Lo period of the reset control signal and the state with a small time constant are roughly consistent.

[0018] Here, consider the following situation of the reset control signal 1-0: It becomes Lo at point a (110 ns) where the amplitude value of the input voltage is 0 and the phase is 0°, and becomes Hi at point b (140 ns) where the amplitude value of the input voltage is 0 and the phase is 0°. In the state where the reset control signal is Lo, the time constant is very small, so the cut-off frequency of the HPF is higher than the sine wave frequency. Therefore, Figure 4 in (D) of

[0019] the output voltage of the AC coupling circuit disappears at point a, and at point b where the time constant switches to Hi, the output voltage waveform 2-0 immediately appears. At point b, since it is output from the initial state where the instantaneous amplitude of the sine wave is 0 and the phase is 0°, the output voltage waveform 2-0 does not have a DC component and immediately obtains a normal AC-coupled output sine wave.Next, consider the case of the reset control signal 1-1 with a phase shift of 36°. As Figure 4 the output voltage of the AC coupling circuit of (D), at the timing delayed by 36° in phase from point b, the output voltage waveform 2-1 appears. At this time, the output voltage waveform 2-1 starts from the initial state of the amplitude value on the + side, reaches the + peak, and then decreases toward the negative side. As a result, the AC coupling output becomes the output waveform 2-1 with the DC component shifted toward the negative side.

[0020] Consider the case of the reset control signal 1-2 with a phase further shifted by 36° from the reset control signal 1-1. As Figure 4 the output voltage of the AC coupling circuit of (D), at the timing delayed by 72° in phase from point b, the output voltage waveform 2-2 appears. Compared with the output waveform 2-1, the AC coupling output becomes the output voltage waveform 2-2 with the DC component further increasing toward the negative side. As time goes by, the output waveforms 2-1 and 2-2 in the state of DC component shift, as Figure 3 shown, the DC component gradually converges to 0, and a normal AC coupling output is obtained.

[0021] Consider the case of the reset control signal 1-5 with a phase shifted by 180° from the reset control signal 1-0. As Figure 4 the output voltage of the AC coupling circuit of (D), at the timing delayed by 180° in phase from point b, the output voltage waveform 2-5 appears. Since it is output from the initial state of the instantaneous amplitude 0 of the sine wave, as a result, the DC component of the output voltage waveform 2-5 is 0V, and when it becomes the state with a large time constant when the reset control signal is Hi, a sine wave of a normal AC coupling output is immediately obtained.

[0022] As described above, when the reset control signal changes from Lo to Hi and the time constant changes from the small state to the large state, the initial value of the output voltage appearing from the AC coupling circuit at the edge of the reset control signal changes according to the timing of the reset control signal. Depending on the initial value, the DC component included in the output signal of the AC coupling circuit also varies according to the timing of the reset control signal. As a result, the time until the DC component converges to 0 (VREF) and a normal AC coupling output voltage is obtained varies according to the timing of the applied reset control signal.

[0023] Since the distances from each ONU to the OLT are different, the OLT controls the transmission timing of the data packets of each ONU based on the round-trip time between the OLT and the ONU. However, due to the variation of the round-trip time, the timing of the data packets reaching the TIA circuit of the OLT also varies. This means that in Figure 3 and Figure 4 it is impossible to align the timing of the reset control signal with respect to the sine wave.

[0024] Solution for solving problems

[0025] An object of the present invention is to provide an AC coupling circuit and a transimpedance amplifier that can obtain a stable output voltage in a short time regardless of the timing of a control signal.

[0026] In order to achieve such an object, an embodiment of the AC coupling circuit is characterized by including a switching unit that switches between two different time constants according to the amplitude of an input signal, and the switching time from a small time constant to a large time constant is longer than the switching time from a large time constant to a small time constant.

[0027] Furthermore, an embodiment of the transimpedance amplifier is characterized by including: a transimpedance amplifier core circuit that amplifies the current input to an input terminal with a desired gain and outputs it as a voltage signal; one or more buffer circuits that differentially amplify and output the output signal from the transimpedance amplifier core circuit; and an AC coupling circuit that is inserted between the transimpedance amplifier core circuit and the buffer circuit or between the multiple buffer circuits, and switches between two different time constants according to the amplitude of the output signal, and the switching time of the AC coupling circuit from a small time constant to a large time constant is longer than the switching time from a large time constant to a small time constant.

[0028] Advantages of the Invention

[0029] According to the present invention, an AC coupling circuit and a transimpedance amplifier can be provided, which can obtain a stable output voltage in a short time regardless of the timing of a control signal. Brief Description of the Drawings

[0030] Figure 1 It is a diagram showing the structure of an existing TIA.

[0031] Figure 2 It is a diagram showing the time constant dependence of the output voltage in an existing TIA.

[0032] Figure 3 It is a diagram showing the output voltage of the AC coupling circuit when the time constant changes from small to large in a short time in an existing TIA.

[0033] Figure 4 is Figure 3 An enlarged view during the reset period in.

[0034] Figure 5 It is a diagram showing the operation concept of the TIA according to the first embodiment of the present invention.

[0035] Figure 6 It is a diagram showing the structure of the TIA according to the first embodiment.

[0036] Figure 7 It is a diagram showing the time constant control of the AC coupling circuit of the TIA of the first embodiment.

[0037] Figure 8 It is a diagram showing the output voltage of the AC coupling circuit when the time constant of the TIA of the first embodiment gradually changes from small to large.

[0038] Figure 9 It is Figure 8 An enlarged view during the reset period in

[0039] Figure 10 It is a diagram showing the time constant control of the AC coupling circuit of the TIA of the second embodiment.

[0040] Figure 11 It is a diagram showing the variation of the charge stored in the capacitor of the AC coupling circuit.

[0041] Figure 12 It is a diagram showing the relationship between the difference between VREF and the center value of the sine wave amplitude and the duty ratio of the output waveform.

[0042] Figure 13 It is a diagram showing the relationship between the average voltage of the AC coupling output voltage and the allowable VREF range.

[0043] Figure 14 It is a diagram showing the amplitude of the output signal with respect to a low-pass filter where the input signal is 1 / 10.

[0044] Figure 15 It is a diagram showing the variation of the average voltage of the output signal of a first-order low-pass filter.

[0045] Figure 16 It is a diagram showing the time constant control signal generation circuit of the TIA of the third embodiment.

[0046] Figure 17 It is a diagram showing the structure of the TIA of the third embodiment.

[0047] Figure 18 It is a diagram showing the circuit structure of the AC coupling circuit and the time constant control signal generation circuit.

[0048] Figure 19 It is a diagram showing the time constant control of the time constant control signal generation circuit.

[0049] Figure 20 It is a diagram showing the output voltage of the AC coupling circuit when the time constant of the TIA of the third embodiment gradually changes from small to large.

[0050] Figure 21 It is Figure 20Enlarged view during reset in

[0051] Figure 22 is a diagram showing the output voltage of the AC coupling circuit when the time constant of the TIA of the third embodiment gradually changes from small to large.

[0052] Figure 23 is a diagram showing the output voltage of the AC coupling circuit when the time constant of the TIA of the third embodiment gradually changes from small to large.

[0053] Figure 24 is a diagram showing the structure of an existing TIA that switches the time constant. Detailed Embodiment

[0054] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0055] [First Embodiment]

[0056] Figure 5 is a diagram showing the operation concept of the TIA of the first embodiment of the present invention. As Figure 5 shown in (a) of , the AC coupling circuit of the first embodiment has a switching unit that switches the time constant in two ways according to the input signal amplitude. Here, "switching in two ways" means that there are two ways of switching between different time constants. Specifically, as Figure 5 shown in (b) of , two different time constants are set, and it is switched from a large time constant to a small time constant, or from a small time constant to a large time constant. At this time, the switching time (2) from a small time constant to a large time constant is longer than the switching time (1) from a large time constant to a small time constant.

[0057] Figure 6 is a diagram showing the structure of the TIA of the first embodiment. The TIA20 connected to the PD includes: a TIA core circuit 21 that amplifies the photocurrent input to the input terminal with a desired gain and outputs it as a voltage signal; a buffer circuit 22 that differentially amplifies and outputs the output signal from the core circuit; and an AC coupling circuit 23 that connects the TIA core circuit 21 and the buffer circuit 22. The AC coupling circuit 23 includes a capacitor C connected in series and a resistor R connected in parallel, forming a so-called high-pass filter.

[0058] Moreover, a switch SW is provided in parallel with the resistor R to short-circuit the resistor R. By controlling the on / off of the switch SW with a time constant control signal (RESET) provided from the outside, the resistance value of the resistor constituting the high-pass filter can be changed, and the CR time constant of the AC coupling circuit 23 can be switched in two ways. It should be noted that in the following description, the time constant control signal (RESET) and inFigure 3 and Figure 4 corresponds to the reset control signal described in. By the time constant control signal (RESET) of Hi→Lo→Hi, the switching of the two time constants shown in Figure 5 (b) is implemented.

[0059] It should be noted that in the structure shown in Figure 6 , although the on / off control of the switch SW connected in parallel with the resistor R is performed, for example, multiple resistors and switches can also be used to switch the resistance value in two ways to change the time constant.

[0060] In addition, in the structure shown in Figure 6 , an AC coupling circuit is inserted between the TIA core circuit and the buffer circuit. However, in the case where the buffer circuit is configured in multiple stages, even if the AC coupling circuit is inserted between the buffer circuits, the effects of the present invention can be achieved.

[0061] Figure 7 is a diagram showing the time constant control of the AC coupling circuit of the TIA of the first embodiment. In the above PON system, the OLT receives optical signals from multiple ONUs in a time-division manner. The output voltage of the TIA core circuit 21 varies according to the intensity of the received optical signal. And when a data packet 2 with a small signal amplitude is input, the output voltage of the AC coupling circuit 23 is greatly affected by the change in the time constant. Therefore, in the TIA 20, when the data packet 2 is input, according to the time constant control signal (RESET) provided from the outside, the time constant is switched as shown in Figure 5 (b).

[0062] Specifically, the OLT sets a guard time between the reception periods from each ONU. During this guard time, the time constant control signal (RESET) is output, and time constant control is performed such that the switching time from small to large of the time constant is longer than the switching time from large to small of the time constant. The period without an optical signal between the data packet 1 and the data packet 2 becomes the guard time and is about the length of several pulses, but Figure 7 is a diagram schematically shown, and the time relationship is not limited to the example of Figure 7 .

[0063] Figure 8 is a diagram showing the output voltage of the AC coupling circuit when the time constant of the TIA of the first embodiment gradually changes from small to large. Figure 8 Corresponds to each waveform in the description of the prior art in Figure 3 . If comparing the waveform of the time constant in Figure 3 and Figure 8For the waveform of the time constant, it can be seen that the length of the period during which the time constant switches from small to large is more than several tens of times, and the time constant changes slowly from small to large. In addition, the output voltage of the AC coupling circuit has almost no DC component deviation and immediately becomes a normal AC coupling output within about two periods of the sine wave.

[0064] Figure 9 is an enlarged view Figure 8 during the reset period in. Compare Figure 4 of (B) and Figure 9 of (B), it can be known that the switching time of the time constant from small to large is very long. In the TIA of the first embodiment, regardless of the timing of the reset control signal, the DC component converges to 0 after 10 to 20 ns from the rising edge of the reset control signal from Lo to Hi.

[0065] In Figure 4 the output voltage waveform shown, the Lo state of the reset control signal is roughly consistent with the state of the small time constant, and the Hi state is also roughly consistent with the state of the small time constant. From the moment of the rising edge from Lo to Hi, the HPF becomes a non-attenuating state with respect to the sine wave frequency, and the input voltage appears immediately as it is. Therefore, the instantaneous initial value of the output voltage of the AC coupling circuit varies according to the phase of the output sine wave at the timing of the rising edge. The DC component also varies according to the timing of the reset control signal, and the time to reach the normal AC coupling output varies.

[0066] In contrast, for Figure 9 the output voltage waveform shown in (D), the input voltage does not appear immediately without attenuation from the rising edge of the time constant control signal (reset control signal), but appears gradually (ramp up). This is because, as Figure 9 shown in (B), the state of the time constant changing from small to large changes very slowly, so the cut-off frequency of the HPF of the AC coupling circuit also changes slowly compared with the existing structure. The attenuation amount of the HPF of the AC coupling circuit for the sine wave frequency gradually decreases from the state of the largest attenuation, so the output voltage appears gradually from the time of the rising edge. At the rising edge of the time constant control signal from Lo to Hi, the HPF is still in a state of large attenuation, so the initial value of the output voltage of the AC coupling circuit is approximately around 0. Regardless of the timing of the rising edge, the initial value of the output voltage is approximately 0, and the DC component is also approximately 0, so a normal AC coupling output is obtained immediately within about two periods of the sine wave.

[0067] In this way, the switching time of the time constant from small to large is large enough compared with the phase change of the AC coupling input voltage, so a normal output voltage can be obtained regardless of the timing of the time constant control signal (RESET). Compare Figure 4the AC-coupled output voltage and Figure 9 From the AC-coupled output voltage of, it can be seen that in TIA20, a normal output voltage can be obtained within a short time of about 20 ns from the rising edge of the time constant control signal (RESET).

[0068] [Second Embodiment]

[0069] Figure 10 FIG. is a diagram showing the time constant control of the AC coupling circuit of the TIA according to the second embodiment of the present invention. In the TIA of the second embodiment, the switching time of the time constant from small to large is longer than the switching time from large to small, but it is different from the first embodiment in that the time constant changes discretely through multiple stages from a small state to a large state. For example, in Figure 6 In the structure shown, in order to change the time constant, a plurality of resistors are prepared as the resistor R of the AC coupling circuit 23, and switching is performed using a switch, and the time constant can be changed discretely from a small state to a large state.

[0070] Here, in the case of changing the time constant from a small state to a large state, the lower limit value and the upper limit value of the time constant are quantitatively considered using a specific example.

[0071] Figure 11 FIG. is a diagram showing the change in the charge of the capacitor charged in the AC coupling circuit. Figure 11 (a) of shows the relationship between the AC-coupled output voltage and the change in the charge of the capacitor charged in the AC coupling circuit. The potential difference V between the input and output of the AC coupling circuit is determined by the charge Q of the capacitor C and is expressed by the following equation.

[0072] Q = CV Equation (1)

[0073] In the steady state, the charge charged in the capacitor is constant. After that, if a data packet 2 with a small input signal amplitude is generated, charge charging and discharging occur. The response time at this time is the time until the charge and discharge amount becomes constant and the charge becomes constant. The operation until the charge and discharge charge becomes constant is determined by the time constant of the AC coupling circuit, and the result of the charge and discharge of the charge affects the AC-coupled output voltage.

[0074] Figure 11(b) shows the relationship between the two time constants, i.e., the case where the change amount of charge is small with respect to the time constant and the case where the time constant is large. In order to make the time until the normal output voltage is obtained within a specified time regardless of the AC-coupled input voltage and the timing of changing the time constant from a small state to a large state, it is sufficient that the change amount of this charge converges within a certain range. In order to make the change amount of charge converge within a certain range, it is sufficient that the average voltage of the AC-coupled output voltage is within a certain range from the center voltage of the amplitude. When amplifying the output of the AC-coupled circuit by a buffer circuit, as Figure 6 shown, a reference voltage VREF is set as the reference voltage of the amplifier.

[0075] However, if there is a difference in the average voltage of the AC-coupled output voltage with respect to the reference voltage, the duty ratio of the output waveform of the AC-coupled output voltage changes. Therefore, as the definition of the change amount of charge as a capacitor, i.e., the range of the average voltage, the allowable value of the duty ratio in the output waveform is used. Here, for generalization, the input waveform is set to a sine wave.

[0076] Figure 12 is a graph showing the relationship between the difference of VREF from the center value of the sine wave amplitude and the duty ratio of the output waveform. Here, for simplicity, in Figure 12 (a), the sine wave amplitude is set to ±1 V and the frequency is set to 1 GHz, and the duty ratio is obtained when VREF changes by ±0.5 V in units of 0.1 V. Figure 12 (b) shows the relationship between the duty ratio and the value by which VREF deviates from the center of the sine wave amplitude. From this relationship, it can be seen that when a certain allowable duty ratio is determined, the allowable VREF range corresponding thereto is given by the following formula.

[0077] VREF variation range [V] = allowable duty ratio “%” / 33 Formula (2)

[0078] For example, if the variation of the allowable duty ratio is set to ±3.3% or less, the VREF variation range is about ±0.1 V or less.

[0079] Figure 13 is a graph showing the relationship between the average voltage of the AC-coupled output voltage and the allowable VREF range. For the obtained allowable VREF variation range, the maximum value and the minimum value of the response time constant are obtained under the condition that the time variation of the response time constant is constant. Specifically, as Figure 13 (a) shown, in the case of changing the time constant from a small state to a large state step by step, the maximum value and the minimum value of the time constant when changing only through one intermediate stage are obtained. As Figure 13As shown in (b), when the time constant is small, it is sufficient that the average voltage of the AC-coupled output voltage falls within the VREF allowable range. That is, the allowable value of the duty cycle in the output waveform of the AC-coupled output voltage is satisfied, and the change amount of the charge converges within a specified range in the capacitor of the AC-coupled circuit. On the other hand, when the time constant is large, it is sufficient that the average voltage of the AC-coupled output voltage converges within the VREF allowable range within the desired response time.

[0080] Consider the case where the allowable duty cycle variation is set to ±3.3%, the VREF variation range is about ±0.1 V or less, that is, the sine wave amplitude of the input waveform is 1 / 10. At this time, the lower limit of the time constant only needs to ensure that the average voltage of the AC-coupled output voltage is within the VREF allowable range, so the average voltage of the input waveform only needs to be ±10% or less of the amplitude. Therefore, as Figure 14 shown in (a), as a circuit where the amplitude of the output signal is 1 / 10 of the input signal, assume a first-order low-pass filter composed of a capacitor C and a resistor R. As Figure 14 shown in (b), to make the frequency 1 / 10 of the input signal frequency the cut-off frequency, the CR time constant of the low-pass filter can be set as follows.

[0081] [Equation 1]

[0082]

[0083] Here, f is the frequency of the input signal. On the other hand, as described above, the upper limit of the time constant is the desired response time.

[0084] Figure 15 is a diagram showing the variation of the average voltage of the output signal of the first-order low-pass filter. In the case of the first-order low-pass filter, the variation of the average voltage of the output signal is represented by the following equation.

[0085] [Equation 2]

[0086]

[0087] When the allowable duty cycle variation is ±3.3%, as Figure 15 shown, the time (time constant) when the average voltage is ±10% or less (0.9 or more) is 2.32CR. That is, if the desired response time is set to T settle , the following equation relationship can be obtained.

[0088] [Equation 3]

[0089]

[0090] Therefore, when changing the time constant from a small state to a large state, the time constant has the following relationship with the lower limit value and the upper limit value.

[0091] [Equation 4]

[0092]

[0093] Alternatively, when the waveform of the input signal is a sine wave, the relationship is as follows.

[0094] [Equation 5]

[0095]

[0096] [Third Embodiment]

[0097] In the second embodiment, when the time constant is changed stepwise from a small state to a large state, the lower limit and the upper limit of the time constant are obtained. In the third embodiment, a method of continuously changing the time constant from a small state to a large state will be described.

[0098] Figure 16 is a diagram showing a time constant control signal generation circuit of a TIA according to the third embodiment of the present invention. As Figure 16 (a) of shows, the time constant control signal generation circuit generates a time constant control signal, for example, based on a pulsed control signal (RESET) provided from the outside. As Figure 16 (b) of shows, for the input of the control signal (RESET), it is possible to perform a time constant switching in which the switching time (2) from a small time constant to a large time constant is longer than the switching time (1) from a large time constant to a small time constant.

[0099] Figure 17 is a diagram showing the structure of a TIA according to the third embodiment. The TIA30 connected to the PD includes: a TIA core circuit 31 that amplifies the photocurrent input to the input terminal with a desired gain and outputs it as a voltage signal; a buffer circuit 32 that differentially amplifies and outputs the output signal from the core circuit; and an AC coupling circuit 33 that connects the TIA core circuit 31 and the buffer circuit 32. The AC coupling circuit 33 includes a capacitor C connected in series with both and a resistor R connected in parallel, forming a so-called high-pass filter. Moreover, a switch SW is provided in parallel with the resistor R, and the time constant of the AC coupling circuit 33 is controlled by a time constant control signal generation circuit 34.

[0100] It should be noted that, as described above, when the buffer circuit is configured in multiple stages, the AC coupling circuit can also be inserted between the buffer circuits.

[0101] Figure 18FIG. is a diagram showing the circuit configuration of an AC coupling circuit and a time constant control signal generation circuit. The FET switch SW is connected in parallel with the resistor R of the AC coupling circuit 33, and the FET switch SW is controlled by the time constant control signal generation circuit 34. The time constant control signal generation circuit 34 is constituted by, for example, a two-stage buffer circuit, and generates a control voltage for the FET switch SW having a long falling edge time in response to the input of a rectangular control signal (RESET).

[0102] It should be noted that, in the Figure 18 structure shown, in order to change the time constant, an FET switch connected in parallel with the resistor R of the AC coupling circuit 33 is used, but a variable resistor may be used instead of the switch. Any structure may be used as long as the resistance value of the resistor constituting the high-pass filter can be continuously changed.

[0103] Figure 19 FIG. is a diagram showing the time constant control of the time constant control signal generation circuit. According to the pulsed control signal (RESET) provided from the outside, the FET switch SW control voltage is output from the time constant control signal generation circuit 34 to the AC coupling circuit 33. The circuit constants may be set such that the time constant based on the combined resistance of the FET switch SW and the resistor R (4.9 kΩ) and the capacitor C falls within the above lower limit value and upper limit value range.

[0104] Figure 20 FIG. is a diagram showing the output voltage of the AC coupling circuit when the time constant of the TIA of the third embodiment gradually changes from small to large. Figure 21 is an enlarged view showing Figure 20 the reset period in. It is the result of simulating the response characteristics when the time constants are set to 1 ns, 1.6 ns, 20 ns, and 50 ns. The output voltage of the AC coupling circuit 33, the time constant, and the average voltage of the output voltage are shown arranged.

[0105] When the frequency of the input signal is set to 1 GHz and the desired response time T settle is set to 50 nsec, according to the relational expression shown in the second embodiment, the lower limit value of the time constant is 1.6 nsec and the upper limit value is 21.6 nsec. If the time constant of the AC coupling circuit 33 is within this range, the average voltage of the output voltage of the AC coupling circuit 33 becomes ±10% or less of the amplitude of the output voltage.

[0106] Figure 22 FIG. is a diagram showing the AC coupling output voltage when the time constant is set to 1.6 ns and a control signal (RESET) provided from the outside is applied with a timing offset with respect to the AC coupling input voltage. Figure 23This is a diagram showing the case where the time constant is set to 20 ns. It can be seen that a normal output voltage can be obtained regardless of the timing of the control signal (RESET).

[0107] Description of reference numerals:

[0108] 10, 11-1, 20, 30: TIA; 11, 21, 31: TIA core circuit; 12, 22, 32: buffer circuit; 23, 33: AC coupling circuit; 34: time constant control signal generation circuit.

Claims

1. An AC coupling circuit, characterized in that, Comprising: A switching unit that switches between two different time constants according to the amplitude of an input signal, The switching time from a smaller time constant to a larger time constant is longer than the switching time from a larger time constant to a smaller time constant.

2. The AC coupling circuit according to claim 1, characterized in that, The switching from the smaller time constant to the larger time constant is performed by discretely increasing the time constant.

3. The AC coupling circuit according to claim 1, characterized in that, The switching from the smaller time constant to the larger time constant is performed by continuously increasing the time constant.

4. The AC coupling circuit according to claim 1, 2 or 3, characterized in that, Composed of a high-pass filter including a capacitor and a resistor, The switching unit switches the two time constants by changing the resistance value of the resistor.

5. A transimpedance amplifier, characterized in that, Comprising: A transimpedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs it as a voltage signal; One or more buffer circuits that differentially amplify and output the output signal from the transimpedance amplifier core circuit; And An AC coupling circuit that is inserted between the transimpedance amplifier core circuit and the buffer circuit or between the multiple buffer circuits, and switches between two different time constants according to the amplitude of the output signal, The switching time from a smaller time constant to a larger time constant of the AC coupling circuit is longer than the switching time from a larger time constant to a smaller time constant.

6. The transimpedance amplifier according to claim 5, characterized in that, The AC coupling circuit is composed of a high-pass filter including a capacitor and a resistor, and the switching from the smaller time constant to the larger time constant is performed by discretely increasing the two time constants by switching the resistance value of the resistor.

7. The transimpedance amplifier according to claim 5, characterized in that, The AC coupling circuit is composed of a high-pass filter including a capacitor and a resistor, and the switching from the smaller time constant to the larger time constant is performed by continuously increasing the two time constants by changing the resistance value of the resistor.

Images