Display panel and dead pixel shielding method thereof

Abstract

The invention discloses a display panel and a dead pixel shielding method thereof. The display panel comprises a scanning line, a data line, a common voltage line and a pixel circuit. The scanning line receives grid voltage, the data line receives data voltage, and the common voltage line receives common voltage; the pixel circuit is provided with a transistor and a cholesterol liquid crystal capacitor, wherein the transistor is provided with a first end coupled with a data line, a control end coupled with a scanning line and a second end; in a dead pixel circuit of the pixel circuit, a cholesterol liquid crystal capacitor is coupled between a control terminal of a transistor and a common voltage line, and voltage waveforms of the data voltages and the common voltage are set, so that the cholesterol liquid crystal of the dead pixel circuit is operated in a focal conic state or a focal conic + planar state.

Description

Technical Field

[0001] The present invention relates to a display technology, and more particularly to a display panel and a method for masking defective pixels thereof. Background Art

[0002] In a liquid crystal TV panel, when a pixel in the display panel is a defective pixel, the source and drain of the transistor are cut off, the circuit for supplying a data voltage to the liquid crystal (or liquid crystal circuit) in the pixel is disconnected, and the contact position of the common voltage electrode bridging the pixel in the pixel array is welded, so that the data voltage is maintained at the voltage of the common electrode, that is, the voltage for driving the liquid crystal is 0, thereby darkening the pixel. However, when the liquid crystal is a cholesteric liquid crystal, an alternating voltage is used for the common voltage. After the defective pixel is repaired by the above method, it cannot be darkened, which affects the overall viewing effect. Summary of the Invention

[0003] The present invention provides a display panel and a method for masking defective pixels thereof. In a pixel circuit using cholesteric liquid crystal as a material in the display panel, after the defective pixels determined are repaired and the driving waveform is set, the defective pixels can be darkened, thereby reducing the influence on the overall viewing effect.

[0004] The display panel of the present invention includes a plurality of scan lines, a plurality of data lines, a plurality of common voltage lines, and a plurality of pixel circuits; these scan lines receive a plurality of gate voltages; these data lines are interleaved with these scan lines and receive a plurality of data voltages; these common voltage lines commonly receive a common voltage; these pixel circuits are arranged in an array and each has a transistor and a cholesteric liquid crystal capacitor, wherein the transistor has a first end coupled to one of these data lines, a control end coupled to one of these scan lines, and a second end; in each of these pixel circuits determined to be non-defective pixels, the cholesteric liquid crystal capacitor is coupled between the second end of the transistor and one of these common voltage lines; in a defective pixel circuit among these pixel circuits determined to be defective pixels, the cholesteric liquid crystal capacitor is coupled between the control end of the transistor and one of these common voltage lines, and the voltage waveforms of these data voltages and the common voltage are set such that the cholesteric liquid crystal of the damaged pixel circuit operates in a focal conic state or a focal conic + planar state.

[0005] In an embodiment of the above display panel, a cross voltage of the cholesteric liquid crystal capacitor in the defective pixel circuit is between a homeotropic voltage and a planar voltage, wherein the homeotropic voltage causes the cholesteric liquid crystal to operate in a homeotropic state, and the planar voltage causes the cholesteric liquid crystal to operate in a planar state.

[0006] In an embodiment of the above display panel, during a pixel scan of each of the plurality of pixel circuits, during a waiting period between a reset period and a scan period, a corresponding one of the plurality of data voltages and the common voltage are at a first high voltage level higher than a reference voltage.

[0007] In an embodiment of the above display panel, the reset period before the waiting period includes a positive reset period and a negative reset period after the positive reset period.

[0008] During the positive reset period, a corresponding one of the plurality of data voltages is at the first high voltage level, and the common voltage is at a first low voltage level lower than the reference voltage, and

[0009] During the negative reset period, a corresponding one of the plurality of data voltages is at the first low voltage level, and the common voltage is at the first high voltage level.

[0010] In an embodiment of the above display panel, the scan period after the waiting period sequentially includes a negative common swing period, a negative scan period, a positive common swing period, and a positive scan period.

[0011] During the negative common swing period, a corresponding one of the plurality of data voltages is at a second high voltage level between the first high voltage level and the reference voltage, and the common voltage is at the second high voltage level.

[0012] During a negative scan period, a corresponding one of the plurality of data voltages steps up from a second low voltage level between the first low voltage level and the reference voltage to the second high voltage level, and the common voltage is at the second high voltage level.

[0013] During a positive common swing period, a corresponding one of the plurality of data voltages is at the second high voltage level, and the common voltage is at the second low voltage level, and

[0014] During a positive scan period, a corresponding one of the plurality of data voltages steps down from the second high voltage level to the second low voltage level, and the common voltage is at the second low voltage level.

[0015] In an embodiment of the above display panel, during a sustain period after the pixel scan period, a corresponding one of the plurality of data voltages and the common voltage are at the reference voltage.

[0016] In an embodiment of the above display panel, the reference voltage is zero volts.

[0017] Method for shielding defective pixels of a display panel according to the present invention. The display panel includes a plurality of scan lines for receiving a plurality of gate voltages, a plurality of data lines for receiving a plurality of data voltages, a plurality of common voltage lines for commonly receiving a common voltage, and a plurality of pixel circuits. The method includes the following steps: Among the defective pixel circuits of these pixel circuits determined to be defective pixels, connect the cholesteric liquid crystal capacitor of the defective pixel circuit between the control terminal of the transistor of the defective pixel circuit and one of these common voltage lines, where the transistor has a first end connected to one of these data lines, a control terminal connected to one of these scan lines, and a floating second end. Set the voltage waveforms of these data voltages and the common voltage such that the cholesteric liquid crystal of the damaged pixel circuit operates in the focal conic state or the focal conic + planar state.

[0018] In an embodiment of the above method, a cross voltage of the cholesteric liquid crystal capacitor in the defective pixel circuit is a focal conic voltage, where the focal conic voltage causes the cholesteric liquid crystal to operate in a focal conic state.

[0019] In an embodiment of the above method, it further includes:

[0020] During a pixel scan of each of these pixel circuits, during a waiting period located between a reset period and a scan period, the corresponding one of these data voltages and the common voltage are at a first high voltage level higher than a reference voltage.

[0021] In an embodiment of the above method, the reset period before the waiting period includes a positive reset period and a negative reset period after the positive reset period, and the method further includes:

[0022] During the positive reset period, the corresponding one of these data voltages is at the first high voltage level, and the common voltage is at a first low voltage level lower than the reference voltage; and

[0023] During the negative reset period, the corresponding one of these data voltages is at the first low voltage level, and the common voltage is at the first high voltage level.

[0024] In an embodiment of the above method, the scan period after the waiting period sequentially includes a negative common swing period, a negative scan period, a positive common swing period, and a positive scan period, and the method further includes:

[0025] During the negative common swing period, the corresponding one of these data voltages is at a second high voltage level between the first high voltage level and the reference voltage, and the common voltage is at the second high voltage level;

[0026] During a negative scan period, one of the plurality of data voltages ramps in a stepped manner from a second low voltage level between the first low voltage level and the reference voltage to the second high voltage level, and the common voltage is the second high voltage level;

[0027] During a positive common swing period, one of the plurality of data voltages is at the second high voltage level, and the common voltage is the second low voltage level; and

[0028] During a positive scan period, one of the plurality of data voltages descends in a stepped manner from the second high voltage level to the second low voltage level, and the common voltage is the second low voltage level.

[0029] In an embodiment of the above method, it further includes:

[0030] During a sustain period after the pixel scan period, one of the plurality of data voltages and the common voltage are the reference voltage.

[0031] In an embodiment of the above method, the reference voltage is zero volts.

[0032] Based on the above, in the display panel and the dead pixel masking method according to the embodiments of the present invention, in a pixel circuit using cholesteric liquid crystal as a material in the display panel, one end (i.e., the pixel electrode) of the cholesteric liquid crystal capacitor is coupled to the control end of the transistor, so that the pixel electrode is mostly in the disabled level, and by controlling the voltage waveform of the data voltage, the cholesteric liquid crystal of the dead pixel circuit operates in the focal conic state or the focal conic + planar state, which can darken the dead pixel circuit and reduce the impact on the overall viewing effect.

[0033] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. is a system schematic diagram of a display panel according to an embodiment of the present invention.

[0035] Figure 2 FIG. is a timing waveform schematic diagram of a single pixel scan period of a display panel according to an embodiment of the present invention.

[0036] Figure 3 FIG. is a state timing schematic diagram of a pixel circuit of a display panel according to an embodiment of the present invention driven according to Figure 2 the timing waveform.

[0037] Figure 4Schematic diagram of a timing waveform during a single pixel scan for driving a display panel that does not include a defective pixel circuit according to an embodiment of the present invention.

[0038] Figure 5 The pixel circuit of the display panel according to an embodiment of the present invention is driven according to Figure 4 The state timing schematic diagram of the timing waveform.

[0039] Figure 6 Flowchart of a defective pixel masking method for a display panel according to an embodiment of the present invention.

[0040] Wherein, reference numerals:

[0041] 100: Display panel

[0042] Clc: Cholesteric liquid crystal capacitor

[0043] ComSwing-: Negative common swing period

[0044] ComSwing+: Positive common swing period

[0045] ELpxl: Pixel electrode

[0046] Hold: Hold period

[0047] Lcom: Common voltage line

[0048] Ldat: Data line

[0049] Lsc: Scan line

[0050] PXb: Defective pixel circuit

[0051] PXn: Normal pixel circuit

[0052] Reset-: Negative reset period

[0053] Reset+: Positive reset period

[0054] Scan-: Negative scan period

[0055] Scan+: Positive scan period

[0056] T: Transistor

[0057] Vcom: Common voltage

[0058] VG: Gate voltage

[0059] VGH: Gate high voltage

[0060] VGL: Gate low voltage

[0061] VH1, VH2: High voltage

[0062] VL1, VL2: Low voltage

[0063] Vdata: Data voltage

[0064] Wait: Waiting period

[0065] S110, S120: Steps Detailed implementation manners

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this invention, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0067] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer, or portion from another. Thus, the "first component", "part", "region", "layer", or "portion" discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings herein.

[0068] The terms used herein are for the purpose of describing particular embodiments only and are not limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, regions, wholes, steps, operations, components, and / or parts, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, components, parts, and / or combinations thereof.

[0069] Figure 1 It is a system schematic diagram of a display panel according to an embodiment of the present invention. Please refer to Figure 1, in this embodiment, the display panel 100 includes a plurality of scan lines Lsc, a plurality of data lines Ldat, a plurality of common voltage lines Lcom, and a plurality of pixel circuits (such as a normal pixel circuit PXn and a defective pixel circuit PXb). Among them, the scan lines Lsc receive a plurality of gate voltages VG. The data lines Ldat are interleaved with the scan lines Lsc and receive a plurality of data voltages Vdata. The plurality of common voltage lines Lcom commonly receive a common voltage Vcom.

[0070] These normal pixel circuits PXn and defective pixel circuits PXb are arranged in an array and each has a transistor T and a cholesteric liquid crystal capacitor Clc with cholesteric liquid crystal as the dielectric, where the cholesteric liquid crystal is located, for example, between one of the pixel electrode ELpxl and the common voltage line Lcom. In each of the normal pixel circuit PXn and the defective pixel circuit PXb, the transistor T has a first end coupled to one of these data lines Ldat, a control end coupled to one of these scan lines Lsc, and a second end.

[0071] In each of the normal pixel circuits PXn determined to be non-defective, the cholesteric liquid crystal capacitor Clc is coupled between the second end of the transistor T and one of these common voltage lines Lcom. And in the defective pixel circuit PXb determined to be defective, the cholesteric liquid crystal capacitor Clc is coupled between the control end of the transistor T and one of these common voltage lines Lcom. In other words, the trace between the cholesteric liquid crystal capacitor Clc and the second end of the transistor T is cut off, and a bonding wire is welded or a new trace is formed between the pixel electrode ELpxl and the control end of the transistor T, but the embodiments of the present invention are not limited thereto. Then, the voltage waveforms of the data voltage Vdata and the common voltage Vcom provided via a control circuit (such as a source driver) are set such that a cholesteric liquid crystal of the defective pixel circuit PXb operates in a focal conic state or a focal conic + planar state.

[0072] Generally speaking, when a cholesteric liquid crystal operates in a planar state, the liquid crystal molecules are arranged neatly and can reflect light of a specific wavelength. In this state, the color of the reflected image can be seen. Moreover, when the cholesteric liquid crystal operates in a focal conic state, the arrangement of the liquid crystal molecules scatters light, and the liquid crystal in this state does not display color. Therefore, in a pixel circuit using a cholesteric liquid crystal as a material in a display panel, coupling the pixel electrode ELpxl to the control terminal of the transistor T can keep the pixel electrode ELpxl at a disabled level (such as a low gate voltage VGL) most of the time. And by controlling the voltage waveform of the data voltage Vdata, the cholesteric liquid crystal of the defective pixel circuit PXb is made to operate in a focal conic state or a focal conic + planar state, so that the defective pixel circuit PXb can be darkened, thereby reducing the impact on the overall viewing effect.

[0073] Figure 2 It is a timing waveform diagram during the single-pixel scanning of a display panel according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , where the same or similar components are denoted by the same or similar reference numerals. In this embodiment, it shows the single-pixel scanning of each of the normal pixel circuit PXn and the defective pixel circuit PXb. The single-pixel scanning period, for example, includes a positive reset period Reset+, a negative reset period Reset-, a wait period Wait, a negative common swing period ComSwing-, a negative scan period Scan-, a positive common swing period ComSwing+, and a positive scan period Scan+.

[0074] During the positive reset period Reset+, the corresponding one of the gate voltages VG switches between a high gate voltage VGH (such as +20 volts) and a low gate voltage VGL (such as -24 volts) to form a relatively wide pulse. And the corresponding one of the data voltages Vdata is a high voltage VH2 (corresponding to a first high voltage level, such as +20 volts), and the common voltage Vcom is a low voltage VL2 (corresponding to a first low voltage level, such as -20 volts) lower than zero volts (0V, corresponding to the reference voltage).

[0075] During the negative reset period Reset- after the positive reset period Reset+, the corresponding one of the gate voltages VG also switches between the high gate voltage VGH and the low gate voltage VGL to form a relatively wide pulse. And the corresponding one of the data voltages Vdata switches to the low voltage VL2, and the common voltage Vcom switches to the high voltage VH2.

[0076] During the waiting period Wait after Reset- during negative reset, the corresponding one of the gate voltages VG also switches between the gate high voltage VGH and the gate low voltage VGL to form a wider pulse. Also, the corresponding one of the data voltages Vdata and the common voltage Vcom are the high voltage VH2.

[0077] During the negative common swing period ComSwing- after the waiting period Wait, the corresponding one of the gate voltages VG also switches between the gate high voltage VGH and the gate low voltage VGL to form a wider pulse. Also, the corresponding one of the data voltages Vdata is a high voltage VH1 (corresponding to the second high voltage level, e.g., +10 volts) between the high voltage VH2 and 0V, and the common voltage Vcom is the high voltage VH1.

[0078] During the negative scan period Scan- after the negative common swing period ComSwing-, the corresponding one of the gate voltages VG also switches between the gate high voltage VGH and the gate low voltage VGL to form multiple narrower pulses. Also, the corresponding one of the data voltages Vdata steps up from a low voltage VL1 (corresponding to the second low voltage level, e.g., -10 volts) between the low voltage VL2 and 0V to the high voltage VH1, and the common voltage Vcom is the high voltage VH1. Here, a single pulse corresponds to a voltage level of the data voltage Vdata, that is, a set of written data voltages Vdata (i.e., one of the low voltage VL1, 0V, and high voltage VH1). Further, according to the required gray scale, the corresponding data voltage Vdata is given during the negative scan period Scan-, for example, sequentially providing 6 sets of low voltage VL1, 10 sets of 0V, and 0 sets of high voltage VH1, or sequentially controlling 4 sets of low voltage VL1, 8 sets of 0V, and 4 sets of high voltage VH1, where the total number of sets remains the same, and the data voltages Vdata all step up.

[0079] During the positive common swing period ComSwing+ after the negative scan period Scan-, the corresponding one of the gate voltages VG also switches between the gate high voltage VGH and the gate low voltage VGL to form a wider pulse. Also, the corresponding one of the data voltages Vdata is at the high voltage VH1, and the common voltage Vcom is the low voltage VL1.

[0080] During the positive scan period Scan+ after ComSwing+ during the positive common swing, the corresponding one of the gate voltages VG also switches between the gate high voltage VGH and the gate low voltage VGL to form a plurality of narrower pulses. Also, the corresponding one of the data voltages Vdata steps down from the high voltage VH1 to the low voltage VL1 in a stepped manner, and the common voltage Vcom is the low voltage VL1. Among them, a single pulse corresponds to one voltage level of the data voltage Vdata, that is, writing a set of data voltages Vdata (that is, one of the high voltage VH1, 0V, and low voltage VL1), and its operation is similar to that during the negative scan period Scan-, the difference being that the data voltage Vdata all steps down in a stepped manner.

[0081] In this embodiment, the positive reset period Reset+ and the negative reset period Reset- can be regarded as a reset period, the negative common swing period ComSwing-, the negative scan period Scan-, the positive common swing period ComSwing+ and the positive scan period Scan+ can be regarded as a scan period, and the wait period Wait is located between the reset period and the scan period. Also, the above-mentioned reset period, the wait period Wait and the above-mentioned scan period can be regarded as a pixel scan period.

[0082] In this embodiment, during the hold period Hold after the pixel scan period, the corresponding one of the data voltage Vdata and the common voltage Vcom is 0V.

[0083] Figure 3 It is a state timing diagram of the pixel circuit of the display panel according to an embodiment of the present invention being driven according to Figure 2 the timing waveform. Please refer to Figures 1 to 3 wherein the same or similar components use the same or similar reference numerals. In this embodiment, it is based on Figure 2The waveform shown drives the normal pixel circuit PXn and the defective pixel circuit PXb in the display panel 100. During the positive reset period Reset+, the voltage level of the pixel electrode ELpxl is maintained at the gate high voltage VGH for most of the time (which can be regarded as driving with the high voltage VH2), and a large voltage difference (ΔV) is formed between the high voltage VH2 of the pixel electrode ELpxl and the low voltage VL2 of the common voltage Vcom, so that the cholesteric liquid crystal can be switched to the vertical (homeotropic) state "H"; during the negative reset period Reset-, the voltage level of the pixel electrode ELpxl is maintained at the gate high voltage VGH for most of the time, and the voltage difference (ΔV) between the high voltage VH2 of the pixel electrode ELpxl and the high voltage VH2 of the common voltage Vcom is approximately 0. Therefore, depending on the setting of the gate high voltage VGH, the cholesteric liquid crystal can be switched to the planar state "P", or the planar state "P" + the focal conic state "FC"; during the wait period Wait, the voltage level of the pixel electrode ELpxl is maintained at the gate high voltage VGH for most of the time, and the voltage difference (ΔV) between the high voltage VH2 of the pixel electrode ELpxl and the high voltage VH2 of the common voltage Vcom is approximately 0. Therefore, depending on the setting of the gate high voltage VGH, the cholesteric liquid crystal is maintained in the planar state "P", or the planar state "P" + the focal conic state "FC"; during the negative scan period Scan-, the voltage level of the pixel electrode ELpxl is maintained at the gate low voltage VGL for most of the time (which can be regarded as driving with the low voltage VL2), and the voltage difference (ΔV) between the low voltage VL2 of the pixel electrode ELpxl and the high voltage VH1 of the common voltage Vcom can drive the cholesteric liquid crystal to switch to another planar state "P" + the focal conic state "FC"; and during the positive scan period Scan+, the voltage level of the pixel electrode ELpxl is maintained at the gate low voltage VGL for most of the time, and the voltage difference (ΔV) between the low voltage VL2 of the pixel electrode ELpxl and the high voltage VL1 of the common voltage Vcom will drive the cholesteric liquid crystal to switch to the focal conic state "FC".

[0084] According to the above, during the hold period Hold after the pixel scan period, the voltage difference Vlc of the cholesteric liquid crystal capacitor Clc in the defective pixel circuit PXb is expected to be maintained at the focal conic voltage, so that the cholesteric liquid crystal operates in the focal conic state or the focal conic state + the planar state, where the focal conic voltage makes the cholesteric liquid crystal operate in (switch to) the focal conic state, and due to circuit design or material reasons, the voltage difference Vlc of the cholesteric liquid crystal capacitor Clc may be slightly lower than the focal conic voltage, so that some cholesteric liquid crystal molecules may not be able to switch to the focal conic state (i.e., still in the planar state).

[0085] Figure 4Schematic diagram of a timing waveform during a single pixel scan for driving a display panel that does not include a defective pixel circuit according to an embodiment of the present invention. Figure 5 For a pixel circuit of a display panel according to an embodiment of the present invention Figure 4 The state timing diagram of driving according to the timing waveform. Please refer to Figures 1 to 5 , where the same or similar components are denoted by the same or similar reference numerals. In this embodiment, for example, the normal pixel circuit PXn in the display panel 100 is driven with the waveform shown in Figure 4 . The waveform shown in Figure 4 is substantially the same as Figure 2 , except that during the waiting period Wait, one of the corresponding data voltages Vdata and the common voltage Vcom are 0V. And, the positive common swing period ComSwing+ and the positive scan period Scan+ are located before the negative common swing period ComSwing- and the negative scan period Scan-. And, as shown in Figure 5 , during the waiting period Wait, the cross voltage Vlc of the cholesteric liquid crystal capacitor Clc climbs and transitions to the planar state "P" + the focal conic state "FC"; during the positive scan period Scan+, the cross voltage Vlc of the cholesteric liquid crystal capacitor Clc increases, and the cholesteric liquid crystal transitions to the focal conic state "FC"; and, during the negative scan period Scan-, the cross voltage Vlc of the cholesteric liquid crystal capacitor Clc increases again, thus transitioning to the vertical state "H", and after power-off (i.e., during the hold period Hold), the cholesteric liquid crystal transitions to the planar state "P". Therefore, relative to Figure 2 , under the drive of the waveform shown in Figure 4 , the defective pixel circuit PXb will still display a relatively high brightness, which is easily noticed by the user and cannot achieve the shielding effect.

[0086] Figure 6 Flowchart of a defective pixel shielding method for a display panel according to an embodiment of the present invention. Please refer to Figure 6 , in this embodiment, the display panel includes a plurality of scan lines for receiving a plurality of gate voltages, a plurality of data lines for receiving a plurality of data voltages, a plurality of common voltage lines for commonly receiving a common voltage, and a plurality of pixel circuits, and the defective pixel shielding method includes the following steps.

[0087] In step S110, in the defective pixel circuit determined to be a defective pixel, the cholesteric liquid crystal capacitor of the defective pixel circuit is coupled between the control terminal of the transistor of the defective pixel circuit and one of these common voltage lines, where the transistor has a first end coupled to one of these data lines, a control terminal coupled to one of these scan lines, and a floating second end. And, in step S120, the voltage waveform of the data voltage is set such that the cholesteric liquid crystal of the defective pixel circuit operates in the focal conic state or the focal conic + planar state. Herein, the steps of steps S110 and S120 are used for illustration, and the embodiments of the present invention are not limited thereto. And the details of steps S110 and S120 can be referred to Figures 1 to 5 as shown, and will not be elaborated herein.

[0088] In summary, for the display panel and its defective pixel masking method according to the embodiments of the present invention, in the pixel circuit using cholesteric liquid crystal as a material in the display panel, the pixel electrode of the cholesteric liquid crystal capacitor is coupled to the control terminal of the transistor, so that the pixel electrode can be mostly at the disabled level, and by controlling the voltage waveform of the data voltage, the cholesteric liquid crystal of the defective pixel circuit operates in the focal conic state or the focal conic + planar state, which can darken the defective pixel circuit and reduce the impact on the overall viewing effect.

[0089] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention pertains can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended patent application scope.

Claims

1. A display panel, characterized in that: include: A plurality of scanning lines receiving a plurality of gate voltages; a plurality of data lines interlaced with the plurality of scan lines and receiving a plurality of data voltages; A plurality of common voltage lines receive a common voltage; A plurality of pixel circuits are arranged in an array and each of them has a transistor and a cholesterol liquid crystal capacitor, wherein the transistor has a first end coupled to one of the plurality of data lines, a control end coupled to one of the plurality of scan lines, and a second end. Wherein, in each of the plurality of pixel circuits determined to be a non-defective pixel, the cholesterol liquid crystal capacitor is coupled between the second end of the transistor and one of the plurality of common voltage lines, and In a bad pixel circuit of the plurality of pixel circuits determined as a bad pixel, the cholesterol liquid crystal capacitor is coupled between the control terminal of the transistor and one of the plurality of common voltage lines, and A voltage waveform of the plurality of data voltages and the common voltage is set so that a cholesterol liquid crystal of the dead pixel circuit operates in a focal conic state or a focal conic+planar state.

2. The display panel according to claim 1, wherein: A voltage across the cholesterol liquid crystal capacitor in the dead pixel circuit is between a homeotropic voltage and a planar voltage, wherein the homeotropic voltage causes the cholesterol liquid crystal to operate in a homeotropic state, and the planar voltage causes the cholesterol liquid crystal to operate in a planar state.

3. The display panel according to claim 1, wherein: In a pixel scanning period of each of the plurality of pixel circuits, in a waiting period between a reset period and a scanning period, a corresponding one of the plurality of data voltages and the common voltage are a first high voltage level higher than a reference voltage.

4. The display panel according to claim 3, wherein: The reset period before the waiting period includes a positive reset period and a negative reset period after the positive reset period. During the forward reset period, a corresponding one of the plurality of data voltages is the first high voltage level, and the common voltage is a first low voltage level lower than the reference voltage, and During the negative-going reset period, a corresponding one of the plurality of data voltages is the first low voltage level, and the common voltage is the first high voltage level.

5. The display panel according to claim 4, wherein: The scanning period after the waiting period includes a negative common oscillation period, a negative scanning period, a positive common oscillation period and a positive scanning period in sequence. During the negative common swing period, a corresponding one of the plurality of data voltages is a second high voltage level between the first high voltage level and the reference voltage, and the common voltage is the second high voltage level. During a negative scanning period, a corresponding one of the plurality of data voltages rises stepwise from a second low voltage level between the first low voltage level and the reference voltage to the second high voltage level, and the common voltage is the second high voltage level. During a positive common swing period, a corresponding one of the plurality of data voltages is at the second high voltage level, and the common voltage is at the second low voltage level, and In a forward scanning period, a corresponding one of the plurality of data voltages drops from the second high voltage level to the second low voltage level in a step-like manner, and the common voltage is the second low voltage level.

6. The display panel according to claim 3, wherein: In a sustaining period after the pixel scanning period, a corresponding one of the plurality of data voltages and the common voltage are the reference voltage.

7. The display panel according to claim 3, wherein: The reference voltage is zero volts.

8. A bad pixel shielding method for a display panel, characterized in that: The display panel includes a plurality of scan lines receiving a plurality of gate voltages, a plurality of data lines receiving a plurality of data voltages, a plurality of common voltage lines receiving a common voltage, and a plurality of pixel circuits. The method includes: In a bad pixel circuit of the plurality of pixel circuits determined as a bad pixel, a cholesterol liquid crystal capacitor of the bad pixel circuit is coupled between a control terminal of a transistor of the bad pixel circuit and one of the plurality of common voltage lines, wherein the transistor has a first terminal coupled to one of the plurality of data lines, the control terminal coupled to one of the plurality of scan lines, and a second terminal that is floating; and A voltage waveform of the plurality of data voltages is set so that a cholesterol liquid crystal of the dead pixel circuit operates in a focal conic state or a focal conic+planar state.

9. The bad pixel shielding method according to claim 8, characterized in that: A voltage across the cholesteric liquid crystal capacitor in the dead pixel circuit is a focal conic voltage, wherein the focal conic voltage causes the cholesteric liquid crystal to operate in a focal conic state.

10. The bad pixel shielding method according to claim 8, characterized in that: Also includes: In a pixel scanning period of each of the plurality of pixel circuits, in a waiting period between a reset period and a scanning period, a corresponding one of the plurality of data voltages and the common voltage are at a first high voltage level higher than a reference voltage.

11. The bad pixel shielding method according to claim 10, characterized in that: The reset period before the waiting period includes a positive reset period and a negative reset period after the positive reset period, and the method further includes: During the forward reset period, a corresponding one of the plurality of data voltages is the first high voltage level, and the common voltage is a first low voltage level lower than the reference voltage; and During the negative-going reset period, a corresponding one of the plurality of data voltages is the first low voltage level, and the common voltage is the first high voltage level.

12. The bad pixel shielding method according to claim 11, characterized in that: The scanning period after the waiting period sequentially includes a negative common oscillation period, a negative scanning period, a positive common oscillation period and a positive scanning period, and the method further includes: During the negative common swing period, a corresponding one of the plurality of data voltages is a second high voltage level between the first high voltage level and the reference voltage, and the common voltage is the second high voltage level; During a negative scanning period, a corresponding one of the plurality of data voltages rises in a step-like manner from a second low voltage level between the first low voltage level and the reference voltage to the second high voltage level, and the common voltage is the second high voltage level; During a forward common swing period, a corresponding one of the plurality of data voltages is at the second high voltage level, and the common voltage is at the second low voltage level; and In a forward scanning period, a corresponding one of the plurality of data voltages drops from the second high voltage level to the second low voltage level in a step-like manner, and the common voltage is the second low voltage level.

13. The bad pixel shielding method according to claim 10, characterized in that: Also includes: In a sustaining period after the pixel scanning period, a corresponding one of the plurality of data voltages and the common voltage are the reference voltage.

14. The bad pixel shielding method according to claim 10, characterized in that: The reference voltage is zero volts.

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