Cyclic redundancy check method and device, electronic equipment and medium

Abstract

The embodiment of the invention provides a cyclic redundancy check method and device, electronic equipment and a medium. The method comprises the following steps: determining a target pre-calculation result according to a target parameter; the target parameter comprises a target generator polynomial and a target data bit width; the target pre-calculation result comprises a cyclic redundancy check (CRC) input coefficient matrix and an input data coefficient matrix; determining a parallel CRC calculation logic according to the target pre-calculation result; the parallel CRC calculation logic is used for calculating a CRC check result of each check cycle in each check cycle; and updating the to-be-verified system according to the parallel CRC calculation logic, and when the to-be-verified system receives the to-be-verified data, controlling the to-be-verified system to execute the parallel CRC calculation logic to verify the to-be-verified data to obtain a verification result. The method is used for achieving the effect of efficiently determining the parallel CRC calculation logic applied to the to-be-verified system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a cyclic redundancy check method, apparatus, electronic device, and medium. Background Art

[0002] Cyclic Redundancy Check (CRC), as a key error detection technology, has a very wide range of applications in the field of digital communication, especially in the field of chip design.

[0003] Currently, to improve the CRC check efficiency, a parallel CRC algorithm has been proposed in the known technology, which is used to process multiple data bits in parallel through matrix transformation and multi-channel synchronous processing, etc., to achieve the effect of accelerating the CRC check efficiency. Specifically, in the known technology, after determining the generating polynomial and data bit width for generating the CRC algorithm, the parallel CRC calculation logic is derived based on the generating polynomial and data bit width, and the corresponding hardware description language for this process is manually written to enable the corresponding hardware structure in the system to be verified to implement the parallel CRC calculation logic.

[0004] In the above process, due to the inability to efficiently generate the parallel CRC calculation logic, there is a defect that the system applying the parallel CRC calculation logic cannot implement cyclic redundancy check in a timely and efficient manner. Summary of the Invention

[0005] Embodiments of this application provide a cyclic redundancy check method, apparatus, electronic device, and medium, so as to achieve the effect of quickly generating the parallel CRC calculation logic according to the target parameters, which is beneficial to enabling the system to be verified to verify the data to be verified in a timely and efficient manner.

[0006] In a first aspect, embodiments of this application provide a cyclic redundancy check method, including:

[0007] Determine a target pre-calculation result according to the target parameters; the target parameters are related to the verification requirements of the system to be verified, and the target parameters include a target generating polynomial and a target data bit width; the target pre-calculation result includes a cyclic redundancy check (CRC) input coefficient matrix and an input data coefficient matrix;

[0008] Determine the parallel CRC calculation logic according to the target pre-calculation result; the parallel CRC calculation logic is used to calculate the CRC check result of the check period according to the intermediate CRC check result of the system to be verified, the CRC input coefficient matrix, the input data coefficient matrix, and the input data of the system to be verified in each check period;

[0009] Update the system to be verified according to the parallel CRC calculation logic, and when the system to be verified receives data to be verified, control the system to be verified to execute the parallel CRC calculation logic to verify the data to be verified, and obtain a verification result.

[0010] In a possible implementation, the method further includes:

[0011] Obtain the hardware configuration information of the system to be verified, and determine optional parameters according to the hardware configuration information; the optional parameters include an optional generating polynomial and an optional data bit width;

[0012] Determine the target generating polynomial and the target data bit width from the optional parameters according to the verification requirements.

[0013] In a possible implementation, when the system to be verified receives data to be verified, controlling the system to be verified to execute the parallel CRC calculation logic to verify the data to be verified, and obtaining a verification result includes:

[0014] When the system to be verified receives data to be verified, divide the data to be verified into at least one input data according to the target data bit width;

[0015] Control the system to be verified to sequentially calculate the CRC verification result corresponding to each input data according to the CRC calculation logic, and determine the verification result according to the CRC verification result.

[0016] In a possible implementation, each input data corresponds to a verification period; controlling the system to be verified to sequentially calculate the CRC verification result corresponding to each input data according to the CRC calculation logic, and determining the verification result according to the CRC verification result includes:

[0017] Control the system to be verified to use the CRC verification result of the previous verification period as the intermediate CRC verification result in each verification period, and input the input data of the verification period and the intermediate CRC verification result into a CRC calculation module for implementing the parallel CRC calculation logic to obtain the CRC verification result of the verification period;

[0018] When the calculation of all input data is completed, use the CRC verification result of the current verification period as the verification result.

[0019] In a possible implementation, the method further includes:

[0020] For any parameter, control a preset software tool to generate a corresponding pre-calculation result based on the generating polynomial and data bit width included in the parameter;

[0021] Store the parameter and the corresponding pre - calculated result in a preset hardware lookup table;

[0022] Determining the target pre - calculated result according to the target parameter includes:

[0023] Search for the target parameter in the preset hardware lookup table to obtain the target pre - calculated result.

[0024] In a possible implementation, the control preset software tool generates a corresponding pre - calculated result based on the generating polynomial and data bit width included in the parameter, including:

[0025] Input the generating polynomial and data bit width into the preset software tool to obtain the pre - calculated result; when receiving the generating polynomial and the data bit width, the preset software tool generates a coefficient matrix and an identity matrix according to the generating polynomial and the data bit width, generates a feedback matrix according to the coefficient matrix, the identity matrix and a preset generation rule, and obtains the pre - calculated result according to the feedback matrix; wherein, the coefficient matrix is an N×1 matrix, and N is related to the highest power of the generating polynomial; the identity matrix is an (N - 1) - order matrix.

[0026] In a possible implementation, when generating the feedback matrix, the preset software tool determines the input data coefficient matrix according to the feedback matrix and determines the input data coefficient matrix according to the feedback matrix and a zero matrix.

[0027] In a second aspect, an embodiment of the present application provides a cyclic redundancy check device, including:

[0028] A first determination module, configured to determine a target pre - calculated result according to a target parameter; the target parameter is related to the check requirement of the system to be checked, and the target parameter includes a target generating polynomial and a target data bit width; the target pre - calculated result includes a cyclic redundancy check (CRC) input coefficient matrix and an input data coefficient matrix;

[0029] A second determination module, configured to determine a parallel CRC calculation logic according to the target pre - calculated result; the parallel CRC calculation logic is used to calculate the CRC check result of each check cycle according to the intermediate CRC check result of the system to be checked, the CRC input coefficient matrix, the input data coefficient matrix, and the input data of the system to be checked;

[0030] A check module, configured to update the system to be checked according to the parallel CRC calculation logic, and when the system to be checked receives data to be checked, control the system to be checked to execute the parallel CRC calculation logic to check the data to be checked and obtain a check result.

[0031] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory and a processor;

[0032] The memory stores computer-executable instructions;

[0033] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementation manners of the first aspect.

[0034] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the above first aspect and / or various possible implementation manners of the first aspect.

[0035] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the above first aspect and / or various possible implementation manners of the first aspect.

[0036] The cyclic redundancy check method, device, electronic device and medium provided by the embodiments of the present application. Specifically, the method of the present application first determines a target pre-computation result through target parameters related to the check requirements of the system to be checked, then determines the parallel CRC calculation logic according to the target pre-computation result, and finally updates the system to be checked according to the parallel CRC calculation logic. Based on this, when the system to be checked receives the data to be checked, the system to be checked is controlled to execute the parallel CRC calculation logic to check the data to be checked and obtain a check result. In the method of the present application, since the process of calculating the target parameters in real time to determine the parallel CRC calculation logic is saved, the whole process only involves simple memory access and does not require complex logical operations, so there is a more efficient advantage, which is conducive to the system to be checked to complete the CRC check in time. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0038] Figure 1 It is a schematic diagram of the scenario of the cyclic redundancy check method provided by the present application;

[0039] Figure 2 It is a schematic flow chart of the cyclic redundancy check method provided by the present application Figure 1 ;

[0040] Figure 3 It is a schematic flow chart of the cyclic redundancy check method provided by the present application Figure 2 ;

[0041] Figure 4 Flow schematic of the cyclic redundancy check method provided for this application Figure 3 ;

[0042] Figure 5 Structural schematic diagram of the cyclic redundancy check device provided for this application;

[0043] Figure 6 Structural schematic diagram of the electronic device provided for this application.

[0044] Through the above-mentioned drawings, specific embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0045] First, explanations are given for the terms involved in this application:

[0046] Cyclic Redundancy Check (CRC): It is a fast algorithm that generates a short fixed-length check code based on data such as network data packets or computer files, mainly used to detect or verify possible errors that may occur after data transmission or storage. CRC utilizes the principles of division and remainders to achieve the function of error detection, and has advantages such as clear principles and simple implementation.

[0047] Generating polynomial: Defines how the CRC algorithm processes data. It determines the grouping method of data during CRC calculation and the generation rules of check bits. Different generating polynomials will result in different CRC check results.

[0048] Data bit width: In CRC, the data bit width refers to the number of bits by which data is processed in blocks during CRC calculation.

[0049] CRC input coefficient matrix: Used to describe the transition of the CRC state, that is, how to transition from the current intermediate CRC check result to the next intermediate CRC check result.

[0050] Input data coefficient: Used to describe how the input data changes the CRC state, that is, the influence of the input data on the intermediate CRC check result.

[0051] In addition to the above terms, terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. In the descriptions of the following embodiments, "a plurality" means more than two, unless otherwise specifically defined.

[0052] As a key error detection technology, CRC has a very wide range of applications in the field of digital communication, especially in the field of chip design. CRC processes data through a generating polynomial to generate a check code, thereby detecting possible errors during data transmission or storage.

[0053] Currently, traditional CRC mostly adopts serial calculation. Specifically, the data to be verified is input bit by bit into a Linear Feedback Shift Register (LFSR) to generate a check code. In traditional serial CRC calculation, each bit of the LFSR is calculated bit by bit according to the data to be verified and the CRC polynomial. The serial process usually requires M clock cycles to process M input data (i.e., the data to be verified). In each clock cycle, the CRC check result of the current clock cycle is calculated through the following formula: CRCout = (CRCin ≫ 1) ⊕ ((CRCin & MSB_MASK) ⋅ (Poly & LOWER_BITS)), where MSB_MASK is the most significant bit mask (e.g., 0x8000 for 16-bit CRC), Poly is the hexadecimal number corresponding to the fixed polynomial, LOWER_BITS is the part of the fixed polynomial after removing the most significant bit (e.g., for CRC-16-CCITT's 0x1021, removing the most significant bit corresponds to 0x1021 & 0x7FFF = 0x1021), and ≫ is the right shift operator.

[0054] It can be understood that the above serial method performs well in low-speed or medium-speed data transmission scenarios. However, with the significant increase in data transmission rate and the growth of data frame length, especially in the scenario of large-scale data processing in integrated circuits, the performance of serial CRC check has been difficult to meet the requirements.

[0055] In the known technology, to improve the CRC check efficiency, an optimization scheme called the look-up table method is proposed. Specifically, the look-up table method uses each byte of the data to be verified as an index, directly looks up the corresponding intermediate CRC check result in the table according to this index, and then obtains the final CRC check result by gradually merging these intermediate CRC check results. It can be understood that this method is very suitable for processing scenarios with a large amount of data because each pre-calculated result in the table can accelerate the entire calculation process.

[0056] It should be noted that when obtaining the CRC check result according to the look-up table method, it is first necessary to construct the table Table[k]: according to the CRC generation polynomial G(x), pre-calculate the intermediate results corresponding to all possible 8-bit input values, and construct a look-up table of 256 items. Specifically, for an 8-bit index, Table[k]=CRC(k≪(N-8), G(x)), where k∈[0, 255]. Here, N is the CRC bit width. For example, for a 32-bit CRC, N = 32. k is used to represent the 8-bit index value (0x00 - 0xFF), and ≪ is the left shift operator, and the overflow part of the high bit is truncated.

[0057] More specifically, the calculation formula for obtaining the CRC check result based on the look-up table method is: Index=(CRCin≫(N−8))⊕Data[i], CRCout=(CRCin≪8)⊕Table[Index]. Here, N is the data bit width of the CRC algorithm, CRCin represents the CRC check result of the previous clock cycle, Data[i] represents the i-th input data, Table is the CRC check result table generated according to the polynomial generation formula, Index is the index value of the element table, and CRCout represents the CRC check result of the current clock cycle.

[0058] It can be understood that the look-up table method pre-calculates and stores all possible intermediate CRC check results, and directly looks up the corresponding intermediate CRC check results according to the input during actual operation, thus greatly reducing the calculation time. This method performs excellently in high data rate scenarios, with a constant response time and relatively simple implementation, and can be efficiently implemented through a read-only memory (ROM) in hardware.

[0059] However, the look-up table method consumes a large amount of storage space. Especially when dealing with long data frames or complex CRC algorithms, the storage requirements will increase significantly, which poses a significant challenge to embedded systems or FPGA designs with limited resources. In addition, as the length of the data frame increases, the management and generation of the look-up table become more and more complex, thus limiting the practical application of the look-up table method in large-scale systems.

[0060] To address the above limitations, a parallel CRC algorithm has been proposed in the known technology. For example, it is used to process multiple data bits in parallel through matrix transformation and multi-channel synchronous processing, etc., to achieve the effect of accelerating the CRC check efficiency. Specifically, in the known technology, after determining the generation polynomial and data bit width for generating the CRC algorithm, the parallel CRC calculation logic is derived according to the generation polynomial and data bit width, and the corresponding hardware description language (such as VHDL or Verilog) for this process is manually written, and based on this hardware description language, the corresponding hardware structure in the system to be checked can implement this parallel CRC calculation logic.

[0061] However, although the parallel CRC algorithm obtained by the above process significantly improves the speed of CRC calculation, manually writing complex hardware description language (such as Verilog or HDL) code still faces the risks of high complexity and error-proneness. Especially when dealing with multi-byte long data frames, this complexity will increase exponentially, posing a huge challenge to the hardware design work. Thus, there is a defect that the parallel CRC calculation logic and the corresponding hardware description language cannot be generated efficiently, which further leads to the inability to enable the system applying the parallel CRC calculation logic to implement cyclic redundancy check in a timely and efficient manner.

[0062] Therefore, the present application proposes a cyclic redundancy check method, device, electronic device and medium to solve the above problems. Specifically, in the method of the present application, it is proposed to determine the corresponding target pre-calculation result through the target parameter, and then the corresponding parallel CRC calculation logic can be determined according to the target pre-calculation result. By enabling the system to be verified to execute the parallel CRC calculation logic, the verification of the data to be verified input into the system to be verified is realized.

[0063] It can be understood that the cyclic redundancy check method of the present application can be executed by any electronic device, and the method of the present application is applicable to any scenario that needs to perform CRC check on transmitted data or stored data, such as network communication, storage devices, file transfer, embedded systems, etc. Exemplarily, Figure 1 is a schematic diagram of the scenario of the cyclic redundancy check method provided by the present application. As Figure 1 shown, the present application can be used for the CRC check scenario of in-vehicle embedded systems. Specifically, the in-vehicle embedded system interacts with an electronic device configured with the cyclic redundancy check method of the present application.

[0064] The electronic device determines the corresponding target pre-calculation result according to the target parameter related to the verification requirement of the in-vehicle embedded system, and then determines the parallel CRC calculation logic according to the target pre-calculation result, and updates the in-vehicle embedded system according to the parallel CRC calculation logic. When the in-vehicle embedded system has a verification requirement, it controls the in-vehicle embedded system to execute the CRC calculation logic to verify the data to be verified and obtain the verification result.

[0065] Based on this setting, on the one hand, the electronic device can efficiently determine the corresponding target pre-calculation result according to the target parameter indicated by the in-vehicle embedded system, and then can quickly obtain the parallel CRC calculation logic applicable to the in-vehicle embedded system without involving complex logical operations and the process of writing hardware description language, thus having a higher efficiency effect. On the other hand, the process does not involve the step of manually writing hardware description language, so the problem of low accuracy caused by writing mistakes can be avoided.

[0066] The following uses specific embodiments to elaborate in detail on the technical solution of the present application and how the technical solution of the present application solves the above technical problems. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be elaborated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0067] It should be noted that the method of the present application is specifically executed by any electronic device. The electronic device can be independently set differently from the system to be verified, or can be integrated into the system to be verified. This is not limited in the embodiments of the present application.

[0068] Figure 2 It is a flow schematic diagram of the cyclic redundancy check method provided by the present application Figure 1 , such as Figure 2 shown, the method includes:

[0069] S201. Determine the target pre-computation result according to the target parameter.

[0070] Specifically, the target parameter is related to the verification requirement of the system to be verified, and the target parameter includes the target generation polynomial and the target data bit width; the target pre-computation result includes the cyclic redundancy check (CRC) input coefficient matrix and the input data coefficient matrix.

[0071] It can be understood that different verification requirements of the system to be verified result in different corresponding target generation polynomials. Further, the corresponding target data bit width is determined in combination with the system to be verified. Exemplarily, in a network communication scenario, the corresponding verification requirement indicates using a 32-bit generation polynomial for calculation. At this time, if the network communication system implements the CRC32 algorithm through an 8-bit microcontroller, the data bit width can be 8 bits.

[0072] It can be understood that the system to be verified is any system that needs to perform CRC verification, which can be a network communication system, a storage device, a file transfer system, an embedded system, etc. This is not limited in this embodiment.

[0073] In this embodiment, a preset hardware lookup table (Lookup Table, LUT) is maintained in the electronic device, and the pre-computation results under different parameters are stored in the preset hardware lookup table. Specifically, in this embodiment, for any parameter, the preset software tool is controlled to generate the corresponding pre-computation result based on the generation polynomial and data bit width included in the parameter; further, the parameter and the corresponding pre-computation result are stored in the preset hardware lookup table. On this basis, the electronic device obtains the corresponding target pre-computation result by looking up the target parameter in the preset hardware lookup table.

[0074] Specifically, the preset software tool can be Python code, which can output the corresponding pre-computed result when the input generating polynomial and data bit width are provided. It can be understood that the preset software tool can also be code in other high-level languages, which is not limited in this embodiment.

[0075] Further, the electronic device stores the pre-computed result corresponding to the current parameter into a preset hardware lookup table. Specifically, the electronic device stores the pre-computed result as a configuration file or directly generates the parameters required in the hardware description language code. Specifically, the file or parameter can be in formats such as simple text files, JSON, XML, etc., or a direct numerical list.

[0076] In this embodiment, by using the preset software tool to determine the pre-computed result, the automatic generation of the pre-computed result is achieved. It can separate complex data calculations and logical derivations from the hardware design, simplify the configuration of different generating polynomials and data bit widths, reduce the complexity of manual design and debugging, significantly shorten the development cycle, and facilitate easier adjustment and verification. In addition, by maintaining the preset hardware lookup table, it can quickly adapt to different parameters, thus avoiding frequent logical modifications and verifications in the design and greatly reducing the verification complexity.

[0077] S202. Determine the parallel CRC calculation logic according to the target pre-computed result.

[0078] Among them, the parallel CRC calculation logic is used to calculate the CRC check result of each check cycle according to the intermediate CRC check result of the system to be checked, the CRC input coefficient matrix, the input data coefficient matrix, and the input data of the system to be checked.

[0079] In this embodiment, the specific manifestation form of the parallel CRC calculation logic is hardware description language, such as Verilog code. After the electronic device determines the target pre-computed result of the target parameter, it uses the target pre-computed result as the input of the Verilog code to obtain the parallel CRC calculation logic in the corresponding hardware description language.

[0080] It can be understood that the number of check cycles is specifically related to the length of the data to be checked and the target data bit width. The target data bit width specifically indicates the number of bits of the input data in each check cycle. The parallel CRC calculation logic processes the input data with the number of bits corresponding to the data bit width in parallel in each check cycle.

[0081] Specifically, the parallel CRC calculation logic is described as follows: within each verification period, the CRC verification result of the current verification period is the result of exclusive-OR operation between the product of the CRC input coefficient matrix and the intermediate CRC verification result and the product of the input data coefficient matrix and the input data of the current verification period. It should be understood that the intermediate CRC verification result is specifically the CRC verification result of the previous verification period of the current verification period. If the current verification period is the first verification period, the intermediate CRC verification result is the initial default value.

[0082] More specifically, the parallel CRC calculation logic can be expressed by the following formula: CRCout = C ⋅ CRCin ⊕ D ⋅ Data, where CRCout is used to represent the CRC verification result of the current verification period, C is used to represent the CRC input coefficient matrix, CRCin is used to represent the intermediate CRC verification result, D is used to represent the input data coefficient matrix, and Data is used to represent the input data of the current verification period.

[0083] From the above content, it can be seen that the intermediate CRC verification result of the previous verification period and the input data of the current verification period are independent variables, and the CRC verification result of the current verification period is the dependent variable. Therefore, after determining the CRC input coefficient matrix and the input data coefficient matrix, that is, the target pre-calculation result corresponding to the target parameter, the unique parallel CRC calculation logic can be determined.

[0084] S203. Update the system to be verified according to the parallel CRC calculation logic, and when the system to be verified receives the data to be verified, control the system to be verified to execute the parallel CRC calculation logic to verify the data to be verified and obtain the verification result.

[0085] In this embodiment, after the electronic device obtains the parallel CRC calculation logic, it updates the system to be verified according to the corresponding hardware description language, so that when the system to be verified receives the data to be verified, it can control the system to be verified to execute the parallel CRC calculation logic to verify the data to be verified, thereby obtaining the verification result.

[0086] Specifically, when there is no CRC calculation module in the system to be verified, the electronic device adds the hardware description language of the parallel CRC calculation logic as a new module to the system design, and updates the connection status of the input and output interfaces between other parts of the system to be verified and this module to ensure that this module can receive correct data, control signals and output correct signals, etc.

[0087] When the electronic device has a CRC calculation module in the system to be verified, replace the logic of the existing CRC calculation module according to the hardware description language of the parallel CRC calculation logic, and maintain the interface consistency to ensure that the interface of the current CRC calculation module is the same as that of the original CRC calculation module. Alternatively, make corresponding adjustments in the system to be verified to adapt to the interface of the current CRC calculation module.

[0088] Based on the above process, when the electronic device receives the data to be verified in the system to be verified, input the data to be verified into the CRC calculation module through the corresponding interface, and at the same time send a control signal to the CRC calculation module, so that the CRC calculation module verifies the data to be verified according to the parallel CRC calculation logic to obtain the verification result.

[0089] It can be understood that the manifestation form of the parallel CRC calculation logic in S202 can also be a high-level language. Further, before updating the system to be verified according to the parallel CRC logic calculation logic in S203, first generate the parallel CRC calculation logic in the form of hardware description language according to the parallel CRC calculation logic in the form of high-level language, and then update the system to be verified according to the parallel CRC calculation logic in the form of hardware description language.

[0090] The cyclic redundancy check method provided by the embodiments of this application determines the corresponding target pre-calculation result according to the target parameters determined by the verification requirements of the system to be verified, and determines the parallel CRC calculation logic according to the target budget result. Finally, update the system to be verified according to the parallel CRC calculation logic, and when the system to be verified receives the data to be verified, control the system to be verified to execute the parallel CRC calculation logic to implement the verification of the data to be verified and obtain the verification result.

[0091] Through the method of this embodiment, when the electronic device determines the parallel CRC calculation logic for the system to be verified, there is no need to perform complex logical operations according to the target parameters, but only simple memory access is involved, so that the parallel CRC calculation logic can be determined efficiently, and then can be applied to the verification scenario of the system to be verified in time.

[0092] In addition, it can be understood that the hardware configuration information of the system to be verified will affect the implementation method of the parallel CRC calculation logic, that is, the hardware configuration information of different systems to be verified can support different parallel CRC calculation logics, and the hardware configuration information of the system to be verified may have the ability to implement multiple parallel CRC calculation logics.

[0093] Therefore, as a preferred embodiment, for any system to be verified, the electronic device determines the target parameters in the following manner: obtaining the hardware configuration information of the system to be verified, determining the optional parameters according to the hardware configuration information; and determining the target generation polynomial and the target data bit width from the optional parameters according to the verification requirements. Among them, the optional parameters include the optional generation polynomial and the optional data bit width.

[0094] Specifically, the hardware configuration information may include the processor type, available storage resources, data bus width, clock frequency, and other relevant hardware characteristics. The electronic device determines the optional generation polynomial and the optional data bit width according to the hardware configuration information. Exemplarily, if the bus width of the system to be verified is 8 bits, the optional data bit width is limited to 8 bits or a multiple thereof. If the processor performance is higher and the clock frequency is higher, the optional generation polynomial can be more complex.

[0095] Furthermore, the electronic device determines the target generation polynomial and the target data bit width from the optional parameters according to the verification requirements of the system to be verified. It can be understood that in this embodiment, the specific process of determining the target parameters according to the hardware configuration information and the verification requirements is not limited, as long as it can ultimately ensure that the target data bit width is compatible with other parts of the system to be verified (such as the data bus), and the target generation polynomial meets the verification requirements.

[0096] It can be understood that in practical applications, the target parameters can also be directly input by the user to the electronic device, and this embodiment does not limit this.

[0097] Based on the foregoing embodiments, the present application also provides a method embodiment for further elaborating on the cyclic redundancy check method of the present application. Specifically, this embodiment specifically elaborates on the process of controlling the system to be verified to obtain the verification result.

[0098] It is worth noting that in this embodiment, there is no existing CRC calculation module in the system to be verified. After the electronic device determines the parallel CRC calculation logic for the system to be verified, it defines a CRC calculation module. The interface of this CRC calculation module includes an interface for receiving input data, an interface for receiving control signals, and an interface for outputting the CRC verification result, and updates the connection relationship between other relevant parts of the system to be verified and these interfaces.

[0099] Specifically, the electronic device declares a register in the system to be verified for storing the CRC verification result and initializes the initial CRC verification result to zero or other default values. It can be understood that this register is connected to the interface of the CRC calculation module for outputting the CRC verification result.

[0100] On this basis, Figure 3 is the flowchart of the cyclic redundancy check method provided by the present applicationFigure 2 , as Figure 3 shown, the method of this embodiment includes:

[0101] S301. When the system to be verified receives the data to be verified, according to the target data width, the data to be verified is divided into at least one input data.

[0102] Specifically, in this embodiment, the system to be verified includes a status register, which is used to indicate the data reception status. The electronic device determines whether the system to be verified has received the data to be verified by checking the status of this status register.

[0103] Furthermore, when the system to be verified receives the data to be verified, the electronic device divides the data to be verified into at least one input data according to the target data width. Specifically, if the target data width is 8 bits and the data to be verified is 32 bits, the data to be verified will be divided into four input data.

[0104] It can be understood that each input data corresponds to a verification cycle, that is, within each verification cycle, the CRC calculation module outputs a CRC verification result according to the input data of the current verification cycle.

[0105] In this embodiment, when the electronic device obtains at least one input data, it controls the system to be verified to sequentially calculate the CRC verification results corresponding to the at least one input data according to the CRC calculation logic, and determines the verification result according to the CRC verification results.

[0106] Specifically, within each verification cycle, the electronic device inputs the corresponding input data into the CRC calculation module through the interface of the CRC calculation module for receiving the input data, so that the CRC calculation module performs parallel processing on the received input data according to the corresponding parallel CRC calculation logic to finally obtain the verification result. More specifically, the process of the electronic device determining the verification result can be seen in the content of S302 and S303.

[0107] S302. Control the system to be verified to use the CRC verification result of the previous verification cycle as the intermediate CRC verification result within each verification cycle, and input the input data of the verification cycle and the intermediate CRC verification result into the CRC calculation module for implementing the parallel CRC calculation logic to obtain the CRC verification value of the verification cycle.

[0108] S303. When the calculation of all input data is completed, use the CRC verification result of the current verification cycle as the verification result.

[0109] Specifically, in this embodiment, the CRC calculation module further includes an interface for receiving the intermediate CRC verification result, and this interface is connected to the register for storing the CRC verification result.

[0110] In each verification period, the electronic device controls the system to be verified to input the corresponding input data into the CRC calculation module through the interface of the CRC calculation module for receiving input data, and controls the system to be verified to input the latest CRC verification result stored in the register for storing the CRC verification result into the CRC calculation module. At the same time, a control signal is sent to the CRC calculation module through the interface of the CRC calculation module for receiving control signals, so that the CRC calculation module responds to the control signal and performs parallel processing on the currently input input data according to the parallel CRC calculation logic to obtain the CRC verification result of the current verification period.

[0111] It can be understood that when the CRC calculation module completes the calculation of all input data, the CRC verification result output in the corresponding verification period is the final verification result corresponding to the data to be verified. Therefore, when the CRC calculation module completes the calculation of all input data, the electronic device uses the CRC verification result of the current verification period as the verification result of the data to be verified.

[0112] It can be understood that during serial CRC calculation, each calculation is only based on one input data bit. In the method provided in the embodiments of the present application, for each input data containing the target data bit width, the electronic device can perform parallel calculation on multiple input data bits simultaneously through the CRC calculation module for implementing parallel CRC calculation logic, reducing the processing delay and greatly improving the calculation speed.

[0113] Through the method of this embodiment, the system to be verified can meet the requirements for high-speed data verification, that is, the method of this embodiment is applicable to scenarios such as real-time data stream processing and network communication.

[0114] The present application also provides a method embodiment for further elaborating on the system startup method of the present application. Specifically, this embodiment elaborates in detail on the process of determining the pre-calculation result.

[0115] It is worth noting that parallel CRC calculation realizes the function of processing multiple input data bits at one time through matrix operations on the input data and the intermediate CRC verification result. The key lies in constructing the matrix CRC input coefficient matrix C and the input data coefficient matrix D, and parallelizing the serial shift and feedback process through matrix operations.

[0116] In this embodiment, the preset software tool is specifically Python code, and parallel CRC calculation logic is generated through the Python code. Specifically, the electronic device inputs the generating polynomial and the data bit width into the Python code, and the Python code converts the polynomial into a binary format, and then generates a key matrix for parallel CRC calculation. Among them, the key matrix is the CRC input coefficient matrix C and the input data coefficient matrix D, which are used to generate the parallel CRC calculation logic.

[0117] It can be understood that the parallel CRC calculation logic at this time is in the form of a high-level language. The electronic device further generates the parallel CRC calculation logic in the form of a hardware description language based on this. Exemplarily, Verilog code is generated and the Verilog code is saved as a crc.v file. To ensure the correctness of the parallel CRC calculation logic and the accuracy of the hardware implementation, the electronic device can simulate the generated hardware logic through Verilator and view the simulation waveform using GTKWave to obtain the verification result.

[0118] More specifically, in this embodiment, taking the automotive electronic communication field as an example, the generating polynomial G(x) is set to x^8 + x^4 + x^3 + x^2 + 1, and the data bit width M is 8 (since automotive electronic communication usually transmits data in bytes, M being 8 is a commonly used data bit width in real-time data processing), and the process of determining the pre-computation result is described in detail. In this embodiment, the electronic device configures the preset software tool to: when the generating polynomial and the data bit width are input, output the corresponding pre-computation result. Figure 4 Flow schematic of the cyclic redundancy check method provided by this application Figure 3 , such as Figure 4 As shown, the process of the preset software tool in this embodiment determining the corresponding pre-computation result according to the generating polynomial and the data bit width includes:

[0119] S401. Generate a coefficient matrix according to the generating polynomial.

[0120] Among them, the coefficient matrix is an N×1 matrix, and N is related to the highest power of the generating polynomial.

[0121] It can be understood that the generating polynomial G(x) is represented in binary form as: 100011101. In this embodiment, N is specifically the position where the highest power of the generating polynomial is located, that is, the coefficient matrix is specifically a 9×1 matrix.

[0122] S402. Generate an identity matrix.

[0123] Specifically, the identity matrix is an (N-1)-order matrix with a size of (N−1)×(N−1), where the elements on the diagonal are 1, which is used to represent that in the no-feedback state, the value of each register bit is directly retained in the next clock cycle. The other elements are 0, which is used to represent no data transfer or influence, ensuring that the register state is not interfered by other bits. The identity matrix is used to represent the situation where the state of the shift register is not affected, and maintains the register state when constructing the matrix.

[0124] S403. Generate a feedback matrix according to the coefficient matrix, the identity matrix, and a preset generation rule.

[0125] Specifically, the preset generation rule is used to enable the feedback matrix to implement data feedback and update logic. In this embodiment, the feedback matrix F defines how the input data is fed back to the CRC register, so that the hardware can efficiently calculate the CRC check result. Specifically, in this implementation, the preset generation rule is expressed as follows:

[0126] .

[0127] Among them, F[i][j] is used to represent the element in the i-th row and the j-th column of the feedback matrix F. The specific description of this preset generation rule is: when i = j + 1, set F[i][j] = 1, which means that under the drive of the clock signal, the current bit of the CRC register will shift to the next position. This operation ensures that the register state can be updated in real time with the change of the input data, so as to achieve the effective propagation of CRC.

[0128] When i = 0, set F[0][j] = G[j], where G[j] is the j-th bit of the CRC polynomial. This setting ensures that the feedback term is correctly applied to the current state of the register according to the definition of the CRC polynomial, enhancing the error detection ability.

[0129] Under other conditions, set F[i][j] = 0 to indicate that this position is not involved in any data feedback or shift operation. This setting ensures the stability of the matrix structure without changing the register state.

[0130] On this basis, in this embodiment, the foregoing coefficient matrix is used as the first column of the feedback matrix, so that the first column of the feedback matrix directly reflects the feedback logic of the generating polynomial, and defines which bits will affect the generation of the CRC check result. The setting of this column ensures that when data is input, the feedback operation can be accurately applied to the current state of the CRC register according to the polynomial definition. The subsequent columns implement the state transfer of the register through the shift logic. The elements in each column are set to 1 to ensure that the input data can be effectively propagated in each clock cycle. This design enables the CRC register to respond quickly and update its state every time new data is input.

[0131] S404. Calculate the L-th power of the feedback matrix and take the modulus 2 to obtain the CRC input coefficient matrix.

[0132] Specifically, in this embodiment, the M-th power of the feedback matrix F is calculated and the modulus 2 is taken to obtain the CRC input coefficient matrix. This process is represented by the formula: C = F^M mod 2.

[0133] Among them, each column and row of the feedback matrix F reflects how data affects the propagation state of the CRC check result under a specific input data bit width M. By calculating F^M, it is possible to simulate how the feedback logic leads to the generation of different states when M input data bits are input. The modulo 2 operation ensures that all elements in the matrix are binary values (0 or 1). The CRC input coefficient matrix C provides all possible initial states, provides a basis for subsequent CRC check calculations, ensures the accurate propagation of states during data processing, and thus improves the efficiency and reliability of the CRC algorithm.

[0134] S405. Determine the zero matrix according to the feedback matrix, and determine the input data coefficient matrix according to the feedback matrix and the zero matrix.

[0135] It can be understood that the input data coefficient matrix is used to generate corresponding CRC check bits for the input data bit width M. In this embodiment, a zero matrix d with dimensions X×Y is first initialized, where X is the number of rows of the feedback matrix F, and then each column of the input data coefficient matrix D is calculated through the following formula: D[:, M - i] = F^i mod 2.

[0136] For the calculation process from i = 1 to M, each power operation of the feedback matrix F uses the modulo 2 operation to ensure that all matrix elements remain within the binary range (0 or 1). This operation enables each element to effectively reflect the generation logic of the CRC check bits when processing data bits.

[0137] Specifically, the (M - i)-th column of the input data coefficient matrix D stores the CRC check bits when the input data length is i. That is, if the input data length is 4, then the first column D[:, 3] represents the CRC check value at this length; if the input data length is 3, then the second column D[:, 2] represents the CRC check value at this length, and so on. Through this structured design, the input data coefficient matrix D provides an effective way to obtain CRC check information related to the input data length, ensuring that these check bits can be directly used for CRC calculations in subsequent steps.

[0138] It can be understood that in the above process, the electronic device configures a preset software tool to be able to determine a corresponding precomputation result based on the input generation polynomial and data bit width. In practical applications, the preset software tool can also be configured to directly generate CRC parallel computing logic in the form of a high-level language according to the input generation polynomial and data bit width. Further, the electronic device can obtain the CRC parallel computing logic in the form of a hardware description language based on this form of CRC parallel computing logic, and update the CRC computing module of the system to be verified based on this form of CRC parallel computing logic. This is not limited in this embodiment.

[0139] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0140] It should be further noted that although the steps in the flowchart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0141] This application also provides an embodiment of a cyclic redundancy check device. Figure 5 The structural schematic diagram of the cyclic redundancy check device provided by this application is as Figure 5 shown. The cyclic redundancy check device provided in this embodiment includes:

[0142] A first determination module 51, configured to determine a target precomputation result according to target parameters; the target parameters are related to the verification requirements of the system to be verified, and the target parameters include a target generation polynomial and a target data bit width; the target precomputation result includes a cyclic redundancy check (CRC) input coefficient matrix and an input data coefficient matrix;

[0143] A second determination module 52, configured to determine a parallel CRC calculation logic according to a target pre-calculation result; the parallel CRC calculation logic is used to calculate a CRC check result of a check period according to an intermediate CRC check result of a system to be checked, a CRC input coefficient matrix, an input data coefficient matrix, and input data of the system to be checked in each check period;

[0144] A check module 53, configured to update the system to be checked according to the parallel CRC calculation logic, and when the system to be checked receives data to be checked, control the system to be checked to execute the parallel CRC calculation logic to check the data to be checked, so as to obtain a check result.

[0145] In a possible implementation manner, the first determination module 51 is further configured to:

[0146] Obtain hardware configuration information of the system to be checked, and determine optional parameters according to the hardware configuration information; the optional parameters include an optional generating polynomial and an optional data bit width;

[0147] Determine a target generating polynomial and a target data bit width from the optional parameters according to the check requirements.

[0148] In a possible implementation manner, the check module 53 is specifically configured to:

[0149] When the system to be checked receives data to be checked, divide the data to be checked into at least one input data according to the target data bit width;

[0150] Control the system to be checked to sequentially calculate CRC check results corresponding to each input data according to the CRC calculation logic, and determine a check result according to the CRC check results.

[0151] In a possible implementation manner, each input data corresponds to a check period; the check module 53 is specifically configured to:

[0152] Control the system to be checked to use the CRC check result of the previous check period as an intermediate CRC check result in each check period, and input the input data and the intermediate CRC check result of the check period into a CRC calculation module for implementing the parallel CRC calculation logic, so as to obtain a CRC check result of the check period;

[0153] When the calculation of all input data is completed, use the CRC check result of the current check period as the check result.

[0154] In a possible implementation manner, the first determination module 51 is further configured to:

[0155] For any parameter, control a preset software tool to generate a corresponding pre-calculation result based on the generating polynomial and data bit width included in the parameter;

[0156] Store the parameter and the corresponding pre-computed result in a preset hardware lookup table;

[0157] The first determination module 51 is specifically configured to:

[0158] Search for the target parameter in the preset hardware lookup table to obtain the target pre-computed result.

[0159] In a possible implementation, the first determination module 51 is specifically configured to:

[0160] Input the generating polynomial and the data bit width into a preset software tool to obtain the pre-computed result; when receiving the generating polynomial and the data bit width, the preset software tool generates a coefficient matrix and an identity matrix according to the generating polynomial and the data bit width, generates a feedback matrix according to the coefficient matrix, the identity matrix and a preset generation rule, and obtains the pre-computed result according to the feedback matrix; wherein, the coefficient matrix is a matrix of N×1, and N is related to the highest power of the generating polynomial; the identity matrix is an (N - 1)-order matrix.

[0161] In a possible implementation, when generating the feedback matrix, the preset software tool determines the input data coefficient matrix according to the feedback matrix and determines the input data coefficient matrix according to the feedback matrix and a zero matrix.

[0162] The cyclic redundancy check device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here in this embodiment.

[0163] This application also provides an electronic device, Figure 6 which is a schematic structural diagram of the electronic device provided in this application. As Figure 6 shown, the electronic device provided in this embodiment includes: a processor 61 and a memory 62. Among them, the processor 61 and the memory 62 are connected, such as connected through a bus 63. Optionally, the electronic device may further include a transceiver 64. It should be noted that in practical applications, the transceiver 64 is not limited to one, and the structure of this electronic device does not constitute a limitation to the embodiments of this application.

[0164] The processor 61 may be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in connection with the disclosure of this application. The processor 61 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0165] The bus 63 may include a path for transmitting information between the above components. The bus 63 may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus 63 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 only a thick line is shown in the figure, but it does not mean that there is only one bus 63 or one type of bus 63.

[0166] The memory 62 may be a read only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), or other type of dynamic storage device that can store information and instructions. It may also be an electrically erasable programmable read only memory (EEPROM), a compact disc read only memory (CD-ROM), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic storage media, or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0167] The memory 62 is used to store the application program code for implementing the solution of this application, and is controlled by the processor 61 for execution. The processor 61 is used to execute the application program code stored in the memory 62 to implement the content shown in the foregoing method embodiments.

[0168] This application also provides a computer-readable storage medium, which may include: various media that can store program code, such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs. Specifically, the computer-readable storage medium stores program instructions for implementing the methods in the above embodiments.

[0169] This application embodiment also provides a computer program product, including a computer program that implements the technical solutions of the above method embodiments when executed by a processor. The implementation principle and technical effects are similar and will not be elaborated here.

[0170] Those skilled in the art will readily conceive of other implementations of this application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include known common knowledge or conventional technical means in the technical field not disclosed in this application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of this application are pointed out by the claims.

[0171] It should be understood that this application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is only limited by the appended claims.

Claims

1. A cyclic redundancy check method, characterized in that: The method comprises: Determine a target pre-calculation result according to a target parameter; the target parameter is related to the verification requirement of the system to be verified, and the target parameter includes a target generating polynomial and a target data bit width; the target pre-calculation result includes a cyclic redundancy check CRC input coefficient matrix and an input data coefficient matrix; Determine a parallel CRC calculation logic according to the target pre-calculation result; the parallel CRC calculation logic is used to calculate the CRC check result of the check period according to the intermediate CRC check result of the system to be checked, the CRC input coefficient matrix, the input data coefficient matrix, and the input data of the system to be checked in each check period; The system to be checked is updated according to the parallel CRC calculation logic, and when the system to be checked receives the data to be checked, the system to be checked is controlled to execute the parallel CRC calculation logic to check the data to be checked to obtain a check result.

2. The method according to claim 1, characterized in that The method further comprises: Acquire hardware configuration information of the system to be verified, and determine optional parameters according to the hardware configuration information; the optional parameters include an optional generating polynomial and an optional data bit width; The target generator polynomial and the target data bit width are determined from the optional parameters according to verification requirements.

3. The method according to claim 1 or 2, characterized in that: When the system to be checked receives the data to be checked, controlling the system to be checked to execute the parallel CRC calculation logic to check the data to be checked and obtain a check result, including: When the system to be verified receives the data to be verified, the system to be verified divides the data to be verified into at least one input data according to the target data bit width; The system to be checked is controlled to calculate the CRC check result corresponding to each input data in sequence according to the CRC calculation logic, and the check result is determined according to the CRC check result.

4. The method according to claim 3, characterized in that Each input data corresponds to a verification cycle; the controlling the system to be verified sequentially calculates the CRC verification result corresponding to each input data according to the CRC calculation logic, and determines the verification result according to the CRC verification result, including: Control the system to be checked to use the CRC check result of the previous check cycle as the intermediate CRC check result in each check cycle, and input the input data of the check cycle and the intermediate CRC check result into a CRC calculation module for implementing the parallel CRC calculation logic to obtain the CRC check result of the check cycle; When the calculation of all input data is completed, the CRC check result of the current check cycle is used as the check result.

5. The method according to claim 1 or 2, characterized in that: The method further comprises: For any parameter, controlling the preset software tool to generate a corresponding pre-calculation result based on the generator polynomial and data bit width included in the parameter; Storing the parameters and corresponding pre-calculated results in a preset hardware lookup table; Determining the target pre-calculation result according to the target parameter includes: The target parameter is searched in the preset hardware lookup table to obtain the target pre-calculation result.

6. The method according to claim 5, characterized in that The control preset software tool generates corresponding pre-calculation results based on the generator polynomial and data bit width included in the parameters, including: The generating polynomial and the data bit width are input into the preset software tool to obtain the pre-calculation result; when receiving the generating polynomial and the data bit width, the preset software tool generates a coefficient matrix and a unit matrix according to the generating polynomial and the data bit width, generates a feedback matrix according to the coefficient matrix, the unit matrix and preset generation rules, and obtains the pre-calculation result according to the feedback matrix; wherein the coefficient matrix is ​​an N×1 matrix, N is related to the highest power of the generating polynomial; and the unit matrix is ​​an N-1 order matrix.

7. The method according to claim 6, characterized in that When generating the feedback matrix, the preset software tool determines the input data coefficient matrix according to the feedback matrix, and determines the input data coefficient matrix according to the feedback matrix and a zero matrix.

8. A cyclic redundancy check device, characterized in that: include: A first determination module, used to determine a target pre-calculation result according to a target parameter; The target parameters are related to the verification requirements of the system to be verified, and the target parameters include a target generating polynomial and a target data bit width; The target pre-calculation result includes a cyclic redundancy check CRC input coefficient matrix and an input data coefficient matrix; A second determination module, used to determine the parallel CRC calculation logic according to the target pre-calculation result; The parallel CRC calculation logic is used to calculate the CRC check result of the check period in each check period according to the intermediate CRC check result of the system to be checked, the CRC input coefficient matrix, the input data coefficient matrix, and the input data of the system to be checked; The verification module is used to update the system to be verified according to the parallel CRC calculation logic, and when the system to be verified receives the data to be verified, control the system to be verified to execute the parallel CRC calculation logic to verify the data to be verified and obtain a verification result.

9. An electronic device, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

11. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 7 when being executed by a processor.

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