Processor-oriented data preprocessing, data transmission and memory access system and method

Abstract

The invention discloses a processor-oriented data preprocessing, data transmission and memory access system and method, and the system comprises an off-chip storage and access unit, a data transmission and preprocessing control unit, an on-chip data preprocessing and storage unit, an on-chip memory access execution unit and a calculation unit. By designing a flexible and efficient data preprocessing function in a transmission structure, an original data format of an application is efficiently converted into a data format friendly to a processor and is stored in an on-chip cache, and meanwhile, an efficient memory access structure fully simplifies a memory access process, so that data can be quickly read from the on-chip cache, and the memory access efficiency is improved. And then, the calculation component can efficiently process the data, so that the calculation power of the high-density calculation component is effectively exerted.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular, to a system and method for data preprocessing, data transmission, and memory access for a processor. Background Art

[0002] With the popularization of technologies such as artificial intelligence and big data, more and more application scenarios use these as underlying algorithm technologies and build solutions that meet different requirements on top of them. The development of these underlying algorithm technologies requires the processor to provide rich and efficient computing power. In order to improve the computing power, mainstream processors often adopt vector computing components or even tensor computing components to provide high-density computing for various application processes. From the development of the processor architecture, the growth rate of the computing power of the processor is faster than the growth rate of memory access, making it increasingly difficult for the memory access bandwidth to match the computing power of the processor. Therefore, many research works on the processor architecture are focused on how to solve this problem. So far, the gap between the memory access bandwidth and the processor computing power has been improved to a certain extent, but the memory access bandwidth and memory access efficiency have always been the key objects of concern for the overall performance of the processor.

[0003] After analysis, it is found that for most applications, the data to be processed is continuously stored according to conventional dimensions, and the data format basically follows the most intuitive rules for transmission and storage. In the vector calculation in the processor, each basic calculation unit executes the same calculation in parallel. Therefore, it is required that the data to be processed be arranged and stored in a certain format when input into the calculation component. The tensor calculation component generally processes a two-dimensional or multi-dimensional matrix and performs certain regular operations on the matrix, requiring the data to be processed to conform to the storage format of the target matrix. For various applications, the original data format often has difficulty in efficiently exerting the efficiency of the high-density calculation component when passing through the calculation component in the processor, and needs to be preprocessed according to certain rules and then sent to the calculation component to better exert the efficiency of the calculation component.

[0004] Figure 1 Schematic diagram of the existing data and instruction storage and transmission structure, such as Figure 1As shown, in the existing technical solutions, the data transmission system mainly realizes the ordinary data handling function, and efficiently moves data from the source address to the destination address according to the configuration information, but cannot synchronously implement the flexible and configurable data preprocessing function during this process. Since the processor cannot implement the data preprocessing function during the memory access stage, when executing algorithm applications, the data preprocessing cannot be efficiently implemented, thus affecting the overall execution efficiency of the processor. The memory access path obtains data from the specified address according to the instruction information or configuration information and sends it to the computing unit, and does not change the data format during this process. Therefore, in the processor, the data organization format and the relative position relationship are not changed, and the diverse requirements of the computing unit for the data format in different application scenarios cannot be met, and the utilization rate of the computing unit is thus affected. In addition, in the existing technical solutions, the processor cannot jointly implement the flexible and configurable data preprocessing function in the data transmission and memory access stages, resulting in the underutilization of the processing unit and affecting the overall execution performance and efficiency of the processor. Summary of the Invention

[0005] To solve the problem of low memory access efficiency caused by the special requirements of data formats when a processor including a vector component or a tensor component executes various application algorithms, the present invention provides a system and method for data preprocessing, data transmission, and memory access for a processor. First, a data transmission structure is proposed, and a flexible and efficient data preprocessing function is designed in this transmission structure to efficiently convert the original data format of the application into a processor-friendly data format and store it in the on-chip cache. At the same time, an efficient memory access structure is designed to fully simplify the memory access process, so that data can be quickly read out from the on-chip cache and written into the register of the computing component, and then the computing component can efficiently process the data, thereby effectively exerting the computing power of the high-density computing component. The present invention designs a data transmission system and a data memory access system with a preprocessing function for improving the execution performance and efficiency of the processor. A flexible and configurable data preprocessing mechanism is designed in the data transmission stage to synchronously implement the data preprocessing function during the data transmission process, and the original data is processed into the expected format according to the configuration requirements to prepare for the next data memory access; then in the data memory access stage, the corresponding preprocessing function logic is designed and implemented based on the configuration information to organize the data in a computing component-friendly manner and send it to the computing unit for processing, greatly improving the utilization rate of the computing unit, and thus realizing the improvement of the overall performance and efficiency of the processor when executing various algorithm applications.

[0006] To achieve the above object, the present invention provides a system for data preprocessing, data transmission, and memory access for a processor, which includes an off-chip storage and access unit, a data transmission and preprocessing control unit, an on-chip data preprocessing and storage unit, an on-chip memory access execution unit, and a computing unit, wherein:

[0007] The off-chip storage and access unit is preset with: a first data storage module, data read / write logic, and bus interface logic. Among them, the bus interface logic is used for data transmission with the data transmission and preprocessing control unit;

[0008] The data transmission and preprocessing control unit is preset with: transmission control logic, configuration information receiving and storing logic, read data address generation logic, off-chip storage data reading logic, data reading bus protocol conversion logic, on-chip storage data sending logic, preprocessing control information parsing module, on-chip storage data reading logic, write data address generation logic, off-chip storage data sending logic, and data sending bus protocol conversion logic; among them, the configuration information receiving and storing logic is used for receiving the configuration information sent from the outside;

[0009] The on-chip data preprocessing and storage unit is preset with: data preprocessing control logic, data splitting and distribution logic, a second data storage module, data read / write interface logic, and data reading and integration logic. Among them, the data read / write interface logic is used for data transmission with the on-chip memory access execution unit, and the data preprocessing control logic is used for parsing the received preprocessing control information and performing data preprocessing operations;

[0010] The on-chip memory access execution unit is preset with: an instruction fetch module, an instruction storage module, an instruction execution module, memory access control logic, data loading address calculation logic, data loading mode parsing logic, data loading logic, data return address calculation logic, data return mode parsing logic, and data return logic; and

[0011] The computing unit includes a vector computing component and a tensor computing component.

[0012] The present invention also provides a method for data preprocessing, data transmission, and memory access for a processor, which is implemented through the above system, and includes:

[0013] Step S1: Place the original data to be processed into the first data storage module in the off-chip storage and access unit;

[0014] Step S2: The data transmission and preprocessing control unit receives the configuration information sent from the outside through the configuration information receiving and storing logic;

[0015] Step S3: After the transmission control logic of the data transmission and preprocessing control unit parses the received configuration information, it obtains data from the off-chip storage unit according to the configuration information and generates a control signal;

[0016] Step S4: The transmission control logic of the data transmission and preprocessing control unit sends the control signal to the read data address generation logic. The read data address generation logic generates consecutive addresses according to the configuration information, and then the transmission control logic sends the consecutive addresses and the control signal to the off-chip storage data reading logic;

[0017] Step S5: The off-chip storage data reading logic performs a data reading operation, generates an off-chip data reading signal according to consecutive addresses, and sends it to the data reading bus protocol conversion logic;

[0018] Step S6: The data reading bus protocol conversion logic receives the control signal from the transmission control logic and the off-chip data reading signal, and converts them into a data read operation signal that meets the bus interface protocol and sends it to the off-chip storage and access unit;

[0019] Step S7: The off-chip storage and access unit receives the data read operation signal through the bus interface logic and parses it, generates a read operation signal for internal data and sends it to the data reading and writing logic. The data reading and writing logic initiates a data reading operation, obtains the original data from the corresponding address in the data storage module, and sends it to the data transmission and preprocessing control unit through the bus interface logic;

[0020] Step S8: The data transmission and preprocessing control unit forwards the configuration information to the preprocessing control information parsing module for parsing to obtain the preprocessing control information. At the same time, the transmission control logic sends the control signal to the on-chip storage data sending logic, and the on-chip storage data sending logic sends the obtained original data and preprocessing control information to the on-chip data preprocessing and storage unit;

[0021] Step S9: After receiving the preprocessing control information, the data preprocessing control logic of the on-chip data preprocessing and storage unit performs a data preprocessing operation, and sends the original data and configuration information to the data splitting and distribution logic. The data splitting and distribution logic preprocesses the original data and stores the preprocessed data in the second data storage module;

[0022] Step S11: The memory access control logic of the on-chip memory access execution unit initiates an instruction fetching operation through the instruction fetching module, obtains the instruction information from the instruction storage module, and then the instruction execution module parses the instruction information and generates control information and feeds it back to the memory access control logic;

[0023] Step S12: The memory access control logic generates a control signal to start the data loading address calculation logic and the data loading mode parsing logic. The data loading logic performs a data loading operation according to the received instruction information and reads data from the on-chip data preprocessing and storage unit under the control of the memory access control logic;

[0024] Step S13: The on-chip memory access execution unit sends the read data to the calculation unit for processing, and sends the processed data back to the off-chip storage unit for storage.

[0025] In an embodiment of the present invention, the configuration information in step S2 includes: the starting address of the source data in the off-chip storage and access unit, the starting address of the data stored in the on-chip data preprocessing and storage unit, the data transfer direction, the data size of the transferred configuration information, the data transfer mode of the configuration information, the control information related to data transfer, and the control information related to data preprocessing.

[0026] In an embodiment of the present invention, the configuration information forwarded to the preprocessing control information parsing module for parsing in step S8 is the control information related to data preprocessing. After parsing, the starting address stored in the on-chip data preprocessing and storage unit, the functional mode of preprocessing, the size of the data block, and the data masking information are obtained.

[0027] In an embodiment of the present invention, after step S9, there is also step S10: Repeat steps S1 - S9 until all the data to be processed is completely transferred from the off-chip storage and access unit to the on-chip data preprocessing and storage unit.

[0028] In an embodiment of the present invention, the instruction information field in step S11 includes: operation type, memory access address, memory access mode, and instruction control information.

[0029] In an embodiment of the present invention, step S12 specifically includes:

[0030] Step S1201: When the instruction control information is a read on-chip storage instruction, the memory access control logic starts the data loading address calculation logic and sends the instruction information to the data loading mode parsing logic for parsing. After parsing the mode information, it is fed back to the data loading logic;

[0031] Step S1202: The data loading logic integrates the memory access address and memory access mode of data loading and generates a data loading signal, which is sent to the on-chip data preprocessing and storage unit;

[0032] Step S1203: The on-chip data preprocessing and storage unit reads data from the second data storage module through the data read / write interface logic and sends it to the on-chip memory access execution unit.

[0033] In an embodiment of the present invention, before step S13 performs the feedback, it is also necessary to determine whether the instruction is a feedback operation instruction, specifically:

[0034] Step S1301: The value fetching module obtains the instruction information from the instruction storage module, and then the instruction execution module parses the instruction information;

[0035] Step S1302: When it is determined that the parsed instruction is a data transmission operation instruction, the memory access control logic activates the data transmission address calculation logic, and sends the instruction information to the data transmission mode parsing logic for parsing. After parsing out the mode information, it is fed back to the data transmission logic;

[0036] Step S1303: The data transmission logic integrates the memory access address for data loading, the data transmission information, and the control information, and initiates a write operation to the on-chip data preprocessing and storage unit;

[0037] Step S1304: The on-chip data preprocessing and storage unit converts the signal of the write operation into an operation of writing to the second data storage module through the data read / write interface logic, so as to complete the transmission of data to the second data storage module.

[0038] In an embodiment of the present invention, after step S1304, it further includes a process of transmitting the data transmitted and stored in the second data storage module to the off-chip storage unit, specifically including:

[0039] Step S1305: The configuration information receiving and storing logic of the data transmission and preprocessing control unit receives and stores the configuration information from the outside, and the transmission control logic parses the configuration information and generates a control signal;

[0040] Step S1306: The transmission control logic sends the generated control signal to the on-chip storage data reading logic, and at the same time, the preprocessing control information parsing module sends the extracted preprocessing information to the on-chip data preprocessing and storage unit;

[0041] Step S1307: The data preprocessing control logic of the on-chip data preprocessing and storage unit parses the preprocessing information, and activates the data reading and integration logic to read and integrate the data transmitted in the second data storage module;

[0042] Step S1308: The transmitted data is preprocessed and then returned to the data transmission and preprocessing control unit. The transmission control logic sends a control signal to activate the write data address generation logic to generate a write address. At the same time, the transmission control logic sends a control signal to activate the off-chip storage data sending logic, and the generated write address and the transmitted data are sorted out to form a data sending logic;

[0043] Step S1309: Under the action of the control signal of the transmission control logic, the data sending bus protocol conversion logic converts the sending request of the data sending logic into a bus interface protocol request and sends it to the off-chip storage and access unit;

[0044] Step S1310: After the off-chip storage and access unit receives a bus interface protocol request through the bus interface logic, it sends the data to be returned, the write address, and the control signal to the data read / write logic, and the data read / write logic writes the received data to the corresponding address in the data storage module;

[0045] Step S1311: Repeat steps S1305 - S1310 until all the data sizes specified in the configuration information are completely returned.

[0046] The system and method for data preprocessing, data transmission, and memory access for a processor provided by the present invention, compared with the prior art, can realize a flexible and configurable data preprocessing function during the data transmission and memory access processes, making the time consumed in the data preprocessing process negligible. By jointly implementing the data preprocessing function in the data transmission stage and the memory access stage, the data processing process is more flexible, the data preprocessing function is richer, and the data preprocessing process is more efficient. Through the flexible and configurable and function-rich data preprocessing logic, when processing various types of algorithm applications, the computing unit in the processor can obtain the data in the desired format and perform efficient operations, greatly improving the utilization rate of the computing unit and enhancing the overall computing efficiency and performance of the processor. Description of the Drawings

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0048] Figure 1 It is a schematic diagram of the existing data and instruction storage and transmission structure;

[0049] Figure 2 It is a schematic diagram of the system architecture of the data transmission and preprocessing subsystem according to an embodiment of the present invention;

[0050] Figure 3 It is a schematic diagram of the system architecture of the data memory access subsystem according to an embodiment of the present invention;

[0051] Figure 4 It is a schematic diagram of the data preprocessing, data transmission, and memory access process according to an embodiment of the present invention. Detailed Embodiments

[0052] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] Figure 2 It is a schematic diagram of the system architecture of the data transmission and preprocessing subsystem according to an embodiment of the present invention. Figure 3 It is a schematic diagram of the system architecture of the data memory access subsystem according to an embodiment of the present invention. Figure 4 It is a schematic diagram of the data preprocessing, data transmission and memory access process according to an embodiment of the present invention. As Figures 2 to 4 shown, this embodiment provides a system for data preprocessing, data transmission and memory access for a processor, which includes an off-chip storage and access unit, a data transmission and preprocessing control unit, an on-chip data preprocessing and storage unit, an on-chip memory access execution unit and a computing unit. The off-chip storage and access unit, the data transmission and preprocessing control unit and the on-chip data preprocessing and storage unit constitute the data transmission and preprocessing subsystem, and the on-chip memory access execution unit and the computing unit constitute the data memory access subsystem, wherein:

[0054] The off-chip storage and access unit is preset with: a first data storage module, a data read / write logic and a bus interface logic. Among them, the bus interface logic is used for data transmission with the data transmission and preprocessing control unit.

[0055] The data transmission and preprocessing control unit is preset with: a transmission control logic, a configuration information receiving and storing logic, a read data address generation logic, an off-chip storage data reading logic, a data reading bus protocol conversion logic, an on-chip storage data sending logic, a preprocessing control information parsing module, an on-chip storage data reading logic, a write data address generation logic, an off-chip storage data sending logic and a data sending bus protocol conversion logic.

[0056] Among them, the configuration information receiving and storing logic is used for receiving the configuration information sent externally.

[0057] The on-chip data preprocessing and storage unit is preset with: a data preprocessing control logic, a data splitting and distributing logic, a second data storage module, a data read / write interface logic and a data reading and integrating logic. Among them, the data read / write interface logic is used for data transmission with the on-chip memory access execution unit.

[0058] Among them, the data read / write interface logic is used for data transmission with the on-chip memory access execution unit, and the data preprocessing control logic is used for parsing the received preprocessing control information and performing corresponding data preprocessing operations.

[0059] The on-chip memory execution unit is preset with: an instruction fetch module, an instruction storage module, an instruction execution module, a memory access control logic, a data load address calculation logic, a data load mode parsing logic, a data load logic, a data return address calculation logic, a data return mode parsing logic, and a data return logic; and

[0060] The computing unit includes a vector computing component and a tensor computing component.

[0061] The process of the original data being transmitted from off-chip storage, preprocessed, and then loaded by the memory access unit and sent to the computing component for processing is as Figure 4 shown. This embodiment provides a method for data preprocessing, data transmission, and memory access for a processor, which includes:

[0062] Step S1: Place the original data Src_Data to be processed in the first data storage module in the off-chip storage and access unit;

[0063] Step S2: The data transmission and preprocessing control unit receives the configuration information sent externally through the configuration information receiving storage logic;

[0064] In this embodiment, as Figure 4 shown, the configuration information includes: the starting address Src_Addr of the source data in the off-chip storage and access unit, the starting address Dst_Addr of the data stored in the on-chip data preprocessing and storage unit, the data transmission direction Data_Direc, the data size Data_Size of the transmitted configuration information, the data transmission mode Trans_Mode of the configuration information, the control information TransCtrl_info related to data transmission, and the control information Preprocess_info related to data preprocessing;

[0065] Step S3: After the transmission control logic of the data transmission and preprocessing control unit parses the received configuration information, it obtains data from the off-chip storage unit according to the configuration information and generates a control signal;

[0066] Step S4: The transmission control logic of the data transmission and preprocessing control unit sends the control signal to the read data address generation logic. The read data address generation logic generates consecutive addresses according to the configuration information, and the transmission control logic then sends the consecutive addresses and the control signal to the off-chip storage data reading logic;

[0067] Step S5: The off-chip storage data reading logic performs a data reading operation, generates an off-chip data reading signal according to the consecutive addresses and sends it to the data reading bus protocol conversion logic; In this embodiment, through the consecutive address data reading operation, the bandwidth efficiency of the off-chip storage unit can be fully utilized;

[0068] Step S6: The data read bus protocol conversion logic receives the control signal from the transmission control logic and the off-chip data read signal, and converts them into a data read operation signal that meets the bus interface protocol and sends it to the off-chip storage and access unit;

[0069] Among them, the process of converting the read operation signal in step S6 further includes: parsing the received signal to determine the read address, the size of the read data, and the read valid and ready handshake signals (signals of the two-way flow control mechanism); then converting the operation corresponding to the off-chip data read signal into a bus protocol signal, that is, converting the internal read operation signal protocol into a standard bus protocol signal. Among them, the starting address of the first operation is Src_Addr (the starting address of the source data in the off-chip storage and access unit), and the read operation is performed in the data transmission mode Trans_Mode of the configuration information. The overall size of the read operation can be the data size Data_Size of the configuration information.

[0070] Step S7: The off-chip storage and access unit receives and parses the data read operation signal through the bus interface logic, generates an internal data read operation signal and sends it to the data read / write logic. The data read / write logic initiates a data read operation, obtains the original data Src_Data from the corresponding address in the data storage module, and sends it to the data transmission and preprocessing control unit through the bus interface logic;

[0071] Step S8: The data transmission and preprocessing control unit forwards the configuration information to the preprocessing control information parsing module for parsing to obtain the preprocessing control information. At the same time, the transmission control logic sends the control signal to the on-chip stored data sending logic, and the on-chip stored data sending logic sends the obtained original data Src_Data and the preprocessing control information to the on-chip data preprocessing and storage unit;

[0072] In this embodiment, among them, the configuration information forwarded to the preprocessing control information parsing module for parsing in step S8 is the control information Preprocess_info related to data preprocessing. After parsing, the starting address Dst_Addr stored in the on-chip data preprocessing and storage unit, the functional mode Mode_info of the preprocessing, the size Slice_info of the data block, and the data masking information Mask_info are obtained.

[0073] Step S9: The data preprocessing control logic of the on-chip data preprocessing and storage unit performs data preprocessing operations after receiving the preprocessing control information, and sends the original data Src_Data and the configuration information, etc. to the data splitting and distribution logic. The data splitting and distribution logic preprocesses the original data Src_Data and stores the preprocessed data in the second data storage module; in this embodiment, the preprocessed data is marked as Data, asFigure 4 As shown, the preprocessing in this embodiment may include splitting the original data Src_Data into smaller granularities and sending them to the data storage module for caching, but it is not limited thereto;

[0074] In this embodiment, after step S9, there is also step S10: repeating steps S1 - S9 until all the data to be processed is completely transferred from the off-chip storage and access unit to the on-chip data preprocessing and storage unit.

[0075] The above process is used to illustrate the specific execution process of obtaining data from the off-chip storage unit during the data transmission stage. For a processor designed with vector components or tensor components, during the execution of an application program, it is generally required that the data to be processed be stored in a certain format so as to better exert the execution efficiency of the processor's computing components.

[0076] Step S11: The memory access control logic of the on-chip memory access execution unit initiates an instruction fetch operation through the instruction fetch module, obtains instruction information from the instruction storage module, and then the instruction execution module parses the instruction information and generates control information to feedback to the memory access control logic;

[0077] In this embodiment, the instruction information fields in step S11 include: operation type OP, memory access address Addr, memory access mode Mode, and instruction control information Ctrl_info.

[0078] Step S12: The memory access control logic generates control signals to start the data loading address calculation logic and the data loading mode parsing logic. The data loading logic, according to the received instruction information, performs a data loading operation under the control of the memory access control logic and reads data from the on-chip data preprocessing and storage unit;

[0079] In this embodiment, step S12 specifically includes:

[0080] Step S1201: When the instruction control information is a read on-chip storage instruction, the memory access control logic starts the data loading address calculation logic and sends the instruction information to the data loading mode parsing logic for parsing. After parsing out the mode information, it is feedback to the data loading logic;

[0081] Step S1202: The data loading logic integrates the memory access address and memory access mode of the data loading and generates a data loading signal, which is sent to the on-chip data preprocessing and storage unit;

[0082] Step S1203: The on-chip data preprocessing and storage unit reads data from the second data storage module through the data read / write interface logic and sends it to the on-chip memory access execution unit.

[0083] Step S13: The on-chip memory access execution unit sends the read data to the computing unit for processing, and the processed data is finally sent back to the off-chip storage unit for storage.

[0084] In this embodiment, before the data is sent back in step S13, it is also necessary to determine whether the instruction is a data return operation instruction. Specifically:

[0085] Step S1301: The fetching module obtains instruction information from the instruction storage module, and then the instruction execution module parses the instruction information;

[0086] Step S1302: When it is determined that the parsed instruction is a data return operation instruction, the memory access control logic starts the data return address calculation logic, and sends the instruction information to the data return mode parsing logic for parsing. After parsing the mode information, it is fed back to the data return logic;

[0087] Step S1303: The data return logic integrates the memory access address for data loading, the data return information, the control information, etc., and initiates a write operation to the on-chip data preprocessing and storage unit;

[0088] Step S1304: The on-chip data preprocessing and storage unit converts the signal of the write operation into an operation of writing to the second data storage module through the data read / write interface logic, so as to complete the data return to the second data storage module.

[0089] In this embodiment, after step S1304, it also includes the process of transmitting the data returned and stored in the second data storage module to the off-chip storage unit. Specifically:

[0090] Step S1305: The configuration information receiving and storing logic of the data transmission and preprocessing control unit receives and stores the configuration information from the outside, and the transmission control logic parses the configuration information and generates a control signal;

[0091] Step S1306: The transmission control logic sends the generated control signal to the on-chip storage data reading logic, and at the same time, the preprocessing control information parsing module sends the extracted preprocessing information to the on-chip data preprocessing and storage unit;

[0092] Step S1307: The data preprocessing control logic of the on-chip data preprocessing and storage unit parses the preprocessing information, and starts the data reading and integration logic to read and integrate the data returned in the second data storage module;

[0093] Step S1308: The data to be transmitted back is returned to the data transmission and preprocessing control unit after preprocessing. The transmission control logic sends a control signal to start the write data address generation logic to generate a write address. At the same time, the transmission control logic sends a control signal to start the off-chip storage data transmission logic, and forms a data transmission logic after organizing the generated write address and the data to be transmitted back. The organization in this embodiment mainly refers to converting the address format, aligning, and splicing and integrating multiple groups of received data, etc.

[0094] Step S1309: Under the action of the control signal of the transmission control logic, the data transmission bus protocol conversion logic converts the transmission request of the data transmission logic into a bus interface protocol request and sends it to the off-chip storage and access unit.

[0095] Step S1310: After receiving the bus interface protocol request through the bus interface logic, the off-chip storage and access unit sends the data to be transmitted back, the write address, and the control signal to the data read / write logic, and the data read / write logic writes the received data to the corresponding address in the data storage module.

[0096] Step S1311: Repeat steps S1305 - S1310 until all the data sizes specified in the configuration information are completely transmitted back.

[0097] The above is the process of transmitting the data stored on the chip to the off-chip storage unit after preprocessing. Since the format of the data in the processor is relatively special, the data processed by the processor needs to be used by other modules. Therefore, the data temporarily stored in the on-chip storage unit after processing needs to be transmitted back to the off-chip storage unit through the transmission module, and it is required that the data format in the off-chip storage unit is the same as before.

[0098] The system and method for data preprocessing, data transmission, and memory access provided by the present invention can realize a flexible and configurable data preprocessing function synchronously during the data transmission and memory access processes, making the time consumed by the data preprocessing process negligible. By jointly implementing the data preprocessing function in the data transmission stage and the memory access stage, the data processing process is more flexible, the data preprocessing function is richer, and the data preprocessing process is more efficient. Through the flexible and configurable and function-rich data preprocessing logic, when processing various types of algorithm applications, the computing unit in the processor can obtain the data in the desired format and perform efficient operations, greatly improving the utilization rate of the computing unit and enhancing the overall computing efficiency and performance of the processor.

[0099] Those of ordinary skill in the art can understand that the drawings are only schematic diagrams of an embodiment, and the modules or processes in the drawings are not necessarily essential for implementing the present invention.

[0100] Those of ordinary skill in the art can understand that the modules in the devices in the embodiments can be distributed in the devices in the embodiments as described in the embodiments, or can be correspondingly changed to be located in one or more devices different from the present embodiments. The modules in the above embodiments can be combined into one module, or can be further split into multiple sub-modules.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features. And these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor-oriented data preprocessing, data transmission and memory access system, characterized in that: It includes an off-chip storage and access unit, a data transmission and preprocessing control unit, an on-chip data preprocessing and storage unit, an on-chip memory access execution unit and a computing unit, wherein: The off-chip storage and access unit is preset with: a first data storage module, a data read and write logic, and a bus interface logic, wherein the bus interface logic is used for data transmission with the data transmission and preprocessing control unit; The data transmission and preprocessing control unit is preset with: transmission control logic, configuration information receiving and storing logic, read data address generating logic, off-chip storage data reading logic, data reading bus protocol conversion logic, on-chip storage data sending logic, preprocessing control information parsing module, on-chip storage data reading logic, write data address generating logic, off-chip storage data sending logic and data sending bus protocol conversion logic; wherein, the configuration information receiving and storing logic is used to receive the configuration information sent from the outside; The on-chip data preprocessing and storage unit is preset with: data preprocessing control logic, data splitting and distribution logic, a second data storage module, data read-write interface logic, and data reading and integration logic, wherein the data read-write interface logic is used to transmit data with the on-chip memory access execution unit, and the data preprocessing control logic is used to parse the received preprocessing control information and perform data preprocessing operations; The on-chip memory access execution unit is preset with: an instruction fetch module, an instruction storage module, an instruction execution module, a memory access control logic, a data loading address calculation logic, a data loading mode parsing logic, a data loading logic, a data return address calculation logic, a data return mode parsing logic and a data return logic; and The computing unit includes a vector computing component and a tensor computing component.

2. A method for processor-oriented data preprocessing, data transmission and memory access, implemented by the system of claim 1, characterized in that: include: Step S1: putting the original data to be processed into the first data storage module in the off-chip storage and access unit; Step S2: The data transmission and preprocessing control unit receives the configuration information sent from the outside through the configuration information receiving storage logic; Step S3: after the transmission control logic of the data transmission and preprocessing control unit parses the received configuration information, it obtains data from the off-chip storage unit according to the configuration information and generates a control signal; Step S4: the transmission control logic of the data transmission and preprocessing control unit sends a control signal to the read data address generation logic, the read data address generation logic generates a continuous address according to the configuration information, and the transmission control logic then sends the continuous address and the control signal to the off-chip storage data reading logic; Step S5: the off-chip storage data reading logic performs a data reading operation, generates an off-chip data reading signal according to the continuous address, and sends the signal to the data reading bus protocol conversion logic; Step S6: the data read bus protocol conversion logic receives the control signal of the transmission control logic and the off-chip data read signal, and converts it into a data read operation signal that meets the bus interface protocol and sends it to the off-chip storage and access unit; Step S7: the off-chip storage and access unit receives and analyzes the data read operation signal through the bus interface logic, generates an internal data read operation signal and sends it to the data read and write logic, the data read and write logic initiates a data read operation, obtains the original data from the corresponding address in the data storage module, and sends it to the data transmission and preprocessing control unit through the bus interface logic; Step S8: the data transmission and preprocessing control unit forwards the configuration information to the preprocessing control information parsing module for parsing to obtain the preprocessing control information, and at the same time, the transmission control logic sends the control signal to the on-chip storage data sending logic, and the on-chip storage data sending logic sends the acquired original data and preprocessing control information to the on-chip data preprocessing and storage unit; Step S9: the data preprocessing control logic of the on-chip data preprocessing and storage unit performs data preprocessing operations after receiving the preprocessing control information, and sends the original data and the configuration information to the data splitting and distribution logic, and the data splitting and distribution logic preprocesses the original data and stores the preprocessed data in the second data storage module; Step S11: the memory access control logic of the on-chip memory access execution unit initiates an instruction fetch operation through the instruction fetch module, obtains instruction information from the instruction storage module, and then the instruction execution module parses the instruction information and generates control information to feed back to the memory access control logic; Step S12: the memory access control logic generates a control signal to start the data loading address calculation logic and the data loading mode analysis logic. The data loading logic performs a data loading operation under the control of the memory access control logic according to the received instruction information and reads data from the on-chip data preprocessing and storage unit; Step S13: the on-chip memory access execution unit sends the read data to the computing unit for processing, and transmits the processed data back to the off-chip storage unit for storage.

3. The method according to claim 2, characterized in that The configuration information of step S2 includes: the starting address of the source data in the off-chip storage and access unit, the starting address of the data stored in the on-chip data preprocessing and storage unit, the direction of data transmission, the data size of the transmitted configuration information, the data transmission mode of the configuration information, the control information related to data transmission, and the control information related to data preprocessing.

4. The method according to claim 3, characterized in that The configuration information forwarded to the preprocessing control information analysis module for analysis in step S8 is control information related to data preprocessing. After analysis, the starting address, preprocessing function mode, data block size and data masking information stored in the on-chip data preprocessing and storage unit are obtained.

5. The method according to claim 2, characterized in that: After step S9, the method further includes step S10: repeating steps S1 to S9 until all the data to be processed are transferred from the off-chip storage and access unit to the on-chip data preprocessing and storage unit.

6. The method according to claim 2, characterized in that The instruction information field in step S11 includes: operation type, memory access address, memory access mode and instruction control information.

7. The method according to claim 6, characterized in that Step S12 specifically includes: Step S1201: When the instruction control information is an instruction to read on-chip storage, the memory access control logic starts the data loading address calculation logic, and sends the instruction information to the data loading mode parsing logic for parsing, and feeds back the parsed mode information to the data loading logic; Step S1202: the data loading logic integrates the memory access address and memory access mode of the data loading, and generates a data loading signal, which is sent to the on-chip data preprocessing and storage unit; Step S1203: the on-chip data preprocessing and storage unit reads data from the second data storage module through the data read / write interface logic and sends the data to the on-chip memory access execution unit.

8. The method according to claim 6, characterized in that Step S13, before returning, also determines whether the instruction is a return operation instruction, specifically: Step S1301: the value acquisition module obtains instruction information from the instruction storage module, and then the instruction execution module parses the instruction information; Step S1302: When it is determined that the instruction after parsing is a data return operation instruction, the memory access control logic starts the data return address calculation logic, and sends the instruction information to the data return mode parsing logic for parsing, and feeds back the parsed mode information to the data return logic; Step S1303: the data return logic integrates the memory access address, return data information and control information of the data loading, and initiates a write operation to the on-chip data preprocessing and storage unit; Step S1304: the on-chip data preprocessing and storage unit converts the write operation signal into a write operation to the second data storage module through the data read / write interface logic, so as to complete the data transmission back to the second data storage module.

9. The method according to claim 8, characterized in that After step S1304, the process of transmitting the returned data stored in the second data storage module to the off-chip storage unit includes: Step S1305: the configuration information receiving and storing logic of the data transmission and preprocessing control unit receives and stores the configuration information from the outside, and the transmission control logic parses the configuration information and generates a control signal; Step S1306: the transmission control logic sends the generated control signal to the on-chip storage data reading logic, and the pre-processing control information parsing module sends the extracted pre-processing information to the on-chip data pre-processing and storage unit; Step S1307: the data preprocessing control logic of the on-chip data preprocessing and storage unit analyzes the preprocessing information, and starts the data reading and integration logic to read the data returned from the second data storage module and integrate it; Step S1308: The returned data is pre-processed and then returned to the data transmission and pre-processing control unit. The transmission control logic sends a control signal to start the write data address generation logic to generate a write address. At the same time, the transmission control logic sends a control signal to start the off-chip storage data sending logic to generate the write address and the returned data, and then the data sending logic is formed after being sorted. Step S1309: under the control signal of the transmission control logic, the data transmission bus protocol conversion logic converts the transmission request of the data transmission logic into a bus interface protocol request and sends it to the off-chip storage and access unit; Step S1310: After receiving the bus interface protocol request through the bus interface logic, the off-chip storage and access unit sends the data to be returned, the write address and the control signal to the data read-write logic, and the data read-write logic writes the received data to the corresponding address in the data storage module; Step S1311: Repeat steps S1305 to S1310 until all the data size specified in the configuration information is completed and returned.

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