An Equivalence Verification Method Based on Exclusive-Or Majority Logic

Abstract

The present invention discloses an equivalence verification method based on exclusive-or majority logic. Two circuits to be verified for equivalence are constructed into a Miter circuit. If the main output values of the Miter circuit after structural rewriting are not all zero, the method ends; otherwise, a SAT solver is used to perform equivalence verification on the Miter circuit. If the SAT solver obtains a solution result, the method ends; otherwise, simulation signals of all nodes in the Miter circuit are obtained through random simulation, potential equivalent nodes are classified into equivalence classes and optimized, nodes with potential equivalent relationships are randomly obtained from the optimized equivalence classes, equivalent nodes are iteratively merged to obtain an optimized Miter circuit, and then the SAT solver is used to perform final equivalence verification on the optimized Miter circuit. This method can improve the efficiency and accuracy of equivalence verification and is particularly suitable for verifying complex multiply-accumulate mixed arithmetic circuits and XOR-intensive circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design automation, and particularly relates to an equivalence verification method based on exclusive - or majority logic. Background Art

[0002] With the continuous expansion of the scale of integrated circuit design and the continuous improvement of circuit complexity, the importance of verification in the integrated circuit design process has become increasingly prominent. As an indispensable key link in the design process, the core goal of verification is to ensure the functional correctness and implementation reliability of circuit design, avoid tape - out failures, reduce development costs, and effectively shorten the product's time - to - market. However, in the face of the increasing design scale and complexity, the traditional verification methods relying on manual verification and simple simulation are difficult to meet the requirements of modern design for efficiency and accuracy. Therefore, it is urgent to introduce more efficient and highly automated verification means to improve verification efficiency and design quality.

[0003] Combinational Equivalence Checking (CEC) is one of the core technologies in the Electronic Design Automation (EDA) process, and is widely used in various stages of integrated circuit design from high - level descriptions (such as Register Transfer Level, RTL) to physical implementation and even silicon wafer manufacturing. The main task of CEC is to ensure the functional equivalence between the results of logic synthesis, optimization, and different design implementations, and to ensure that the function remains consistent during the optimization process. Usually, the same design will produce implementation versions with significantly different structures due to different optimization strategies, so it is necessary to prove their functional consistency through equivalence verification. However, the existing equivalence verification methods face many challenges. Especially in complex combinational logic circuits, the widely existing exclusive - or (XOR) structures and intricate interconnection characteristics greatly increase the difficulty of equivalence verification.

[0004] The &cec command in the existing open - source logic synthesis tool ABC is one of the most widely used circuit equivalence verification methods. This method is based on AIG representation, and verifies the equivalence of internal circuit nodes in topological order through a SAT solver, and merges equivalent nodes to achieve fast verification. However, in practical applications, the circuit to be verified often contains equivalent node pairs with a small fan - out cone but a high XOR chain density. For traditional SAT solvers, it is a great challenge to prove the equivalence of such node pairs, resulting in a decrease in verification efficiency. The traditional equivalence verification method based on the Boolean Satisfiability Problem (SAT), although theoretically complete, faces problems of low solving efficiency and large consumption of computing resources when dealing with circuits containing a large amount of XOR logic and highly optimized circuits. Summary of the Invention

[0005] To overcome the limitations of traditional equivalence verification methods when dealing with high-density XOR circuits, the present invention provides an equivalence verification method based on XOR majority logic to improve the efficiency and accuracy of equivalence verification. By utilizing the structural characteristics represented by XOR majority logic, the method of the present invention provides a more compact circuit representation, which is particularly suitable for expressing arithmetic circuits containing a large number of XOR structures.

[0006] Aiming at the problem of low efficiency in existing combinational equivalence verification when dealing with multiply-accumulate hybrid arithmetic circuits and XOR-intensive circuits, a more efficient solution is proposed.

[0007] The technical solution adopted by the present invention to solve the above technical problems is as follows: An equivalence verification method based on XOR majority logic, and the method is as follows:

[0008] Construct two circuits to be verified for equivalence into a Miter circuit, read the And-Inverter Graph (AIG) containing the information of the Miter circuit, and convert the AIG into an XOR majority logic graph XMG. The XMG contains 3-input XOR and MAJ logic gates and is more compact than the AIG containing 2-input AND gates; perform structural rewriting on the XMG to reduce the number of nodes, logical levels, and the number of inverters in the XMG, reduce the circuit complexity, and generate a circuit structure with more high-fanout nodes;

[0009] Calculate the Primary Output (PO) value of the Miter circuit after structural rewriting. By preferentially calculating the primary output value, the equivalence of the two circuits can be quickly verified, improving the verification efficiency; if the primary output values are not all zero, the method ends, otherwise, use a SAT solver to perform equivalence verification on the Miter circuit after structural rewriting; if the SAT solver obtains a solution result, the method ends, otherwise, obtain the simulation signals of all nodes in the Miter circuit after structural rewriting through random simulation, set the nodes with equal simulation signals as potentially equivalent nodes, and divide the potentially equivalent nodes into equivalence classes;

[0010] Optimize the equivalence classes to reduce the low-quality nodes in the equivalence classes. By optimizing the equivalence classes, the quality gap between the equivalence classes and the equivalence classes after the subsequent merging of equivalent nodes can be narrowed as quickly as possible to reduce the low-quality nodes in the equivalence classes, thereby reducing the calls to the SAT solver in step 7 of the subsequent steps, accelerating the merging of equivalent nodes, and improving the overall scanning efficiency of the SAT solver; randomly obtain two nodes with potentially equivalent relationships from the optimized equivalence classes for merging equivalent nodes, and iterate to merge equivalent nodes until the equivalence classes are empty or reach the preset number of iterative executions to obtain an optimized Miter circuit, and then use a SAT solver to perform final equivalence verification on the optimized Miter circuit.

[0011] An equivalence verification method based on exclusive - or majority logic proposed by the present invention is an efficient equivalence verification method for Miter circuits, which can improve the efficiency and accuracy of equivalence verification. It is particularly suitable for verifying complex multiply - add mixed arithmetic circuits and XOR - intensive circuits, providing a new solution for equivalence verification.

[0012] Preferably, the equivalence verification method based on exclusive - or majority logic of the present invention specifically includes the following steps:

[0013] Step 1: Construct two circuits to be verified for equivalence into a Miter circuit, read the AND - Inverter Graph (AIG) containing the Miter circuit information, and use the Look - Up Table (LUT) mapping and exact synthesis method to convert the AIG into an exclusive - or majority logic graph (XMG). Then, use the algebraic properties of XOR gates and MAJ gates to rewrite the structure of the XMG.

[0014] Step 2: Calculate the primary output value of the Miter circuit after structure rewriting. If the primary output values are not all zero, it is determined that the two circuits are not equivalent, and this method ends. Otherwise, proceed to Step 3.

[0015] Step 3: Preset the conflict count limit of the SAT solver to M times. Use the SAT solver to perform equivalence verification on the Miter circuit after structure rewriting. If the SAT solver obtains a solution result within the M - time conflict count limit, this method ends. Otherwise, obtain the simulation signals of all nodes in the Miter circuit after structure rewriting through random simulation, set the nodes with equal simulation signals as potential equivalent nodes, and divide the potential equivalent nodes into equivalence classes.

[0016] Step 4: Optimize the equivalence classes to reduce the low - quality nodes in the equivalence classes. Randomly obtain two nodes with potential equivalent relationships from the optimized equivalence classes and perform equivalent node merging. Iteratively merge equivalent nodes in this way until the equivalence classes are empty or reach the preset N - time iteration execution count, obtaining an optimized Miter circuit.

[0017] Step 5: Use the SAT solver to perform the final equivalence verification on the optimized Miter circuit. The final solution result output by the SAT solver is the equivalence verification result of the two circuits.

[0018] Preferably, in Step 1, a Miter circuit is constructed based on combinational equivalence checking (CEC), that is, the corresponding output ports of the two circuits to be verified for equivalence are connected one by one through XOR gates, and the outputs of all XOR gates are converged to an OR gate to form the primary output of the Miter circuit.

[0019] More preferably, the specific process of Step 2 is:

[0020] Assign a set of random values to the input ports of the Miter circuit after structural rewriting, and perform local simulation on an XOR gate, that is, extract the information of each node in the XOR gate and its logic cone. Starting from the input ports of the Miter circuit after structural rewriting, deduce the simulation signals of each node step by step upward in the order of the connection relationships of the nodes in the logic cone, and use the calculated simulation signal of the XOR gate as the output value of the XOR gate; traverse all XOR gates to obtain the output values of all XOR gates;

[0021] If there is a case where the output value is 1 among the output values of all XOR gates, it indicates that there is a case where the main output value of the OR gate in the Miter circuit after structural rewriting is 1, that is, the main output values are not all zero, then it is determined that the two circuits are not equivalent, and this method ends; if the output values of all XOR gates are 0, it indicates that the main output values of the OR gates in the Miter circuit after structural rewriting are all 0, that is, the main output values are all zero, and proceed to step 3.

[0022] In the process of calculating the main output value of the Miter circuit after structural rewriting above, calculating the output value of the XOR gate based on logical cone tracking of relevant nodes can narrow the simulation range, avoid redundant simulation of irrelevant logic, and improve the calculation efficiency. Since the Miter circuit is represented by XMG and the calculation of its MAJ gate depends on 3-input XOR, the rewritten results of the MAJ gate can be fully reused during local simulation, reducing the probability of repeated calculation.

[0023] Preferably, the specific process of optimizing the equivalence class in step 4 is as follows:

[0024] By traversing the nodes in the equivalence class, preferentially exclude the nodes in the equivalence class whose simulation signals are all 0 or all 1, and then exclude the low-quality nodes in the equivalence class whose proportion of the characters 0 or 1 in the simulation signals is less than 20%, so as to generate simulation signals with a higher switching rate, thereby improving the efficiency of subsequent potential equivalent node merging;

[0025] Calculate the flip rate of each node in the equivalence class. If the flip rate of a certain node exceeds the preset threshold, skip this node; if the flip rate of a certain node does not exceed the preset threshold, then flip the last bit of the simulation signal of this node to 0 or 1 as the bit value of the next simulation signal of this node. Based on this bit value, verify this node with a SAT solver. If the solution result is UNSAT, it indicates that the output of the simulation signal of this node is always 0 or always 1, and replace this node with a constant node, thereby reducing the subsequent calculation burden.

[0026] Preferably, the specific process of equivalent node merging in step 4 is as follows: randomly obtain two nodes with potential equivalent relationships from the optimized equivalent classes, use a SAT solver to verify whether these two nodes are equivalent. If the solution result of the SAT solver is UNSAT, it is determined that these two nodes are equivalent and merge these two nodes; otherwise, it is determined that these two nodes are not equivalent, obtain the input signals of the SAT solver that cause these two nodes to be not equivalent, and use this input signal as a new simulation signal for re-simulation to refine the equivalent classes.

[0027] Preferably, the process of re-simulation in step 4 is as follows: add the new simulation signal to a set of random values assigned to the input ports of the Miter circuit after structural rewriting to obtain updated random values, use the updated random values to perform a re-simulation on the Miter circuit after structural rewriting, obtain the simulation signals of all nodes in the Miter circuit after structural rewriting, set the nodes with equal simulation signals as new equivalent nodes, construct new equivalent classes with the new equivalent nodes, compare the new equivalent classes with the equivalent classes obtained in step 5, and eliminate inconsistent simulation signals to refine the equivalent classes.

[0028] Compared with the prior art, the present invention has the following advantages: The equivalent verification method based on XOR majority logic of the present invention is an efficient Miter circuit equivalent verification method, which can improve the efficiency and accuracy of equivalent verification, and is particularly suitable for verifying complex multiply-accumulate mixed arithmetic circuits and XOR-intensive circuits, providing a new solution for equivalent verification. Compared with the existing &cec and hybrid_cec methods, the method of the present invention shows good experimental results. The verification speed of the method of the present invention for circuit equivalence is increased by 2.81 times and 2.74 times respectively compared with &cec and hybrid_cec. After optimizing the circuit structure through the c2rs synthesis flow command of the logic synthesis tool ABC for the test examples, the verification speed of the method of the present invention is increased by 1.51 times compared with &cec and 3.71 times compared with hybrid_cec. Therefore, the method of the present invention provides a new research idea for circuit structures with high XOR density, and at the same time shows good experimental results, having strong engineering practical significance and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the Miter circuit constructed in the embodiment;

[0030] Figure 2 It is an example diagram of converting the AND-OR-Invert graph AIG containing Miter circuit information into an XOR majority logic graph XMG;

[0031] Figure 3 It is a schematic diagram of classifying potential equivalent nodes into equivalent classes in the embodiment;

[0032] Figure 4 Schematic diagram of nodes with potential equivalence relationships constructed in the embodiments. Detailed implementation manners

[0033] The present invention will be further described in detail below in conjunction with the embodiments with reference to the drawings.

[0034] Embodiment: Take Figure 1 the two circuits Design1 and Design2 in

[0035] as the two circuits to be verified for equivalence, and use the method of the present invention for equivalence verification, including the following steps:

[0035] Step 1: Based on the combinational equivalence checking (CEC), construct the Miter circuit for the two circuits Design1 and Design2 to be verified for equivalence. As Figure 1 shown, the two circuits Design1 and Design2 have the same primary inputs Pi1~Pi n , connect the primary output po1 1 ~po1 n of Design1 and the corresponding primary output po2 1 ~po2 n of Design2 to XOR1~XORn gates one by one with XOR, and converge the outputs of the XOR1~XORn gates to an OR gate to form the primary output of the Miter circuit; read the AND-Inverter Graph (AIG) containing the Miter circuit information, and use the LUT mapping and exact synthesis method to convert the AIG into an Exclusive-Or Majority Graph (XMG), as Figure 2 shown. Figure 2 FIG. Figure 2 is an example diagram of converting the AND-Inverter Graph (AIG) containing the Miter circuit information into an Exclusive-Or Majority Graph (XMG). In Figure 2 , the AIG includes three primary inputs a, b, and c, two primary outputs P0 and P1, and six AND gates. Among them, the black dotted line with an arrow represents the directed edge with an inverter, and the black solid line with an arrow represents the signal transmission path; the XMG includes three primary inputs a, b, and c, two primary outputs P0 and P1, and two XOR gates and one MAJ gate.

[0036] Step 2: Optimize the structure of the XMG, and use the algebraic properties of the XOR gate and the MAJ gate to rewrite the structure to obtain the Miter circuit after structure rewriting.

[0037] Step 3: Calculate the primary output value of the Miter circuit after structure rewriting. If the primary output values are not all zero, it is determined that the two circuits are not equivalent. The specific process of Step 3 is as follows:

[0038] Step 3.1: Assign a set of random values to the input ports of the Miter circuit after structural rewriting, and perform local simulation on an XOR gate, that is, extract the information of each node in the XOR gate and its logic cone. Starting from the input ports of the Miter circuit after structural rewriting, deduce the simulation signals of each node step by step upward in the order of the connection relationships of the nodes in the logic cone, and use the calculated simulation signal of the XOR gate as the output value of the XOR gate; traverse all XOR gates to obtain the output values of all XOR gates;

[0039] Step 3.2: If there is a case where the output value is 1 among the output values of all XOR gates, it indicates that there is a case where the main output value of the OR gate in the Miter circuit after structural rewriting is 1, that is, the main output values are not all zero, then it is determined that the two circuits are not equivalent, and this method ends; if the output values of all XOR gates are 0, it indicates that the main output values of the OR gates in the Miter circuit after structural rewriting are all 0, that is, the main output values are all zero, and proceed to Step 4.

[0040] Step 4: Preset the conflict count limit of the SAT solver to M = 50 times, and use the SAT solver to perform the first equivalence verification on the Miter circuit after structural rewriting. If the SAT solver obtains a solution result within the M conflict count limit, then this method ends; otherwise, proceed to Step 5.

[0041] Step 5: Obtain the simulation signals of all nodes in the Miter circuit after structural rewriting through random simulation, set the nodes with equal simulation signals as potential equivalent nodes, and divide the potential equivalent nodes into equivalence classes. As Figure 3 shown, assign the simulation signals 1111 and 0000 to the input terminals of G1, G2, and G3. In this way, the simulation signals of G1, G2, G4, and G5 are 1111, and the simulation signals of G3 and G6 are 0000. Then, the equivalence classes are G1, G2, G4, G5 and G3, G6 respectively. Among them, G1, G2, and G4 are AND gates, G3 is an OR gate, G5 is an XOR gate, and G6 is a NAND gate.

[0042] Step 6: Optimize the equivalence classes. The specific process is as follows:

[0043] Step 6.1: By traversing the nodes in the equivalence class, first exclude the nodes in the equivalence class whose simulation signals are all 0 or all 1, and then exclude the low-quality nodes in the equivalence class whose proportion of the characters 0 or 1 in the simulation signals is less than 20%;

[0044] Step 6.2: Calculate the flip rate of each node in the equivalence class. If the flip rate of a certain node exceeds the preset threshold, skip this node; if the flip rate of a certain node does not exceed the preset threshold, then flip the last bit of the simulation signal of this node to 0 or 1 as the bit value of the next simulation signal of this node. Based on this bit value, verify this node using a SAT solver. If the solution result is UNSAT, it indicates that the output of the simulation signal of this node is always 0 or always 1. Replace this node with a constant node to reduce the low-quality nodes in the equivalence class and obtain an optimized equivalence class.

[0045] Step 7: Randomly obtain two nodes with potential equivalence relationships from the optimized equivalence class, and construct the outputs of these two nodes through XOR, as Figure 4 shown. A and B, C and D, E and F are respectively connected and constructed through XOR1, XOR2, and XOR3. Use a SAT solver to verify whether these two nodes are equivalent. If the solution result of the SAT solver is UNSAT, it is determined that these two nodes are equivalent and merge these two nodes; otherwise, it is determined that these two nodes are not equivalent, obtain the input signal of the SAT solver that causes these two nodes to be not equivalent, and use this input signal as a new simulation signal for re-simulation to refine the equivalence class. Among them, the process of re-simulation is: add the new simulation signal to a set of random values assigned to the input ports (PIs) of the Miter circuit after structural rewriting to obtain updated random values, use the updated random values to perform a re-simulation on the Miter circuit after structural rewriting, obtain the simulation signals of all nodes in the Miter circuit after structural rewriting, set the nodes with equal simulation signals as new equivalent nodes, construct a new equivalence class with the new equivalent nodes, compare the new equivalence class with the equivalence class obtained in Step 5, and eliminate inconsistent simulation signals to refine the equivalence class.

[0046] Step 8: Iteratively execute Step 7. The preset number of iterative executions is N = 8 times until the equivalence class is empty or the number of iterative executions reaches N times to obtain an optimized Miter circuit.

[0047] Step 9: Use a SAT solver to perform a final equivalence verification on the optimized Miter circuit. The final solution result output by the SAT solver is the equivalence verification result of the two circuits.

[0048] The method of the present invention optimizes the number of nodes, logical levels, etc. of the Miter circuit. As Figure 2 shown, the comparison result between AIG and XMG shows that XMG has a more compact structure in representation.

[0049] Table 1 shows the node information of AIG and XMG in different test circuits, and Table 2 shows the comparison of the time required for the equivalence verification of the method of the present invention and the existing &cec and hybrid_cec methods. e1 to e8, e1_c2rs to e8_c2rs in Table 1 and Table 2 are examples of equivalent circuits, and une1 and une2, une1_c2rs and une2_c2rs are examples of non-equivalent circuits.

[0050] Table 1 Node Information of AIG and XMG in Different Test Circuits

[0051]

[0052] Table 2 Comparison of the Time Required for the Equivalence Verification of the Method of the Present Invention and the Existing &cec and hybrid_cec Methods

[0053]

[0054] The data in the upper half of Table 1 show that compared with AIG, the number of logic gates of XMG is reduced by 49%, the logic level is reduced by 24%, and the number of fan-out nodes is significantly increased by 56%. The lower half of Table 1 shows the results after optimizing the circuit structure through the c2rs synthesis flow command of the logic synthesis tool ABC. The optimization process of the method of the present invention changes the optimization method of the original logic structure. The results show that compared with AIG, XMG reduces the number of logic gates by 38%, reduces the logic level by 33%, and increases the number of fan-out nodes by 9%.

[0055] As can be seen from Table 2, the verification speed of the method of the present invention for circuit equivalence is increased by 2.81 times and 2.74 times compared with &cec and hybrid_cec respectively. After optimizing the circuit structure through the c2rs synthesis flow command of the logic synthesis tool ABC for the test examples, the verification speed of the method of the present invention is increased by 1.51 times compared with &cec and by 3.71 times compared with hybrid_cec.

[0056] In summary, compared with the traditional method, the equivalence verification method based on exclusive-or majority logic proposed by the present invention significantly improves the verification efficiency. Especially for examples of non-equivalent circuits, it achieves faster and more effective verification, which has important practical significance for the application in the field of logic synthesis and the development of equivalence verification tools.

Claims

1. An equivalence verification method based on exclusive-or majority logic, characterized in that, The method specifically includes the following steps: Step 1: Construct two circuits to be verified for equivalence into a Miter circuit, read the NAND graph AIG containing the Miter circuit information, use the LUT mapping and exact synthesis method to convert the AIG into an exclusive-OR majority logic graph XMG, and perform structural rewriting on the XMG using the algebraic properties of XOR gates and MAJ gates; Step 2: Calculate the primary output value of the Miter circuit after structural rewriting. If the primary output values are not all zero, it is determined that the two circuits are not equivalent, and this method ends. Otherwise, proceed to Step 3; Step 3: Preset the conflict count limit of the SAT solver to M times. Use the SAT solver to verify the equivalence of the Miter circuit after structural rewriting. If the SAT solver obtains a solution result within the M - time conflict count limit, this method ends. Otherwise, obtain the simulation signals of all nodes in the Miter circuit after structural rewriting through random simulation, set the nodes with equal simulation signals as potentially equivalent nodes, and classify the potentially equivalent nodes into equivalence classes; Step 4: Optimize the equivalence classes to reduce the low - quality nodes in the equivalence classes; randomly obtain two nodes with potentially equivalent relationships from the optimized equivalence classes, perform equivalent node merging. Iteratively merge equivalent nodes in this way until the equivalence classes are empty or the preset N - time iteration execution count is reached, obtaining an optimized Miter circuit; Step 5: Use the SAT solver to perform the final equivalence verification on the optimized Miter circuit. The final solution result output by the SAT solver is the equivalence verification result of the two circuits.

2. The equivalence verification method based on XOR majority logic according to claim 1, wherein, In Step 1, a Miter circuit is constructed based on the combinational equivalence check CEC, that is, the corresponding output ports of the two circuits to be verified for equivalence are connected one by one through XOR gates, and the outputs of all XOR gates are aggregated to an OR gate to form the primary output of the Miter circuit.

3. The equivalence verification method based on exclusive-or majority logic according to claim 1, characterized in that The specific process of Step 2 is as follows: Assign a set of random values to the input ports of the Miter circuit after structural rewriting, perform local simulation on an XOR gate, that is, extract the information of each node in the XOR gate and its logic cone, starting from the input ports of the Miter circuit after structural rewriting, and deduce the simulation signals of each node step by step upward in the order of the connection relationships of the nodes in the logic cone to calculate the simulation signal of the XOR gate as the output value of the XOR gate; traverse all XOR gates to obtain the output values of all XOR gates; If there is a case where the output value of an XOR gate is 1 among the output values of all XOR gates, it indicates that there is a case where the primary output value of the OR gate in the Miter circuit after structural rewriting is 1, that is, the primary output values are not all zero, then it is determined that the two circuits are not equivalent, and this method ends; if the output values of all XOR gates are 0, it indicates that the primary output values of the OR gates in the Miter circuit after structural rewriting are all 0, that is, the primary output values are all zero, and proceed to Step 3.

4. The equivalence verification method based on exclusive-or majority logic according to claim 1, characterized in that The specific process of optimizing the equivalence classes in Step 4 is as follows: By traversing the nodes in the equivalence class, the nodes whose simulation signals are all 0 or all 1 in the equivalence class are excluded first, and then the low-quality nodes whose simulation signals have the characters 0 or 1 accounting for less than 20% in the equivalence class are excluded; Calculate the flip rate of each node in the equivalence class. If the flip rate of a node exceeds the preset threshold, skip the node. If the flip rate of a node does not exceed the preset threshold, flip the last bit of the simulation signal of the node to 0 or 1, which is used as the bit value of the next simulation signal of the node. Based on the bit value, perform SAT solver verification on the node. If the solution result is UNSAT, it means that the output of the simulation signal of the node is always 0 or always 1, and replace the node with a constant node.

5. The equivalence verification method based on exclusive-or majority logic according to claim 1, characterized in that, The specific process of merging equivalent nodes in step 4 is as follows: randomly obtain two nodes with potential equivalence relationship from the optimized equivalence class, use the SAT solver to verify whether the two nodes are equivalent, if the solution result of the SAT solver is UNSAT, then the two nodes are determined to be equivalent and merged; otherwise, the two nodes are determined to be unequal, obtain the input signal of the SAT solver that causes the two nodes to be unequal, and use this input signal as a new simulation signal to re-simulate to refine the equivalence class.

6. The equivalence verification method based on exclusive-or majority logic according to claim 5, wherein, The re-simulation process in step 4 is: adding the new simulation signal to a set of random values assigned to the input port of the Miter circuit after the structural rewrite to obtain an updated random value, using the updated random value to re-simulate the Miter circuit after the structural rewrite to obtain the simulation signals of all nodes in the Miter circuit after the structural rewrite, setting the nodes with equal simulation signals as new equivalent nodes, constructing a new equivalence class with the new equivalent nodes, comparing the new equivalence class with the equivalence class obtained in step 5, eliminating inconsistent simulation signals, and refining the equivalence class.

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