Clock grid simulation timing annotation method and device applied to POCV analysis mode

Abstract

The present invention discloses a clock grid simulation timing annotation method and device for use in a POCV analysis mode. The method comprises: using an auxiliary file to package the driver devices and the root nodes of a multi-source clock tree subtree in the clock grid into independent logical levels; the clock grid has multiple clock paths that drive the grid lines in parallel, one of which is selected as a reserved path, and the timing arcs of the devices and wire nets outside the reserved path are shielded; Monte Carlo simulation is used to obtain the mean and standard deviation of the delay of each device and wire net in the reserved path, as well as the mean and standard deviation of the delay of the root nodes of the multi-source clock tree subtree and its input terminal wire net; the devices and wire nets in the reserved path are respectively equivalent, and the delay of each root node of the multi-source clock tree subtree and its input terminal wire net is corrected. Accordingly, the clock grid short-circuit structure is converted into a "pseudo-clock tree" structure containing complete process fluctuation information, which can achieve accurate static timing analysis in the POCV mode.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and in particular to a clock grid simulation timing labeling method and device applied to a POCV analysis mode. Background Art

[0002] In advanced semiconductor processes, such as FinFET / GAA, process variation significantly impacts integrated circuit performance and yield. Parametric On-Chip Variation (POCV) analysis technology accurately characterizes process variation, improves the accuracy of static timing analysis (STA), and reduces pessimism during timing and power analysis and optimization. It is widely used in advanced process design.

[0003] Clock grid technology can effectively reduce the impact of process fluctuations on designs. However, the gate-level STA algorithms used in existing electronic design automation (EDA) tools only work with tree-shaped clock structures and cannot handle non-tree short-circuit structures on clock grids. This prevents EDA tools from directly obtaining accurate fluctuation information from the LVFLiberty library when using POCV analysis mode, as they do with traditional clock trees, affecting the accuracy of POCV STA.

[0004] Transistor-level Monte Carlo simulations using EDA tools such as Spectre and FineSim can reveal fluctuation information related to clock grid short-circuit structures. The primary challenge addressed by this paper is how to fully back-annotate these fluctuation statistics into the STA architecture of the POCV analysis mode, thereby accurately describing the fluctuations in the clock grid's related timing paths during the STA analysis phase. Summary of the Invention

[0005] The purpose of the present invention is to provide a clock grid simulation timing annotation method and device applied to the POCV analysis mode, aiming to solve the problem of describing the fluctuation of the clock grid timing path.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A clock grid simulation timing annotation method applied to a POCV analysis mode, wherein the clock grid includes a driver device and a line network; the clock grid is loaded with multiple multi-source clock tree subtree root nodes; the method includes:

[0008] Using auxiliary files, respectively package the driver devices in the clock grid and the plurality of multi-source clock tree subtree root nodes into independent logic levels;

[0009] The clock grid has multiple clock paths driving the grid lines in parallel, one of the clock paths is selected as a reserved path, and timing arcs of driving devices and lines outside the reserved path are shielded;

[0010] Using Monte Carlo simulation to obtain the mean and standard deviation of the driver device and line network delay in the reserved path and the mean and standard deviation of the line network delay of the root node of the multi-source clock tree subtree and its input end;

[0011] Equivalent the mean and standard deviation of the delay of each driving device in the reserved path to an equivalent device in the reserved path;

[0012] Equivalently assigning the mean and standard deviation of the delay of each network in the reserved path to an equivalent network in the reserved path;

[0013] Setting the mean and standard deviation of the delays of the non-equivalent devices and non-equivalent network in the reserved path to 0;

[0014] Equivalently assigning a mean and a standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device to the equivalent network;

[0015] Equivalently equate the mean and standard deviation of the input end network delay differences between the remaining multi-source clock tree subtree root nodes and the nearest multi-source clock tree subtree root node to the mean and standard deviation of the device delay of each corresponding multi-source clock tree subtree root node;

[0016] Static timing analysis is performed on a timing path including the clock grid and multiple multi-source clock tree subtrees in POCV analysis mode.

[0017] Preferably, the reserved path is a path with the shortest delay.

[0018] Preferably, the step of “equating the mean and standard deviation of the delay of each driving device in the reserved path to an equivalent device” includes:

[0019] Equivalently adding the average value of the delay of each driving device in the reserved path to the equivalent device in the form of cumulative sum;

[0020] The standard deviation of the delay of each driving device in the reserved path is equivalent to the equivalent device in the form of a root mean square of the standard deviation.

[0021] Preferably, the step of "equating the mean and standard deviation of the delay of each network of the reserved path to an equivalent network" includes:

[0022] Equivalently adding the average of the delays of the network of each of the reserved paths to the equivalent network in the form of cumulative sum;

[0023] The standard deviation of the delay of each network in the reserved path is equated to the equivalent network in the form of a root mean square of the standard deviation.

[0024] Preferably, the equivalent device is a driver device of the last-stage short-circuit line of the clock grid in the reserved path.

[0025] Preferably, the step of “equating the mean and standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device to the equivalent network” includes:

[0026] Equivalently add the average of the input end network delays of the root node of the multi-source clock tree subtree closest to the equivalent device to the equivalent network in the form of a cumulative sum;

[0027] The standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device is equated to the equivalent network in the form of a root mean square of the standard deviation.

[0028] A clock grid simulation timing annotation method applied to a POCV analysis mode, wherein the clock grid includes devices and wire nets; the method comprises:

[0029] A computing device includes: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid simulation timing labeling method applied to the POCV analysis mode is implemented.

[0030] A computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the clock grid simulation timing annotation method applied to the POCV analysis mode.

[0031] The advantages of the present invention are:

[0032] The clock grid simulation timing annotation method and device provided by the present invention for the POCV analysis mode can accurately back-annotate the process fluctuation statistical data obtained by transistor-level Monte Carlo simulation to the clock grid timing path, thereby improving the accuracy of STA analysis under the POCV mode, and is particularly suitable for the timing sign-off of advanced process high-performance chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram of the main flow of a clock grid simulation timing annotation method applied to the POCV analysis mode in an embodiment of the present invention;

[0034] Figure 2is a schematic diagram of a driver device and multiple multi-source clock tree subtree root nodes in a clock grid according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of a clock grid driver and multiple multi-source clock tree subtree root nodes packaged into an independent logical hierarchy in an embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of a reserved path in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the effect of timing equivalence between a driver device and a line network in a clock grid retention path in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention first uses transistor-level simulation with EDA simulation tools such as Spectre / FineSim to obtain fluctuation statistics for the circuits associated with the clock grid short-circuit portion. This is then back-annotated using the proposed method. This allows timing signoff tools (such as Synopsys PrimeTime) to convert the clock grid short-circuit structure into a timing-equivalent "pseudo-tree" structure, allowing analysis using traditional STA processes. The present invention is further described in detail below with reference to the accompanying figures and examples.

[0039] See Figure 1 , which is the main process of a clock grid simulation timing annotation method applied to POCV analysis mode. Figure 1 As shown, the clock grid simulation timing annotation method applied to the POCV analysis mode provided in this embodiment includes:

[0040] Step S1: using auxiliary files to package driver devices in a clock grid and multiple multi-source clock tree subtree root nodes into independent logic levels.

[0041] Specifically, the clock grid includes driver devices and wire nets; the clock grid is loaded with multiple root nodes of multi-source clock tree subtrees. STA analysis of the clock grid timing path uses a side file format supported by commercial EDA tools to implement fluctuation modeling of transistor-level Monte Carlo simulation statistics. To use the side file, the logic hierarchy of clock grid-related devices needs to be preprocessed, and the devices whose fluctuations are described using the side file are packaged into independent logic hierarchies. In other words, all driver devices (Pre-Mesh Driver) in the clock grid are packaged into an independent logic module; the root nodes of the multiple multi-source clock tree (Post-MeshSub-Tree) subtrees directly loaded by the clock grid are each packaged into a separate logic module.

[0042] See Figure 2 , is a schematic diagram of a clock grid in one embodiment. This embodiment is a universal two-level clock grid structure, including corresponding driver devices and wire nets. The final clock grid drives the root nodes of two multi-source clock tree subtrees. Auxiliary files (Side Files) are used to record the fluctuation information of devices in the packaged hierarchical module. Figure 3 , is a schematic diagram after being packaged into independent logic levels. Among them, all clock grid driver devices have an independent logic level, and each multi-source clock tree subtree root node has an independent logic level.

[0043] Step S2: The clock grid has multiple clock paths driving the grid lines in parallel. One of the clock paths is selected as a reserved path, and timing arcs of driving devices and nets other than the reserved path are shielded.

[0044] Specifically, there are multiple clock paths from the root node of the clock grid to the final clock grid line. One of the clock paths is selected as the reserved path, and the timing arcs of the devices and wire nets outside the reserved path are shielded. The reserved path is preferably the shortest path from the root node to the final clock grid line driving device, so as to facilitate calculations in subsequent processing. Figure 4 The part marked by the dotted rectangle is the clock path that needs to be shielded, and the remaining part is the selected retained path.

[0045] Step S3: Monte Carlo simulation is used to obtain the mean and standard deviation of the delay of the driver devices and the network in the reserved path, as well as the mean and standard deviation of the delay of the root node of the multi-source clock tree subtree and its input terminal network.

[0046] Step S4: Equivalent the mean and standard deviation of the delay of each driver device in the reserved path to an equivalent device in the reserved path.

[0047] Specifically, the equivalent device is preferably a driver device of the last stage clock grid short-circuit line in the reserved path. The average value of the delay of each driver device in the reserved path is equivalent to the equivalent device in the form of cumulative sum, which is expressed as ,in, For the The average value of the driving devices, is the mean value of the equivalent device. The standard deviation of the delay of each driver device in the reserved path is equivalent to the equivalent device in the form of root mean square, which is expressed as ,in, For the The standard deviation of each driver device, is the standard deviation of the equivalent device.

[0048] Step S5: Equivalent the mean and standard deviation of the delay of each network in the reserved path to an equivalent network in the reserved path.

[0049] Specifically, the mean delay of each network in the retained path is added to the equivalent network in the form of cumulative sum, which is expressed as ,in, For the The mean of the line network, is the mean of the equivalent network; the standard deviation of the delay of each network in the retained path is equivalent to the equivalent network in the form of root mean square, which is expressed as ,in, For the The standard deviation of the line network, is the standard deviation of the equivalent line network.

[0050] In the auxiliary file, all devices in the hierarchical module can only use the same device coefficient, and the wire net can only use the same wire net coefficient. Through the above equivalence, the clock grid retains only one valid leaf-level device and wire net in the path, so that the auxiliary file can model the complete fluctuation information of the grid line driving circuit. Figure 5 , is a schematic diagram of the effect after the timing equivalence of devices and wire networks in the clock grid.

[0051] Step S6: setting the mean and standard deviation of the delays of the non-equivalent devices and non-equivalent network in the retained path to 0.

[0052] Specifically, the mean and standard deviation of the delays of the driving devices and the equivalent network other than the equivalent devices and the equivalent network in the retained path are set to 0.

[0053] Step S7: Equivalent the mean and standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device to the equivalent network.

[0054] Specifically, the mean of the input-end network delays of the multi-source clock tree subtree root node closest to the equivalent device is cumulatively added to the equivalent network. The standard deviation of the input-end network delays of the multi-source clock tree subtree root node closest to the equivalent device is squared and applied to the equivalent network. The equivalent method is described in steps S4 and S5 and will not be further detailed here.

[0055] By combining the mean and standard deviation of the input net delay of the multi-source clock tree subtree root node closest to the equivalent device into the equivalent net in the grid-driving device logic module, the timing pessimism of the clock reconvergence path (CRPR, Clock Reconvergence Pessimism Removal) is further reduced.

[0056] Step S8: Equivalent the mean and standard deviation of the input network delay differences between the remaining multi-source clock tree subtree root nodes and the multi-source clock tree subtree root node closest to the equivalent device to the mean and standard deviation of the device delay of each corresponding multi-source clock tree subtree root node.

[0057] Specifically, the mean and standard deviation of the input delay differences of the remaining multi-source clock tree root nodes and the multi-source clock tree subtree root nodes closest to the equivalent device are respectively equivalent to the mean and standard deviation of the device delay of the corresponding multi-source clock tree subtree root node. The mean is equivalent in the form of a cumulative sum, and the standard deviation is equivalent in the form of a root mean square.

[0058] The average of the network delay differences between the root nodes of the remaining multi-source clock tree subtrees and the nearest multi-source clock tree subtree root node input is expressed as ,in, For the The average of the network delays at the input of the root node of the multi-source clock tree subtree, is the mean value of the network delay at the input of the root node of the multi-source clock tree subtree closest to the equivalent device; the standard deviation of the delay difference is expressed as ,in, For the The standard deviation of the network delay at the input of the root node of the multi-source clock tree subtree is It is the standard deviation of the net delay at the input of the root node of the multi-source clock tree subtree closest to the equivalent device.

[0059] Step S9: Perform static timing analysis on the timing path including the clock grid and the multiple multi-source clock tree subtrees in POCV analysis mode.

[0060] Specifically, through the operations in the aforementioned steps, the clock grid and multiple multi-source clock tree subtrees are converted into a "pseudo clock tree" containing complete process fluctuation information, which can perform accurate static timing analysis in POCV analysis mode.

[0061] This embodiment provides a computing device, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid simulation timing labeling method applied to the POCV analysis mode is implemented.

[0062] This embodiment also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the clock grid simulation timing annotation method applied to the POCV analysis mode.

[0063] Those skilled in the art should be able to appreciate that the method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of electronic hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0064] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a parameter, method or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or inherent to those parameters, methods or apparatus.

[0065] The above are preferred embodiments of the present invention and the technical principles used therein. For those skilled in the art, any obvious changes such as equivalent transformations, simple replacements, etc. based on the technical solution of the present invention, without departing from the spirit and scope of the present invention, are within the scope of protection of the present invention.

Claims

1. A clock grid simulation timing annotation method applied to a POCV analysis mode, wherein the clock grid includes a driver device and a line network; the clock grid is loaded with multiple multi-source clock tree subtree root nodes; characterized in that: The method comprises: Using auxiliary files, respectively package the driver devices in the clock grid and the plurality of multi-source clock tree subtree root nodes into independent logic levels; The clock grid has multiple clock paths driving the grid lines in parallel, one of the clock paths is selected as a reserved path, and timing arcs of driving devices and lines outside the reserved path are shielded; Using Monte Carlo simulation to obtain the mean and standard deviation of the driver device and line network delay in the reserved path and the mean and standard deviation of the line network delay of the root node of the multi-source clock tree subtree and its input end; Equivalent the mean and standard deviation of the delay of each driving device in the reserved path to an equivalent device in the reserved path; Equivalently assigning the mean and standard deviation of the delay of each network in the reserved path to an equivalent network in the reserved path; Setting the mean and standard deviation of the delays of the non-equivalent devices and non-equivalent network in the reserved path to 0; Equivalently assigning a mean and a standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device to the equivalent network; Equivalently equate the mean and standard deviation of the input end network delay differences between the remaining multi-source clock tree subtree root nodes and the nearest multi-source clock tree subtree root node to the mean and standard deviation of the device delay of each corresponding multi-source clock tree subtree root node; Static timing analysis is performed on a timing path including the clock grid and multiple multi-source clock tree subtrees in POCV analysis mode.

2. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, characterized in that: The reserved path is the path with the shortest delay.

3. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, characterized in that: The step of “equating the mean and standard deviation of the delay of each driving device in the reserved path to an equivalent device in the reserved path” includes: Equivalently adding the average value of the delay of each driving device in the reserved path to the equivalent device in the form of cumulative sum; The standard deviation of the delay of each driving device in the reserved path is equivalent to the equivalent device in the form of a root mean square of the standard deviation.

4. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, characterized in that: The step of “equating the mean and standard deviation of the delay of each network in the reserved path to an equivalent network in the reserved path” includes: Equivalently add the average of the delays of each network in the reserved path to the equivalent network in the form of cumulative sum; The standard deviation of the delay of each network in the reserved path is equated to the equivalent network in the form of a root mean square of the standard deviation.

5. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, characterized in that: The equivalent device is a driving device of the last-stage short-circuit line of the clock grid in the reserved path.

6. The clock grid simulation timing annotation method applied to the POCV analysis mode according to claim 1, characterized in that: The step of “equating the mean and standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device to the equivalent network” includes: Equivalently add the average value of the input end network delay of the root node of the multi-source clock tree subtree closest to the equivalent device to the equivalent network in the form of a cumulative sum; The standard deviation of the input end network delay of the multi-source clock tree subtree root node closest to the equivalent device is equated to the equivalent network in the form of a root mean square of the standard deviation.

7. A computing device comprising: memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the clock grid simulation timing labeling method applied to the POCV analysis mode as described in any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the clock grid simulation timing annotation method applied to the POCV analysis mode as described in any one of claims 1 to 6.

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