Simulation circuit post-simulation performance evaluation method based on graph transfer learning, electronic equipment and storage medium

Abstract

The invention discloses an analog circuit post-simulation performance evaluation method based on graph transfer learning, electronic equipment and a storage medium, circuit design parameters are reasonably sampled through Latin hypercube sampling, a circuit topological structure is converted into a graph structure, and an ECC model in a graph neural network is adopted. In the ECC model, not only are node features considered, but also weighted aggregation is carried out on information transmission between nodes based on edge features, and the nonlinear relation and topological structure influence in circuit design are captured more accurately. According to the method, post-simulation data acquisition is completed by using a small number of sampling points, model parameters are optimized through transfer learning, so that the model can adapt to a post-simulation scene, the prediction precision and the consistency of feature distribution are ensured, and efficient and accurate post-simulation performance evaluation is realized. According to the method, efficient and accurate post-simulation performance evaluation is realized on the premise that the post-simulation sample acquisition cost is remarkably reduced, and the method is suitable for rapid design and optimization of analog integrated circuits.

Description

Technical Field

[0001] The present invention relates to a method, an electronic device, and a storage medium for evaluating the post-simulation performance of analog circuits based on graph transfer learning, belonging to the technical field of integrated circuit design automation (EDA). Background Art

[0002] With the gradual reduction of integrated circuit manufacturing processes, the number of transistors contained in a single chip has increased from several thousand to billions, significantly improving the chip integration level and also significantly increasing the design complexity. This trend poses higher challenges to integrated circuit designers, making the design process increasingly dependent on optimized design methods and tools. Currently, relatively mature EDA tools have been developed in the field of digital integrated circuit design, greatly shortening the design cycle and improving the design efficiency. However, different from digital circuit design, analog integrated circuit design still highly relies on manual operations, lacks perfect EDA auxiliary tools, and has low design efficiency and a long cycle.

[0003] There are two main bottlenecks in the traditional analog circuit design process. First, designers need to repeatedly perform the "pre-simulation → layout design → post-simulation" cycle. And due to the significant impact of parasitic parameters (such as parasitic resistance and capacitive coupling effects) on circuit performance, multiple re-designs are often required, and the single iteration cycle can be as long as several days. Second, in the initial design stage, due to the lack of accurate estimation of layout parasitic effects, designers are difficult to accurately predict the performance during post-simulation, resulting in a rework rate of more than 60% in the later stage. This high-frequency rework and iteration seriously slow down the design process and increase the development cost.

[0004] Therefore, it is particularly important to be able to quickly and accurately evaluate the post-simulation performance of analog circuits based on the circuit topology structure and design parameters in the initial design stage. By establishing an early performance evaluation model, designers can predict the post-simulation results in the pre-simulation stage, avoid bringing potential design defects into the physical implementation stage, thus effectively avoiding design risks and reducing later rework. Moreover, early performance prediction can not only shorten the design cycle, but also theoretically shorten the design cycle by about 40% by reducing the number of actual layout generations. In addition, reducing the number of layout iterations can also significantly reduce the labor cost in the optimization process. Each layout iteration involves the collaboration of multiple engineer roles (such as layout engineers, verification engineers, etc.), and after establishing the evaluation model, the required manual participation can be reduced, thereby improving the overall efficiency.

[0005] However, when current technologies attempt to establish a prediction model of "circuit parameters → post-simulation performance" through neural networks, they face double obstacles in data acquisition and model training. Since generating layouts with parasitic parameters requires complex physical design processes, the preparation of a single sample may take several hours. In addition, traditional deep learning methods usually require a huge amount of data to reliably train prediction models, but the available training samples obtained in actual projects often far from meet the requirements of deep learning samples, resulting in unsatisfactory model training effects. This contradiction severely restricts the application of data-driven methods in analog circuit design, and there is an urgent need for new solutions to break through the data bottleneck and achieve efficient performance prediction and optimization. Summary of the Invention

[0006] Objective: To overcome the deficiencies in the prior art, the present invention provides a method, an electronic device, and a storage medium for evaluating the post-simulation performance of analog circuits based on graph transfer learning. The present invention makes full use of the similarity between pre-simulation performance and post-simulation performance, and based on pre-simulation performance data, combined with a small amount of post-simulation performance data, realizes efficient modeling and rapid evaluation through transfer learning.

[0007] Technical Solution: To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0008] In a first aspect, a method for evaluating the post-simulation performance of analog circuits based on graph transfer learning specifically includes:

[0009] According to the netlist of the analog circuit, sample the design parameters of the analog circuit to obtain a design parameter sample set. Perform pre-simulation on the netlist of the analog circuit to obtain the pre-simulation performance data corresponding to the design parameter sample set.

[0010] According to the netlist of the analog circuit, construct a heterogeneous graph structure of the analog circuit, use the design parameter sample set as node features, the connection method of nodes as edge features, and the heterogeneous graph structure, node features, and edge features as graph data.

[0011] Use the graph data and the pre-simulation performance data as the first training sample, and use the first training sample to train the pre-simulation performance evaluation model to obtain a trained pre-simulation performance evaluation model.

[0012] According to the pre-simulation performance data, divide different performance regions, select several sample points with a performance difference greater than a threshold from the design parameter sample set for different performance regions, and perform post-simulation on the sample points to obtain the circuit performance of the post-simulation.

[0013] Use the sample points and the circuit performance of the post-simulation as the second training sample, and use the second training sample to train the pre-simulation performance evaluation model to obtain a trained post-simulation performance evaluation model.

[0014] Obtain the post-layout simulation performance evaluation model trained with the netlist of the analog circuit to be tested, and obtain the post-layout simulation performance of the analog circuit to be tested.

[0015] As a preferred solution, sampling the design parameters of the analog circuit according to the netlist of the analog circuit to obtain a design parameter sample set, specifically including:

[0016] According to the netlist of the analog circuit, determine the categories of the design parameters and the constraints of the design parameters. Among them, the categories of the design parameters are divided according to different types of electrical devices; the constraints of the design parameters include, but are not limited to, taking the same design parameter values for symmetric devices in the circuit and setting an interval range for all design parameters to avoid violating physical design rules;

[0017] Sampling the design parameters of the analog circuit by using the Latin hypercube sampling method according to the categories of the design parameters and the constraints of the design parameters to obtain a design parameter sample set. The design parameter sample set is divided according to the categories of the design parameters and corresponds to different types of nodes. The node features include the design parameters of the electrical devices. The design parameters include, but are not limited to, the length, width, number of parallel transistors, number of fingers of the transistor, and the length, width, and number of parallels of the capacitor and resistor.

[0018] As a preferred solution, the pre-layout simulation performance data uses the circuit target performance.

[0019] As a preferred solution, the edge feature has the following expression:

[0020]

[0021] Among them, indicates whether the start end of the connection line is connected to the gate of the MOS transistor, indicates whether the start end of the connection line is connected to the source of the MOS transistor, indicates whether the start end of the connection line is connected to the drain of the MOS transistor, indicates whether the start end of the connection line is connected to the capacitor, indicates whether the start end of the connection line is connected to the resistor; indicates whether the end of the connection line is connected to the gate of the MOS transistor, indicates whether the end of the connection line is connected to the source of the MOS transistor, indicates whether the end of the connection line is connected to the drain of the MOS transistor, indicates whether the end of the connection line is connected to the capacitor, indicates whether the end of the connection line is connected to the resistor; if connected, the number is set to 1, otherwise set to 0.

[0022] As a preferred solution, the pre-simulation performance evaluation model includes a conditional convolutional graph neural network and a fully connected layer module connected in series.

[0023] As a preferred solution, the method for obtaining pre-simulation performance data of the pre-simulation performance evaluation model specifically includes:

[0024] Obtain graph data, where the heterogeneous graph structure , where: represents the node set, represents the edge set; the node feature matrix and the edge feature .

[0025] Input the graph data into the conditional convolutional graph neural network to obtain the updated feature values of the nodes , where the expression for the updated feature values of the nodes is as follows:

[0026]

[0027] where, represents the updated feature value of the node at the th layer, is a non-linear activation function, is the linear transformation weight of the node itself, represents the updated feature value of the node at the th layer, is the adjacent node of the node, is the set of adjacent nodes of the node, represents a multi-layer perceptron, represents the node to the node edge feature, represents the updated feature value of the node at the th layer, is the bias term.

[0028] where, the initial value of is expressed as follows:

[0029]

[0030] where, W type [ v ] is related to the node type type [ v ] The corresponding transformation matrix is the node 's original feature is the node of the 0th layer 's feature value

[0031] Input the feature value of the updated node into the fully connected layer module to obtain the pre-simulation performance data. Among them, the expression of the pre-simulation performance data is as follows:

[0032]

[0033] Among them, is the pre-simulation performance data is the graph-level aggregation function is the fully connected layer module

[0034] As a preferred solution, according to the pre-simulation performance data, different performance regions are divided, and several sample points with performance differences greater than the threshold are selected from the design parameter sample set for different performance regions. Specifically, it includes:

[0035] Use the K-means clustering analysis method to cluster the pre-simulation performance data and divide the samples into multiple performance regions

[0036] Select at least one sample point with a performance difference greater than the threshold for each performance region

[0037] As a preferred solution, post-simulate the sample points to obtain the post-simulation circuit performance. Specifically, it includes:

[0038] Input the netlist of the analog circuit into the open-source layout generation tool to output the GDS layout file

[0039] Input the GDS layout file into the parasitic parameter extraction tool. In the extraction process, select the modes of parasitic resistance, parasitic capacitance, and coupling capacitance, and select the output format to be a parasitic network model that meets the simulation requirements to obtain the layout of the analog circuit

[0040] Use the simulation tool to simulate the layout of the analog circuit to obtain the post-simulation circuit performance corresponding to the sample points

[0041] As a preferred solution, use the second training sample to train the pre-simulation performance evaluation model to obtain the trained post-simulation performance evaluation model. Specifically, it includes:

[0042] Fix the convolution layer parameters of the edge-conditioned convolutional graph neural network in the pre-simulation performance evaluation model

[0043] Use the second training sample to train the pre-simulation performance evaluation model and calculate the joint loss function

[0044] According to the combined loss function, the backpropagation algorithm is used to obtain the optimized parameters of the fully connected layer module in the pre-layout performance evaluation model.

[0045] Replace the corresponding parameters in the pre-layout performance evaluation model with the optimized parameters of the fully connected layer module to obtain the trained post-layout performance evaluation model.

[0046] In a second aspect, a computer-readable storage medium stores a computer program thereon. When the computer program is executed by a processor, it implements a method for evaluating the post-layout performance of a simulated circuit based on graph transfer learning as described in any one of the first aspects.

[0047] In a third aspect, a computer device includes:

[0048] A memory for storing instructions.

[0049] A processor for executing the instructions, such that the computer device performs the operations of a method for evaluating the post-layout performance of a simulated circuit based on graph transfer learning as described in any one of the first aspects.

[0050] Beneficial effects: The present invention provides a method for evaluating the post-layout performance of a simulated circuit based on graph transfer learning, an electronic device, and a storage medium. By using Latin hypercube sampling to reasonably sample circuit design parameters, converting the circuit topology structure into a graph structure, and adopting the edge-conditioned convolution (ECC) model in the graph neural network. In the ECC model, not only node features are considered, but also the information transfer between nodes is weighted and aggregated based on edge features, more accurately capturing the non-linear relationships and topological structure impacts in circuit design. Subsequently, a small number of sampling points are used to complete layout generation, parasitic parameter extraction, and post-layout simulation data acquisition, and the model parameters are optimized through transfer learning to enable it to adapt to the post-layout scenario, ensuring the accuracy of prediction and the consistency of feature distribution, thereby achieving efficient and accurate post-layout performance evaluation. The present invention realizes efficient and accurate post-layout performance evaluation on the premise of significantly reducing the cost of obtaining post-layout samples, and is applicable to the rapid design and optimization of analog integrated circuits.

[0051] The present invention realizes efficient fine-tuning through a small number of post-layout samples, significantly reducing the cost of obtaining post-layout data, and at the same time completing high-precision evaluation of the post-layout performance of a simulated circuit with low computational overhead, meeting the requirements of rapid modeling and engineering practice. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic flowchart of an embodiment of a method for evaluating the post-layout performance of a simulated circuit based on graph transfer learning according to the present invention.

[0053] Figure 2It is the circuit diagram of a second-stage amplifier and its corresponding schematic diagram of the graph structure. Among them, Figure 2 in (a) is the original circuit diagram, Figure 2 in (b) is the schematic diagram of the graph structure generated by mapping the original circuit diagram.

[0054] Figure 3 It is the schematic diagram of the Edge Condition Convolution (ECC) model structure. Specific implementation manners

[0055] Next, in combination with the accompanying drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

[0056] Next, the present invention will be further described in combination with specific embodiments.

[0057] Embodiment 1:

[0058] This embodiment introduces a method for evaluating the post-simulation performance of analog circuits based on graph transfer learning. As Figure 1 shown, the specific steps are as follows:

[0059] Step S1: Input the SPICE (Simulation Program with Integrated Circuit Emphasis) netlist of the analog circuit, set an upper and lower value range for the design parameters of the analog circuit according to manual experience, and then use the Latin hypercube sampling method to uniformly generate a large number of representative sample points. Perform pre-simulation on these sample points through SPICE simulation to obtain the pre-simulation performance values of the circuit, providing support for the basic data samples of the design parameter → circuit pre-simulation performance model.

[0060] Furthermore, when establishing a fitting model for post-simulation performance modeling and evaluation, since the generation of post-simulation performance data requires complex operations such as layout generation, parasitic extraction, and post-simulation, it usually consumes a large amount of computing resources and human resources, resulting in a high cost of obtaining post-simulation data. In contrast, the pre-simulation stage does not involve these complex processes, so pre-simulation performance data is easier to obtain and is suitable as the main data source for model training. At this stage, a large amount of pre-simulation performance data can be collected for the processing of learning features and the transmission of messages. The specific process of this step will be introduced in detail below:

[0061] Step 1.1: Input the SPICE netlist of the analog circuit, determine the design parameters, and constrain the numerical values of the design parameters.

[0062] The SPICE netlist is a fundamental file in analog circuit design, containing the circuit structure and component parameters. The design parameters described in this invention are component parameters, including the length and width of transistors, the number of parallel transistors, the number of fingers, as well as the length, width, and number of parallel connections of capacitors and resistors, which are used as input features of the model. To ensure the rationality of sampling, it is necessary to constrain the design parameters according to the circuit function requirements and process requirements before sampling. The main constraints include that symmetric devices in the circuit (such as differential pair transistors) obtain the same design parameter values and setting a suitable range for all design parameters to avoid violating physical design rules.

[0063] Step 1.2: Use Latin Hypercube Sampling (LHS) to achieve a large number of reasonable and representative samplings of the design parameters. The specific sampling process is as follows:

[0064] Partition the parameter space: Equally and probabilistically divide the sampling range corresponding to the n-dimensional parameter variables into several non-overlapping small intervals, each interval having the same probability; Generate candidate samples: Randomly select sample points in each interval of each dimension; Randomly combine samples: Randomly draw the selected points from each dimension to form a candidate sample matrix. Through the above sampling process, a uniformly distributed and representative design parameter sample set can be generated.

[0065] Step 1.3: Use the HSPICE simulation tool to calculate the circuit performance data corresponding to each set of design parameters.

[0066] The HSPICE simulation tool can implement the simulation of analog circuits through a simple scripting language to obtain the pre-layout simulation performance values. The pre-layout simulation performance values focus on the circuit target performance that design engineers need to optimize. For example, for operational amplifiers, performance indicators such as gain, bandwidth, power supply rejection ratio (PSRR), and common-mode rejection ratio (CMRR) are more important and concerned.

[0067] Step S2: Define each electrical component in the circuit as a node in the graph structure, and different electrical connection relationships as edges in the graph structure to construct a heterogeneous graph structure that can comprehensively represent the circuit topology characteristics and connection relationships. Then, substitute the design parameters sampled in Step 1 into the node features in the heterogeneous graph structure to obtain graph data as the input of the graph neural network.

[0068] Furthermore, in addition to the design parameters of the circuit, the circuit topology structure also has a significant impact on the circuit performance. Therefore, converting the circuit topology structure into a graph structure and using the graph neural network to process information transmission can efficiently model the topological relationship and electrical characteristics of the circuit, thereby capturing the non-linear relationships in the design.

[0069] Step 2.1: Construct a graph structure and determine the nodes in the graph structure.

[0070] The construction of the graph structure uses electrical devices as nodes, and different types of devices are used as different categories of nodes, including four categories: NMOS, PMOS, capacitors, and resistors. After extracting the nodes, the design parameters in Step 1 are used as node features and assigned to the corresponding graph nodes. Taking a two-stage operational amplifier as an example, its construction form is shown in Figure 2, where Figure 2 (a) is the original circuit diagram, including: MOS transistors M1 to M8, DC source Id, and capacitor C. Figure 2 (b) is a schematic diagram of the graph structure generated by mapping the original circuit diagram. The MOS transistors M1 to M8, DC source Id, and capacitor C are used as nodes, and the relevant nodes are connected with edges and converted into a graph structure.

[0071] Step 2.2: Construct a graph structure and determine the edges in the graph structure.

[0072] The edges in the graph structure are distinguished by the connection methods in the circuit. For example, the connection between the gate and drain of a MOS transistor is regarded as an independent connection method. To represent different connection methods, One-Hot encoding (hot encoding) is used, specifically represented as a 10-dimensional vector:

[0073]

[0074] The first five bits ( to ) record the information of the start end of the connection line: respectively represent whether it is connected to the gate, source, and drain of the MOS transistor, represents whether it is connected to the capacitor and resistor. If it is connected to any of the above, the number is set to 1, otherwise it is set to 0. The last five bits ( to ) record the information of the end of the connection line, and the representation method is the same as that of the start end. In addition, the fan-out (the number of branches connecting multiple lines) of the edge is also included as an edge feature in feature processing and message passing.

[0075] Step S3: Establish a pre-simulation performance evaluation model based on the Edge-Conditioned Convolutional Graph Neural Network (ECC) and the Fully Connected Layer (FC). Use the edge features as the weights for node aggregation to realize the embedding and message passing of graph nodes. Subsequently, use the Fully Connected Layer (FC) to fit the processed graph features.

[0076] Furthermore, in step S3, by using sample data and combining the Edge-Conditioned Convolutional Graph Neural Network (ECC) and the fully connected layer (FC), the processing ability of graph-structured data is effectively improved. ECC uses edge features as weights for node aggregation, which can accurately capture the relationships between nodes and the messages transmitted, thus enhancing the information expression ability during the node embedding process. At the same time, ECC dynamically adjusts the convolutional kernel weights through a multi-layer perceptron, further improving the flexibility of feature fusion and the fitting ability of the model. Subsequently, the fully connected layer performs deep aggregation and transformation on the processed node features to extract global features for performance prediction. This method not only improves the accuracy of the pre-simulation performance prediction but also enhances the robustness and generalization ability of the model through hierarchical information processing. Specifically, it includes the following:

[0077] Step 3.1: The ECC processing module, and the specific processing method and model structure are as Figure 3 shown.

[0078] Step 3.1.1: Input the heterogeneous graph structure obtained in step 2.

[0079] In the ECC model, the input graph structure is the heterogeneous graph structure obtained in step 2 , where: represents the node set, represents the edge set; the node feature matrix and the edge feature .

[0080] Step 3.1.2: Introduce the type transformation matrix.

[0081] To efficiently process the features of different types of nodes, a type transformation matrix is introduced to map the features of different types of nodes to the same feature space:

[0082]

[0083] where, W type [ v ] is the transformation matrix corresponding to the node type type [ v ] , is the original feature of the node , the feature value at the 0th layer.

[0084] Step 3.1.3: Update and convolution of node features.

[0085] The convolution operation of the ECC model updates the representation of each node by aggregating its own node features and the neighbor node features. At the th layer, the node The characteristic values are updated through the following formula:

[0086]

[0087] where represents the characteristic value of the node feature at the th layer, is the linear transformation weight of the node itself, is the set of adjacent nodes of the node, is an adjacent node of the node, is a multi-layer perceptron (MLP) that takes the edge feature as input and generates dynamic convolutional kernel weights, is the bias term, is a non-linear activation function used to enhance the expressiveness of the function.

[0088] Through such a processing process, ECC can effectively capture the complex relationships between nodes, dynamically adjust the feature update, and further improve the fitting ability and prediction accuracy of the model.

[0089] Step 3.2: Construction of the fully connected layer (FC module) to achieve the fitting prediction of the pre-layout performance.

[0090] After the last layer of convolution, the node features of the graph are aggregated into global features through the fully connected layer (FC module) for the prediction of the pre-layout performance,

[0091]

[0092] where Aggregate is a graph-level aggregation function; the FC module contains multiple fully connected layers, and each layer performs linear transformation, non-linear activation, and regularization (Dropout or Batch Normalization). The FC module enhances the expressiveness of the model and the robustness of training by extracting global depth features layer by layer. Through the collaborative effect of the above ECC and FC modules, the finally output predicted value is the prediction result of the pre-layout performance, is the node set.

[0093] Step S4: According to the pre-layout performance data of the initial samples, select a small number of sample points with significant performance differences, perform layout generation, parasitic parameter extraction, and post-layout simulation, and obtain the post-layout performance data to provide samples for optimizing the post-layout performance evaluation model.

[0094] Further, in step S4, after the preliminary establishment of the model, to further improve the accuracy and generalization ability of the post-layout simulation performance evaluation model, it is necessary to select representative sample points from the pre-layout simulation performance data to generate post-layout simulation performance data, so as to enhance the training effect and robustness of the post-layout simulation performance evaluation model. In addition, a layout automatic generation tool is used to realize the full automation of the entire process.

[0095] Step 4.1: According to the pre-layout simulation performance data of the initial samples, select several sample points with performance differences greater than the threshold from different performance regions to cover different performance regions.

[0096] Use K-means clustering analysis to cluster the pre-layout simulation performance data, divide the samples into multiple performance regions, and ensure that each region has at least one sample point as a representative to cover the entire performance space.

[0097] Step 4.2: Automatic layout generation, parasitic parameter extraction, and post-layout simulation.

[0098] For the selected sample points, use the MAGICAL open-source layout generation tool, input the SPICE netlist, and output the GDS layout file to quickly complete the layout generation. This step can achieve full automation of the prediction. When the GDS layout file is obtained, use the Calibre-XRC tool (parasitic parameter extraction tool) to extract the parasitic parameters of the generated layout. The extraction process selects the R+C+CC (parasitic resistance, parasitic capacitance, and coupling capacitance) mode to consider both the speed and accuracy of the post-layout simulation, and the output format selects the parasitic network model (SPICE format) that meets the simulation requirements. Subsequently, use HSPICE to simulate the circuit after layout to obtain the circuit performance of the post-layout simulation, and the type of circuit performance is the same as that obtained in step 1.

[0099] Step S5: On the basis of fixing the convolution layer parameters of the ECC model in the pre-layout simulation performance evaluation model, fine-tune the fully connected layer parameters through transfer learning, and train using the combined loss function of the maximum mean discrepancy (MMD) and the mean square error (MSE) to quickly construct the post-layout simulation performance evaluation model.

[0100] Further, in step S5, after the preliminary establishment of the model, transfer learning is used to fine-tune the fully connected layer parameters to improve the adaptability and prediction accuracy of the model to the post-layout simulation performance data. Specifically, transfer learning can make full use of the model trained in the pre-layout simulation stage to ensure that the model can converge quickly and fine-tune it to be able to handle the characteristic distribution of the post-layout simulation data. This method can not only accelerate the model training process but also enhance the generalization ability of the model.

[0101] Specifically, it includes the following key steps:

[0102] Step 5.1: Fix the parameters of the convolutional layer.

[0103] First, fix the parameters of the convolutional layer in the pre-layout performance evaluation model (i.e., the ECC model part) to keep the model's understanding of the circuit topology and feature relationships unchanged. This step ensures that the model can retain the learning results of the original circuit characteristics during the migration process.

[0104] Step 5.2: Fine-tune the transformation matrix and the parameters of the fully connected layer.

[0105] Based on the fixed parameters of the convolutional layer, adjust the transformation matrix before the convolutional layer and the parameters of the fully connected layer for prediction after the convolutional layer to make the model adapt to the distribution characteristics of the post-layout data. In this way, the post-layout performance evaluation model can more accurately predict the post-layout performance data.

[0106] Step 5.3: Optimize the combined loss function.

[0107] Use the Maximum Mean Discrepancy (MMD) and the Mean Squared Error (MSE) as the combined loss function for training. The loss function is defined as:

[0108] where and are both weight hyperparameters used to adjust the relative importance of the two parts of the loss. During the calculation of the loss function, the Mean Squared Error is used to measure the error between the model's predicted value and the true post-layout performance data, and the formula is:

[0109]

[0110] where is the predicted post-layout performance value by the model, is the true post-layout performance value. The Maximum Mean Discrepancy is used to measure the difference between the feature distributions of the pre-layout and post-layout samples, and the formula is:

[0111]

[0112] where and are the features of the pre-layout and post-layout samples obtained through the convolutional layer respectively, is the kernel function mapping that maps the features to a high-dimensional space to measure the difference in the feature distributions of the pre-layout and post-layout samples; and are the numbers of pre-layout and post-layout samples respectively.

[0113] MMD ensures the consistency of the feature distributions between the pre-layout and post-layout data, while MSE is used to measure the difference between the model's predicted value and the true post-layout performance data. The combination of the two ensures the accuracy and stability during the training process.

[0114] Step 5.4: Backpropagation optimization.

[0115] Optimize the parameters of the fully connected layer through the backpropagation algorithm, enabling the model to converge rapidly and ultimately obtaining an accurate post-layout simulation performance evaluation model.

[0116] Step S6: Obtain the post-layout simulation performance of the analog circuit under test by inputting the netlist of the analog circuit under test into the trained post-layout simulation performance evaluation model.

[0117] Embodiment 2:

[0118] A computer-readable storage medium storing a computer program, which when executed by a processor, implements a method for post-layout simulation performance evaluation of an analog circuit based on graph transfer learning as described in any one of Embodiment 1.

[0119] Embodiment 3

[0120] A computer device, comprising:

[0121] A memory for storing instructions.

[0122] A processor for executing the instructions, causing the computer device to perform the operations of a method for post-layout simulation performance evaluation of an analog circuit based on graph transfer learning as described in any one of Embodiment 1.

[0123] Embodiment 4:

[0124] This embodiment introduces the verification effect of the method of the present invention on a two-stage transconductance operational amplifier. The experimental verification is carried out on a software and hardware platform (Intel Xeon Gold 5118 CPU + NVIDIA A100 GPU) composed of MAGICAL (automatic layout generation), Calibre-XRC (parasitic parameter extraction), HSPICE (post-layout simulation), and PyTorchGeometric (graph neural network implementation) for a typical analog circuit, namely the two-stage transconductance operational amplifier. The key design parameters of the test circuit include transistor size (W / L), bias voltage, and load capacitance, etc. 300 groups of pre-layout simulation samples are generated by Latin Hypercube Sampling (LHS) for model pre-training, and 50 groups of samples are selected for layout generation and post-layout simulation to obtain the true performance indicators, and an additional 50 groups of independent post-layout simulation data are reserved as the test set. The circuit topology is converted into a graph data model, the node features cover transistor type (NMOS / PMOS), size, and bias state, the edge features include the connection relationship between devices, and the adjacency matrix is automatically generated from the circuit netlist for topological connection. The experiment uses a 3-layer Edge-Conditioned Convolution (ECC) model combined with a global pooling layer, fixes the hyperparameters of the ECC layer through a transfer learning strategy, and fine-tunes the fully connected layer to complete the training.

[0125] To comprehensively evaluate the performance of the method of the present invention, the following methods are selected as comparison benchmarks in the experiment: Gaussian process regression (GPR), XGBoost, and the ECC model without using transfer learning. The evaluation metrics include mean squared error (MSE), coefficient of determination (R²), the demand for post-simulation data, and the required time. The specific data is shown in the following table:

[0126] method <![CDATA[MSE (* 10 -3 )]]> <![CDATA[R 2 > Post-simulation data requirement Required time (hours) GPR 5.21 0.87 200 post-simulations 6.3 XGBoost 4.78 0.89 200 post-simulations 6.1 ECC 1.24 0.94 200 post-simulations 6.5 This invention 1.56 0.93 300 pre-simulations + 50 post-simulations 2.2

[0127] Since the proportion of the post-simulation time is relatively long, the time spent by the model is mainly used for obtaining simulation samples. And the amount of post-simulation samples required by the present invention is small, so a great advantage in time can be achieved. The combination of using graph structure modeling and transfer learning can more accurately capture the relationship between the circuit non-linear characteristics and the post-simulation parasitic effects, ensuring that the final prediction result of the post-simulation performance obtains sufficient accuracy. In summary, the method of the present invention shows superior performance in the optimization of analog circuit design, which helps to improve the efficiency and feasibility of automated design.

[0128] The present invention first performs large-scale sampling on the circuit design parameters. To ensure the universality and representativeness of the data, the Latin hypercube sampling method is adopted, and based on the basic circuit knowledge, the reasonable range of the design parameters and the parameter consistency of the symmetric devices are ensured. On this basis, the pre-simulation performance data of the circuit corresponding to each group of design parameters is generated through SPICE simulation for the training of the preliminary model. Subsequently, the circuit topology structure is transformed into a heterogeneous graph representation, where different types of electrical devices (such as NMOS, PMOS, capacitors, resistors) are used as different types of nodes, and the design parameters are used as node features. At the same time, one-hot encoding is used to represent the edge features to distinguish different connection methods. The graph structure constructed in this way can effectively express the circuit topology relationship.

[0129] Based on this graph structure, an edge-conditioned convolution (ECC) model is used to construct a graph neural network, which dynamically adjusts the information transfer weights between nodes by combining edge features, and realizes the aggregation of node features and the modeling of the non-linear relationship of the circuit topology. Through the ECC model, an initial pre-simulation performance prediction model is generated. In the transfer learning stage, based on the pre-simulation performance prediction model, a small amount of post-simulation performance data is used to fine-tune the parameters of the fully connected layer, while the parameters of the convolutional layer remain fixed to ensure that the learning of the circuit topology structure is not affected. To improve the adaptability and prediction accuracy of the model during the transfer learning process, a joint loss function of maximum mean discrepancy (MMD) and mean squared error (MSE) is adopted during the training process. MMD is used to measure the consistency of the feature distributions of the pre-simulation and post-simulation data to ensure the alignment of the feature distributions during the transfer learning process; MSE is used to measure the error between the model prediction value and the real post-simulation performance data, so as to ensure the accuracy of the evaluation.

[0130] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for evaluating the performance of analog circuit post-simulation based on graph transfer learning, characterized in that: Specifically include: According to the netlist of the analog circuit, the design parameters of the analog circuit are sampled to obtain a design parameter sample set; Pre-simulation is performed on the netlist of the analog circuit to obtain pre-simulation performance data corresponding to the design parameter sample set; According to the netlist of the analog circuit, a heterogeneous graph structure of the analog circuit is constructed, and the design parameter sample set is used as the node feature, the node connection mode is used as the edge feature, and the heterogeneous graph structure, node feature and edge feature are used as graph data; The graph data and the pre-simulation performance data are used as first training samples, and the pre-simulation performance evaluation model is trained using the first training samples to obtain a trained pre-simulation performance evaluation model; According to the pre-simulation performance data, different performance regions are divided, and for different performance regions, a number of sample points with performance differences greater than a threshold are selected from the design parameter sample set, and post-simulation is performed on the sample points to obtain post-simulation circuit performance; The sample points and the post-simulation circuit performance are used as second training samples, and the pre-simulation performance evaluation model is trained using the second training samples to obtain a trained post-simulation performance evaluation model; The netlist of the analog circuit to be tested is obtained and input into the trained post-simulation performance evaluation model to obtain the post-simulation performance of the analog circuit to be tested.

2. The method for evaluating the performance of analog circuit post-simulation based on graph transfer learning according to claim 1, characterized in that: The step of sampling the design parameters of the analog circuit according to the netlist of the analog circuit to obtain a design parameter sample set specifically includes: According to the netlist of the analog circuit, determine the category of the design parameters and the constraints of the design parameters, wherein the category of the design parameters is divided according to different types of electrical equipment; the constraints of the design parameters include but are not limited to taking the same design parameter values ​​for symmetrical devices in the circuit and setting an interval range for all design parameters to avoid violating physical design rules; According to the categories of design parameters and the constraints of design parameters, the Latin hypercube sampling method is used to sample the design parameters of the analog circuit to obtain a design parameter sample set. The design parameter sample set is divided according to the categories of design parameters and corresponds to different types of nodes. The node characteristics include the design parameters of the electrical equipment.

3. The method for evaluating the performance of analog circuit post-simulation based on graph transfer learning according to claim 1, characterized in that: The edge feature The expression is as follows: ； in, Indicates whether the beginning of the connection line is connected to the gate of the MOS tube. Indicates whether the beginning of the connection line is connected to the source of the MOS tube. Indicates whether the beginning of the connection line is connected to the drain of the MOS tube. Indicates whether the beginning of the connection line is connected to a capacitor. Indicates whether the beginning of the connection line is connected to a resistor; Indicates whether the tail of the connection line is connected to the gate of the MOS tube. Indicates whether the tail of the connection line is connected to the source of the MOS tube. Indicates whether the tail of the connection line is connected to the drain of the MOS tube. Indicates whether the end of the connecting line is connected to a capacitor. Indicates whether a resistor is connected to the end of the connecting line; if so, the number is set to 1, otherwise it is set to 0.

4. The method for evaluating the performance of analog circuit post-simulation based on graph transfer learning according to claim 1, characterized in that: The pre-simulation performance evaluation model includes a serially connected edge conditional convolutional graph neural network and a fully connected layer module.

5. The method for evaluating post-simulation performance of analog circuits based on graph transfer learning according to claim 1, characterized in that: The method for obtaining pre-simulation performance data of a pre-simulation performance evaluation model specifically includes: Get graph data, where heterogeneous graph structure ,in: Represents a collection of nodes. Represents edge set; node feature matrix And edge features ; Input the graph data into the edge conditional convolutional graph neural network to obtain the updated nodes The characteristic value of The characteristic numerical expression of is as follows: ； in, Indicates Updated nodes of the layer The characteristic value of is a nonlinear activation function, is the linear transformation weight of the node itself, Indicates Updated nodes of the layer The characteristic value of yes The neighboring nodes of a node, yes The set of adjacent nodes of a node, represents a multilayer perceptron, Representation Node To Node The characteristics of the edge, Indicates Updated nodes of the layer The characteristic value of is the bias term; in, Initial value of The expression is as follows: ； in, Is the node type The corresponding transformation matrix is, Is a node The original characteristics of It is a node at level 0 The characteristic value of The updated node The characteristic values ​​of are input into the fully connected layer module to obtain the pre-simulation performance data, where the pre-simulation performance data expression is as follows: ； in, is the pre-simulation performance data, is a graph-level aggregation function, It is a fully connected layer module.

6. The method for evaluating the performance of analog circuit post-simulation based on graph transfer learning according to claim 1, characterized in that: The method of dividing different performance areas according to the pre-simulation performance data and selecting a number of sample points whose performance differences are greater than a threshold from the design parameter sample set for different performance areas specifically includes: The K-means cluster analysis method is used to cluster the pre-simulation performance data and divide the samples into multiple performance areas; For each performance area, at least one sample point whose performance difference is greater than a threshold is selected.

7. The method for evaluating the performance of analog circuit post-simulation based on graph transfer learning according to claim 1, characterized in that: The post-simulation of the sample points to obtain the post-simulation circuit performance specifically includes: Input the netlist of the analog circuit into the open source layout generation tool and output the GDS layout file; Input the GDS layout file into the parasitic parameter extraction tool, select the mode of parasitic resistance, parasitic capacitance and coupling capacitance in the extraction process, select the parasitic network model that meets the simulation requirements as the output format, and obtain the layout of the simulation circuit; Use simulation tools to simulate the layout of the analog circuit to obtain the post-simulation circuit performance corresponding to the sample points.

8. The method for evaluating post-simulation performance of analog circuits based on graph transfer learning according to claim 1, characterized in that: The method of training the pre-imitation performance evaluation model using the second training sample to obtain a trained post-imitation performance evaluation model specifically includes: Fix the convolutional layer parameters of the edge-conditional convolutional graph neural network in the pre-simulation performance evaluation model; Using the second training sample to train the pre-imitation performance evaluation model, and calculating the joint loss function; According to the joint loss function, the back propagation algorithm is used to obtain the optimization parameters of the fully connected layer module in the pre-simulation performance evaluation model; The optimized parameters of the fully connected layer module replace the corresponding parameters in the pre-imitation performance evaluation model to obtain the trained post-imitation performance evaluation model.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, it implements a method for evaluating post-simulation performance of an analog circuit based on graph transfer learning as described in any one of claims 1 to 8.

10. A computer device, characterized in that: include: A memory for storing instructions; A processor is used to execute the instructions so that the computer device performs the operations of the post-simulation performance evaluation method of analog circuits based on graph transfer learning as described in any one of claims 1 to 8.

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