Dynamic ramp compensation circuit for switching power converter and electronic device thereof

Abstract

The invention discloses a dynamic slope compensation circuit for a single-inductor dual-output switching power converter and electronic equipment. The circuit comprises a first operational amplifier, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second PMOS tube, a third PMOS tube, a third resistor, a third capacitor, a first AND gate and a second AND gate, wherein the first operational amplifier, the first NMOS tube and the third resistor form a voltage-to-current branch, and the voltage-to-current branch is used for converting a first output voltage into a first branch current; the first PMOS tube, the second PMOS tube and the third PMOS tube form a current mirror structure which is used for copying the first branch current into a second branch current and a third branch current in proportion; and the second branch current and the third branch current charge the third capacitor in sequence in stages, so that the compensation voltage correspondingly has a first increasing slope and a second increasing slope in the rising stage of the inductive current, and staged dynamic slope compensation is realized.

Description

Technical Field

[0001] The present invention relates to a dynamic ramp compensation circuit for a single-inductor dual-output switching power supply converter, and also relates to a switching power supply converter and a corresponding electronic device including the dynamic ramp compensation circuit, belonging to the technical field of switching power supplies. Background Art

[0002] With the continuous development of integrated circuit technology, a system on chip (SoC) can highly integrate multiple subsystems in a CMOS chip. These subsystems have independent and strict requirements for power supplies respectively. Therefore, a power management chip is required to stably provide multiple power supplies with different voltage levels simultaneously. In the above SoC application scenario, a single-inductor dual-output (SIDO) switching power supply converter, with its excellent ability to generate two independent voltage source outputs using only one off-chip inductor, significantly reduces the number of off-chip inductors used, effectively saves the area of the PCB board and reduces the chip cost. Therefore, the single-inductor dual-output switching power supply converter is widely used in portable electronic devices.

[0003] In the prior art, the switching power supply converter usually adopts a peak current mode control method to regulate the output voltage. This control method has advantages such as a relatively fast transient closed-loop response. However, when the duty cycle of the control signal exceeds 50%, in order to avoid the circuit generating subharmonic oscillations and affecting stability, ramp compensation needs to be performed during the inductor current rising stage. However, due to the single-inductor dual-output switching power supply converter having two independent different voltage outputs, it has two different inductor current falling slopes, resulting in a poor ramp compensation effect in the prior art. Therefore, it is necessary to perform precise and effective segmented dynamic ramp compensation for the two voltage outputs of the single-inductor dual-output switching power supply converter to meet the power supply requirements of the SoC system.

[0004] In the Chinese patent application with the application number 202210600131.8, a flyback ramp compensation system and its compensation method are disclosed. The ramp compensation system includes an error detection unit, an adjustment control logic unit, a compensation register unit, and a flyback compensation current generation unit; the compensation method determines whether to adjust the size of the internal compensation ramp by detecting the difference in conduction time within two adjacent cycles in real time, and finds the optimal compensation ramp value through a flyback adjustment method to achieve real-time adjustment when there are disturbances in the system. Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a dynamic ramp compensation circuit for a single-inductor dual-output switching power supply converter.

[0006] Another technical problem to be solved by the present invention is to provide a single-inductor dual-output switching power supply converter including the dynamic ramp compensation circuit.

[0007] Yet another technical problem to be solved by the present invention is to provide a corresponding electronic device.

[0008] To achieve the above object, the present invention adopts the following technical solutions:

[0009] According to the first aspect of the embodiment of the present invention, there is provided a dynamic ramp compensation circuit for a single-inductor dual-output switching power supply converter, including a first operational amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a third resistor, a third capacitor, a first AND gate, and a second AND gate; wherein,

[0010] The first operational amplifier, the first NMOS transistor, and the third resistor form a voltage-to-current branch for converting the first output voltage of the single-inductor dual-output switching power supply converter into a first branch current;

[0011] The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor form a current mirror structure for proportionally replicating the first branch current into a second branch current and a third branch current;

[0012] In each period of the inductor current of the single-inductor dual-output switching power supply converter, the second branch current and the third branch current sequentially charge the third capacitor in stages, so that the compensation voltage output by the dynamic ramp compensation circuit has a first growth slope and a second growth slope during the rising stage of the inductor current, realizing staged dynamic ramp compensation for the single-inductor dual-output switching power supply.

[0013] Preferably, the current ratio of the current mirror structure formed by the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor is 1:1:K, where the value of K is the ratio of the second output voltage to the first output voltage of the single-inductor dual-output switching power supply converter.

[0014] Preferably, the non-inverting input terminal of the first operational amplifier is connected to the first output terminal of the single-inductor dual-output switching power supply converter, the output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the first operational amplifier's inverting input terminal through the third resistor, and the other end of the third resistor is connected to the ground potential terminal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor.

[0015] Preferably, the drain of the first PMOS transistor is connected to the gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, and the sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the power supply terminal; the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, and the sources of the second NMOS transistor and the third NMOS transistor are connected to each other and then connected to the third capacitor and the drain of the fourth NMOS transistor on one hand and to the compensation voltage output terminal on the other hand; the other end of the third capacitor and the source of the fourth NMOS transistor are both connected to the ground potential terminal.

[0016] Preferably, the gate of the fourth NMOS transistor is connected to the input terminal of the second control signal; the gate of the second NMOS transistor is connected to the output terminal of the first AND gate, the first input terminal of the first AND gate is connected to the input terminal of the first control signal, and the second input terminal of the first AND gate is connected to the input terminal of the third control signal; the gate of the third NMOS transistor is connected to the output terminal of the second AND gate, the first input terminal of the second AND gate is connected to the input terminal of the first control signal, and the second input terminal of the second AND gate is connected to the input terminal of the fourth control signal; wherein, the first control signal, the second control signal, the third control signal, and the fourth control signal are respectively the control signals of the first output switch, the second input switch, the first output switch, and the second output switch of the single-inductor dual-output switching power supply converter.

[0017] Preferably, the first branch current, the second branch current, and the third branch current respectively satisfy the following formulas:

[0018]

[0019] where, I M6 is the first branch current, I M7 is the second branch current, I M8 is the third branch current; V OUTA is the first output voltage of the single-inductor dual-output switching power supply converter, V OUTB is the second output voltage of the single-inductor dual-output switching power supply converter; R2 is the resistance value of the third resistor.

[0020] Preferably, the first rising slope and the second rising slope of the compensation voltage respectively satisfy the following formulas:

[0021]

[0022] Wherein, m1 is the first growth slope, and m2 is the second growth slope; V OUTA is the first output voltage of the single-inductor dual-output switching power supply converter, and V OUTB is the second output voltage of the single-inductor dual-output switching power supply converter; R2 is the resistance value of the third resistor, and C2 is the capacitance value of the third capacitor.

[0023] Preferably, in the falling stage of the inductor current, the second NMOS transistor is in the cut-off state, the third NMOS transistor is in the cut-off state, and the fourth NMOS transistor is in the conducting state, so that the third capacitor discharges rapidly through the fourth NMOS transistor, and the compensation voltage output by the dynamic slope compensation circuit rapidly drops to 0.

[0024] According to the second aspect of the embodiments of the present invention, a single-inductor dual-output switching power supply converter including the above dynamic slope compensation circuit is provided.

[0025] According to the third aspect of the embodiments of the present invention, an electronic device is provided, which includes the above single-inductor dual-output switching power supply converter.

[0026] Compared with the prior art, the dynamic slope compensation circuit for a single-inductor dual-output switching power supply converter provided by the present invention effectively solves the stability problem of the single-inductor dual-output switching power supply converter when the duty cycle exceeds 50% through a staged dynamic slope compensation technique, realizes precise compensation for the two output voltages, avoids the generation of subharmonic oscillations, improves the accuracy of slope compensation and the stability of power supply. At the same time, the circuit is ingeniously designed, has a low cost and excellent performance, and can be widely applied to various electronic devices requiring precise power management. Description of the Drawings

[0027] Figure 1 is the circuit schematic diagram of a typical single-inductor dual-output switching power supply converter in the prior art;

[0028] Figure 2 is the schematic diagram of the periodic variation of the control signal and the inductor current of the single-inductor dual-output switching power supply converter in the prior art;

[0029] Figure 3 is the schematic diagram of a typical slope compensation circuit in the prior art;

[0030] Figure 4 The schematic diagram of a dynamic slope compensation circuit for a single-inductor dual-output switching power supply converter provided by the embodiments of the present invention;

[0031] Figure 5 is the schematic diagram of the periodic variation of the control signal, the inductor current and the compensation voltage of the single-inductor dual-output switching power supply converter in the embodiments of the present invention;

[0032] Figure 6 In the embodiment of the present invention, it is a structural block diagram of a single-inductor dual-output switching power supply converter with a dynamic slope compensation circuit;

[0033] Figure 7 In the embodiment of the present invention, it is a timing comparison diagram of multiple control signals of a single-inductor dual-output switching power supply converter with a dynamic slope compensation circuit;

[0034] Figure 8 It is a schematic structural diagram of an electronic device provided by the embodiment of the present invention. Specific embodiments

[0035] The technical content of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] As Figure 1 shown, a typical single-inductor dual-output switching power supply converter in the prior art includes a first input switch S1, a second input switch S2, a first output switch S3, and a second output switch S4, as well as a first inductor L, a first capacitor C A , a second capacitor C B , a first load resistor R A , a second load resistor R B and an input voltage source V IN ; V OUTA is the first output voltage, and V OUTB is the second output voltage. The switching power supply converter circuit controls the on / off of the input / output switches in different time sequences, so that the first inductor L supplies power to the loads at the two output terminals in a sequential energy distribution control manner.

[0037] When the single-inductor dual-output switching power supply converter is working normally, the on / off states of the input / output switches S1, S2, S3, S4 and the current I of the first inductor L L change as Figure 2 shown. Among them, the input / output switches S1, S2, S3, S4 are all closed when their switch control signals are high and opened when they are low. The magnitude of the inductor current I L changes periodically. In the first time period t1 of a cycle, the first output switch S1 is closed, the second input switch S2 is opened, the first output switch S3 is closed, and the second output switch S4 is opened. The inductor current I L gradually increases to charge the first capacitor C at the first output terminal A ; In the second time period t2, the first output switch S1 is closed, the second input switch S2 is opened, the first output switch S3 is opened, and the second output switch S4 is closed. The inductor current I LContinue to increase the second capacitor C for the second output terminal B to charge; in the third time period t3, the first output switch S1 is turned off, the second input switch S2 is turned on, the first output switch S3 is turned off, and the second output switch S4 is turned on, and the inductor current I L gradually decreases to discharge the second load resistor R for the second output terminal B ; in the fourth time period t4, the first output switch S1 is turned off, the second input switch S2 is turned on, the first output switch S3 is turned on, and the second output switch S4 is turned off, and the inductor current I L continues to decrease to discharge the first load resistor R for the first output terminal A ..

[0038] For a switching power supply converter using peak current mode control, when the duty cycle of the control signal exceeds 50%, ramp compensation is required during the inductor current rising stage. A typical ramp compensation circuit in the prior art is as Figure 3 shown. The operational amplifier A1, NMOS transistor M1, and resistor R1 form a voltage-to-current branch. The PMOS transistors M2 and M3 form a current mirror structure. The NMOS transistor M4 is a switching transistor, and the control signal K at its control terminal S2 uses the control signal of the second input switch S2. The capacitor C1 is a charge-discharge capacitor. During the charging of the inductor current I of the first inductor L, that is, in the first time period t1 and the second time period t2, the control signal K L is at a low level, the NMOS transistor M4 is in an off state, and the current mirror structure copies the fixed current of the voltage-to-current branch to charge the capacitor C1. The voltage generated on the capacitor C1 is the compensation voltage V S2 , and the compensation voltage V slop rises at a fixed slope; during the discharging of the inductor current I of the first inductor L, that is, in the third time period t3 and the fourth time period t4, the control signal K slop is at a high level, the NMOS transistor M4 is in a closed state, and the capacitor C1 discharges through the NMOS transistor M4, and the compensation voltage V L drops to 0. S2 Since in a single-inductor dual-output switching power supply converter, the inductor current I slop has two different decreasing slopes during the discharging period, the ramp compensation formed by the compensation voltage V L cannot accurately compensate the inductor current I slop during the discharging period, the ramp compensation formed by the compensation voltage V L formed cannot accurately compensate the inductor current I 10Compensation is performed during the decline. Therefore, to solve the above problems existing in the prior art, the present invention provides a dynamic ramp compensation circuit for a single-inductor dual-output switching power supply converter, which adopts a segmented dynamic compensation method to dynamically determine and adjust the compensation slope, so as to ensure that the single-inductor dual-output switching power supply converter can achieve accurate and effective slope compensation.

[0040] As Figure 4 shown, a dynamic ramp compensation circuit for a single-inductor dual-output switching power supply converter provided by an embodiment of the present invention includes a first operational amplifier A2, a first NMOS transistor M5, a second NMOS transistor M9, a third NMOS transistor M 10 , a fourth NMOS transistor M 11 and a first PMOS transistor M6, a second PMOS transistor M7, a third PMOS transistor M8, as well as a third resistor R2, a third capacitor C2, and a first AND gate A nd1 , a second AND gate A nd2 . Among them, the first operational amplifier A2, the first NMOS transistor M5, and the third resistor R2 form a voltage-to-current branch for converting the first output voltage V OUTA of the single-inductor dual-output switching power supply converter into a first branch current I M6 ; the first PMOS transistor M6, the second PMOS transistor M7, and the third PMOS transistor M8 form a current mirror structure for proportionally copying the first branch current I M6 into a second branch current I M7 and a third branch current I M8 ; the current ratio of the current mirror is 1:1:K, where the value of K is the ratio of the second output voltage V OUTB to the first output voltage V OUTA of the single-inductor dual-output switching power supply converter, that is, K = V OUTB / V OUTA .

[0041] During each period of the inductor current I L of the single-inductor dual-output switching power supply converter, the second branch current I M7 and the third branch current I M8 charge the third capacitor C2 in stages in sequence, so that the compensation voltage V slop has a first growth slope and a second growth slope during the rising stage of the inductor current I L , realizing staged dynamic ramp compensation for the single-inductor dual-output switching power supply converter.

[0042] In the dynamic ramp compensation circuit, the non-inverting input terminal of the first operational amplifier A2 is connected to the first output terminal of the switching power supply converter, the output terminal of the first operational amplifier A2 is connected to the gate of the first NMOS transistor M5, the source of the first NMOS transistor M5 is connected to the third resistor R2 and the inverting input terminal of the first operational amplifier A2, and the other end of the third resistor R2 is connected to the ground potential terminal GND; the drain of the first NMOS transistor M5 is connected to the drain of the first PMOS transistor M6 and the gates of the first PMOS transistor M6, the second PMOS transistor M7, and the third PMOS transistor M8, and the sources of the first PMOS transistor M6, the second PMOS transistor M7, and the third PMOS transistor M8 are all connected to the power supply terminal VDD; the drain of the second PMOS transistor M7 is connected to the drain of the second NMOS transistor M9, the drain of the third PMOS transistor M8 is connected to the drain of the third NMOS transistor M 10 The sources of the second NMOS transistor M9 and the third NMOS transistor M 10 are connected to each other and are connected to the third capacitor C2 and the drain of the fourth NMOS transistor M 11 on the one hand, and are connected to the compensation voltage V slop output terminal on the other hand. The other end of the third capacitor C2 and the source of the fourth NMOS transistor M 11 are both connected to the ground potential terminal GND; the gate of the fourth NMOS transistor M 11 is connected to the input terminal of the second control signal K S2 ; the gate of the second NMOS transistor M9 is connected to the output terminal of the first AND gate A nd1 , the first input terminal of the first AND gate A nd1 is connected to the input terminal of the first control signal K S1 , and the second input terminal of the first AND gate A nd1 is connected to the input terminal of the third control signal K S3 ; the gate of the third NMOS transistor M 10 is connected to the output terminal of the second AND gate A nd2 , the first input terminal of the second AND gate A nd2 is connected to the input terminal of the first control signal K S1 , and the second input terminal of the second AND gate A nd2 is connected to the input terminal of the fourth control signal K S4 . Among them, the first control signal K S1 , the second control signal K S2 , the third control signal K S3 , and the fourth control signal K S4 are the control signals of the first output switch S1, the second input switch S2, the first output switch S3, and the second output switch S4 of the single-inductor dual-output switching power supply converter respectively.

[0043] In the initial state of the dynamic ramp compensation circuit, the output compensation voltage Vslop is 0. When the single-inductor dual-output switching power supply converter starts to work, the first output terminal and the second output terminal respectively output the first output voltage V OUTA and the second output voltage V OUTB . In the dynamic ramp compensation circuit, the first output voltage V OUTA generates a first branch current I M6 through the voltage-to-current branch. The magnitude of the first branch current I M6 is:

[0044]

[0045] where R2 is the resistance value of the third resistor R2.

[0046] The branch current I M6 is mirror-copied into a second branch current I M7 and a third branch current I M8 respectively through a current mirror structure composed of the first PMOS transistor M6, the second PMOS transistor M7, and the third PMOS transistor M8.

[0047] During the first time period t1 of a cycle of the inductor current I L , since the first control signal K S1 is at a high level, the second control signal K S2 is at a low level, the third control signal K S3 is at a high level, and the fourth control signal K S4 is at a low level, after the logical operations of the first AND gate A nd1 and the second AND gate A nd2 , the output signals respectively control the second NMOS transistor M9 to be in an on state, the third NMOS transistor M 10 to be in an off state, and the fourth NMOS transistor M 11 to be in an off state. Therefore, the second branch current I M7 charges the third capacitor C2 through the second NMOS transistor M9. The magnitude of the second branch current I M7 is:

[0048]

[0049] The terminal voltage of the third capacitor C2 gradually increases, that is, the compensation voltage V slop output by the dynamic ramp compensation circuit gradually increases. At this time, the first growth slope m1 of the rising compensation voltage V slop is:

[0050]

[0051] where C2 is the capacitance value of the third capacitor C2.

[0052] During the second time period t2 of a cycle of the inductor current I L Since the first control signal K S1 is at a high level, the second control signal K S2 is at a low level, the third control signal K S3 is at a low level, and the fourth control signal K S4 is at a high level. After the logical operations of the first AND gate A nd1 and the second AND gate A nd2 , the output signals respectively control the second NMOS transistor M9 to be in a cut-off state, the third NMOS transistor M 10 to be in a conducting state, and the fourth NMOS transistor M 11 to be in a cut-off state. Therefore, the current I M8 in the third branch charges the third capacitor C2 through the third NMOS transistor M 10 . The magnitude of the current I M8 in the third branch is:

[0053]

[0054] where K is the current ratio of the current mirror, and the value is K = V OUTB / V OUTA .

[0055] The terminal voltage of the third capacitor C2 continues to increase, that is, the compensation voltage V slop output by the dynamic ramp compensation circuit continues to increase. At this time, the second growth slope m2 of the rising compensation voltage V slop is:

[0056]

[0057] During the third time period t3 of a cycle of the inductor current I L Since the first control signal K S1 is at a low level, the second control signal K S2 is at a high level, the third control signal K S3 is at a low level, and the fourth control signal K S4 is at a high level; during the fourth time period t4 of a cycle of the inductor current I L Since the first control signal K S1 is at a low level, the second control signal K S2 is at a high level, the third control signal K S3 is at a high level, and the fourth control signal K S4 is at a low level; during the falling stage of the inductor current I L , that is, during the time periods t3 and t4, after the logical operations of the first AND gate A nd1 and the second AND gate A nd2After the logic operation, the output signals respectively control the second NMOS transistor M9 to be in the cut-off state and the third NMOS transistor M 10 to be in the cut-off state, and the fourth NMOS transistor M 11 to be in the on state. Therefore, the third capacitor C2 discharges rapidly through the fourth NMOS transistor M 11 . The terminal voltage of the third capacitor C2 rapidly drops to 0, that is, the compensation voltage V slop output by the dynamic ramp compensation circuit rapidly drops to 0.

[0058] The compensation voltage V slop output by the dynamic ramp compensation circuit L repeats the above change process in each period of the inductor current I Figure 5 as shown. This makes the compensation voltage V slop have two different growth rates, namely the first growth slope m1 and the second growth slope m2, during the rising stage of each period of the inductor current I L , and precisely match the inductor current I L , so as to realize providing ramp compensation for the single-inductor dual-output switching power supply converter in a phased dynamic manner.

[0059] The above has described in detail the structure and working principle of the dynamic ramp compensation circuit provided by the present invention for a single-inductor dual-output switching power supply converter. Based on the above dynamic ramp compensation circuit, an embodiment of the present invention further provides a single-inductor dual-output switching power supply converter with a dynamic ramp compensation circuit, as shown in Figure 6 and Figure 7 . This single-inductor dual-output switching power supply converter includes a switching power supply main circuit 1, a voltage sampling circuit 2, a peak current mode control circuit 3, a control logic and drive circuit, an inductor current detection circuit, and a dynamic ramp compensation circuit. Among them, when the duty cycle of the control signal exceeds 50%, the compensation voltage V slop output by the dynamic ramp compensation circuit L can provide ramp compensation for the single-inductor dual-output switching power supply converter in a phased dynamic manner during the rising stage of each period of the inductor current I

[0060] . For the specific circuit structure and working principle of the dynamic ramp compensation circuit, they will not be elaborated here. slop can provide ramp compensation for the single-inductor dual-output switching power supply converter in a phased dynamic manner during the rising stage of each period of the inductor current I LDuring the rising stage of each cycle, ramp compensation is dynamically provided in stages for the single-inductor dual-output switching power supply converter to meet the power supply requirements and operating stability of electronic devices.

[0061] In an embodiment of the present invention, as Figure 8 shown, the electronic device at least includes a processor, a memory, and a power supply component, and may further include a communication component, a sensor component, a multimedia component, and an input / output interface according to actual needs. Among them, the memory, the communication component, the sensor component, the power supply component, the multimedia component, and the input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc. The processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, multimedia components, etc. can all be implemented by general components and will not be specifically described here.

[0062] In summary, compared with the prior art, the dynamic ramp compensation circuit for the single-inductor dual-output switching power supply converter provided by the present invention effectively solves the stability problem of the single-inductor dual-output switching power supply converter when the duty cycle exceeds 50% through the staged dynamic ramp compensation technology, realizes the precise compensation of the two output voltages, avoids the generation of subharmonic oscillations, improves the accuracy of ramp compensation and the stability of power supply. At the same time, the circuit is ingeniously designed, has a low cost, and excellent performance, and can be widely applied to various electronic devices that require precise power management.

[0063] It should be noted that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0064] The above has described in detail the dynamic ramp compensation circuit and the electronic device for the single-inductor dual-output switching power supply converter provided by the present invention. For those of ordinary skill in the art, any obvious changes made without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A dynamic slope compensation circuit for a single-inductor dual-output switching power converter, characterized in that It includes a first operational amplifier, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a third resistor, a third capacitor, a first AND gate, and a second AND gate; wherein, The first operational amplifier, the first NMOS transistor and the third resistor form a voltage-to-current branch, which is used to convert the first output voltage of the single-inductor dual-output switching power converter into a first branch current; The first PMOS tube, the second PMOS tube and the third PMOS tube form a current mirror structure, which is used to copy the first branch current into the second branch current and the third branch current in proportion; In each cycle of the inductor current of the single-inductor dual-output switching power supply converter, the second branch current and the third branch current charge the third capacitor in stages in sequence, so that the compensation voltage output by the dynamic slope compensation circuit has a first growth slope and a second growth slope respectively in the rising stage of the inductor current, thereby realizing the phased dynamic slope compensation for the single-inductor dual-output switching power supply.

2. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: The current ratio of the current mirror structure composed of the first PMOS tube, the second PMOS tube and the third PMOS tube is 1:1:K, wherein the value of K is the ratio of the second output voltage to the first output voltage of the single-inductor dual-output switching power supply converter.

3. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: The non-inverting input terminal of the first operational amplifier is connected to the first output terminal of the single-inductor dual-output switching power supply converter, the output terminal of the first operational amplifier is connected to the gate of the first NMOS tube, the source of the first NMOS tube is connected to the third resistor and the inverting input terminal of the first operational amplifier, and the other end of the third resistor is connected to the ground potential terminal; the drain of the first NMOS tube is connected to the drain of the first PMOS tube.

4. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: The drain of the first PMOS tube is connected to the gates of the first PMOS tube, the second PMOS tube and the third PMOS tube, and the sources of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected to the power supply electrode; the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the drain of the third PMOS tube is connected to the drain of the third NMOS, the sources of the second NMOS tube and the third NMOS tube are connected to each other and then connected to the drains of the third capacitor and the fourth NMOS tube on the one hand, and to the compensation voltage output end on the other hand; the other end of the third capacitor and the source of the fourth NMOS tube are both connected to the ground potential end.

5. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: The gate of the fourth NMOS tube is connected to the input end of the second control signal; the gate of the second NMOS tube is connected to the output end of the first AND gate, the first input end of the first AND gate is connected to the input end of the first control signal, and the second input end of the first AND gate is connected to the input end of the third control signal; the gate of the third NMOS tube is connected to the output end of the second AND gate, the first input end of the second AND gate is connected to the input end of the first control signal, and the second input end of the second AND gate is connected to the input end of the fourth control signal; wherein, the first control signal, the second control signal, the third control signal, and the fourth control signal are control signals of the first output switch, the second input switch, the first output switch, and the second output switch of the single-inductor dual-output switching power converter, respectively.

6. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: The first branch current, the second branch current, and the third branch current respectively satisfy the following formulas: Among them, I M6 is the first branch current, I M7 is the second branch current, I M8 is the third branch current; V OUTA is the first output voltage of the single-inductor dual-output switching power converter, V OUTB is the second output voltage of the single-inductor dual-output switching power supply converter; R2 is the resistance value of the third resistor.

7. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: The first increasing slope and the second increasing slope of the compensation voltage respectively satisfy the following formulas: Wherein, m1 is the first growth slope, m2 is the second growth slope; V OUTA is the first output voltage of the single-inductor dual-output switching power converter, V OUTB is the second output voltage of the single-inductor dual-output switching power supply converter; R2 is the resistance value of the third resistor, and C2 is the capacitance value of the third capacitor.

8. The dynamic slope compensation circuit for a single-inductor dual-output switching power converter according to claim 1, wherein: In the decreasing phase of the inductor current, the second NMOS tube is in the off state, the third NMOS tube is in the off state, and the fourth NMOS tube is in the on state, so that the third capacitor is quickly discharged through the fourth NMOS tube, and the compensation voltage output by the dynamic slope compensation circuit quickly drops to 0.

9. A single-inductor dual-output switching power converter, characterized in that The invention comprises the dynamic slope compensation circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that It includes the single-inductor dual-output switching power converter described in claim 9.

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