Method for generating pwm signal, microcontroller and pwm generation circuit

Abstract

The embodiment of the present application discloses a PWM signal generation method. The generation method comprises the following steps: determining a set delay time and a reset delay time of an nth PWM delay signal, determining a first comparison result of the set delay time and a preset clock cycle and a second comparison result of the reset delay time and the preset clock cycle, assigning a first delay time to a delay module and a first comparison threshold to a first comparator according to the first comparison result, and assigning a second delay time to the delay module and a second comparison threshold to a second comparator according to the second comparison result. The embodiment of the present application does not need to depend on a high-precision clock chip, can realize the delay processing of the PWM signal on a low-cost hardware circuit through fine adjustment, can delay not only the duty cycle but also the signal cycle, the time resolution involved in the delay is relatively high, and the more accurate and stable PWM signal can be output.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the electronic technical field, and particularly relate to a PWM signal generation method, a microcontroller and a PWM generation circuit. BACKGROUND

[0002] With the rapid development of electronic technology, digital PWM (Pulse Width Modulation) technology has been widely used in power electronics, motor control, industrial automation and other fields. When the engineering needs the digital pulse width modulation signal circuit to output various PWM signals, due to the problem of insufficient precision of the traditional digital pulse width modulation signal circuit, it cannot accurately output various PWM signals. The related technology can accurately output various PWM signals through the programming mode of the microprocessor. However, this approach needs to rely on a very high clock frequency output by the chip, and the cost of such a chip is relatively high, thereby increasing the production cost of the digital pulse width modulation signal circuit. SUMMARY

[0003] An object of embodiments of the present application is to provide a PWM signal generation method, a microcontroller and a PWM generation circuit, so as to solve the technical problem that the related art needs to rely on a high clock frequency to output a high-precision PWM signal.

[0004] In a first aspect, an embodiment of the present application provides a PWM signal generation method, the generation method comprising: determining a set delay time and a reset delay time of an nth PWM delay signal, the set delay time being a time of delaying setting to output a high level of the nth PWM delay signal, the reset delay time being a time of delaying resetting to output a low level of the nth PWM delay signal, n being a positive integer; determining a first comparison result of the set delay time and a preset clock period, and a second comparison result of the reset delay time and the preset clock period; assigning a first delay time to a delay module and a first comparison threshold to a first comparator according to the first comparison result, so that when a count value output by a counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level, the set high level is transmitted to a set end of a latch after being processed by the delay module for the first delay time, so that the latch outputs an nth high level, and a total delay time of the delay module is less than or equal to the preset clock period; assigning a second delay time to the delay module and a second comparison threshold to a second comparator according to the second comparison result, so that when a count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level, the reset high level is transmitted to a reset end of the latch after being processed by the delay module for the second delay time, so that the latch outputs an nth low level, and the nth high level and the nth low level form the nth PWM delay signal.

[0005] The PWM generation circuit provided by the embodiment of the present application not only can be compatible with coarse adjustment, but also can be compatible with fine adjustment, and does not need to rely on a high-precision clock chip, and can realize delay processing of a PWM signal through fine adjustment on a low-cost hardware circuit, wherein not only the duty cycle can be delayed, but also the signal period can be delayed, the time resolution involved in the delay is relatively high, and this is beneficial to output a more accurate and stable PWM signal.

[0006] Optionally, the determination of the set delay time of the nth PWM delay signal comprises: determining a high level delay time, the high level delay time being a time difference between a high level of a PWM delay signal and a high level of a PWM original signal, multiplying n by the high level delay time to obtain the set delay time of the nth PWM signal.

[0007] Optionally, the determination of the reset delay time of the nth PWM signal comprises: determining a period delay time, the period delay time being a difference between a signal period of a PWM delay signal and a signal period of a PWM original signal, and adding the set delay time and the period delay time to obtain the reset delay time of the nth PWM signal.

[0008] Optionally, the assigning the first delay time to the delay module according to the first comparison result comprises: in response to the first comparison result indicating that the set delay time is greater than or equal to a preset clock period, dividing the set delay time by the preset clock period to obtain a first remainder, determining the first remainder as the first delay time; and in response to the first comparison result indicating that the set delay time is less than the preset clock period, determining the set delay time as the first delay time.

[0009] Optionally, the delay module comprises a first delay unit, the first delay unit comprises a first selector and a plurality of first delayers connected in sequence, and total delay time of all the first delayers is less than or equal to a preset clock period; the generating method further comprises: determining a first delay order based on the first delay time and delay time of the first delayers, and controlling the first selector to select a number of first delayers corresponding to the first delay order, so that the number of first delayers corresponding to the first delay order processes the set high level for the first delay time.

[0010] Optionally, the assigning the first comparison threshold to the first comparator according to the first comparison result comprises: obtaining a first local threshold of the first comparator, in response to the first comparison result indicating that the set delay time is greater than or equal to a preset clock period, accumulating a first specified value on the basis of the first local threshold to obtain a first comparison threshold, the first specified value being a quotient obtained by dividing the set delay time by the preset clock period, and in response to the first comparison result indicating that the set delay time is less than the preset clock period, determining the first local threshold as the first comparison threshold.

[0011] Optionally, the assigning the second delay time to the delay module according to the second comparison result comprises: in response to the second comparison result indicating that the reset delay time is greater than or equal to a preset clock period, dividing the reset delay time by the preset clock period to obtain a second remainder, determining the second remainder as the second delay time; and in response to the second comparison result indicating that the reset delay time is less than the preset clock period, determining the reset delay time as the second delay time.

[0012] Optionally, the delay module includes a second delay unit, the second delay unit includes a second selector and a plurality of second delay units connected in series, and a total delay time of all the second delay units is less than or equal to a preset clock cycle, and the generation method further includes: determining a second delay order based on the second remainder and a delay time of the second delay unit, and controlling the second selector to select a number of second delay units corresponding to the second delay order, so that the number of second delay units corresponding to the second delay order performs a second delay time processing on the reset high level.

[0013] Optionally, the assigning the second comparison threshold to the second comparator according to the second comparison result includes: obtaining a second local threshold of the second comparator, in response to the second comparison result indicating that the reset delay time is greater than or equal to a preset clock cycle, accumulating a second specified value on the basis of the second local threshold to obtain the second comparison threshold, the second specified value being a quotient obtained by dividing the reset delay time by the preset clock cycle, and in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determining the second local threshold as the second comparison threshold.

[0014] Optionally, the generation method further includes: determining a current counting period of the counter according to the reset delay time and an original counting period of the counter, and performing a clear operation on the counter in response to a counting value of the counter being equal to the current counting period.

[0015] In a second aspect, an embodiment of the present application provides a microcontroller, including a memory and a processor, the memory being connected to the processor, and the processor being configured to execute one or more computer programs stored in the memory, and the processor, when executing the one or more computer programs, causes the microcontroller to implement the PWM signal generation method described above.

[0016] In a third aspect, an embodiment of the present application provides a PWM generation circuit, including a counter, a first comparator, a second comparator, a first delay unit, a second delay unit, a latch, and the microcontroller described above, the microcontroller being communicatively connected to the counter, the first comparator, the second comparator, the first delay unit, and the second delay unit, respectively, the counter being communicatively connected to the first comparator and the second comparator, respectively, the first comparator being communicatively connected to the first delay unit, the second comparator being communicatively connected to the second delay unit, and a set end of the latch being communicatively connected to an output end of the first delay unit, and a reset end of the latch being communicatively connected to an output end of the second delay unit.

[0017] In a fourth aspect, an embodiment of the present application provides a digital pulse width modulation signal circuit, comprising the PWM generation circuit.

[0018] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising the PWM generation circuit.

[0019] In a sixth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, the computer program comprising program instructions, the program instructions causing a processor to execute the PWM signal generation method when executed by the processor.

[0020] The PWM generation circuit provided by the embodiment of the present application can not only be compatible with coarse adjustment, but also be compatible with fine adjustment, and does not need to rely on a high-precision clock chip, and can realize delay processing of a PWM signal on a low-cost hardware circuit through fine adjustment, wherein not only the duty cycle can be delayed, but also the signal period can be delayed, the time resolution involved in the delay is relatively high, which is beneficial to output a more accurate and stable PWM signal. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0022] Figure 1 A circuit structure schematic diagram of a PWM generation circuit provided by an embodiment of the present application;

[0023] Figure 2 A circuit structure schematic diagram of a PWM generation circuit provided by another embodiment of the present application;

[0024] Figure 3 A circuit structure schematic diagram of a PWM generation circuit provided by yet another embodiment of the present application;

[0025] Figure 4 A timing diagram of a PWM original signal and a PWM delay signal provided by an embodiment of the present application;

[0026] Figure 5 A flowchart of a PWM signal generation method provided by an embodiment of the present application;

[0027] Figure 6 A structure schematic diagram of a PWM signal generation apparatus provided by an embodiment of the present application;

[0028] Figure 7 A structure schematic diagram of a microcontroller provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0030] It should be noted that the various features of the embodiments of the present application can be combined with each other without conflict, and all fall within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Furthermore, the "first", "second", "third" and the like used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0031] When the related art needs a PWM generation circuit to output a PWM signal with fixed signal period and duty cycle, the circuit structure of the PWM generation circuit usually includes a cycle counter and a comparator. When the count value output by the cycle counter to the comparator is less than the comparison threshold of the comparator, the comparator outputs a low level. When the count value output by the cycle counter to the comparator is greater than or equal to the comparison threshold of the comparator, the comparator outputs a high level. When the count value of the cycle counter reaches the preset count threshold, the cycle counter is automatically cleared and re-counted.

[0032] The architecture of such a PWM generation circuit is not only simple, but also stable and reliable in operation. However, the time resolution that can be achieved by this approach is limited by the clock period of the counter. If it is desired to finely control the signal period and duty cycle of the PWM to an accuracy of 1 nanosecond (ns), the corresponding clock frequency needs to be as high as 1 gigahertz (GHz). Further, if a picosecond (ps) level of accuracy is pursued, a huge cost investment will be incurred, which is unacceptable from the perspective of chip mass production.

[0033] In the following, an embodiment of the present application provides a PWM generation circuit, which can be applied to a digital pulse width modulation signal circuit or an electronic device. For example, the electronic device is a switching power supply device, and the digital pulse width modulation signal circuit containing the PWM generation circuit can provide a PWM signal for the switching power supply device.

[0034] Please refer toFigure 1 The PWM generation circuit 100 comprises a counter 11, a first comparator 12, a second comparator 13, a delay module 14, a latch 15 and a microcontroller 16.

[0035] The counter 11 is in communication connection with the microcontroller 16, wherein the counter 11 is configured with an original counting period, and the microcontroller 16 sends a clock signal to the counter 11, and the counter 11 counts based on the clock signal to output a counting value, and the preset clock period of the clock signal is defined as c in the present disclosure.

[0036] The first comparator 12 is in communication connection with the counter 11 and the microcontroller 16 respectively, specifically, the first comparator 12 comprises two input ends, one of which is in communication connection with the output end of the counter 11, and the other of which is in communication connection with the microcontroller 16, and the microcontroller 16 can configure a first comparison threshold (for example, the expression of the first comparison threshold is "=0") for the other input end of the first comparator 12. For example, the first comparison threshold is 0 or 1 or 2, etc. When the counter 11 starts to receive the clock signal for counting, if the first comparison threshold is 0, when the counter 11 outputs the counting value i=0, the first comparator 12 outputs high level, and when the counter 11 outputs the counting value i≠0, the first comparator 12 outputs low level. For another example, if the first comparison threshold is 1, when the counter 11 outputs the counting value i=0, the first comparator 12 outputs low level. When the counter 11 outputs the counting value i=1, the first comparator 12 outputs high level.

[0037] The second comparator 13 is in communication connection with the counter 11 and the microcontroller 16 respectively, specifically, the second comparator 13 comprises two input ends, one of which is in communication connection with the output end of the counter 11, and the other of which is in communication connection with the microcontroller 16, and the microcontroller 16 can configure a second comparison threshold (for example, the expression of the second comparison threshold is "=NUM") for the other input end of the second comparator 13. The second comparison threshold is greater than the first comparison threshold, and exemplarily, the second comparison threshold is 5 or 6 or 7 or 8, etc.

[0038] For example, if the second comparison threshold is 8, when the counter 11 outputs the counting value i=8, the second comparator 13 outputs high level, and when the counter 11 outputs the counting value i≠8, the second comparator 13 outputs low level. For another example, if the second comparison threshold is 9, when the counter 11 outputs the counting value i=8, the second comparator 13 outputs low level. When the counter 11 outputs the counting value i=9, the first comparator 12 outputs high level.

[0039] The delay module 14 is connected to the first comparator 12 and the second comparator 13 respectively and is also controlled by the microcontroller 16, and is used to delay the high level outputted by the first comparator 12 and the second comparator 13 respectively. The delay module 14 provides a plurality of delay stages, and the higher the delay stage is, the longer the delay time is, and the lower the delay stage is, the shorter the delay time is.

[0040] The microcontroller 16 can control the delay module 14 to select a corresponding delay stage to delay the high level outputted by the first comparator 12 and the second comparator 13 respectively.

[0041] The total delay time of the delay module 14 is less than or equal to a preset clock period, for example, the total delay time of the delay module 14 is less than or equal to a clock period of the clock signal. , is the total stage number of the delay module 14, is the delay time of each delay stage, is the total delay time. The delay time of the high level of the PWN signal is , e is a positive integer, g is less than c, and the expression of g can be: , h is less than k. Embodiments of the present application allocate the first delay time to the delay module 14 according to the time g, and select the delay stage h.

[0042] In the case that the delay time of the high level of the PWN signal is not equal to an integral multiple of the clock frequency, or in the case that the delay time of the signal period of the PWN signal is not equal to an integral multiple of the clock frequency, embodiments of the present application can utilize the feature that the total delay time of the delay module 14 is less than or equal to a preset clock period to meet the demand of outputting more accurate high level time or more accurate signal period.

[0043] In some embodiments, referring to Figure 2 , the delay module 14 includes a first delay unit 141 and a second delay unit 142.

[0044] The first delay unit 141 is connected to the first comparator 12 and the microcontroller 16 respectively, and the output end of the first delay unit 141 is connected to the set end S of the latch 15. The microcontroller 16 configures the first delay unit 141 with the first delay time. When the count value outputted by the counter 11 is equal to the first comparison threshold of the first comparator 12, the first comparator 12 outputs a high level to the first delay unit 141, the first delay unit 141 delays the high level by the first delay time, and finally outputs the high level to the set end S of the latch 15.

[0045] The second delay unit 142 is connected with the second comparator 13 and the microcontroller 16 respectively, and the output of the second delay unit 142 is connected with the reset end R of the latch 15. The microcontroller 16 configures the second delay time for the second delay unit 142. When the count value output by the counter 11 is equal to the second comparison threshold of the second comparator 13, the second comparator 13 outputs a high level to the second delay unit 142, and the second delay unit 142 delays the high level for the second delay time and then outputs to the reset end R of the latch 15.

[0046] In some embodiments, referring to Figure 3 , the first delay unit 141 includes a plurality of first delay devices 1411 and a first selector 1412. The plurality of first delay devices 1411 are connected in series, and the first selector 1412 is a multiple-to-one selector, for example, a 64-to-1 selector. The first selector 1412 includes a plurality of channel input ends and an output end, one channel input end is connected with the output end of one first delay device 1411, and the output end of the first selector 1412 is connected with the set end S of the latch 15.

[0047] The microcontroller 16 selects a corresponding number of first delay devices 1411 according to the delay order to delay the high level output by the first comparator 12, wherein the delay time of each first delay device is the same, the sum of the delay times of the plurality of first delay devices 1411 is the total delay time, the total delay time is less than the preset clock period, and the delay order multiplied by the delay time of the first delay device 1411 is equal to the first delay time.

[0048] In some embodiments, referring to Figure 3 , the second delay unit 142 includes a plurality of second delay devices 1421 and a second selector 1422. The plurality of second delay devices 1421 are connected in series, and the second selector 1422 is a multiple-to-one selector, for example, a 64-to-1 selector. The second selector 1422 includes a plurality of channel input ends and an output end, one channel input end is connected with the output end of one second delay device 1421, and the output end of the second selector 1422 is connected with the reset end R of the latch 15.

[0049] The microcontroller 16 selects a corresponding number of second delay devices 1421 according to the delay order to delay the high level output by the first comparator 12, wherein the delay time of each second delay device 1421 is the same, the sum of the delay times of the plurality of second delay devices 1421 is the total delay time, the total delay time is less than the preset clock period, and the delay order multiplied by the delay time of the first delay device 1411 is equal to the first delay time.

[0050] The latch 15 may be any type of latch. For example, the latch 15 includes an SR latch, a D flip-flop, a JK latch, and the like.

[0051] The microcontroller 16 can control the above components to work together to generate a PWM signal.

[0052] In order to elaborate on the working principle of the PWM generation circuit provided by the embodiment of the present application, the embodiment of the present application is combined with the attached Figure 4 A detailed explanation is given for this. It is understandable that the "delay" described in the embodiments of the present application is based on the situation of "no delay", and the situation of "no delay" is the situation where the first delay unit and the second delay unit do not participate in the generation of the PWM signal. This article defines "the situation where the first delay unit and the second delay unit do not participate in the generation of the PWM signal" as a coarse adjustment situation. The "delay" situation is the situation where the first delay unit and the second delay unit participate in the generation of the PWM signal. This article defines "the situation where the first delay unit and the second delay unit participate in the generation of the PWM signal" as a fine adjustment situation. First, the first comparison threshold of the first comparator is "=0", and the second comparison threshold of the second comparator is "=NUM".

[0053] ① The embodiment of this application is combined with the attached Figure 4 Explanation for the coarse adjustment situation:

[0054] like Figure 4 As shown, the counter is triggered by the rising edge of the third clock signal and begins counting. When the counter reaches 0, the first comparator outputs a high level. The microcontroller 16 does not control the first selector 1412 to select any of the first delay units 1411. Instead, it directly controls the first selector 1412 to output the high level output by the first comparator. This high level is considered the original set signal S(n). The original set signal S(n) is applied to the set terminal S of the latch 15, and the latch 15 outputs a high level and latches the high level.

[0055] When the counter reaches the count value NUM at the falling edge of the fourth clock signal, the second comparator outputs a high level. The microcontroller 16 does not control the second selector 1422 to select any of the second delay units 1421. Instead, the microcontroller 16 directly controls the second selector 1422 to output the high level output by the second comparator. The high level at this time is regarded as the original reset signal R(n). The original reset signal R(n) is applied to the reset terminal R of the latch 15, and the latch 15 outputs a low level and latches the low level.

[0056] When the count value of the counter reaches the preset count threshold at the sixth clock signal, the counter starts to be reset. At this point, the latch 15 is able to output the complete original PWM signal origin_pwm.

[0057] When the rising edge of the seventh clock signal arrives, the counter starts counting and outputs the count value 0, and outputs the next PWM original signal origin_pwm according to the above process.

[0058] ② The embodiment of this application is combined with the attached Figure 4 Explanation of the fine-tuning situation:

[0059] First, the set delay time is Nα, and the reset delay time is Nα+β, where α is the time difference between the high levels of two adjacent PWM signals. Figure 4 In the equation, α is 0.5c (i.e., half of the clock period). β is the difference between the signal periods of two adjacent PWM signals. Figure 4 In the example, β is 0.5c (i.e., half the clock period).

[0060] like Figure 4 As shown, the counter is triggered by the rising edge of the third clock signal and begins counting. When the counter reaches 0, the first comparator outputs a high level. The microcontroller 16 then controls the first delay unit 141 to perform a first delay time of 1*α. Specifically, it controls the first selector 1412 to select a corresponding number of first delay units 1411 to perform the first delay time. After the first delay time, the high level output by the first comparator is output to the set terminal S of the latch 15. This high level is then considered the delayed set signal S_P(n). The delayed set signal S_P(n) is applied to the set terminal S of the latch 15, causing the latch 15 to output a high level and latch the high level.

[0061] When the counter's count value is NUM at the falling edge of the fourth clock signal, the second comparator outputs a high level. The microcontroller 16 needs to control the second delay unit 142 to perform a second delay time of 1*α+β (i.e., 1 c), that is, control the first selector 1412 to select the corresponding number of second delay units 1411 to perform the second delay time processing. Alternatively, since the second delay time is a complete clock cycle, the microcontroller 16 does not need to control the second delay unit 142 to work, but instead increases the second comparison threshold of the second comparator by a natural number 1, which can also achieve equivalent delay. After the high level output of the second comparator is delayed, it is output to the reset terminal R of the latch 15. The high level at this time is regarded as the delayed reset signal R_P(n). The delayed reset signal R_P(n) is applied to the reset terminal R of the latch 15, and the latch 15 outputs a low level and latches the low level.

[0062] When the count value of the counter reaches the preset count threshold at the seventh clock signal, the counter starts to be reset. At this point, the latch 15 is able to output the complete PWM delay signal delay_pwm.

[0063] When the rising edge of the 8th clock signal comes, the counter starts counting, outputs the count value 0, and outputs the next PWM delay signal delay_pwm according to the above flow.

[0064] Further, by Figure 4 It can be seen that the first original set signal S(n) is different from the first delay set signal S_P(n) by 1 alpha, the second original set signal S(n) is different from the second delay set signal S_P(n) by 2 alpha, the third original set signal S(n) is different from the third delay set signal S_P(n) by 3 alpha, and so on.

[0065] Similarly, the first original reset signal R(n) is different from the first delay reset signal R_P(n) by (alpha+beta), the second original reset signal R(n) is different from the second delay reset signal R_P(n) by (2*alpha+beta), the third original reset signal R(n) is different from the third delay reset signal R_P(n) by (3*alpha+beta), and so on.

[0066] The PWM generation circuit provided by the embodiment of the present application not only can be compatible with the coarse adjustment situation, but also can be compatible with the fine adjustment situation, and does not need to rely on a high-precision clock chip, and can realize the delay processing of the PWM signal on a low-cost hardware circuit through fine adjustment, wherein not only the duty cycle can be delayed, but also the signal period can be delayed, the time resolution involved in the delay is relatively high, which is beneficial to output a more accurate and stable PWM signal.

[0067] In the following, the embodiment of the present application provides a PWM signal generation method, wherein the PWM signal can be the PWM original signal origin_pwm described in the above embodiment when a condition is met, and can be the PWM delay signal delay_pwm described in the above embodiment when another condition is met.

[0068] Please refer to Figure 5 The PWM signal generation method comprises steps S51 to S54.

[0069] The embodiment of the present application executes step S51 to determine the set delay time and the reset delay time of the nth PWM signal.

[0070] The set delay time is the time of delaying the set to output the high level of the nth PWM signal, and n is a positive integer. For example Figure 4As shown, for the first PWM delay signal delay_pwm, relative to the first PWM original signal origin_pwm, the embodiment of the present application controls the first selector to select a corresponding number of the first delay unit to delay the high level output by the first comparator for a delay time (0.5c), and the latch can output the high level of the first PWM delay signal delay_pwm, thus the delay time 0.5c is the set delay time. For the second PWM delay signal delay_pwm, relative to the second PWM original signal origin_pwm, the embodiment of the present application controls the first selector to select a corresponding number of the first delay unit to delay the high level output by the first comparator for a delay time (a preset clock cycle c), or to increase the second comparison threshold of the second comparator by 1 to equivalently realize the delay, and the latch can output the high level of the second PWM delay signal delay_pwm, thus the delay time c is the set delay time.

[0071] The set delay time of the nth PWM signal includes the following steps: determining a high level delay time, the high level delay time being a time difference between the high level of the PWM delay signal and the high level of the PWM original signal, multiplying the high level delay time by n to obtain the set delay time of the nth PWM signal. For example, the time difference between the high level of the PWM delay signal and the high level of the PWM original signal is a, the high level delay time is a, and the set delay time is n a.

[0072] For example, for the first PWM delay signal, the set delay time P of the first PWM delay signal is 1 a. For example, for the second PWM delay signal, the set delay time P of the second PWM delay signal is 2 a. And so on.

[0073] The reset delay time is the time of delaying the reset to output the low level of the nth PWM signal. The reset delay time of the nth PWM signal includes the following steps: determining a period delay time, the period delay time being a difference between the signal period of the PWM delay signal and the signal period of the PWM original signal, and adding the set delay time and the period delay time to obtain the reset delay time of the nth PWM signal. For example, the difference between the signal period of the PWM delay signal and the signal period of the PWM original signal is b, the period delay time is b, and the reset delay time is n a+b.

[0074] For example, for the first PWM delay signal, the reset delay time W of the first PWM delay signal is 1 a+b. For example, for the second PWM delay signal, the reset delay time W of the second PWM delay signal is 2 a+b. And so on.

[0075] In the embodiment of the present application, step S52 is executed to determine a first comparison result between the set delay time and the preset clock period, and a second comparison result between the reset delay time and the preset clock period.

[0076] The first comparison result includes a first type of result and a second type of result. The first type of result indicates that the set delay time is greater than or equal to a preset clock period. The second type of result indicates that the set delay time is less than the preset clock period. Determining the first comparison result between the set delay time and the preset clock period includes the following steps: generating the first type of result in response to the set delay time being greater than or equal to the preset clock period, and generating the second type of result in response to the set delay time being less than the preset clock period.

[0077] The second comparison result includes a third type of result and a fourth type of result. The third type of result indicates that the reset delay time is greater than or equal to the preset clock period. The fourth type of result indicates that the reset delay time is less than the preset clock period. Determining the second comparison result between the reset delay time and the preset clock period includes the following steps: generating a third type of result in response to the reset delay time being greater than or equal to the preset clock period, and generating a fourth type of result in response to the reset delay time being less than the preset clock period.

[0078] In the embodiment of the present application, step S53 is executed to assign a first delay time to the delay module and a first comparison threshold to the first comparator according to the first comparison result, so that when the count value output by the counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level, and the set high level is processed by the delay module for the first delay time and then transmitted to the set end of the latch, so that the latch outputs the nth high level, and the total delay time of the delay module is less than or equal to the preset clock period.

[0079] like Figure 4 As shown in the figure, for the first PWM delay signal delay_pwm, the first delay time is α. The counter is triggered by the rising edge of the third clock signal and starts counting. When the counter count value is 0, the first comparator output is set to a high level. The microcontroller needs to control the first delay unit to process the first delay time of 1*α. If α=u* , the microcontroller controls the first selector to select u first delay devices for processing for the first delay time. The set high level output by the first comparator is processed for the first delay time and then output to the set terminal S of the latch. This set high level is considered the delayed set signal S_P(n). The delayed set signal S_P(n) is applied to the set terminal S of the latch, causing the latch to output a high level and latch the high level.

[0080] Allocating a first delay time to the delay module according to the first comparison result includes the following steps: In response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock period, divide the set delay time by the preset clock period to obtain a first remainder, and determine the first remainder as the first delay time; in response to the first comparison result indicating that the set delay time is less than the preset clock period, determine the set delay time as the first delay time.

[0081] For example, if the set delay time p = nα is greater than or equal to the preset clock period c, the embodiment of the present application obtains the first delay time according to the following formula, as shown below: , where x is the quotient obtained by dividing the set delay time by the preset clock period, is the first remainder, and the first remainder is used as the first delay time.

[0082] For another example, if the set delay time p = nα is less than the preset clock period c, the embodiment of the present application directly uses the set delay time as the first delay time.

[0083] The delay module includes a first delay unit. The first delay unit includes a first selector and a plurality of first delay elements connected in series in sequence. The total delay time of all the first delay elements is less than or equal to the preset clock period. The generation method further includes the following steps: Determine the first delay stage number based on the first delay time and the delay time of the first delay element, and control the first selector to select the corresponding number of first delay elements according to the first delay stage number, so that the corresponding number of first delay elements perform a first delay time processing on the set high level.

[0084] If the delay time of each first delay element is , the first delay stage number , where is the first delay stage number, is the first delay time. The embodiment of the present application selects first delay elements to perform a first delay time processing on the set high level.

[0085] Allocating a first comparison threshold to the first comparator according to the first comparison result includes the following steps: Obtain the first local threshold of the first comparator. In response to the first comparison result indicating that the set delay time is greater than or equal to the preset clock period, accumulate a first specified value on the basis of the first local threshold to obtain the first comparison threshold. The first specified value is the quotient obtained by dividing the set delay time by the preset clock period. In response to the first comparison result indicating that the set delay time is less than the preset clock period, determine the first local threshold as the first comparison threshold.

[0086] For example, the first local threshold of the first comparator is 0, and if the set delay time p = nα is greater than or equal to the preset clock cycle c, as shown below: , x is the quotient obtained by dividing the set delay time by the preset clock cycle, and 0 + x = x in the embodiment of the application, that is, the first comparison threshold is x.

[0087] For another example, if the set delay time p = nα is less than the preset clock cycle c, the embodiment of the application directly takes 0 as the first comparison threshold.

[0088] The embodiment of the application performs step S54, assigns a second delay time to the delay module and a second comparison threshold to the second comparator according to the second comparison result, so that when the count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level, the reset high level is processed by the delay module for the second delay time, and then is transmitted to the reset end of the latch, so that the latch outputs the nth low level, and the nth high level and the nth low level form the nth PWM delay signal.

[0089] Assigning the second delay time to the delay module according to the second comparison result includes the following steps: in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock cycle, dividing the reset delay time by the preset clock cycle to obtain a second remainder, determining the second remainder as the second delay time, and in response to the second comparison result indicating that the reset delay time is less than the preset clock cycle, determining the reset delay time as the second delay time.

[0090] For example, if the reset delay time W = nα + β is greater than or equal to the preset clock cycle c, the embodiment of the application obtains the second delay time according to the following formula, as shown below: , is the quotient obtained by dividing the reset delay time by the preset clock cycle, is the second remainder, and the second remainder is taken as the second delay time.

[0091] For another example, if the reset delay time W = nα + β is less than the preset clock cycle c, the embodiment of the application directly takes the reset delay time as the second delay time.

[0092] The delay module includes a second delay unit, and the second delay unit includes a second selector and a plurality of second delay devices connected in sequence, and the total delay time of all the second delay devices is less than or equal to the preset clock cycle. The generation method further includes the following steps: determining a second delay order based on the second delay time and the delay time of the second delay device, and controlling the second selector to gate a number of second delay devices corresponding to the second delay order, so that the number of second delay devices corresponding to the second delay order processes the reset high level for the second delay time.

[0093] the second delay stage wherein, the second delay stage, the second delay time. The embodiment of the present application selects The second delay time is processed by the second delay device for the high level.

[0094] According to the second comparison result, the second comparison threshold is assigned to the second comparator, including the following steps: obtaining the second local threshold of the second comparator, in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock period, adding a second specified value on the basis of the second local threshold to obtain the second comparison threshold, the second specified value is the quotient obtained by dividing the reset delay time by the preset clock period, in response to the second comparison result indicating that the reset delay time is less than the preset clock period, determining the second local threshold as the second comparison threshold.

[0095] For example, the second local threshold of the second comparator is NUM, and if the reset delay time W = nα + β is greater than or equal to the preset clock period c, as follows: , The quotient obtained by dividing the reset delay time by the preset clock period, and the embodiment of the present application obtains the second comparison threshold NUM = NUM + m.

[0096] For another example, if the reset delay time W = nα + β is less than the preset clock period c, the embodiment of the present application directly takes the second local threshold NUM as the second comparison threshold.

[0097] It can be understood that in some embodiments, the original counting period of the counter can be continued to be used in the delay case. In some embodiments, the current counting period of the counter can be determined according to the reset delay time and the original counting period of the counter in the delay case, and the counter is executed to clear in response to the counting value of the counter being equal to the current counting period. For example, the current counting period of the counter , the current counting period, the original counting period, and the counter is executed to clear when the counting value of the counter is equal to the current counting period.

[0098] In order to elaborate the working principle of the PWM signal generation method provided by the embodiment of the present application, the following examples are provided for illustration, as follows:

[0099] A1. When starting to work, the current counting period of the counter is updated to wherein the first comparison threshold is 0 and the second comparison threshold is NUM.

[0100] A2. The counter starts to work, and the arrival of each clock cycle will make the count value of the counter increase.

[0101] ① In the case that n*α is greater than or equal to c, and nα+β is greater than or equal to c:

[0102] Since the quotient of α divided by c is 1, the first comparison threshold is updated to 1, and the first remainder of α divided by c is divided by the delay time of the first delay device to obtain the first delay stage, and finally the first selector is controlled to enable the multiple first delay devices corresponding to the first delay stage.

[0103] Since the quotient of (nα+β) divided by c is 1, the second comparison threshold is updated to NUM+1, and the second remainder of (nα+β) divided by c is divided by the delay time of the second delay device to obtain the second delay stage, and finally the second selector is controlled to enable the multiple second delay devices corresponding to the second delay stage.

[0104] When the count value of the counter is 0, both the first comparator and the second comparator output low level.

[0105] When the next clock cycle arrives, the count value of the counter is 1, the first comparator outputs a set high level, and the set high level is processed by the multiple first delay devices corresponding to the first delay stage for the first delay time, and then is applied to the set end of the latch to make the latch output high level and latch the high level.

[0106] With the clock signal continuously inputting the counter, when the count value of the counter is NUM+1, the second comparator outputs a reset high level, and the reset high level is processed by the multiple second delay devices corresponding to the second delay stage for the second delay time, and then is applied to the reset end of the latch to make the latch output low level and latch the low level.

[0107] With the clock signal continuously inputting the counter, when the count value of the counter reaches the current count period, the counter performs a clear operation, and the first comparison threshold, the second comparison threshold, and the count period of the counter are restored to the initial state, the generation of the next PWM signal is continued, and the process returns to A1.

[0108] ② In the case that n*α is greater than or equal to c, and nα+β is less than c:

[0109] Since the quotient of α divided by c is 1, the first comparison threshold is updated to 1, and the first remainder of α divided by c is divided by the delay time of the first delay device to obtain the first delay stage, and finally the first selector is controlled to enable the multiple first delay devices corresponding to the first delay stage.

[0110] The second comparison threshold value is kept unchanged as NUM, and (nα+β) is divided by the delay time of the second delayers to obtain a second delay series, and finally the second selector is controlled to enable the second delayers corresponding to the second delay series.

[0111] When the count value of the counter is 0, the first comparator and the second comparator both output low level.

[0112] When the next clock cycle arrives, the count value of the counter is 1, the first comparator outputs a set high level, and the set high level is applied to the set end of the latch after being processed by the first delay time through the first delayers corresponding to the first delay series, so that the latch outputs high level and latches the high level.

[0113] With the clock signal continuously inputting the counter, when the count value of the counter is NUM, the second comparator outputs a reset high level, and the reset high level is applied to the reset end of the latch after being processed by the second delay time through the second delayers corresponding to the second delay series, so that the latch outputs low level and latches the low level.

[0114] With the clock signal continuously inputting the counter, when the count value of the counter reaches the current count period, the counter performs a clear operation, and the first comparison threshold value, the second comparison threshold value and the count period of the counter are restored to the initial state, and the generation of the next PWM signal is continued, returning to A1.

[0115] ③ In the case that n*α is less than c, and nα+β is greater than or equal to c:

[0116] The first comparison threshold value is kept unchanged as 0, and n*α is divided by the delay time of the first delayers to obtain a first delay series, and finally the first selector is controlled to enable the first delayers corresponding to the first delay series.

[0117] Since the quotient of (nα+β) divided by c is 1, the second comparison threshold value is updated as NUM+1, and the second remainder of (nα+β) divided by c is divided by the delay time of the second delayers to obtain a second delay series, and finally the second selector is controlled to enable the second delayers corresponding to the second delay series.

[0118] When the count value of the counter is 0, the first comparator outputs a set high level, and the set high level is applied to the set end of the latch after being processed by the first delay time through the first delayers corresponding to the first delay series, so that the latch outputs high level and latches the high level.

[0119] When the count value of the counter is NUM+1, the second comparator outputs a reset high level. The reset high level is processed by a plurality of second delay units corresponding to the second delay stage for a second delay time, and then is applied to the reset terminal of the latch to make the latch output a low level and latch the low level.

[0120] When the count value of the counter reaches the current count period, the counter performs a clear operation, and restores the first comparison threshold value, the second comparison threshold value and the count period of the counter to the initial state, and continues the generation of the next PWM signal, returning to A1.

[0121] (4) In the case where n*α is less than c and n*α+β is less than c:

[0122] The first comparison threshold value is kept unchanged, and n*α is divided by the delay time of the first delay unit to obtain the first delay stage. Finally, the first selector is controlled to select a plurality of first delay units corresponding to the first delay stage.

[0123] The second comparison threshold value is kept unchanged, and (n*α+β) is divided by the delay time of the second delay unit to obtain the second delay stage. Finally, the second selector is controlled to select a plurality of second delay units corresponding to the second delay stage.

[0124] When the count value of the counter is 0, the first comparator outputs a set high level. The set high level is processed by a plurality of first delay units corresponding to the first delay stage for a first delay time, and then is applied to the set terminal of the latch to make the latch output a high level and latch the high level.

[0125] When the count value of the counter is 1 in the next clock period, the first comparator outputs a set high level. The set high level is processed by a plurality of first delay units corresponding to the first delay stage for a first delay time, and then is applied to the set terminal of the latch to make the latch output a high level and latch the high level.

[0126] When the count value of the counter is NUM, the second comparator outputs a reset high level. The reset high level is processed by a plurality of second delay units corresponding to the second delay stage for a second delay time, and then is applied to the reset terminal of the latch to make the latch output a low level and latch the low level.

[0127] When the count value of the counter reaches the current count period, the counter performs a clear operation, and restores the first comparison threshold value, the second comparison threshold value and the count period of the counter to the initial state, and continues the generation of the next PWM signal, returning to A1.

[0128] The PWM signal generation method provided by the embodiments of the present application can achieve high-precision, high-stability and fast-response control effect with low hardware cost, and significantly improves the precision and performance of the PWM.

[0129] It should be noted that in the above various embodiments, the above steps do not necessarily have a certain sequence, and those skilled in the art can understand from the description of the embodiments of the present application that the above steps can have different execution sequences in different embodiments, that is, they can be executed in parallel, or they can be executed in exchange, and the like.

[0130] As another aspect of the embodiments of the present application, the embodiments of the present application provide a PWM signal generation device. The PWM signal generation device can be a software module, and the software module includes a plurality of instructions stored in a memory, and a processor can access the memory and call the instructions for execution to complete the PWM signal generation method described in the above various embodiments.

[0131] In some embodiments, the PWM signal generation device can also be built by hardware devices, for example, the PWM signal generation device can be built by one or more chips, and each chip can work in coordination with each other to complete the PWM signal generation method described in the above various embodiments. For another example, the PWM signal generation device can also be built by various logic devices, such as built by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a single-chip microcomputer, an ARM (Acorn RISC Machine), or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, or any combination of these components.

[0132] Please refer to Figure 6 , the PWM signal generation device 600 includes a delay time determination module 61, a comparison result determination module 62, a first delay module 63 and a second delay module 64.

[0133] The delay time determination module 61 is configured to determine a set delay time and a reset delay time of the nth PWM delay signal, the set delay time is a time of delaying setting to output a high level of the nth PWM delay signal, the reset delay time is a time of delaying resetting to output a low level of the nth PWM delay signal, and n is a positive integer. The comparison result determination module 62 is configured to determine a first comparison result of the set delay time and a preset clock period, and a second comparison result of the reset delay time and the preset clock period. The first delay module 63 is configured to allocate a first delay time to the delay module and a first comparison threshold to the first comparator according to the first comparison result, so that when a count value output by the counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level, the set high level is processed by the delay module for the first delay time, and then transmitted to a set end of the latch, so that the latch outputs the nth high level, and a total delay time of the delay module is less than or equal to the preset clock period. The second delay module 64 is configured to allocate a second delay time to the delay module and a second comparison threshold to the second comparator according to the second comparison result, so that when a count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level, the reset high level is processed by the delay module for the second delay time, and then transmitted to a reset end of the latch, so that the latch outputs the nth low level, and the nth high level and the nth low level form the nth PWM delay signal.

[0134] The embodiment of the application does not depend on a high-precision clock chip, and can realize delay processing of a PWM signal on a low-cost hardware circuit through fine adjustment, which can not only delay a duty cycle but also delay a signal period, the time resolution involved in the delay is relatively high, and the PWM signal output is more accurate and stable.

[0135] In some embodiments, the delay time determination module 61 is specifically configured to: determine a high-level delay time, the high-level delay time is a time difference between a high level of the PWM delay signal and a high level of the PWM original signal, multiply the high-level delay time by n to obtain the set delay time of the nth PWM signal.

[0136] In some embodiments, the delay time determination module 61 is specifically configured to: determine a period delay time, the period delay time is a difference between a signal period of the PWM delay signal and a signal period of the PWM original signal, and the set delay time and the period delay time are added to obtain the reset delay time of the nth PWM signal.

[0137] In some embodiments, the first delay module 63 is specifically used to: respond to the first comparison result used to indicate that the set delay time is greater than or equal to the preset clock period, divide the set delay time by the preset clock period to obtain a first remainder, determine the first remainder as the first delay time, respond to the first comparison result used to indicate that the set delay time is less than the preset clock period, and determine the set delay time as the first delay time.

[0138] In some embodiments, the delay module includes a first delay unit, the first delay unit includes a first selector and a plurality of first delay devices connected in series in sequence, the total delay time of all the first delay devices is less than or equal to a preset clock period, and the first delay module 63 is specifically used to: determine the first delay level based on the first delay time and the delay time of the first delay device, control the first selector to select the first delay devices corresponding to the first delay level, so that the first delay devices corresponding to the first delay level process the set high level for the first delay time.

[0139] In some embodiments, the first delay module 63 is specifically used to: obtain a first local threshold of the first comparator, respond to the first comparison result to indicate that the set delay time is greater than or equal to the preset clock period, accumulate a first specified value on the basis of the first local threshold to obtain a first comparison threshold, the first specified value is the quotient obtained by dividing the set delay time by the preset clock period, respond to the first comparison result to indicate that the set delay time is less than the preset clock period, and determine that the first local threshold is the first comparison threshold.

[0140] In some embodiments, the second delay module 64 is specifically used to: respond to the second comparison result to indicate that the reset delay time is greater than or equal to the preset clock period, divide the reset delay time by the preset clock period to obtain a second remainder, determine the second remainder as the second delay time, respond to the second comparison result to indicate that the reset delay time is less than the preset clock period, and determine the reset delay time as the second delay time.

[0141] In some embodiments, the delay module includes a second delay unit, the second delay unit includes a second selector and a plurality of second delays connected in series in sequence, the total delay time of all the second delays is less than or equal to a preset clock period, and the second delay module 64 is specifically used to: determine the second delay level based on the second remainder and the delay time of the second delay, control the second selector to select the second delays corresponding to the number of the second delay levels, so that the second delays corresponding to the number of the second delay levels process the reset high level for the second delay time.

[0142] In some embodiments, the second delay module 64 is specifically configured to: obtain a second local threshold of the second comparator, in response to the second comparison result indicating that the reset delay time is greater than or equal to the preset clock period, accumulate a second specified value on the basis of the second local threshold to obtain a second comparison threshold, the second specified value being a quotient obtained by dividing the reset delay time by the preset clock period, and in response to the second comparison result indicating that the reset delay time is less than the preset clock period, determine the second local threshold as the second comparison threshold.

[0143] In some embodiments, the second delay module 64 is specifically configured to: determine a current counting period of the counter according to the reset delay time and the original counting period of the counter, and in response to the counting value of the counter being equal to the current counting period, perform a clear operation on the counter.

[0144] It should be noted that the above-mentioned PWM signal generation device can perform the PWM signal generation method provided in the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method. Technical details not described in detail in the PWM signal generation device embodiments can be referred to the PWM signal generation method provided in the embodiments of the present application.

[0145] Referring to Figure 7 , Figure 7 A structural schematic diagram of a microcontroller is provided in the embodiments of the present application. The microcontroller 700 includes one or more processors 71 and a memory 72. The memory 72 is connected to the one or more processors 71, for example, connected to the processor 71 through a bus.

[0146] The processor 71 is configured to support the microcontroller to perform the corresponding functions in the methods in the above-mentioned method embodiments. The processor can be a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof. The above-mentioned hardware chip can be an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0147] The memory 72 is configured to store program codes and the like. The memory can include volatile memory (VM), such as random access memory (RAM), and / or non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD), and / or a combination thereof.

[0148] The memory 72 can be configured to store non-volatile software programs, non-volatile computer-executable programs and modules, such as program instructions / modules corresponding to the PWM signal generation method according to the embodiments of the present application. The processor executes various functional applications and data processing of the PWM signal generation method and the PWM signal generation apparatus by running the non-volatile software programs, instructions and modules stored in the memory, i.e., realizes the functions of each module or unit of the PWM signal generation method and the PWM signal generation apparatus provided by the above method embodiments.

[0149] The memory 72 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function. The data storage area can store data created according to the use of the PWM signal generation apparatus, and the like. In some embodiments, the memory can optionally include a memory remotely arranged with respect to the processor, and these remote memories can be connected to the PWM signal generation apparatus through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0150] The one or more modules are stored in the memory and, when executed by the one or more processors, perform the PWM signal generation method in any of the above method embodiments, e.g., perform the method steps described in the above method embodiments, and realize the functions of the modules described in the above apparatus embodiments.

[0151] The embodiments of the present application also provide a computer readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a microcontroller, cause the microcontroller to perform the method according to the foregoing embodiments.

[0152] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware. The program can be stored in a computer readable storage medium, and when the program is executed, the program can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0153] The above disclosure is only the preferred embodiment of the present application, and of course cannot limit the scope of the right of the present application, so the equivalent changes made according to the claims of the present application still belong to the scope covered by the present application.

Claims

1. A method of generating a PWM signal, characterized by, The generating method comprises: determining a set time of an n-th PWM delay signal, the set time being a time of delaying setting to output a high level of the n-th PWM delay signal, n being a positive integer; determining a first comparison result of the set time and a preset clock period, and a second comparison result of a reset time and the preset clock period; according to the first comparison result, assigning a first delay time to a delay module and a first comparison threshold to a first comparator, so that when a count value output by a counter to the first comparator is equal to the first comparison threshold, the first comparator outputs a set high level, the set high level is processed by the delay module for the first delay time, and then is transmitted to a set end of a latch, so that the latch outputs an n-th high level, and a total delay time of the delay module is less than or equal to the preset clock period; according to the second comparison result, assigning a second delay time to the delay module and a second comparison threshold to a second comparator, so that when a count value output by the counter to the second comparator is equal to the second comparison threshold, the second comparator outputs a reset high level, the reset high level is processed by the delay module for the second delay time, and then is transmitted to a reset end of the latch, so that the latch outputs an n-th low level, and the n-th high level and the n-th low level form the n-th PWM delay signal.

2. The generation method of claim 1, wherein, The method further comprises: determining a high level delay time, the high level delay time being a time difference between a high level of a PWM delay signal and a high level of a PWM original signal; multiplying n by the high level delay time to obtain the set time of the n-th PWM signal.

3. The generation method of claim 1, wherein, The method further comprises: determining a period delay time, the period delay time being a difference between a signal period of the PWM delay signal and a signal period of the PWM original signal; adding the set time and the period delay time to obtain the reset time of the n-th PWM signal.

4. The generation method of claim 1, wherein, The method further comprises: in response to the first comparison result indicating that the set time is greater than or equal to the preset clock period, dividing the set time by the preset clock period to obtain a first remainder, and determining the first remainder as the first delay time; in response to the first comparison result indicating that the set time is less than the preset clock period, determining the set time as the first delay time.

5. The generation method of claim 4, wherein, The delay module comprises a first delay unit, the first delay unit comprising a first selector and a plurality of first delayers connected in sequence, a total delay time of all the first delayers being less than or equal to the preset clock period, and the method further comprises: determining a first delay order based on the first delay time and a delay time of the first delayers; The first selector is controlled to enable a number of first delay units corresponding to the first delay stage number, so that the number of first delay units corresponding to the first delay stage number processes the set high level for a first delay time.

6. The generation method of claim 1, wherein, The first comparison threshold is assigned to the first comparator according to the first comparison result, including: a first local threshold of the first comparator is obtained; in response to the first comparison result indicating that the set delay time is greater than or equal to a preset clock period, a first specified value is added to the first local threshold to obtain the first comparison threshold, the first specified value being a quotient obtained by dividing the set delay time by the preset clock period; in response to the first comparison result indicating that the set delay time is less than the preset clock period, the first local threshold is determined as the first comparison threshold.

7. The generation method of claim 1, wherein, The second delay time is assigned to the delay module according to the second comparison result, including: in response to the second comparison result indicating that the reset delay time is greater than or equal to a preset clock period, a second remainder is determined by dividing the reset delay time by the preset clock period, and the second remainder is determined as the second delay time; in response to the second comparison result indicating that the reset delay time is less than the preset clock period, the reset delay time is determined as the second delay time.

8. The generation method of claim 7, wherein, The delay module includes a second delay unit, the second delay unit including a second selector and a plurality of second delay units connected in sequence, a total delay time of all the second delay units being less than or equal to a preset clock period, and the generation method further includes: a second delay stage number is determined based on the second remainder and a delay time of the second delay unit; the second selector is controlled to enable a number of second delay units corresponding to the second delay stage number, so that the number of second delay units corresponding to the second delay stage number processes the reset high level for a second delay time.

9. The generation method of claim 1, wherein, The second comparison threshold is assigned to the second comparator according to the second comparison result, including: a second local threshold of the second comparator is obtained; in response to the second comparison result indicating that the reset delay time is greater than or equal to a preset clock period, a second specified value is added to the second local threshold to obtain the second comparison threshold, the second specified value being a quotient obtained by dividing the reset delay time by the preset clock period; in response to the second comparison result indicating that the reset delay time is less than the preset clock period, the second local threshold is determined as the second comparison threshold.

10. The method of generating according to any one of claims 1 to 9, characterized in that, The generation method further includes: a current counting period of the counter is determined according to the reset delay time and an original counting period of the counter; in response to a counting value of the counter being equal to the current counting period, a clear operation is performed on the counter.

11. A microcontroller, characterized by The microcontroller includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, and the processor being configured to cause the microcontroller to implement the PWM signal generation method according to any one of claims 1-10 when executing the one or more computer programs.

12. A PWM generation circuit, characterized by comprising: The microcontroller as claimed in claim 11, wherein the microcontroller is connected in communication with the counter, the first comparator, the second comparator, the first delay unit and the second delay unit, respectively; the counter is connected in communication with the first comparator and the second comparator, respectively; the first comparator is connected in communication with the first delay unit; the second comparator is connected in communication with the second delay unit; a set terminal of the latch is connected in communication with an output terminal of the first delay unit; and a reset terminal of the latch is connected in communication with an output terminal of the second delay unit.

13. A digital pulse width modulated signal circuit, characterized by The PWM generation circuit as claimed in claim 12.

14. An electronic device, comprising: The PWM generation circuit as claimed in claim 12.

15. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, the computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method of generating a PWM signal according to any one of claims 1-10.

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