Low-jitter phase-locked loop for ultra-high-speed sampling
By designing a low-jitter phase-locked loop for ultra-high-speed sampling, and using charge sharing and low-pass filtering to indirectly control the voltage-controlled oscillator for the charge pump output, the problem of difficulty in achieving low spurs in the phase-locked loop system in the prior art is solved, and the effects of low jitter and low reference spurs are achieved.
Patent Information
- Application Number
- CN202510174900.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2025-06-24
AI Technical Summary
The existing phase-locked loop systems are difficult to achieve low spuriousness while achieving low jitter, especially under high-speed sampling conditions, which leads to the impact of the performance of the ADC.
A low-jitter phase-locked loop for ultra-high-speed sampling is designed, and a time-amplification frequency phase-detector, charge pump, master-slave sampling filter, low-pass filter, transconductive charge pump and voltage-controlled oscillator are used to indirectly control the voltage-controlled oscillator through charge sharing and low-pass filtering, forming a parallel proportional path and integral path to optimize reference spurs.
Reference spurs are significantly optimized, completely eliminating the impact of non-ideal characteristics of the charge pump on reference spurs, achieving low jitter and low reference spurs, and reducing the difficulty of optimizing in-band noise.
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Figure CN120200607A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of wireless communication, and particularly relates to a low-jitter phase-locked loop for ultra-high-speed sampling. Background Art
[0002] With the continuous development of communication technologies, high-speed sampling clocks are applied in a wider and wider range of fields, such as high-speed analog-to-digital converters, wireless communication, wired communication, medical imaging, etc. In a communication system, a low-jitter and low-spurious sampling clock source is a prerequisite for various applications. Taking a high-speed analog-to-digital converter (ADC) as an example, the quality of the high-speed sampling clock source will directly affect the performance of the ADC. The Nyquist theorem requires that the sampling rate of the ADC is limited by the frequency of the sampling clock, and the clock sampling rate in turn limits the maximum signal bandwidth that the ADC can process; clock jitter will cause the sampling points of the ADC to shift in the time domain, resulting in additional frequency components in the output of the ADC and reducing its spurious-free dynamic range. Therefore, as a commonly used high-speed sampling clock source, whether the phase-locked loop system can achieve low jitter and low spurs at the same time is a major difficulty for the current phase-locked loop system.
[0003] As the architecture of the phase-locked loop system, the phase-locked loop not only provides the noise transfer function of the frequency synthesizer, but also suppresses the non-ideal characteristics of each module to varying degrees. The gain of the sampling phase discriminator (SPD) in the sampling phase-locked loop is limited by the parasitic capacitance of the sampling points; although the sub-sampling phase-locked loop makes up for the gain deficiency of the sampling phase-locked loop, it requires an additional frequency-locked loop and has poor reference spur performance; the gain of the charge pump in the traditional charge-pump phase-locked loop is limited by power consumption and the charge-pump dead zone, and since the output of the charge pump directly participates in the tuning of the voltage-controlled oscillator, the periodic voltage fluctuations caused by the non-ideal characteristics of the charge pump directly act on the voltage-controlled oscillator, thereby generating significant reference spurs. Therefore, a phase-locked loop architecture that can achieve low jitter and low spurs at the same time is needed. Summary of the Invention
[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-jitter phase-locked loop for ultra-high-speed sampling. The technical problems to be solved by the present invention are achieved through the following technical solutions:
[0005] The present invention provides a low-jitter phase-locked loop for ultra-high-speed sampling, including: a time-amplitude frequency discriminator and phase detector, a charge pump, a master-slave sampling filter, a low-pass filter, a transconductance charge pump, and a voltage-controlled oscillator; the time-amplitude frequency discriminator and phase detector, the charge pump, the master-slave sampling filter, and the low-pass filter are connected in sequence; within one reference period, the charge output by the charge pump is first stored in the sampling capacitor in the master-slave sampling filter, and after the sampling stops, charge sharing is performed with the subsequent circuit modules connected thereto, so as to indirectly control the voltage-controlled oscillator by the charge pump; after the low-pass filter, a parallel proportional path and integral path are formed; in the proportional path, the output signal of the low-pass filter enters the voltage-controlled oscillator; in the integral path, the output signal of the low-pass filter enters the transconductance charge pump; wherein, the time error amplifier in the time-amplitude frequency discriminator and phase detector is used to increase the gain of the time-amplitude frequency discriminator and phase detector to suppress the in-band noise of the phase-locked loop system.
[0006] In an embodiment of the present invention, the time-amplitude frequency discriminator and phase detector inputs a phase signal and amplifies the phase signal; the charge pump and the master-slave sampling filter are used to convert the amplified phase signal into a voltage signal and filter the voltage signal in the low-pass filter.
[0007] In an embodiment of the present invention, the charge pump includes: a current source and a capacitor C P ; the two current sources are connected in series, and each current source is connected in series with a switch, and the first end of the capacitor C P is respectively connected to the first end and the second end of the two switches connected in series, and the second end of the capacitor C P is grounded.
[0008] In an embodiment of the present invention, the master-slave sampling filter includes: a switch S1, a sampling capacitor C1, a switch S2, and a capacitor C2; the first end of the switch S1, the first plate of the sampling capacitor C1, and the first end of the switch S2 are connected; the second end of the switch S1 is connected to a reference voltage terminal; the second end of the sampling capacitor C1 is grounded; the second end of the switch S2 is connected to the first plate of the capacitor C2, and the second plate of the capacitor C2 is grounded.
[0009] In an embodiment of the present invention, the low-pass filter includes: a resistor R3 and a capacitor C3; the first end of the resistor R3 is connected to the second end of the switch S2, the first plate of the capacitor C3 is connected to the second end of the resistor R3, and the second plate of the capacitor C3 is grounded.
[0010] In an embodiment of the present invention, the low-jitter phase-locked loop for ultra-high-speed sampling further includes: a capacitor C I; The first electrode plate of the capacitor C I is connected to the output end of the transconductance charge pump, and the second electrode plate of the capacitor C I is grounded.
[0011] In an embodiment of the present invention, the low-jitter phase-locked loop for ultra-high-speed sampling further includes: a frequency divider; the frequency divider is respectively connected to the voltage-controlled oscillator and the time-amplified frequency discriminator and phase detector, and is used for adjusting the frequency of the output signal of the voltage-controlled oscillator according to a frequency division ratio, and inputting the output signal of the voltage-controlled oscillator with the adjusted frequency into the time-amplified frequency discriminator and phase detector.
[0012] In an embodiment of the present invention, the low-jitter phase-locked loop for ultra-high-speed sampling further includes: a multi-pulse generator; the multi-pulse generator is respectively connected to the time-amplified frequency discriminator and phase detector and the master-slave sampling filter, and is used for controlling the sampling and charge sharing of the master-slave sampling filter.
[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0014] For the low-jitter phase-locked loop for ultra-high-speed sampling of the present invention, the charge output by the charge pump is stored on the sampling capacitor, and after charge sharing and low-pass filtering, it enters the proportional path and the integral path simultaneously, avoiding the ripple generated by the non-ideal characteristics of the charge pump from acting on the voltage-controlled oscillator, blocking the direct participation of the charge pump output in the tuning of the voltage-controlled oscillator, and adopting the method of indirectly controlling the voltage-controlled oscillator by the charge pump output, which significantly optimizes the reference spurs and completely eliminates the influence of the non-ideal characteristics of the charge pump on the reference spurs. At the same time, a time error amplifier is used, so that the main source of in-band noise is no longer the charge pump but the time error amplifier, and the means of reducing in-band noise changes from optimizing the charge pump to optimizing the time error amplifier, reducing the difficulty of optimizing in-band noise. Finally, by adjusting the loop bandwidth of the phase-locked loop system, the in-band noise and the out-of-band noise are balanced, and low jitter and low reference spurs are achieved simultaneously.
[0015] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings
[0016] Figure 1 is a schematic diagram of the low-jitter phase-locked loop for ultra-high-speed sampling provided by an embodiment of the present invention;
[0017] Figure 2 is a schematic diagram of the noise model of the low-jitter phase-locked loop for ultra-high-speed sampling provided by an embodiment of the present invention. Detailed Embodiments
[0018] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following will, in conjunction with the accompanying drawings and specific embodiments, provide a detailed description of a low-jitter phase-locked loop for ultra-high-speed sampling proposed according to the present invention.
[0019] The foregoing and other technical contents, features, and effects of the present invention can be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solution of the present invention.
[0020] Embodiment 1
[0021] As Figure 1 shown, Figure 1 is a schematic diagram of a low-jitter phase-locked loop for ultra-high-speed sampling provided by an embodiment of the present invention.
[0022] In this embodiment, a low-jitter phase-locked loop for ultra-high-speed sampling includes: a time-amplified frequency and phase detector, a charge pump, a master-slave sampling filter, a low-pass filter, a transconductance charge pump, and a voltage-controlled oscillator; the time-amplified frequency and phase detector, the charge pump, the master-slave sampling filter, and the low-pass filter are connected in sequence; within one reference period, the charge output by the charge pump is first stored in the sampling capacitor in the master-slave sampling filter, and after the sampling stops, charge sharing is performed with the subsequent circuit modules connected thereto to achieve indirect control of the voltage-controlled oscillator by the charge pump; a parallel proportional path and integral path are formed after the low-pass filter; in the proportional path, the output signal of the low-pass filter enters the voltage-controlled oscillator; in the integral path, the output signal of the low-pass filter enters the transconductance charge pump; wherein, the time error amplifier in the time-amplified frequency and phase detector is used to increase the gain of the time-amplified frequency and phase detector to suppress the in-band noise of the phase-locked loop system.
[0023] In an optional embodiment, the time-amplified frequency and phase detector inputs a phase signal and amplifies the phase signal; the charge pump and the master-slave sampling filter are used to convert the amplified phase signal into a voltage signal and filter the voltage signal in the low-pass filter.
[0024] It can be understood that a parallel proportional path and integral path are formed after the low-pass filter. Among them, the output signal of the proportional path directly enters the voltage-controlled oscillator to adjust the phase; the output signal of the integral path enters the transconductance charge pump to adjust the frequency and suppress noise.
[0025] In an optional embodiment, the charge pump includes: two current sources and a capacitor C P; Two current sources are connected in series, and each current source is connected in series with a switch. The first end of capacitor C P is respectively connected to the first end and the second end of the two switches connected in series. The second end of capacitor C P is grounded.
[0026] It should be noted that for the low-jitter phase-locked loop for ultra-high-speed sampling in this embodiment, a charge pump phase-locked loop with a time error amplification frequency discriminator and phase detector is used, so that the main source of in-band noise is no longer the charge pump, but the time error amplifier, making the means of reducing in-band noise change from optimizing the charge pump to optimizing the time error amplifier. In other words, by optimizing the in-band noise through the time error amplifier, the difficulty of optimizing the in-band noise is reduced. Additionally, low jitter and low reference spurs can be achieved by adjusting the loop bandwidth.
[0027] In an alternative embodiment, the master-slave sampling filter includes: switch S1, sampling capacitor C1, switch S2, and capacitor C2; the first end of switch S1, the first plate of sampling capacitor C1, and the first end of switch S2 are connected; the second end of switch S1 is connected to the reference voltage terminal; the second end of sampling capacitor C1 is grounded; the second end of switch S2 is connected to the first plate of capacitor C2, and the second plate of capacitor C2 is grounded.
[0028] In an alternative embodiment, the low-pass filter includes: resistor R3 and capacitor C3; the first end of resistor R3 is connected to the second end of switch S2, the first plate of capacitor C3 is connected to the second end of resistor R3, and the second plate of capacitor C3 is grounded.
[0029] In an alternative embodiment, the low-jitter phase-locked loop for ultra-high-speed sampling further includes: capacitor C I ; The first plate of capacitor C I is connected to the output terminal of the transconductance charge pump, and the second plate of capacitor C I is grounded.
[0030] In an alternative embodiment, the low-jitter phase-locked loop for ultra-high-speed sampling further includes: a frequency divider; the frequency divider is respectively connected to the voltage-controlled oscillator and the time amplification frequency discriminator and phase detector, and is used to adjust the frequency of the output signal of the voltage-controlled oscillator according to the frequency division ratio, and input the output signal of the voltage-controlled oscillator with the adjusted frequency to the time amplification frequency discriminator and phase detector.
[0031] In an alternative embodiment, the low-jitter phase-locked loop for ultra-high-speed sampling further includes: a multi-pulse generator; the multi-pulse generator is respectively connected to the time amplification frequency discriminator and phase detector and the master-slave sampling filter, and is used to control the sampling and charge sharing of the master-slave sampling filter.
[0032] It should be noted that the low-jitter phase-locked loop for ultra-high-speed sampling in this embodiment can isolate the non-ideal characteristics of the charge pump and achieve low reference spurs by controlling the voltage-controlled oscillator through a dual-path.
[0033] The principle is that, to avoid the periodic voltage fluctuations caused by the non-ideal characteristics of the charge pump directly acting on the voltage-controlled oscillator, which would generate significant reference spurs, the low-jitter phase-locked loop for ultra-high-speed sampling in this embodiment, based on the traditional dual-path charge-pump phase-locked loop, directly inputs the voltage signal output by the low-pass filter into the integral path and the proportional path, stores the charge output by the charge pump on the sampling capacitor C1, and does not tune the voltage-controlled oscillator until the switch S2 for controlling charge sharing is turned on, thus avoiding the ripple caused by the non-ideal characteristics of the charge pump from acting on the voltage-controlled oscillator and significantly optimizing the reference spurs; the integral path uses a transconductance charge pump and C I in a cascaded form to provide a zero point for the loop gain, ensuring the stability of the phase-locked loop system. At the same time, due to the existence of large C I , the voltage ripple of the integral path is greatly suppressed, and the reference spurs output by the phase-locked loop mainly come from the proportional path; also, since the voltage ripple of the proportional path has been suppressed by the foregoing process, the overall reference spurs of the phase-locked loop system are significantly optimized.
[0034] Exemplarily, the low-jitter phase-locked loop for ultra-high-speed sampling in this embodiment uses the standard 65nm CMOS process and achieves both low jitter and low reference spurs while having a strong locking ability.
[0035] As Figure 2 shown, Figure 2 is a schematic diagram of the noise model of the low-jitter phase-locked loop for ultra-high-speed sampling provided by an embodiment of the present invention.
[0036] It should be noted that the noise of each module refers to the noise of each module itself within the phase-locked loop system. They can be voltage noise, current noise, or phase noise. The noise of each module passes through its respective noise transfer function and finally appears at the output of the phase-locked loop, manifested as phase noise.
[0037] Therefore, in this embodiment, by establishing a linear model of the phase-locked loop system in the s domain and analyzing the noise transfer function from each module to the output, the overall output noise of the phase-locked loop system is obtained. Thus, the loop bandwidth of the phase-locked loop system can be adjusted according to the overall output noise and the noise transfer function from each module to the output, so that the in-band noise and the out-of-band noise reach a balance and the optimal jitter performance is achieved.
[0038] Exemplarily, the transfer function from the reference clock noise to the output is:
[0039]
[0040] Among them, is the phase noise introduced by the reference clock; is the noise equivalent to the output end of the phase noise of the reference clock itself; N is the frequency division ratio; G(s) is the loop gain of the phase-locked loop system.
[0041]
[0042] Among them, K slope (s) is the gain of the time-amplified frequency discriminator and phase detector and the charge pump, K ta is the gain of the time error amplifier in the time-amplified frequency discriminator and phase detector; I cp is the output current of the charge pump; T ref is the reference clock period; C1 is the capacitance value of the main sampling capacitor C1 in the master-slave sampling filter; R2 is the resistance value of the equivalent resistance R2 of the master-slave sampling filter, s is the complex variable jω; C2 is the capacitance value of the slave sampling capacitor C2; R3 is the resistance value of the resistor R3 in the low-pass filter; C3 is the capacitance value of the capacitor C3 in the low-pass filter; g m is the gain of the transconductance charge pump; C I is the capacitance value of the load capacitor C I of the transconductance charge pump; K vco_I is the gain of the integral path of the voltage-controlled oscillator; K vco_P is the gain of the proportional path of the voltage-controlled oscillator.
[0043] The transfer function from the frequency divider DIV to the output end is:
[0044]
[0045] Among them, is the phase noise equivalent to the output end of the phase noise of the frequency divider itself; is the phase noise introduced by the frequency divider.
[0046] It can be found that the reference clock noise and the frequency divider have the same transfer function, and its DC gain is related to the frequency division ratio. After the frequency increases to a certain extent, it decreases at a rate of 60 dB per decade with the increase of frequency.
[0047] The transfer function from the charge pump CP to the output end is (here, the noise jointly introduced by the time-amplified frequency discriminator and phase detector TAPFD, the charge pump CP, the master-slave sampling filter PSSF, and the low-pass filter LPF is equivalent to the output end of the low-pass filter LPF):
[0048]
[0049] Among them, is the phase noise equivalent to the output end of the time-amplified frequency discriminator and phase detector, charge pump, master-slave sampling filter, and low-pass filter; is the voltage noise introduced by the time-amplified frequency discriminator and phase detector, charge pump, master-slave sampling filter, and low-pass filter.
[0050] The DC gain of the noise transfer function of the charge pump CP is related to the frequency division ratio, the gain of the time-amplified frequency discriminator and phase detector TAPFD, and the gain of the charge pump CP. After the frequency increases to a certain extent, it decreases at 40 dB per decade with the increase of frequency.
[0051] Transconductance charge pump G m The transfer function to the output end is:
[0052]
[0053] Among them, is the phase noise equivalent to the output end of the transconductance charge pump's own current noise; is the current noise introduced by the transconductance charge pump; K vco_I is the gain of the integral path of the voltage-controlled oscillator.
[0054] The amplitude-frequency characteristic of the noise transfer function of the voltage-controlled oscillator VCO rises at 40 dB per decade when its frequency is small, and the gain becomes 1 when the frequency increases to a certain extent.
[0055] The transfer function of the voltage-controlled oscillator VCO to the output end is:
[0056]
[0057] Among them, is the phase noise equivalent to the output end of the voltage-controlled oscillator's own phase noise; is the phase noise introduced by the voltage-controlled oscillator.
[0058] The total noise of the phase-locked loop is the linear superposition of the noises of each module at the output end:
[0059]
[0060] Among them, is the total phase noise at the output end.
[0061] Mainly contributes to the out-of-band noise of the phase-locked loop system; the remaining each module respectively contributes to the in-band noise of the phase-locked loop system. By adjusting K ta 、I cp 、C I 、g m 、K vco_I 、C1 and K vco_PParameters such as [parameters] are used to adjust the loop bandwidth of the phase-locked loop system, so that the in-band noise and out-of-band noise reach a balance, achieving optimal jitter performance. For example, increasing K ta can increase the loop bandwidth and further suppress the phase noise introduced by the voltage-controlled oscillator. However, it will also weaken the suppression of the noise introduced by other circuit modules, and these modules mainly contribute to the in-band noise.
[0062] It should be noted that in this embodiment, a time error amplifier is used in the time-amplified frequency discriminator and phase detector. Due to the presence of the time error amplifier, the gain of the frequency discriminator and phase detector is increased from 1 to K ta , increasing the forward gain of the phase-locked loop by K ta , increasing the suppression of the in-band noise of the phase-locked loop system by 20log 10 K ta , making up for the problem of insufficient charge pump gain.
[0063] The low-jitter phase-locked loop for ultra-high-speed sampling of the present invention stores the charge output by the charge pump on the sampling capacitor. After charge sharing and low-pass filtering, it enters the proportional path and the integral path simultaneously, avoiding the ripple generated by the non-ideal characteristics of the charge pump from acting on the voltage-controlled oscillator, blocking the direct participation of the charge pump output in the tuning of the voltage-controlled oscillator, and adopting the method of indirectly controlling the voltage-controlled oscillator by the charge pump output, significantly optimizing the reference spurs and completely eliminating the influence of the non-ideal characteristics of the charge pump on the reference spurs. At the same time, by using a time error amplifier, the main source of in-band noise is no longer the charge pump but the time error amplifier, and the means of reducing in-band noise changes from optimizing the charge pump to optimizing the time error amplifier, reducing the difficulty of optimizing in-band noise. Finally, by adjusting the loop bandwidth of the phase-locked loop system, the in-band noise and out-of-band noise reach a balance, achieving both low jitter and low reference spurs at the same time.
[0064] In other words, through the innovative design of indirectly controlling the voltage-controlled oscillator by the charge pump output and the introduction of the time error amplifier, the present invention significantly improves the performance of the phase-locked loop system, achieves low jitter and low reference spurs, and provides a new solution for the field of wireless communication technology.
[0065] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the element. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "above", "below", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.
[0066] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.
Claims
1. A low-jitter phase-locked loop for ultra-high-speed sampling, characterized in that: include: Time amplification frequency detector, phase detector, charge pump, master-slave sampling filter, low-pass filter, transconductance charge pump, voltage-controlled oscillator; The time-amplified frequency-phase detector, the charge pump, the master-slave sampling filter and the low-pass filter are connected in sequence; within a reference cycle, the charge output by the charge pump is first stored in the sampling capacitor in the master-slave sampling filter, and after stopping sampling, the charge is shared with the connected subsequent circuit modules to achieve indirect control of the voltage-controlled oscillator by the charge pump; A proportional path and an integral path connected in parallel are formed after the low-pass filter; in the proportional path, the output signal of the low-pass filter enters a voltage-controlled oscillator; in the integral path, the output signal of the low-pass filter enters a transconductance charge pump; The time error amplifier in the time amplification frequency detector is used to increase the gain of the time amplification frequency detector to suppress the in-band noise of the phase-locked loop system.
2. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 1, characterized in that: The time-amplifying phase-frequency detector inputs a phase signal and amplifies the phase signal; The charge pump and the master-slave sampling filter are used to convert the amplified phase signal into a voltage signal, and filter the voltage signal in the low-pass filter.
3. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 1, characterized in that: The charge pump comprises: a current source and a capacitor C P ; The two current sources are connected in series, and each current source is connected in series with a switch, and the capacitor C P The first end of the capacitor C is connected to the first end and the second end of the two switches in series. P The second end is grounded.
4. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 1, characterized in that: The master-slave sampling filter comprises: a switch S1, a sampling capacitor C1, a switch S2 and a capacitor C2; the first end of the switch S1, the first plate of the sampling capacitor C1 and the first end of the switch S2 are connected; the second end of the switch S1 is connected to a reference voltage end; The second end of the sampling capacitor C1 is grounded; the second end of the switch S2 is connected to the first plate of the capacitor C2, and the second plate of the capacitor C2 is grounded.
5. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 4, characterized in that: The low-pass filter includes: a resistor R3 and a capacitor C3; the first end of the resistor R3 is connected to the second end of the switch S2, the first plate of the capacitor C3 is connected to the second end of the resistor R3, and the second plate of the capacitor C3 is grounded.
6. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 1, characterized in that: Also includes: Capacitor C I The capacitor C I The first electrode plate is connected to the output end of the transconductance charge pump, and the capacitor C I The second plate is grounded.
7. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 1, characterized in that: Also includes: Crossover; The frequency divider is connected to the voltage-controlled oscillator and the time-amplified frequency detector and phase detector respectively, and is used to adjust the frequency of the output signal of the voltage-controlled oscillator according to the frequency division ratio, and input the output signal of the voltage-controlled oscillator after adjusting the frequency into the time-amplified frequency detector and phase detector.
8. The low-jitter phase-locked loop for ultra-high-speed sampling according to claim 1, characterized in that: Also includes: Multiple pulse generator; The multiple pulse generator is connected to the time amplification frequency detector and the master-slave sampling filter respectively, and is used to control the sampling and charge sharing of the master-slave sampling filter.