Vehicle-mounted multi-communication protocol test mainboard

Abstract

The invention provides a vehicle-mounted multi-communication protocol test mainboard, and the mainboard comprises a CANFD communication module which is used for transmitting a test frame to a to-be-tested device under the condition that a CANFD test instruction is received; receiving a response frame corresponding to the test frame sent by the to-be-tested device; the vehicle-mounted Ethernet communication module is used for converting the standard Ethernet test signal into a vehicle-mounted Ethernet test signal and sending the vehicle-mounted Ethernet test signal to the equipment to be tested; receiving a vehicle-mounted Ethernet response signal which is sent by the equipment to be tested and corresponds to the vehicle-mounted Ethernet test signal, and converting the vehicle-mounted Ethernet response signal into a standard Ethernet response signal; the processor module is used for generating a CANFD test instruction and a standard Ethernet test signal; and generating an equipment test report of the to-be-tested equipment according to the response frame and the standard Ethernet response signal. According to the invention, the CANFD communication module and the vehicle-mounted Ethernet communication module are integrated, and the processor module is matched to carry out coordination control, so that automatic joint testing of different communication protocols is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle communication, and particularly to a vehicle multi-communication protocol test main board. Background Art

[0002] With the continuous increase in the number of automotive electronic control units, future vehicle systems will increasingly rely on multiple network protocols for efficient data exchange and collaborative control. Among them, Controller Area Network (CAN) and automotive Ethernet have become the mainstream communication methods. To meet the requirements of different systems for bandwidth, real-time performance, and functional safety, a hybrid communication network architecture has gradually become a trend.

[0003] However, existing test systems usually adopt discrete CAN test equipment and Ethernet test equipment, which not only increase the hardware cost and system integration difficulty, but also limit the joint test ability and automation level in a multi-protocol environment. In addition, the separate test scheme has significant deficiencies in handling cross-protocol data synchronization, real-time response monitoring, and consistency verification, and it is difficult to meet the actual requirements of the new generation of intelligent connected vehicles for efficient communication testing. Therefore, there is an urgent need for a test main board and a supporting system that integrate CAN and Ethernet communication capabilities, which can realize functions such as unified software control, synchronous triggering, protocol collaboration, and hybrid log collection, so as to significantly improve the test efficiency, accuracy, and intelligence level of vehicle network systems. Summary of the Invention

[0004] The purpose of the present invention is to provide a vehicle multi-communication protocol test main board, which is used to solve the technical problems in the prior art such as the separation of the CAN test system and the Ethernet test system, poor communication protocol compatibility, high system integration complexity, inconsistent test processes, and difficulty in realizing cross-protocol synchronization.

[0005] To achieve the above purpose, the present invention provides a vehicle multi-communication protocol test main board, including: A CANFD communication module, which is used to send a test frame to a device under test when receiving a CANFD test instruction; and receive a response frame corresponding to the test frame sent by the device under test; A vehicle Ethernet communication module, which is used to convert a standard Ethernet test signal into a vehicle Ethernet test signal and send the vehicle Ethernet test signal to the device under test; receive a vehicle Ethernet response signal corresponding to the vehicle Ethernet test signal sent by the device under test, and convert the vehicle Ethernet response signal into a standard Ethernet response signal; A processor module, which is used to generate a CANFD test instruction and a standard Ethernet test signal; and generate a device test report of the device under test according to the response frame and the standard Ethernet response signal; Among them, the test frame includes a data frame, a control instruction frame, a fault frame, and an error frame, and the in-vehicle Ethernet test signal includes a data packet, a control signal, a fault signal, and an error signal.

[0006] Further, the CANFD communication module includes: An FPGA chip, configured to generate a test frame when receiving the CANFD test instruction; A plurality of CAN transceivers, configured to send the test frame to the device under test; receive the CAN response frame corresponding to the test frame sent by the device under test, and convert the CAN response frame into a response frame compatible with the PCIe bus.

[0007] Further, the CANFD communication module further includes: An SPI Flash chip, configured to store the startup firmware configuration information and communication logic configuration information of the FPGA chip; The FPGA chip is further configured to perform startup configuration according to the startup firmware configuration information and communication logic configuration information.

[0008] Further, the in-vehicle Ethernet communication module includes: An in-vehicle Ethernet transceiver, configured to convert the standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device under test; A general Ethernet transceiver, configured to receive the in-vehicle Ethernet response signal corresponding to the in-vehicle Ethernet test signal sent by the device under test, and convert the in-vehicle Ethernet response signal into a standard Ethernet response signal.

[0009] Further, the in-vehicle Ethernet communication module further includes: A DIP switch, configured to set the in-vehicle Ethernet communication module as the master node when in the first switch state; set the in-vehicle Ethernet communication module as the slave node when in the second switch state.

[0010] Further, the in-vehicle Ethernet communication module further includes: A signal indicator light, configured to go out when the in-vehicle Ethernet transceiver loses power, light up when the in-vehicle Ethernet transceiver is powered on, and blink at a preset frequency when the in-vehicle Ethernet transceiver is working.

[0011] Further, the in-vehicle multi-communication protocol test main board further includes: A power conversion module is used to convert an external first voltage into a second voltage based on the pressing state of a start button and supply power to the in-vehicle multi-communication protocol test main board with the second voltage when the in-vehicle multi-communication protocol test main board is configured in a first start mode; and when the in-vehicle multi-communication protocol test main board is configured in a second start mode, convert the external first voltage into a second voltage based on the external power supply state and supply power to the in-vehicle multi-communication protocol test main board with the second voltage.

[0012] Further, the in-vehicle multi-communication protocol test main board further includes: An HDMI display interface is used to convert device test digital image data into high-speed serial differential signals and send the high-speed serial differential signals to a display. The processor module is further used to convert the device test report into device test digital image data.

[0013] Further, the in-vehicle multi-communication protocol test main board further includes: An NVME interface is used to receive configuration information sent by an external storage device and send the device test report to the external storage device. The processor is further used to configure the in-vehicle multi-communication protocol test main board according to the configuration information.

[0014] Further, the in-vehicle multi-communication protocol test main board further includes: A clock module is used to generate a clock signal. The processor is further used to generate a unified timestamp for the response frame and the standard Ethernet response signal according to the clock signal.

[0015] The present invention integrates two mainstream in-vehicle communication technologies, CANFD and in-vehicle Ethernet, and realizes a highly integrated design of the test main board. Compared with traditional discrete test systems, the number of peripheral devices and external wiring harnesses is significantly reduced, the hardware architecture is simplified, not only the physical complexity of the system is reduced, but also the operation and maintenance costs are effectively reduced. The integrated system can optimize the balance between real-time performance and data transmission efficiency in in-vehicle network testing, greatly improving the test efficiency and ensuring that it can meet the test requirements of future more complex in-vehicle network environments. Especially in the R & D process of intelligent connected vehicles and autonomous driving systems, it can better cope with challenges such as high-speed data transmission, high real-time response, and cross-protocol collaborative verification. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a structural block diagram of a vehicle-mounted multi-communication protocol test main board of the present invention; Figure 2 It is a structural block diagram of the CANFD communication module of the present invention; Figure 3 It is a structural block diagram of the vehicle-mounted Ethernet communication module of the present invention. Specific embodiments

[0018] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the accompanying drawings.

[0019] As Figure 1 shown, the present invention provides a vehicle-mounted multi-communication protocol test main board, including: A CANFD communication module, configured to send a test frame to a device under test when receiving a CANFD test instruction; receive a response frame corresponding to the test frame sent by the device under test; A vehicle-mounted Ethernet communication module, configured to convert a standard Ethernet test signal into a vehicle-mounted Ethernet test signal and send the vehicle-mounted Ethernet test signal to the device under test; receive a vehicle-mounted Ethernet response signal corresponding to the vehicle-mounted Ethernet test signal sent by the device under test and convert the vehicle-mounted Ethernet response signal into a standard Ethernet response signal; A processor module, configured to generate a CANFD test instruction and a standard Ethernet test signal; generate a device test report of the device under test according to the response frame and the standard Ethernet response signal; Wherein, the test frame includes a data frame, a control instruction frame, a fault frame, and an error frame, and the vehicle-mounted Ethernet test signal includes a data packet, a control signal, a fault signal, and an error signal.

[0020] Specifically, a processor module, a memory module, a CANFD communication module, an in-vehicle Ethernet communication module, a PCIe bus, a power conversion module, and a clock module are provided on the main board. The CANFD communication module and the in-vehicle Ethernet communication module communicate with the processor module through the PCIe bus respectively. The power conversion module is connected to an external power supply through a power interface and adaptively supplies power to the processor module, the CANFD communication module, and the in-vehicle Ethernet communication module. The CANFD communication module is connected to an external device under test through a CAN interface. The in-vehicle Ethernet module is connected to an external device under test through a common Ethernet interface and an in-vehicle Ethernet interface. The processor module is connected to an external display device and an external storage device through an HDMI interface and an NVME interface respectively. Among them, the processor module can adopt an Intel i7 series processor, and the memory module can adopt a DDR4 SODIMM dual in-line memory module.

[0021] The CANFD communication module is used to generate and actively send a test frame including specified content to the device under test in accordance with a preset protocol format when receiving a CANFD test instruction sent by the processor module; wherein, the types of the test frame include but are not limited to data frames, control instruction frames, fault frames, and error frames, and each type of frame can be configured with specific identifiers, data payload lengths, and bit stuffing strategies. In addition, the CANFD communication module is further configured with a response detection and frame filtering mechanism, which is used to listen to the CAN bus in real time and capture the response frame corresponding to the test frame returned by the device under test after sending the test frame; after receiving the response frame, it judges its validity through a verification mechanism, including CRC verification, bit stuffing identification, and frame interval parsing, and uploads the parsed valid frame data to the processor module for subsequent communication performance evaluation, protocol consistency detection, and function response analysis. The in-vehicle Ethernet communication module is configured to implement bidirectional protocol and electrical layer conversion between standard Ethernet and in-vehicle Ethernet compliant with the IEEE 802.3bw (100BASE-T1) or IEEE 802.3bp (1000BASE-T1) specification. Specifically, when receiving a standard Ethernet test signal generated by the processor module, the in-vehicle Ethernet communication module first performs adaptation processing on the test signal, including frame structure reconstruction, data rate adjustment, clock synchronization, and modulation coding, through a protocol conversion unit to generate a test data frame that meets the requirements of in-vehicle Ethernet communication, that is, the in-vehicle Ethernet test signal; then it sends it to the corresponding Ethernet port of the device under test through a physical layer interface circuit. In addition, the in-vehicle Ethernet communication module is further configured with a high-speed listening and frame identification mechanism, which is used to receive in real time the in-vehicle Ethernet response signal corresponding to the above test signal returned by the device under test. After receiving the response signal, it is converted into a standard Ethernet response signal through a reverse protocol conversion process, including frame format restoration, differential signal decoding, signal integrity determination, etc., and uploaded to the processor module. Through the in-vehicle Ethernet communication module, seamless bridging of test signals and response signals between different Ethernet protocols can be achieved, effectively supporting the function and stability testing of in-vehicle Ethernet devices at the physical layer, link layer, and part of the transport layer, and improving the compatibility and coverage of the overall test system. The processor module is used to coordinate and control the multi-communication protocol test process of the entire test mainboard, built-in with support for the CANFD protocol and Ethernet protocol stack, and integrated with a test task scheduling engine, which can generate specific CANFD test instruction sets and standard Ethernet test signal sequences according to a preset test template or user-defined parameters. The CANFD test instructions and standard Ethernet test signal sequences can include content such as function verification commands, bandwidth stress packets, boundary condition trigger frames, and abnormal simulation data to ensure test coverage. During the test process, the processor module is also configured with a response frame parsing unit and a data consistency analysis logic.On the one hand, the processor module receives the response frame sent back from the CANFD communication module, and performs content analysis, frame header recognition, timestamp extraction and anomaly detection on it; on the other hand, it receives the standard Ethernet response signal converted by the vehicle Ethernet communication module, and performs protocol-level verification, data integrity analysis and response delay calculation on it. After completing data collection and analysis, the processor module comprehensively evaluates the test results based on multiple dimensions, such as communication delay, response accuracy, protocol consistency, frame loss rate, error type and frequency, and automatically generates a structured equipment test report. The equipment test report is displayed in parallel in the form of charts and data, and supports exporting to multiple formats for subsequent archiving, comparison or quality analysis. In addition, the processor module also supports uploading the report results to a remote server or cloud platform through external interfaces such as USB, WiFi or on-board diagnostic ports, which facilitates the centralized management and statistical analysis of large-scale equipment test data.

[0022] The test frame is constructed based on the CANFD protocol, including data frames, control command frames, fault frames and error frames. The data frame is used to simulate the transmission of normal business data in the actual vehicle communication environment, including the payload field, frame identifier, data length code and cyclic redundancy check field, which is used to test the data receiving and sending capabilities of the device; the control command frame is used to trigger the device under test to execute specific control logic or state switching, such as start / stop commands, mode switching commands, etc.; the fault frame is used to simulate standard fault conditions that occur in the bus, such as frame loss, interruption, arbitration loss, etc., to verify the fault tolerance mechanism of the device under abnormal bus conditions; the error frame is used to inject illegal format frames or CRC error frames to test the device's recognition and response capabilities to protocol errors, including whether to trigger the error handling process or error counter. The in-vehicle Ethernet test signal is constructed based on the in-vehicle Ethernet protocol, such as BroadR-Reach / 100BASE-T1, and includes data packets, control signals, fault signals and error signals. Data packets carry valid data at the service layer or application layer, and test the data throughput and protocol parsing capabilities of the equipment. Control signals include instruction packets based on Ethernet control protocols, which are used to simulate network management instructions, flow control mechanisms, and QoS triggers. Fault signals simulate network anomalies such as packet loss, retransmission, and link disconnection, and test the equipment's ability to perceive and recover from physical layer and link layer anomalies. Error signals are used to inject illegal Ethernet frames to evaluate the equipment's protocol fault tolerance, error detection accuracy, and defense mechanisms. By flexibly combining multiple types of test frames and test signals in the test process, a highly complex vehicle communication simulation scenario that approximates the actual use environment is constructed, so that the protocol support integrity, anomaly handling capabilities, and stability robustness of the equipment to be tested can be comprehensively evaluated.

[0023] Preferably, refer to Figure 2 , the CANFD communication module includes: An FPGA chip, which is used to generate a test frame when receiving the CANFD test instruction; A plurality of CAN transceivers, which are used to send the test frame to the device under test; receive the CAN response frame corresponding to the test frame sent by the device under test, and convert the CAN response frame into a response frame compatible with the PCIe bus.

[0024] Specifically, the CANFD communication module includes an FPGA chip, an SPI Flash chip, reset and clock, power supply, and four CAN transceivers, and the four CAN transceivers are connected to four CAN buses. The FPGA chip, namely the Field-Programmable Gate Array, is configured to generate test frames compliant with the CANFD protocol specification based on its reconfigurable logic resources under the condition of receiving CANFD test instructions issued by the processor module. Inside the FPGA chip, a CANFD frame construction logic unit is pre-deployed, which dynamically assembles test frame fields according to the instruction content, including frame start bit, arbitration field, control field, data field, CRC check segment, and frame end flag bit. The FPGA chip can generate various types of frame structures according to test requirements, including data frames, control frames, fault simulation frames, and error injection frames in standard format and extended format. In addition, the FPGA chip is also integrated with a frame scheduling controller and a timestamp management unit, supporting periodic transmission, event-triggered transmission of test frames, and precise control of frame intervals, and can meet the requirements of high-bandwidth and high-real-time communication tests. With its hardware-level parallel processing ability, the FPGA chip greatly improves the speed and flexibility of test frame generation and is the key frame generation execution unit in the entire CANFD test process. Several CAN transceivers respectively correspond to multiple CANFD channels, and each transceiver includes a differential signal driving unit, a receiving filter, a bit-level electrical protection module, and interface buffer control logic for realizing bidirectional data communication between the in-vehicle CAN bus physical layer and the main control system logic layer. After receiving the test frame generated by the FPGA chip, the CAN transceiver performs level conversion and differential drive output on the frame and sends the test frame to the device under test through the standard CAN bus topology. In the receiving direction, the CAN transceiver can monitor the bus status in real time and identify the CAN response frame corresponding to the above test frame returned by the device under test. After the CAN response frame completes differential signal restoration and logic level conversion through the transceiver, it will be further transmitted to the subsequent PCIe protocol adaptation unit. During this process, the CAN response frame will be encapsulated into a data frame format compatible with the PCIe bus protocol according to the predefined frame packing rules and transmitted to the processor module or the main control system through the high-bandwidth PCIe channel for subsequent data parsing and test analysis. To improve the concurrent processing ability of the system and the multi-channel data consistency, the CAN transceiver can correspond to multiple independent CAN channels, support parallel testing and data feedback of multiple devices under test or multiple CAN nodes, and each transceiver is configured with an error detection and frame verification mechanism, which can perform real-time warning and status reporting on situations such as abnormal frame format and electrical layer faults, ensuring the stability and traceability of the entire communication test process.

[0025] The CANFD communication module is externally connected through the CAN interface. The CAN interface adopts the form of a DB9 external interface. The signal pins of each CAN interface are configured according to the CAN specifications 2.0A / B and the FD standard. Pin 2 is the CAN_L pin, which is used to transmit the low-level signal of the CAN bus. As part of the differential signal, it participates in the transmission of data frames. Pin 7 is the CAN_H pin, which is used to transmit the high-level signal of the CAN bus. Together with CAN_L, it forms a differential signal to ensure the reliability and anti-interference ability of data transmission. The CAN interface complies with the CAN specifications 2.0A / B, supports the traditional standard frame format and extended frame format, and has a maximum supported transmission rate of 1 Mbit / s, which is suitable for traditional in-vehicle bus communication and device testing. The CAN interface further supports the CAN FD protocol, allowing the use of an extended data field. The effective data length of each data frame can be extended to 64 bytes, resulting in a significant performance improvement compared to CAN 2.0. The maximum supported transmission rate of CAN FD is 12 Mbit / s, which is suitable for test scenarios requiring high-speed data exchange, especially for the large data volume transmission requirements in modern in-vehicle electronic devices. While adopting the differential signal transmission mode, the electrical design of the interface meets the anti-interference requirements of CAN communication, effectively avoiding data loss or error codes caused by electromagnetic interference or long-line transmission, and ensuring communication stability in the complex electromagnetic environment of the in-vehicle system. The DB9 interface form, as a widely used industrial standard, has wide compatibility and supports convenient connection with other devices compliant with the DB9 standard. At the same time, the main board can perform parallel testing through multiple CAN interfaces, thus improving the testing efficiency. Each CAN interface supports real-time monitoring and fault diagnosis functions. The system can capture error frames, bus conflicts, bit errors, etc. during transmission and provide detailed error codes to help developers quickly locate communication faults. Through this CAN interface in the DB9 form, the in-vehicle multi-communication protocol test main board can efficiently and reliably test the CAN protocol, meet the requirements of traditional in-vehicle communication and modern in-vehicle systems for high-speed data exchange, and provide strong technical support for the development and verification of automotive electronic systems.

[0026] The peripheral circuit of the FPGA chip also includes a clock module and a reset control circuit, which are used to ensure that the FPGA chip has a stable and reliable timing reference and reset control ability during power-on initialization, logic configuration, and normal operation. The clock module includes a high-precision crystal oscillator, a clock driver chip, and an optional clock buffer or clock divider, which are used to provide a stable system main clock signal to the FPGA chip. The clock signal serves as the timing reference for the operation of the internal logic blocks of the FPGA, supports multiple frequency configuration schemes, and can dynamically switch between high-frequency and low-frequency clock sources according to different application scenarios. The clock module also collaborates with the unified clock management system of the motherboard to achieve cross-module clock synchronization and unified timestamp allocation. The reset control circuit includes a power-on reset circuit, an external reset input interface, a soft reset control logic, and a reset trigger mechanism linked to the processor, ensuring that the FPGA can achieve deterministic initialization behavior in key states such as power-on, abnormal recovery, or configuration update. The reset circuit also supports a multi-level reset strategy, including global reset, local logic block reset, and configuration logic reset, to improve the stability and fault recovery ability of the system. Through the cooperation of the peripheral circuit, it is ensured that the FPGA chip has a stable working timing and a controllable state recovery mechanism during the configuration, operation, and collaborative communication processes in the motherboard system, providing a reliable hardware foundation for subsequent functional modules such as CANFD test frame generation, Ethernet protocol conversion, and data processing.

[0027] Preferably, referring to Figure 2 , the CANFD communication module further includes: an SPI Flash chip, which is used to store the startup firmware configuration information and communication logic configuration information of the FPGA chip; The FPGA chip is also used to perform startup configuration according to the startup firmware configuration information and communication logic configuration information.

[0028] Specifically, as a non-volatile storage device, the SPI Flash chip is connected to the FPGA chip through a standard SPI bus interface and is used to store the firmware configuration data and communication logic configuration file required for the FPGA to load during the power-on startup process. The startup firmware preset in the SPI Flash chip includes the bitstream information of the FPGA, which is used to define the initialization configuration of the FPGA logic resources, such as the test frame generation module, frame scheduling controller, timestamp unit, interface control logic, etc. The SPI Flash chip also stores communication logic configuration information that can be dynamically updated by the processor, including CANFD frame format templates and injection rules, frame scheduling parameters under different test scenarios, multi-channel configuration parameters, and test state machine configuration and event response logic, etc. When the system is powered on, the FPGA chip actively accesses the Flash chip through the SPI master device interface, loads the configuration data in sequence, and completes the logic reconstruction to ensure that the FPGA has the complete ability to execute test tasks. By integrating the SPI Flash chip, not only the maintainability and flexibility of the system are improved, but also users are allowed to remotely update or online reconfigure the SPI Flash through the processor module or external debugging interface, so as to quickly adapt to the evolution requirements of different test application scenarios or protocol versions. The FPGA chip is further used to execute the system startup configuration process according to the startup firmware configuration information and communication logic configuration information stored in the SPI Flash chip during the power-on initialization stage. Through its built-in startup control logic, after detecting the system power-on or reset signal, the FPGA chip first loads the corresponding bitstream file from the SPI Flash to complete the basic configuration of its programmable logic unit, I / O resources, clock distribution network, and interface control module, and realizes the dynamic construction of the logic architecture. After completing the basic startup, the FPGA chip further parses and applies the communication logic configuration information to complete the fine configuration of multiple communication sub-modules. These configuration parameters can be dynamically updated according to specific test scenarios, including frame type definition, injection timing, priority setting, response determination rules, etc., to ensure that the FPGA has highly flexible communication test logic during operation. Through the above mechanism, the FPGA chip not only undertakes the tasks of hardware-level test frame generation and protocol execution, but also acts as a custom reconfigurable core controller for the entire system, significantly improving the adaptability, scalability, and maintenance efficiency of the test motherboard in multi-protocol and complex scenarios.

[0029] Preferably, referring to Figure 3 , the in-vehicle Ethernet communication module includes: An in-vehicle Ethernet transceiver, which is used to convert the standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device under test; A general Ethernet transceiver is used to receive an in-vehicle Ethernet response signal corresponding to the in-vehicle Ethernet test signal sent by the device under test, and convert the in-vehicle Ethernet response signal into a standard Ethernet response signal.

[0030] Specifically, the in-vehicle Ethernet communication module includes an in-vehicle Ethernet transceiver, a general Ethernet transceiver, a power supply, a DIP switch, and an LED indicator. The in-vehicle Ethernet transceiver is used to implement the conversion of electrical signals and encoding mechanisms between standard Ethernet and in-vehicle Ethernet at the physical layer, and is one of the core components in the in-vehicle Ethernet communication module. The in-vehicle Ethernet transceiver is compatible with a variety of mainstream in-vehicle Ethernet standards, including but not limited to 100BASE-T1 and 1000BASE-T1, supports single-pair unshielded twisted-pair transmission, can effectively reduce the wiring complexity and improve the anti-interference ability, and meets the requirements of the complex in-vehicle electromagnetic environment. On the transmission path, the in-vehicle Ethernet transceiver receives the standard Ethernet test signal output from the protocol conversion module and converts it into a signal format that conforms to the in-vehicle Ethernet physical layer standard, specifically including operations such as differential signal modulation, level conversion, cable equalization, synchronous encoding, and CRC check bit insertion. After completing the signal conversion, the corresponding test signal is sent to the device under test through the in-vehicle Ethernet physical channel. The in-vehicle Ethernet transceiver has characteristics such as low latency, wide-temperature operation, and high jitter tolerance, and supports functions such as PHY Loopback, self-diagnosis, link detection, and error injection, and can cooperate with the test master control module to perform link stability tests, response time measurements, and signal integrity verification. In addition, its built-in ESD protection, EMC suppression, and cable short-circuit protection mechanisms improve the overall safety and reliability of the system, ensuring that the device under test will not be electrically damaged during the test process. The general Ethernet transceiver, also known as an Ethernet PHY chip, is used to complete the physical layer conversion of the in-vehicle Ethernet response signal returned by the device under test into a standard Ethernet response signal. The general Ethernet transceiver is mainly deployed in the receiving path of the Ethernet communication module. Its input interface is connected to the physical output layer of the in-vehicle Ethernet transceiver, and its output interface is docked with the MAC control unit of the processor module, usually based on standard interface formats such as MII, RMII, RGMII, or SGMII. The general Ethernet transceiver has the physical layer decoding ability, can demodulate the encoding mechanism in the in-vehicle Ethernet response signal, complete operations such as signal level restoration, error correction, link alignment, and clock recovery, and output a response signal compatible with the standard MAC layer after restoring it to the standard Ethernet data format. To ensure communication stability in high-interference and high-speed scenarios, the general Ethernet transceiver also integrates a low-jitter clock management unit, an automatic equalizer, a crosstalk suppressor, and a link quality monitoring module, which can monitor the communication quality while maintaining data integrity and issue diagnostic prompts for severe signal attenuation, inter-symbol interference, or cable faults. After the response signal is converted by this module, it can be parsed by the processor module or the subsequent diagnostic system for generating corresponding test reports or further fault analysis. Through the introduction of the in-vehicle Ethernet communication module, seamless docking between in-vehicle Ethernet and standard Ethernet at the physical level is achieved, enhancing the adaptability and scalability of the test motherboard of the present invention in different network protocol environments.

[0031] Preferably, refer to Figure 3 , the vehicle Ethernet communication module also includes: The dip switch is used to set the vehicle-mounted Ethernet communication module as a master node when it is in a first switch state; and to set the vehicle-mounted Ethernet communication module as a slave node when it is in a second switch state.

[0032] Specifically, the vehicle Ethernet communication module also includes a dip switch device for realizing the physical layer configuration and fast switching of the communication module node role. The dip switch is a multi-position mechanical switch or a double-position double-throw dip switch component, which can switch the internal working mode of the module through the physical toggle state, and the FPGA or processor module performs state acquisition and identification when the system is powered on or reset. When the dip switch is in the first switch state, the vehicle Ethernet communication module is set to the master node mode, in which the module will actively send a synchronization signal, a frame start signal or a link establishment request, and control the timing and handshake logic in the communication initialization process; when the dip switch is in the second switch state, the communication module is set to the slave node mode, in which the module will be in a listening state, waiting for the master node to initiate a communication handshake and respond to the synchronization command and test frame signal issued by it. The physical state of the dip switch can be read in real time by the node identification logic unit in the system initialization phase, and the relevant control flags are set through the internal register, thereby driving the Ethernet PHY chip, the MAC layer protocol state machine and the link management controller to enter the corresponding master / slave working state. The configuration results of the DIP switches can also be fed back to the processor module to automatically match the node roles when generating test data frames or response frames, thereby ensuring the consistency of communication topology and protocol timing during the test. By introducing the hardware-level master-slave node configuration mechanism, the system's adaptability to different automotive Ethernet communication topologies is not only improved, but also the user's operational complexity in actual test deployment is simplified, avoiding repeated programming or debugging processes, and improving test efficiency and reliability.

[0033] Preferably, refer to Figure 3 , the vehicle Ethernet communication module also includes: A signal indicator light is used to turn off when the vehicle-mounted Ethernet transceiver loses power, light up when the vehicle-mounted Ethernet transceiver is powered, and flash at a preset frequency when the vehicle-mounted Ethernet transceiver is working.

[0034] Specifically, the in-vehicle Ethernet communication module further includes a signal indicator unit, namely an LED indicator, which is used to visually feedback and real-time indicate the power status and operating status of the in-vehicle Ethernet transceiver. The signal indicator is preferably a low-power and high-brightness LED component, connected to the transceiver power control path and the operating status monitoring module, and can exhibit different indication behaviors in different working states, thus providing an intuitive means for testers to identify the module operating status. When the in-vehicle Ethernet transceiver loses power, the signal indicator is in the off state, indicating that the module is not working or there is a power supply fault; when the transceiver is powered on but the communication link is not activated, the indicator is in the always-on state, indicating that the transceiver has the ability to prepare for communication; when the transceiver is in the normal working state, that is, the physical link has been established and is participating in the transceiver of communication frames, the indicator blinks periodically at a preset frequency, and the preset frequency can be set to be related to the data packet sending frequency or the link heartbeat frequency to reflect the real-time communication activity. To improve the system reliability, the signal indicator control unit also integrates overvoltage protection, abnormal state latching and status feedback interfaces, which can interact with the main control processor. When detecting abnormal power-off, short circuit or communication failure of the transceiver, it gives an alarm prompt through abnormal mode flashing, such as fast flashing, slow flashing, double flashing. In addition, the signal indicator unit is arranged at a prominent position on the test main board, and can enhance the human-computer interaction friendliness by means of silk screen labels, color differentiation, etc., improving the on-site debugging efficiency and the accuracy of fault troubleshooting.

[0035] The in-vehicle Ethernet communication module is connected to the external device under test through the in-vehicle Ethernet interface. The in-vehicle Ethernet interface adopts the HMTD or MATEnet external interface form. Each in-vehicle Ethernet interface provides reliable network communication through a standardized physical connection, supporting data transmission and protocol testing in the in-vehicle Ethernet system. The HMTD adopts a high-performance HMTD connector, which is designed for high-speed data transmission, with excellent anti-interference ability and stability. Through optimized contact design and high-temperature resistance and corrosion resistance characteristics, the HMTD interface adapts to the extreme working conditions in the in-vehicle environment. The MATEnet interface adopts the MATEnet standardized connection method, adapting to various configuration requirements of the in-vehicle Ethernet. The MATEnet connector has high bandwidth capabilities, supports the auto-negotiation function, can intelligently switch the transmission rate according to the transmission requirements, and is compatible with various in-vehicle Ethernet devices.

[0036] Preferably, referring to Figure 1 , the in-vehicle multi-communication protocol test main board further includes: A power conversion module is used to convert an external first voltage into a second voltage based on the pressing state of a start button and supply power to the vehicle-mounted multi-communication protocol test main board with the second voltage when the vehicle-mounted multi-communication protocol test main board is configured in the first start mode; and convert the external first voltage into a second voltage based on the external power supply state and supply power to the vehicle-mounted multi-communication protocol test main board with the second voltage when the vehicle-mounted multi-communication protocol test main board is configured in the second start mode.

[0037] Specifically, the vehicle-mounted multi-communication protocol test main board further includes a power conversion module, which is used to achieve voltage adaptive conversion and modular power supply control according to different start modes, ensuring that the test main board can be stably started and enter the normal working state under various power supply scenarios. When the test main board is configured in the first start mode, such as local debugging or independent power-on mode, the power conversion module receives the first voltage from the external power input interface, preferably a 12V or 24V DC input voltage, and when it detects that the start button is pressed, it converts the first voltage into the second voltage required by the system through a voltage conversion circuit, such as a buck DC-DC converter or an LDO voltage regulator module, and outputs multiple regulated voltages such as 5V, 3.3V or 1.8V, etc., to provide stable power supply for all core functional units including the processor module, FPGA chip, and communication module. When the test main board is configured in the second start mode, such as vehicle-mounted access or remote wake-up mode, the power conversion module does not rely on manual button triggering, but automatically judges the system start condition by detecting the external power supply state signal, such as the vehicle ignition voltage IG or the ACC line voltage. After detecting that the preset power supply threshold is reached, it also converts the external first voltage into the second voltage required for system operation, thus realizing the automatic power-on start of the main board. In this mode, the power module can also work in cooperation with the management controller of the main board to realize the closed-loop control of the power supply timing, soft start curve and voltage rise rate, so as to ensure that each module is powered on in sequence according to the preset timing, and avoid communication interference and equipment damage caused by system instability or voltage mutation. The power conversion module is preferably integrated with reverse connection protection, short-circuit detection, overvoltage and overcurrent protection circuits, and has a power supply state indication function and a fault diagnosis output interface, which can be linked with the main processor for real-time status monitoring and protection strategy adjustment, significantly improving the safety and adaptability of the entire test platform in a multi-power supply environment.

[0038] The power interface of the in-vehicle multi-communication protocol test mainboard adopts a 2PIN latching terminal connector design. The connector is customized for a high-reliability and high-stability power supply system, which can effectively ensure the normal power supply and safe connection of the mainboard in the in-vehicle environment. The connector has a latching function, that is, when connecting, the terminal and the socket form a firm connection through a mechanical locking structure, avoiding contact loosening caused by vibration, external force or long-term use. This design is especially suitable for the high-vibration and high-noise environment in the in-vehicle system, ensuring stable and error-free power transmission. The plug and socket of the connector prevent incorrect connection through a dedicated polarity design, ensuring the correct pairing of positive and negative poles, effectively avoiding problems such as power short circuit, damage to the mainboard or circuit failure caused by incorrect connection. The 2PIN terminal connector selects high-conductivity materials and precision manufacturing processes, making it have excellent contact performance and corrosion resistance, and can withstand the relatively large current loads common in the in-vehicle system, ensuring the high efficiency and low temperature rise of the mainboard power interface during long-term use. The compact design of the 2PIN terminal connector highly matches the miniaturization requirements of in-vehicle electronic devices, and can provide a highly reliable power connection solution in a limited space, facilitating integration into the in-vehicle test mainboard and other electronic modules. The connector has an IPXX protection level and has characteristics such as waterproof and dustproof, adapting to various harsh conditions in the complex in-vehicle environment. By adopting the 2PIN latching terminal connector, the mainboard can ensure the stability and safety of power input, avoid risks such as poor power contact, short circuit or power failure in the in-vehicle system in a high-dynamic environment, and provide a solid power guarantee for the testing work of the whole vehicle or in-vehicle equipment.

[0039] Preferably, referring to Figure 1 , the in-vehicle multi-communication protocol test mainboard further includes: An HDMI display interface, which is used to convert the device test digital image data into high-speed serial differential signals and send the high-speed serial differential signals to the display; The processor module is also used to convert the device test report into device test digital image data.

[0040] Specifically, the in-vehicle multi-communication protocol test main board further includes an HDMI display interface module, which is used to encode the device test digital image data generated by the processor module and convert it into high-speed serial differential signals conforming to the HDMI standard, so as to transmit the image signal to an external display device through a standard HDMI physical interface, realizing the graphical real-time presentation of test data. The HDMI display interface module includes a set of video encoding units, a timing control unit, and a signal driver. The video encoding unit receives the original test image data output by the processor module and performs RGB data encoding, row and column timing generation, synchronization signal insertion, and differential driving according to the HDMI protocol standard; the output TMDS encoded data stream is sent to the connected display in a high-speed serial manner through differential lines, realizing low-latency, high-resolution, and high-refresh-rate image display. The processor module is also configured with a graphics generation engine, which can convert the internally generated device test report, including communication protocol interaction process, response frame parsing result, error frame statistics information, test determination result, etc. into a standard format image data frame, preferably in bitmap, vector graph, or frame buffer format, and overlay visualization elements, such as color markers, chart curves, status icons, etc., to enhance the intuitiveness and readability of test information. Through the above configuration, the test main board of the present invention not only has the ability of automatic multi-protocol testing, but also has the function of graphically and externally displaying the test results, facilitating testers to make immediate observations, result comparisons, and fault tracing, improving the overall test efficiency and operability, and is particularly suitable for application scenarios such as R & D debugging sites, in-vehicle terminal maintenance, and batch device screening.

[0041] Preferably, referring to Figure 1 , the in-vehicle multi-communication protocol test main board further includes: An NVME interface, which is used to receive the configuration information sent by an external storage device and send the device test report to the external storage device; The processor is also used to configure the in-vehicle multi-communication protocol test main board according to the configuration information.

[0042] Specifically, the in-vehicle multi-communication protocol test mainboard further includes an NVMe high-speed interface module, which is used to establish a data communication connection with an external high-speed non-volatile storage device to achieve high-speed reading and writing of test data and dynamic interaction management. The NVME interface is implemented using a physical and protocol stack that complies with the NVMe protocol standard, supports PCIe Gen3 and above versions, and has the storage access capabilities of high bandwidth, low latency, and low power consumption, making it suitable for real-time access and storage of large amounts of data during the testing process. During system initialization or test task switching, the NVMe interface can read configuration information such as pre-stored communication protocol configuration files, test instruction templates, and test item parameter sets from the external storage device and load them into the processor module or FPGA module inside the mainboard through DMA, realizing the rapid configuration and automated deployment of the test system; after the device test is completed, the device test report generated by the processor module can be written to the external NVMe storage device at high speed through the NVMe interface, supporting classification management according to dimensions such as test tasks, device numbers, and timestamps, facilitating subsequent offline analysis, batch backtracking, or quality assessment. The NVMe interface module also integrates a multi-queue data access control unit, a power-off protection mechanism, and a storage integrity verification logic, which can effectively improve the concurrency and system stability during large-scale data interaction and avoid the loss of critical data caused by power fluctuations or test interruptions. Through the above configuration, the test mainboard of the present invention not only has the ability to test multi-communication protocols but also provides high-speed, high-capacity, and structured data interaction and management capabilities, making it suitable for batch device test scenarios and industrial-grade automatic test platforms with strict requirements for storage performance. The processor module is also configured to automatically configure and load parameters for each functional module of this mainboard according to the configuration information during the initialization stage after the in-vehicle multi-communication protocol test mainboard is powered on or restarted. The processor can read configuration information such as communication protocol parameters, test instruction sets, signal mapping rules, module enable status, interface working modes, and power management strategies from configuration files obtained from external storage devices, SPI Flash, or through remote communication ports, and accordingly configure the FPGA chip, CANFD communication module, in-vehicle Ethernet communication module, clock module, power conversion module, and HDMI display interface module of the mainboard one by one to achieve the adaptive startup and function initialization of the system. The processor also supports dynamic configuration and runtime hot update functions. During the execution of the test task, it can dynamically modify the working parameters of specific modules or switch their operating modes according to user instructions or external trigger events to adapt to diverse test requirements and complex application scenarios, improving the flexibility and scalability of the test platform.

[0043] Preferably, referring to Figure 1 , the in-vehicle multi-communication protocol test mainboard further includes: A clock module, which is used to generate a clock signal; The processor is further configured to generate a unified timestamp for the response frame and the standard Ethernet response signal according to the clock signal.

[0044] Specifically, the vehicle-mounted multi-communication protocol test main board further includes a clock module, which is used to provide a stable and configurable system clock signal for each functional module of the main board, ensuring the timing consistency, data synchronization and communication accuracy of the entire test system under the condition of multi-protocol concurrent operation. The clock module includes a high-precision crystal oscillator unit, a clock synthesis circuit, a clock buffer distributor, and an optional programmable oscillator or PLL phase-locked loop component. The clock module generates a reference frequency signal through a crystal oscillator, which serves as the source of the system frequency of the entire test main board; through clock synthesis technologies such as PLL and DPLL, the reference frequency is up-converted or divided to generate different target frequencies, which are respectively provided to modules such as FPGA chips, CANFD communication modules, Ethernet transceivers, and PCIe / NVMe interfaces for use. The clock module supports the master-slave node clock synchronization mechanism in multi-protocol communication scenarios. When performing CANFD or in-vehicle Ethernet communication tests, it can achieve phase locking and edge alignment based on the master node or external clock signal, ensuring accurate timing of communication tests; at the same time, it supports a dual-crystal oscillator hot backup structure, automatically switches to the backup crystal oscillator when the main crystal oscillator fails or the frequency drift exceeds the standard, and realizes online diagnosis and alarm through the clock health monitoring module. The clock module also integrates a jitter eliminator and filtering devices to reduce the jitter and EMI interference of high-frequency clock signals during high-speed differential transmission, ensuring the signal integrity of high-speed interfaces. The processor module is also configured to perform unified time marking processing on the communication response data received during the test based on the high-precision clock signal provided by the clock module, and generate unified format timestamps that conform to the system time base for the response frames from the CANFD communication module and the standard Ethernet response signals converted by the ordinary Ethernet transceiver respectively. The generated timestamps are preferably increasing count values based on nanosecond or microsecond precision, with monotonicity, global uniqueness, and resolvability. The introduction of the unified timestamp enables the processor module to achieve timing alignment and synchronous analysis of the response data returned under different communication protocols, thereby supporting the combined analysis of CANFD response frames and in-vehicle Ethernet response signals on the time axis in the same test task, and realizing the timing matching of cross-protocol events; it can also perform statistical calculations on the timestamp information of specific error frames or lost packets to quickly evaluate their occurrence time, communication delay, and jitter characteristics; and sort, filter, and replay the test response data based on the timestamp order to provide data support for subsequent presentation of timing diagrams / curve diagrams on the HDMI image display interface. To improve the accuracy and consistency of timestamp generation, the processor can also cooperate with the clock module to adopt a hardware-triggered sampling mechanism or an FPGA co-processing method to complete timestamp binding at the moment of data reception, avoiding time offset caused by software delay.

[0045] In some embodiments, the processor module and the memory module in the in-vehicle multi-communication protocol test mainboard adopt a modular design architecture, supporting integrated plug-and-play replacement, so as to facilitate users to quickly upgrade or customize the deployment of CPU computing power or storage capacity according to different test application requirements, computing power load intensity or system function expansion requirements. The modular interface is preferably a standard high-speed interconnect interface, which has the advantages of hot pluggability, strong compatibility, high signal integrity, etc., and can significantly improve the flexible deployment ability and post-maintainability of the test platform. The mainboard system software adopts a hierarchical decoupled architecture, and the application layer program and the communication protocol stack interact through a set of standardized and abstract interface protocols, making the protocol processing logic and the upper-layer test service logic independent and non-coupled from each other. The mainboard supports loading or replacing different protocol stacks according to external configuration files, test environments or FPGA logic changes without modifying the upper-layer application logic; the software bottom-layer driver and the hardware abstraction layer have high generality and can be quickly ported to different processing platforms or embedded operating systems; various peripheral interfaces of the mainboard, such as PCIe, SPI, UART, I2C, etc., realize resource sharing and dynamic scheduling through a unified interface management middleware, improving the overall IO resource utilization efficiency of the system. Through the combination of modular hardware design and decoupled software architecture, the test mainboard provided by the present invention has high scalability, high adaptability and high life cycle management ability, and is suitable for complex in-vehicle electronic system test tasks with multiple vehicle models, multiple suppliers and multiple protocol combinations.

[0046] The in-vehicle multi-communication protocol test mainboard further provides a set of system-level application test software architecture platforms. This platform is deeply integrated with the mainboard hardware structure, constructing a full-stack software support system from the underlying driver to the application layer test logic. The platform pre-integrates and automatically loads the driver programs of various functional modules on the in-vehicle mainboard, supporting operation in both Windows and Linux dual operating system environments to meet the usage preferences of different developers and integrators. At the protocol support level, the platform encapsulates and abstracts the communication protocols at the operating system kernel level, and realizes the complete parsing and management functions of CAN and CANFD protocols as well as TCP, UDP, and IP protocols based on Ethernet in its communication protocol stack. It supports multi-protocol parallel operation, data multiplexing, and protocol-level fault detection, and provides a unified call entry and middleware scheduling mechanism. The software platform also constructs a multi-language application programming interface layer for developers, supporting programming interface calls in mainstream development languages including but not limited to C / C++, Python, Java, Rust, etc. Developers can quickly build customized test processes, simulation tools, or analysis applications based on this platform, greatly improving the programmability and integration convenience of the system. In terms of test task organization and execution, the platform supports the creation of custom test projects, flexible test case management, and use case library maintenance mechanisms. Among them, the test cases have independent description languages or metadata structures, realizing a loose coupling design with the hardware interface and test framework. The test platform supports quickly deploying test cases to any functional module and automatically executing them, with functional modules such as task queue scheduling, error retry, log collection, and result report generation, thus significantly reducing the complexity of test script development and system integration. Through the platformized design of software and hardware collaboration, the system not only realizes a unified test interface for multi-communication protocols, cross-platform operating environment support, dynamic use case deployment, and automated execution, but also has good scalability, maintainability, and engineering implementation capabilities, and is applicable to various scenarios such as production testing, functional verification, and regression testing of in-vehicle electronic systems.

[0047] The on-vehicle multi-communication protocol test mainboard is also integrated with a USB module. The USB 3.0 module includes a main control chip compliant with the USB 3.1 Gen1 standard, a super-high-speed differential signal driving circuit, and a data interaction bus between the processor module or the FPGA module, and can provide a data transmission rate of up to 5 Gbps for realizing the access and data exchange of high-speed and low-latency external devices. The program development of each communication protocol interface of the on-vehicle multi-communication protocol test mainboard is implemented based on the Windows or Linux operating system environment. As the basic platform for the operation of the mainboard software, the operating system has the ability to uniformly manage and schedule various hardware resources on the mainboard, and provides stable kernel support and hardware abstraction interfaces to ensure the stable operation and resource isolation of various functional modules in the multi-task parallel scenario. The USB interface is used for the connection and communication between the on-vehicle multi-communication protocol test mainboard and external devices, and the USB interface can be connected to devices such as mice, keyboards, and USB flash drives.

[0048] The on-vehicle multi-communication protocol test mainboard integrates 8 CAN interfaces and 2 Gigabit on-vehicle Ethernet interfaces, providing an efficient and flexible solution for testing, monitoring, and data transmission in complex vehicle network environments. The test mainboard can be widely applied in multiple fields such as automotive R & D, intelligent transportation, and vehicle detection, and plays a crucial role especially in the testing and verification of domain controllers. During the testing process of the domain controller, the domain controller and the test mainboard perform signal interaction through the on-vehicle bus system, involving bidirectional data transmission of CAN signals and 1000Base-T1 on-vehicle Ethernet signals. The specific test program runs inside the test mainboard to ensure comprehensive verification of on-vehicle communication protocols, data integrity, and real-time performance. The test mainboard can, according to the complexity of the actual vehicle network environment, simulate data exchange between the domain controller and other on-vehicle electronic control units (ECUs) through 8 CAN interfaces and 2 Gigabit on-vehicle Ethernet interfaces. Through the flexibly configurable interfaces, the test mainboard can restore various communication scenarios in the on-vehicle network and simulate interactions and data flows under different communication protocols. The test mainboard can, through dual support for CAN and on-vehicle Ethernet protocols, verify the communication protocols between the domain controller and other ECUs, and check the correctness, integrity, and real-time performance of data packets. Especially when using the CAN FD protocol, the mainboard can verify the high efficiency of data frame transmission and support for large amounts of data, ensuring the stability of the domain controller when dealing with multiple on-vehicle communication protocols. The test mainboard can not only simulate normal communication but also simulate fault situations, such as simulating different faults like communication interruption, data loss, or error frames, to test the reaction ability and error handling mechanism of the domain controller. In addition, the mainboard can perform performance tests under high load, simulate the stability and response time of the on-vehicle system in a stress environment, and verify the reliability of the domain controller under extreme working conditions. During the testing process, the mainboard supports an automated testing process. Users can customize test cases, and the mainboard will automatically execute the tests and generate detailed reports. During the testing process, the mainboard can record all data exchanges and events in real time for subsequent analysis and problem tracking. These data include the content of data packets transmitted in each round of testing, error frames, response times, etc., ensuring that developers can clearly analyze the performance of the domain controller in various scenarios. During the testing process, the test mainboard performs dual communication of CANFD and on-vehicle Ethernet by simulating the on-vehicle bus, and conducts data transmission between the domain controller and other ECUs to ensure the compatibility and interaction stability of different protocols. The mainboard, through a dedicated test program, verifies the transmission accuracy of data packets, checks the integrity, real-time performance, and transmission reliability of data, and ensures that there are no packet losses, delays, or disorders. By simulating various fault situations, it tests the reaction time and fault recovery ability of the domain controller under different abnormal situations, such as the handling mechanism of on-vehicle network faults, communication interruptions, or error frames.Under high-load conditions, test the performance of the domain controller when processing large amounts of data, multiple signal channels, and high-frequency interactions, including response time, bandwidth utilization, and stability under extreme loads. All data during the testing process is recorded in real time, including the content of data packets, timestamps, test results, etc., which can be used later to analyze the performance bottlenecks of the domain controller and provide detailed troubleshooting materials for developers. Through these test functions, the in-vehicle multi-communication protocol test motherboard can not only efficiently and accurately verify the communication capabilities and stability of the domain controller in the in-vehicle network, but also provide detailed performance data and fault reports for developers to help optimize the design of the in-vehicle system and improve the reliability of the system.

Claims

1. A vehicle-mounted multi-communication protocol test main board, characterized in that, Including: A CANFD communication module, configured to send a test frame to a device under test when receiving a CANFD test instruction; Receiving a response frame corresponding to the test frame sent by the device under test; An in-vehicle Ethernet communication module, configured to convert a standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device under test; receiving an in-vehicle Ethernet response signal corresponding to the in-vehicle Ethernet test signal sent by the device under test and converting the in-vehicle Ethernet response signal into a standard Ethernet response signal; A processor module, configured to generate a CANFD test instruction and a standard Ethernet test signal; generating a device test report of the device under test according to the response frame and the standard Ethernet response signal; Wherein, the test frame includes a data frame, a control instruction frame, a fault frame, and an error frame, and the in-vehicle Ethernet test signal includes a data packet, a control signal, a fault signal, and an error signal.

2. The in-vehicle multi-communication protocol test main board according to claim 1, wherein The CANFD communication module includes: An FPGA chip, configured to generate a test frame when receiving the CANFD test instruction; A plurality of CAN transceivers, configured to send the test frame to the device under test; receiving a CAN response frame corresponding to the test frame sent by the device under test and converting the CAN response frame into a response frame compatible with the PCIe bus.

3. The in-vehicle multi-communication protocol test main board according to claim 2, characterized in that The CANFD communication module further includes: An SPI Flash chip, configured to store startup firmware configuration information and communication logic configuration information of the FPGA chip; The FPGA chip is further configured to perform startup configuration according to the startup firmware configuration information and the communication logic configuration information.

4. The in-vehicle multi-communication protocol test main board according to claim 1, characterized in that, The in-vehicle Ethernet communication module includes: An in-vehicle Ethernet transceiver, configured to convert the standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device under test; A common Ethernet transceiver, configured to receive an in-vehicle Ethernet response signal corresponding to the in-vehicle Ethernet test signal sent by the device under test and convert the in-vehicle Ethernet response signal into a standard Ethernet response signal.

5. The in-vehicle multi-communication protocol test main board according to claim 4, wherein, The in-vehicle Ethernet communication module further includes: A DIP switch, configured to set the in-vehicle Ethernet communication module as a master node when in a first switch state; setting the in-vehicle Ethernet communication module as a slave node when in a second switch state.

6. The in-vehicle multi-communication protocol test main board according to claim 4, characterized in that The in-vehicle Ethernet communication module further includes: A signal indicator light, configured to go out when the in-vehicle Ethernet transceiver loses power, light up when the in-vehicle Ethernet transceiver is powered on, and blink at a preset frequency when the in-vehicle Ethernet transceiver is working.

7. The in-vehicle multi-communication protocol test main board according to claim 1, wherein The in-vehicle multi-communication protocol test main board further includes: A power conversion module, which is used to convert an external first voltage into a second voltage based on the pressing state of a start button and supply power to the in-vehicle multi-communication protocol test main board with the second voltage when the in-vehicle multi-communication protocol test main board is configured in a first start mode; and convert the external first voltage into a second voltage based on an external power supply state and supply power to the in-vehicle multi-communication protocol test main board with the second voltage when the in-vehicle multi-communication protocol test main board is configured in a second start mode.

8. The in-vehicle multi-communication protocol test main board according to claim 1, characterized in that The in-vehicle multi-communication protocol test main board further includes: An HDMI display interface, which is used to convert device test digital image data into high-speed serial differential signals and send the high-speed serial differential signals to a display. The processor module is further used to convert the device test report into device test digital image data.

9. The in-vehicle multi-communication protocol test main board according to claim 1, characterized in that The in-vehicle multi-communication protocol test main board further includes: An NVME interface, which is used to receive configuration information sent by an external storage device and send the device test report to the external storage device. The processor is further used to configure the in-vehicle multi-communication protocol test main board according to the configuration information.

10. The in-vehicle multi-communication protocol test main board according to claim 1, characterized in that, The in-vehicle multi-communication protocol test main board further includes: A clock module, which is used to generate a clock signal. The processor is further used to generate a unified timestamp for the response frame and the standard Ethernet response signal according to the clock signal.

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