In-vehicle multi-communication protocol test motherboard

Abstract

The present invention provides an in-vehicle multi-communication protocol test mainboard, comprising: a CANFD communication module for sending a test frame to a device under test upon receiving a CANFD test command; receiving a response frame corresponding to the test frame sent by the device under test; an on-board Ethernet communication module for converting a standard Ethernet test signal into an on-board Ethernet test signal and sending the on-board Ethernet test signal to the device under test; receiving an on-board Ethernet response signal corresponding to the on-board Ethernet test signal sent by the device under test, and converting the on-board Ethernet response signal into a standard Ethernet response signal; a processor module for generating a CANFD test command and a standard Ethernet test signal; and generating a device test report for the device under test based on the response frame and the standard Ethernet response signal. By integrating the CANFD communication module with the on-board Ethernet communication module and coordinating control with the processor module, the present invention achieves automated joint testing of different communication protocols.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle-mounted communication, and in particular to a vehicle-mounted multi-communication protocol test mainboard. Background Art

[0002] As the number of automotive electronic control units continues to grow, future automotive systems will increasingly rely on multiple network protocols for efficient data exchange and coordinated control. Controller Area Networks (CARs) and in-vehicle Ethernet (IoV) have become mainstream communication methods. To meet the bandwidth, real-time performance, and functional safety requirements of diverse systems, hybrid communication network architectures are becoming increasingly popular.

[0003] However, existing test systems usually use separate CAN test equipment and Ethernet test equipment, which not only increases hardware costs and system integration difficulties, but also limits the joint testing capabilities and automation level in multi-protocol environments. In addition, the separation test solution has significant deficiencies in handling cross-protocol data synchronization, real-time response monitoring and consistency verification, making it difficult to meet the actual needs of the new generation of intelligent connected vehicles for efficient communication testing. Therefore, there is an urgent need for a test motherboard and supporting system that integrates CAN and Ethernet communication capabilities, which can achieve unified software control, synchronous triggering, protocol collaboration, hybrid log collection and other functions, thereby significantly improving the test efficiency, accuracy and intelligence level of the vehicle network system. Summary of the Invention

[0004] The purpose of the present invention is to provide a vehicle-mounted multi-communication protocol test motherboard, which is used to solve technical problems in the prior art such as the separation of CAN test system and Ethernet test system, poor communication protocol compatibility, high system integration complexity, inconsistent test process, and difficulty in achieving cross-protocol synchronization.

[0005] In order to achieve the above objectives, the present invention provides a vehicle-mounted multi-communication protocol test motherboard, comprising:

[0006] The CANFD communication module is used to send a test frame to the device under test when a CANFD test command is received; and receive a response frame corresponding to the test frame sent by the device under test;

[0007] The vehicle Ethernet communication module is used to convert a standard Ethernet test signal into a vehicle Ethernet test signal and send the vehicle Ethernet test signal to the device under test; receive a vehicle Ethernet response signal corresponding to the vehicle Ethernet test signal sent by the device under test, and convert the vehicle Ethernet response signal into a standard Ethernet response signal;

[0008] A processor module is configured to generate a CANFD test instruction and a standard Ethernet test signal; and generate a device test report for the device to be tested according to the response frame and the standard Ethernet response signal;

[0009] The test frames include data frames, control instruction frames, fault frames and error frames, and the in-vehicle Ethernet test signals include data packets, control signals, fault signals and error signals.

[0010] Furthermore, the CANFD communication module includes:

[0011] The FPGA chip is used to generate a test frame when receiving the CANFD test instruction;

[0012] Several CAN transceivers are used to send the test frame to the device under test; receive CAN response frames corresponding to the test frame sent by the device under test, and convert the CAN response frames into response frames compatible with the PCIe bus.

[0013] Furthermore, the CANFD communication module also includes:

[0014] SPI Flash chip, used to store the startup firmware configuration information and communication logic configuration information of the FPGA chip;

[0015] The FPGA chip is also used to perform startup configuration according to the startup firmware configuration information and the communication logic configuration information.

[0016] Furthermore, the vehicle-mounted Ethernet communication module includes:

[0017] An in-vehicle Ethernet transceiver, configured to convert the standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device to be tested;

[0018] A common Ethernet transceiver is used to receive a vehicle-mounted Ethernet response signal corresponding to the vehicle-mounted Ethernet test signal and sent by the device to be tested, and convert the vehicle-mounted Ethernet response signal into a standard Ethernet response signal.

[0019] Furthermore, the vehicle-mounted Ethernet communication module further includes:

[0020] The dip switch is used to set the vehicle-mounted Ethernet communication module as a master node when in a first switch state; and to set the vehicle-mounted Ethernet communication module as a slave node when in a second switch state.

[0021] Furthermore, the vehicle-mounted Ethernet communication module further includes:

[0022] A signal indicator light is configured to be extinguished when the vehicle-mounted Ethernet transceiver loses power, to be illuminated when the vehicle-mounted Ethernet transceiver is powered, and to flash at a preset frequency when the vehicle-mounted Ethernet transceiver is working.

[0023] Furthermore, the vehicle-mounted multi-communication protocol test mainboard also includes:

[0024] A power conversion module is used to convert an external first voltage into a second voltage based on the pressing state of the start button when the on-board multi-communication protocol test mainboard is configured in the first startup mode, and use the second voltage to power the on-board multi-communication protocol test mainboard; when the on-board multi-communication protocol test mainboard is configured in the second startup mode, based on the external power supply state, convert the external first voltage into the second voltage, and use the second voltage to power the on-board multi-communication protocol test mainboard.

[0025] Furthermore, the vehicle-mounted multi-communication protocol test mainboard also includes:

[0026] HDMI display interface, used to convert device test digital image data into high-speed serial differential signals and send the high-speed serial differential signals to the display;

[0027] The processor module is further configured to convert the device test report into device test digital image data.

[0028] Furthermore, the vehicle-mounted multi-communication protocol test mainboard also includes:

[0029] NVME interface, used to receive configuration information sent by an external storage device and send the device test report to the external storage device;

[0030] The processor is further configured to configure the vehicle-mounted multi-communication protocol test mainboard according to the configuration information.

[0031] Furthermore, the vehicle-mounted multi-communication protocol test mainboard also includes:

[0032] A clock module, used to generate a clock signal;

[0033] The processor is further configured to generate a unified timestamp for the response frame and the standard Ethernet response signal according to the clock signal.

[0034] This invention integrates two mainstream in-vehicle communication technologies, CANFD and automotive Ethernet, to achieve a highly integrated design for the test motherboard. Compared with traditional discrete test systems, the number of peripheral devices and external wiring harnesses is significantly reduced, the hardware architecture is simplified, and not only the physical complexity of the system is reduced, but also the operation and maintenance costs are effectively reduced. The integrated system can optimize the balance between real-time performance and data transmission efficiency in in-vehicle network testing, significantly improving test efficiency and ensuring that it can meet the testing needs of more complex in-vehicle network environments in the future. In particular, in the development of intelligent connected vehicles and autonomous driving systems, it can better cope with challenges such as high-speed data transmission, high real-time response, and cross-protocol collaborative verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 This is a structural block diagram of a vehicle-mounted multi-communication protocol test mainboard of the present invention;

[0037] Figure 2 This is a structural block diagram of the CANFD communication module of the present invention;

[0038] Figure 3 This is a structural block diagram of the vehicle-mounted Ethernet communication module of the present invention. DETAILED DESCRIPTION

[0039] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0040] like Figure 1 As shown, the present invention provides a vehicle-mounted multi-communication protocol test motherboard, comprising:

[0041] The CANFD communication module is used to send a test frame to the device under test when a CANFD test command is received; and receive a response frame corresponding to the test frame sent by the device under test;

[0042] The vehicle Ethernet communication module is used to convert a standard Ethernet test signal into a vehicle Ethernet test signal and send the vehicle Ethernet test signal to the device under test; receive a vehicle Ethernet response signal corresponding to the vehicle Ethernet test signal sent by the device under test, and convert the vehicle Ethernet response signal into a standard Ethernet response signal;

[0043] A processor module is configured to generate a CANFD test instruction and a standard Ethernet test signal; and generate a device test report for the device to be tested according to the response frame and the standard Ethernet response signal;

[0044] The test frames include data frames, control instruction frames, fault frames and error frames, and the in-vehicle Ethernet test signals include data packets, control signals, fault signals and error signals.

[0045] Specifically, the mainboard is provided with a processor module, a memory module, a CANFD communication module, an on-board Ethernet communication module, a PCIe bus, a power conversion module, and a clock module. The CANFD communication module and the on-board Ethernet communication module communicate with the processor module via the PCIe bus respectively. The power conversion module connects to an external power source via a power interface and provides adaptive power supply to the processor module, the CANFD communication module, and the on-board Ethernet communication module. The CANFD communication module connects to an external device under test via a CAN interface. The on-board Ethernet module connects to an external device under test via a common Ethernet interface and an on-board Ethernet interface. The processor module connects to an external display device and an external storage device via an HDMI interface and an NVME interface, respectively. The processor module can use an Intel i7 series processor, and the memory module can use a DDR4 SODIMM dual in-line memory module.

[0046] Upon receiving a CANFD test command from the processor module, the CANFD communication module generates and proactively sends a test frame containing specified content to the device under test (DUT) in a pre-set protocol format. Test frame types include, but are not limited to, data frames, control command frames, fault frames, and error frames. Each frame can be configured with a specific identifier, data payload length, and bit-stuffing strategy. Furthermore, the CANFD communication module is equipped with a response detection and frame filtering mechanism. After sending a test frame, it monitors the CAN bus in real time and captures any corresponding response frames returned by the DUT. Upon receiving a response frame, it verifies its validity through a validation mechanism, including CRC checking, bit-stuffing detection, and interframe interval analysis. The parsed valid frame data is then uploaded to the processor module for subsequent communication performance evaluation, protocol conformance testing, and functional response analysis. The in-vehicle Ethernet communication module is configured to implement bidirectional protocol and electrical layer conversion between standard Ethernet and in-vehicle Ethernet compliant with the IEEE 802.3bw (100BASE-T1) or IEEE 802.3bp (1000BASE-T1) specifications. Specifically, upon receiving the standard Ethernet test signal generated by the processor module, the vehicle Ethernet communication module first reconstructs the frame structure, adjusts the data rate, synchronizes the clock, and adapts the modulation and coding of the test signal through the protocol conversion unit to generate a test data frame that meets the requirements of vehicle Ethernet communication, namely the vehicle Ethernet test signal; it is then sent to the corresponding Ethernet port of the device under test through the physical layer interface circuit. In addition, the vehicle Ethernet communication module is further configured with a high-speed listening and frame recognition mechanism for receiving the vehicle Ethernet response signal corresponding to the above test signal returned by the device under test in real time. After receiving the response signal, the response signal is converted into a standard Ethernet response signal through a reverse protocol conversion process, including frame format restoration, differential signal decoding, signal integrity determination, and other processing, and uploaded to the processor module. The vehicle Ethernet communication module can achieve seamless bridging between test signals and response signals between different Ethernet protocols, effectively supporting functional and stability testing of vehicle Ethernet devices at the physical layer, link layer, and part of the transport layer, and improving the compatibility and coverage capabilities of the overall test system. The processor module coordinates and controls the multi-protocol testing process for the entire test motherboard. It features built-in support for the CAN FD protocol and Ethernet protocol stack, and integrates a test task scheduling engine. It generates specific CAN FD test instruction sets and standard Ethernet test signal sequences based on preset test templates or user-defined parameters. These CAN FD test instructions and standard Ethernet test signal sequences can include functional verification commands, bandwidth stress packets, boundary condition trigger frames, and exception simulation data to ensure test coverage. During testing, the processor module also includes a response frame parsing unit and data consistency analysis logic.The processor module receives response frames from the CANFD communication module and performs content parsing, frame header identification, timestamp extraction, and anomaly detection. It also receives standard Ethernet response signals converted from the vehicle Ethernet communication module and performs protocol-level verification, data integrity analysis, and response delay calculation. After completing data collection and analysis, the processor module comprehensively evaluates test results based on multiple metrics, such as communication latency, response accuracy, protocol consistency, frame loss rate, error type, and frequency, and automatically generates a structured device test report. The device test report displays charts and data in parallel and can be exported to multiple formats for subsequent archiving, comparison, or quality analysis. The processor module also supports uploading report results to a remote server or cloud platform via external interfaces such as USB, WiFi, or the onboard diagnostic port, facilitating centralized management and statistical analysis of large-scale device test data.

[0047] Test frames are constructed based on the CANFD protocol and include data frames, control command frames, fault frames, and error frames. Data frames simulate the transmission of normal business data in an actual in-vehicle communication environment and contain a payload field, frame identifier, data length code, and cyclic redundancy check field, used to test the device's data transmission and reception capabilities. Control command frames trigger the device under test to execute specific control logic or state transitions, such as start / stop commands and mode switching instructions. Fault frames simulate standard bus fault scenarios, such as frame loss, interruption, and arbitration loss, verifying the device's fault tolerance mechanisms under abnormal bus conditions. Error frames inject illegal format frames or CRC error frames to test the device's ability to identify and respond to protocol errors, including triggering error handling procedures or error counters. Automotive Ethernet test signals are constructed based on automotive Ethernet protocols, such as BroadR-Reach / 100BASE-T1, and include data packets, control signals, fault signals, and error signals. Data packets carry valid data at the service or application layer, testing the device's data throughput and protocol parsing capabilities. Control signals, including instruction packets based on the Ethernet control protocol, simulate network management instructions, flow control mechanisms, and QoS triggering. Fault signals simulate network anomalies such as packet loss, retransmissions, and link disconnections, testing the device's ability to perceive and recover from physical and link layer anomalies. Error signals inject illegal Ethernet frames to evaluate the device's protocol fault tolerance, error detection accuracy, and defense mechanisms. By flexibly combining multiple test frames and test signals within the test process, a highly complex in-vehicle communication simulation scenario is constructed that closely resembles actual usage environments, enabling a comprehensive assessment of the device's protocol support integrity, anomaly handling capabilities, and stability and robustness.

[0048] Preferably, refer to Figure 2 , the CANFD communication module includes:

[0049] The FPGA chip is used to generate a test frame when receiving the CANFD test instruction;

[0050] Several CAN transceivers are used to send the test frame to the device under test; receive CAN response frames corresponding to the test frame sent by the device under test, and convert the CAN response frames into response frames compatible with the PCIe bus.

[0051] Specifically, the CAN FD communication module includes an FPGA chip, an SPI Flash chip, reset and clock signals, a power supply, and four CAN transceivers connected to four CAN buses. The FPGA chip, or Field-Programmable Gate Array (FPGA), is configured to generate test frames compliant with the CAN FD protocol specification based on its reconfigurable logic resources upon receiving CAN FD test commands from the processor module. The FPGA chip is pre-installed with a CAN FD frame construction logic unit, which dynamically assembles test frame fields based on the command content, including the frame start bit, arbitration field, control field, data field, CRC checksum, and frame end flag. The FPGA chip can generate various frame structures based on test requirements, including standard and extended data frames, control frames, fault simulation frames, and error injection frames. Furthermore, the FPGA chip integrates a frame scheduling controller and a timestamp management unit, supporting periodic and event-triggered transmission of test frames, as well as precise control of frame intervals, meeting the requirements of high-bandwidth, high-real-time communication testing. Leveraging its hardware-level parallel processing capabilities, the FPGA chip significantly improves the speed and flexibility of test frame generation, serving as a critical frame generation and execution unit in the entire CAN FD test process. Several CAN transceivers correspond to multiple CAN FD channels. Each transceiver includes a differential signal driver, receive filters, bit-level electrical protection modules, and interface buffer control logic to enable bidirectional data communication between the vehicle's CAN bus physical layer and the host control system's logical layer. After receiving the test frame generated by the FPGA chip, the CAN transceiver performs level conversion and differential drive output on the frame, then transmits the test frame to the device under test (DUT) via a standard CAN bus topology. On the receiving side, the CAN transceiver monitors the bus status in real time and identifies the CAN response frame returned by the DUT corresponding to the test frame. After the CAN response frame undergoes differential signal restoration and logic level conversion by the transceiver, it is transmitted to the subsequent PCIe protocol adapter. During this process, the CAN response frame will be encapsulated into a data frame format compatible with the PCIe bus protocol according to predefined frame packaging rules and transmitted to the processor module or main control system via the high-bandwidth PCIe channel for subsequent data parsing and test analysis. To improve the system's concurrent processing capabilities and multi-channel data consistency, the CAN transceiver can correspond to multiple independent CAN channels, supporting parallel testing and data transmission of multiple devices under test or multiple CAN nodes. Each transceiver is equipped with error detection and frame checking mechanisms, which can provide real-time alarms and status reports for frame format anomalies, electrical layer faults, and other situations, ensuring the stability and traceability of the entire communication test process.

[0052] The CAN FD communication module connects to the outside world via a CAN interface, which utilizes a DB9 external connector. Each CAN interface's signal pins are configured in accordance with CAN specifications 2.0A / B and the FD standard. Pin 2, CAN_L, transmits the CAN bus's low-level signal, forming part of the differential signal and participating in data frame transmission. Pin 7, CAN_H, transmits the CAN bus's high-level signal, forming a differential signal with CAN_L to ensure reliable and interference-resistant data transmission. The CAN interface complies with CAN specifications 2.0A / B, supporting both standard and extended frame formats. It supports a maximum transmission rate of 1 Mbit / s, making it suitable for traditional in-vehicle bus communication and device testing. The CAN interface further supports the CAN FD protocol, allowing for the use of an extended data field. This allows the effective data length of each data frame to be extended to 64 bytes, significantly improving performance compared to CAN 2.0. CAN FD supports a maximum transmission rate of 12 Mbit / s, making it suitable for testing scenarios requiring high-speed data exchange, particularly the large data volumes required in modern in-vehicle electronic devices. While utilizing differential signaling, the interface's electrical design meets CAN communication anti-interference requirements, effectively preventing data loss or errors caused by electromagnetic interference or long transmission lines, ensuring communication stability in the complex electromagnetic environment of in-vehicle systems. The DB9 connector, a widely adopted industry standard, offers broad compatibility and supports convenient connection with other DB9-compliant devices. Furthermore, the board enables parallel testing via multiple CAN interfaces, improving test efficiency. Each CAN interface supports real-time monitoring and fault diagnosis. The system captures transmission errors, bus conflicts, and bit errors, and provides detailed error codes to help developers quickly locate communication faults. Using this DB9 CAN interface, the in-vehicle multi-protocol test board enables efficient and reliable CAN protocol testing, meeting the high-speed data exchange requirements of both traditional and modern in-vehicle communications, providing strong technical support for the development and verification of automotive electronic systems.

[0053] The FPGA chip's peripheral circuitry also includes a clock module and reset control circuitry, ensuring stable and reliable timing references and reset control during power-on initialization, logic configuration, and normal operation. The clock module, comprised of a high-precision crystal oscillator, a clock driver chip, and an optional clock buffer or clock divider, provides the FPGA with a stable system master clock signal. This clock signal serves as the timing reference for the FPGA's internal logic blocks and supports multiple frequency configurations, dynamically switching between high- and low-frequency clock sources based on different application scenarios. The clock module also collaborates with the motherboard's unified clock management system to achieve cross-module clock synchronization and unified timestamp distribution. The reset control circuitry includes a power-on reset circuit, an external reset input interface, soft reset control logic, and a reset trigger mechanism linked to the processor. This ensures deterministic initialization during critical FPGA states, such as power-on, error recovery, and configuration updates. The reset circuitry also supports multi-level reset strategies, including global reset, local logic block reset, and configuration logic reset, enhancing system stability and fault resilience. Through the cooperation of peripheral circuits, the FPGA chip is ensured to have stable working timing and controllable state recovery mechanism during the configuration, operation and collaborative communication process in the mainboard system, providing a reliable hardware foundation for subsequent functional modules such as CANFD test frame generation, Ethernet protocol conversion and data processing.

[0054] Preferably, refer to Figure 2 , the CANFD communication module also includes:

[0055] SPI Flash chip, used to store the startup firmware configuration information and communication logic configuration information of the FPGA chip;

[0056] The FPGA chip is also used to perform startup configuration according to the startup firmware configuration information and the communication logic configuration information.

[0057] Specifically, the SPI Flash chip, acting as a non-volatile memory device, connects to the FPGA chip via a standard SPI bus interface and stores the firmware configuration data and communication logic configuration files required to load during the FPGA's power-up and startup process. The startup firmware pre-installed in the SPI Flash chip includes the FPGA's bitstream information, which defines the initial configuration of the FPGA's logic resources, such as the test frame generation module, frame scheduling controller, timestamp unit, and interface control logic. The SPI Flash chip also stores communication logic configuration information that can be dynamically updated by the processor. This includes CAN FD frame format templates and injection rules, frame scheduling parameters for different test scenarios, multi-channel configuration parameters, and test state machine configuration and event response logic. Upon system power-up, the FPGA chip actively accesses the Flash chip via the SPI master interface, sequentially loading configuration data and completing logic reconfiguration, ensuring the FPGA's full test task execution capabilities. The inclusion of the SPI Flash chip not only improves system maintainability and flexibility, but also allows users to remotely update or reconfigure the SPI Flash online via the processor module or external debug interface, enabling rapid adaptation to evolving test scenarios or protocol versions. The FPGA chip is further configured to execute the system startup configuration process during the power-on initialization phase based on the startup firmware configuration information and communication logic configuration information stored in the SPI Flash chip. Upon detecting a system power-on or reset signal, the FPGA chip, through its built-in startup control logic, first loads the corresponding bitstream file from the SPI Flash to complete the basic configuration of its programmable logic units, I / O resources, clock distribution network, and interface control modules, enabling dynamic construction of the logic architecture. After completing the basic startup, the FPGA chip further parses and applies the communication logic configuration information to complete the detailed configuration of multiple communication submodules. These configuration parameters, including frame type definition, injection timing, priority setting, and response determination rules, can be dynamically updated based on specific test scenarios, ensuring that the FPGA possesses highly flexible communication test logic during runtime. Through this mechanism, the FPGA chip not only performs hardware-level test frame generation and protocol execution tasks, but also serves as a customizable, reconfigurable core controller for the entire system, significantly improving the adaptability, scalability, and maintenance efficiency of the test motherboard in multi-protocol and complex scenarios.

[0058] Preferably, refer to Figure 3 , the vehicle Ethernet communication module includes:

[0059] An in-vehicle Ethernet transceiver, configured to convert the standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device to be tested;

[0060] A common Ethernet transceiver is used to receive a vehicle-mounted Ethernet response signal corresponding to the vehicle-mounted Ethernet test signal and sent by the device to be tested, and convert the vehicle-mounted Ethernet response signal into a standard Ethernet response signal.

[0061] Specifically, the vehicle-mounted Ethernet communication module includes a vehicle-mounted Ethernet transceiver, a common Ethernet transceiver, a power supply, a dial switch and an LED indicator light. The vehicle-mounted Ethernet transceiver is used to realize the conversion of electrical signals and coding mechanisms between standard Ethernet and vehicle-mounted Ethernet at the physical layer, and is one of the core components in the vehicle-mounted Ethernet communication module. The vehicle-mounted Ethernet transceiver is compatible with a variety of mainstream vehicle-mounted Ethernet standards, including but not limited to 100BASE-T1 and 1000BASE-T1, and supports single-pair unshielded twisted pair transmission, which can effectively reduce wiring complexity and improve anti-interference capabilities, and adapt to the needs of complex vehicle-mounted electromagnetic environments. On the transmission path, the vehicle-mounted Ethernet transceiver receives the standard Ethernet test signal output from the protocol conversion module and converts it into a signal format that complies with the vehicle-mounted Ethernet physical layer standard, specifically including differential signal modulation, level conversion, cable equalization, synchronous coding and CRC check bit insertion. After the signal conversion is completed, the corresponding test signal is sent to the device to be tested through the vehicle-mounted Ethernet physical channel. The automotive Ethernet transceiver has features such as low latency, wide operating temperature, and high jitter tolerance. It also supports PHY loopback, self-diagnosis, link detection, and error injection functions. It can cooperate with the test main control module to perform link stability testing, response time measurement, and signal integrity verification. In addition, it has built-in ESD protection, EMC suppression, and cable short-circuit protection mechanisms to enhance the overall safety and reliability of the system and ensure that no electrical damage is caused to the device under test during the test process. Ordinary Ethernet transceivers, also known as Ethernet PHY chips, are used to complete the physical layer conversion of the automotive Ethernet response signal returned by the device under test to the standard Ethernet response signal. Ordinary Ethernet transceivers are mainly deployed in the receiving path of the Ethernet communication module. Its input interface is connected to the physical output layer of the automotive Ethernet transceiver, and its output interface is connected to the MAC control unit of the processor module. It is usually based on standard interface formats such as MII, RMII, RGMII, or SGMII. Ordinary Ethernet transceivers have physical layer decoding capabilities, can demodulate the coding mechanism in the on-board Ethernet response signal, complete operations such as signal level restoration, error correction, link alignment and clock recovery, and output a response signal compatible with the standard MAC layer after restoring it to the standard Ethernet data format. In order to ensure communication stability in high-interference and high-speed scenarios, ordinary Ethernet transceivers also integrate a low-jitter clock management unit, an automatic equalizer, a crosstalk suppressor, and a link quality monitoring module, which can monitor communication quality while maintaining data integrity, and issue diagnostic prompts for severe signal attenuation, inter-code interference, or cable faults. After the response signal is converted by this module, it can be parsed by the processor module or the post-stage diagnostic system to generate a corresponding test report or further fault analysis. Through the introduction of the on-board Ethernet communication module, seamless docking between on-board Ethernet and standard Ethernet at the physical level is achieved, enhancing the adaptability and scalability of the test motherboard of the present invention in different network protocol environments.

[0062] Preferably, refer to Figure 3 , the vehicle Ethernet communication module also includes:

[0063] The dip switch is used to set the vehicle-mounted Ethernet communication module as a master node when in a first switch state; and to set the vehicle-mounted Ethernet communication module as a slave node when in a second switch state.

[0064] Specifically, the vehicle Ethernet communication module also includes a DIP switch device for physical layer configuration and rapid switching of the communication module's node roles. The DIP switch is a multi-position mechanical switch or a dual-position, double-throw DIP switch assembly that switches the module's internal operating mode by physically toggling the state. The FPGA or processor module then collects and identifies the state when the system is powered on or reset. When the DIP switch is in the first switching state, the vehicle Ethernet communication module is set to master node mode. In this mode, the module actively sends synchronization signals, frame start signals, or link establishment requests, and controls the timing and handshake logic during the communication initialization process. When the DIP switch is in the second switching state, the communication module is set to slave node mode. In this mode, the module is in a listening state, waiting for the master node to initiate a communication handshake and responding to the synchronization command and test frame signals it sends. The physical state of the DIP switch can be read in real time by the node identification logic unit during the system initialization phase, and the relevant control flags are set through internal registers, thereby driving the Ethernet PHY chip, MAC layer protocol state machine, and link management controller to enter the corresponding master / slave operating state. The DIP switch configuration results are also fed back to the processor module, automatically matching node roles when generating test data frames or response frames, thereby ensuring consistency in communication topology and protocol timing during testing. The introduction of a hardware-level master-slave node configuration mechanism not only improves the system's adaptability to diverse in-vehicle Ethernet communication topologies but also simplifies operational complexity for users in actual test deployments, avoiding repetitive programming and debugging, and improving test efficiency and reliability.

[0065] Preferably, refer to Figure 3 , the vehicle-mounted Ethernet communication module also includes:

[0066] A signal indicator light is configured to be extinguished when the vehicle-mounted Ethernet transceiver loses power, to be illuminated when the vehicle-mounted Ethernet transceiver is powered, and to flash at a preset frequency when the vehicle-mounted Ethernet transceiver is working.

[0067] Specifically, the vehicle Ethernet communication module also includes a signal indicator light unit, i.e., an LED indicator light, which is used to provide visual feedback and real-time indication of the power status and operating status of the vehicle Ethernet transceiver. The signal indicator light is preferably a low-power, high-brightness LED component, which is connected to the transceiver power control path and the operating status monitoring module, and can exhibit different indication behaviors under different working conditions, thereby providing testers with an intuitive means of identifying the module's operating status. When the vehicle Ethernet transceiver loses power, the signal indicator light is off, indicating that the module is not working or there is a power supply fault; when the transceiver is powered but the communication link is not activated, the indicator light is always on, indicating that the transceiver is ready for communication; when the transceiver is in normal working condition, that is, a physical link has been established and is participating in the transmission and reception of communication frames, the indicator light flashes periodically at a preset frequency. The preset frequency can be set to be related to the data packet sending frequency or the link heartbeat frequency to reflect the real-time communication activity. To enhance system reliability, the signal indicator control unit integrates overvoltage protection, abnormal status latching, and a status feedback interface. It interacts with the main control processor and, upon detecting an abnormal transceiver power outage, short circuit, or communication failure, flashes in abnormal patterns, such as fast flash, slow flash, or double flash, to provide an alarm. Furthermore, the signal indicator unit is prominently positioned on the test motherboard, allowing for enhanced human-computer interaction through silkscreen labeling and color coded differentiation, improving on-site debugging efficiency and troubleshooting accuracy.

[0068] The in-vehicle Ethernet communication module connects to the external device under test via an in-vehicle Ethernet interface, which utilizes either an HMTD or MATEnet external interface. Each in-vehicle Ethernet interface provides reliable network communication through standardized physical connections, supporting data transmission and protocol testing within the in-vehicle Ethernet system. The HMTD utilizes a high-performance HMTD connector, designed for high-speed data transmission and offering excellent anti-interference and stability. Its optimized contact design and high-temperature and corrosion resistance make the HMTD interface suitable for the extreme operating conditions found in in-vehicle environments. The MATEnet interface utilizes the standardized MATEnet connection method, adapting to diverse in-vehicle Ethernet configuration requirements. The MATEnet connector offers high bandwidth and supports auto-negotiation, intelligently switching transmission rates based on transmission requirements, making it compatible with a wide range of in-vehicle Ethernet devices.

[0069] Preferably, refer to Figure 1 , the vehicle-mounted multi-communication protocol test mainboard also includes:

[0070] A power conversion module is used to convert an external first voltage into a second voltage based on the pressing state of the start button when the on-board multi-communication protocol test mainboard is configured in the first startup mode, and use the second voltage to power the on-board multi-communication protocol test mainboard; when the on-board multi-communication protocol test mainboard is configured in the second startup mode, based on the external power supply state, convert the external first voltage into the second voltage, and use the second voltage to power the on-board multi-communication protocol test mainboard.

[0071] Specifically, the vehicle-mounted multi-communication protocol test motherboard also includes a power conversion module, which is used to implement voltage adaptive conversion and modular power supply control according to different startup modes, ensuring that the test motherboard can stably start and enter normal working state in a variety of power supply scenarios. When the test motherboard is configured to the first startup mode, such as local debugging or independent power-on mode, the power conversion module receives a first voltage from the external power input interface, preferably a 12V or 24V DC input voltage, and when it detects that the start button is pressed, the power conversion module converts the first voltage into the second voltage required by the system through a voltage conversion circuit, such as a step-down DC-DC converter or an LDO voltage regulator module, such as a multi-channel regulated output of 5V, 3.3V or 1.8V, which is used to provide stable power supply for all core functional units including the processor module, FPGA chip, and communication module. When the test motherboard is configured to the second startup mode, such as vehicle access or remote wake-up mode, the power conversion module does not rely on manual button triggering, but automatically determines the system startup conditions by detecting external power supply status signals, such as the vehicle ignition voltage IG or ACC line voltage. After detecting that the preset power supply threshold is reached, the external first voltage is also converted into the second voltage required for system operation, thereby realizing automatic power-on startup of the motherboard. In this mode, the power module can also work in conjunction with the management controller of the motherboard to achieve closed-loop control of the power supply timing, soft start curve and voltage rise rate to ensure that each module is powered on in sequence according to the preset timing, avoiding communication interference and equipment damage caused by system instability or voltage mutation. The power conversion module is preferably integrated with reverse connection protection, short circuit detection, overvoltage and overcurrent protection circuits, and has a power supply status indication function and a fault diagnosis output interface. It can be linked with the main processor for real-time status monitoring and protection strategy adjustment, significantly improving the safety and adaptability of the entire test platform in a multi-power supply environment.

[0072] The power interface of the in-vehicle multi-protocol test motherboard utilizes a 2-pin locking terminal connector, specifically designed for high-reliability and high-stability power supply systems. This connector features a locking mechanism, which mechanically locks the terminals and sockets together to create a secure connection, preventing loosening due to vibration, external forces, or prolonged use. This design is particularly suited for the high-vibration and high-noise environments of in-vehicle systems, ensuring reliable power transmission. The connector's plug and socket feature a polarity-sensitive design to prevent incorrect connection, ensuring proper polarity alignment. This effectively prevents problems such as power shorts, motherboard damage, and circuit malfunctions caused by incorrect connections. The 2-pin terminal connector utilizes highly conductive materials and precision manufacturing techniques, resulting in excellent contact performance and corrosion resistance. It can withstand the high current loads commonly found in in-vehicle systems, ensuring high efficiency and low temperature rise during extended use. The compact design of the 2-pin terminal connector perfectly matches the miniaturization requirements of in-vehicle electronic devices, providing a highly reliable power connection solution within limited space and facilitating integration into in-vehicle test motherboards and other electronic modules. The connector has an IPXX rating, offering waterproof and dustproof properties, making it suitable for the harsh conditions of complex in-vehicle environments. By utilizing a 2-pin locking terminal block connector, the motherboard ensures stable and secure power input, preventing risks such as poor contact, short circuits, and power outages in highly dynamic environments. This provides a solid power source for testing vehicles and onboard equipment.

[0073] Preferably, refer to Figure 1 , the vehicle-mounted multi-communication protocol test mainboard also includes:

[0074] HDMI display interface, used to convert device test digital image data into high-speed serial differential signals and send the high-speed serial differential signals to the display;

[0075] The processor module is further configured to convert the device test report into device test digital image data.

[0076] Specifically, the in-vehicle multi-communication protocol test motherboard also includes an HDMI display interface module, which encodes and processes the device test digital image data generated by the processor module and converts it into a high-speed serial differential signal compliant with the HDMI standard. This signal is then transmitted to an external display device via a standard HDMI physical interface, enabling real-time graphical presentation of the test data. The HDMI display interface module comprises a video encoding unit, a timing control unit, and a signal driver. The video encoding unit receives the raw test image data output by the processor module and performs RGB data encoding, row and column timing generation, synchronization signal insertion, and differential drive according to the HDMI protocol standard. The output TMDS encoded data stream is transmitted via differential lines in a high-speed serial manner to the connected display, achieving low-latency, high-resolution, and high-refresh-rate image display. The processor module is also equipped with a graphics generation engine that converts internally generated device test reports, including information on the communication protocol interaction process, response frame parsing results, error frame statistics, and test judgment results, into standard-format image data frames, preferably in bitmap, vector, or frame buffer formats. Visual elements such as color coding, chart curves, and status icons are then overlaid to enhance the intuitiveness and readability of the test information. Through the above configuration, the test motherboard of the present invention not only has the ability of automated multi-protocol testing, but also has the function of graphing and visualizing the test results, which is convenient for testers to conduct real-time observation, result comparison and fault tracing, and improve the overall test efficiency and operability. It is particularly suitable for application scenarios such as R&D and debugging sites, vehicle-mounted terminal maintenance and batch equipment screening.

[0077] Preferably, refer to Figure 1 , the vehicle-mounted multi-communication protocol test mainboard also includes:

[0078] NVME interface, used to receive configuration information sent by an external storage device and send the device test report to the external storage device;

[0079] The processor is further configured to configure the vehicle-mounted multi-communication protocol test mainboard according to the configuration information.

[0080] Specifically, the vehicle-mounted multi-communication protocol test motherboard also includes an NVMe high-speed interface module for establishing a data communication connection with an external high-speed non-volatile storage device to achieve high-speed reading and writing and dynamic interactive management of test data. The NVME interface is implemented using a physical and protocol stack that complies with the NVMe protocol standard, supports PCIe Gen3 and above, and has high-bandwidth, low-latency, and low-power storage access capabilities, making it suitable for real-time access to large amounts of data during the test process. During system initialization or test task switching, the NVMe interface can read pre-stored communication protocol configuration files, test instruction templates, test item parameter sets and other configuration information from the external storage device, and load them into the processor module or FPGA module inside the motherboard via DMA, thereby achieving rapid configuration and automated deployment of the test system. After the device test is completed, the device test report generated by the processor module can be written to the external NVMe storage device at high speed via the NVMe interface, supporting classification management by test tasks, device numbers, timestamps and other dimensions, facilitating subsequent offline analysis, batch backtracking or quality assessment. The NVMe interface module also integrates a multi-queue data access control unit, a power-off protection mechanism, and storage integrity verification logic, which can effectively improve the concurrency and system stability during large-scale data interaction, and avoid the loss of critical data due to power fluctuations or test interruptions. Through the above configuration, the test motherboard of the present invention not only has the ability to test multiple communication protocols, but also provides high-speed, high-capacity, and structured data interaction and management capabilities, which is suitable for batch equipment testing scenarios and industrial-grade automatic testing platforms with strict requirements on storage performance. The processor module is also configured to automatically configure and load parameters for each functional module of the motherboard according to the configuration information during the initialization phase after the vehicle-mounted multi-communication protocol test motherboard is powered on or restarted. The processor can read configuration information such as communication protocol parameters, test instruction sets, signal mapping rules, module enable status, interface working mode, and power management strategy from an external storage device, SPI Flash, or a configuration file obtained through a remote communication port, and accordingly configure the FPGA chip, CANFD communication module, vehicle-mounted Ethernet communication module, clock module, power conversion module, and HDMI display interface module of the motherboard one by one to achieve adaptive startup and function initialization of the system. The processor also supports dynamic configuration and runtime hot update functions. During the execution of test tasks, it dynamically modifies the operating parameters of specific modules or switches their operating modes according to user instructions or external trigger events to adapt to diverse testing requirements and complex application scenarios, thereby improving the flexibility and scalability of the test platform.

[0081] Preferably, refer to Figure 1 , the vehicle-mounted multi-communication protocol test mainboard also includes:

[0082] A clock module, used to generate a clock signal;

[0083] The processor is further configured to generate a unified timestamp for the response frame and the standard Ethernet response signal according to the clock signal.

[0084] Specifically, the in-vehicle multi-communication protocol test motherboard also includes a clock module, which is used to provide a stable and configurable system clock signal for each functional module of the motherboard, ensuring the timing consistency, data synchronization and communication accuracy of the entire test system under the conditions of multi-protocol concurrent operation. The clock module includes a high-precision crystal oscillator unit, a clock synthesis circuit, a clock buffer distributor and an optional programmable oscillator or PLL phase-locked loop component. The clock module generates a reference frequency signal through a crystal oscillator as the source of the system frequency of the entire test motherboard; through clock synthesis technologies such as PLL and DPLL, the reference frequency is up-converted or divided to generate different target frequencies, which are provided to various modules such as the FPGA chip, CANFD communication module, Ethernet transceiver, PCIe / NVMe interface, etc. The clock module supports master-slave clock synchronization in multi-protocol communication scenarios. When conducting CANFD or automotive Ethernet communication tests, it achieves phase lock and edge alignment with a master or external clock signal, ensuring accurate timing during communication tests. It also supports dual-crystal hot-backup, automatically switching to the backup crystal if the master crystal fails or frequency drifts beyond the specified limit. The clock health monitoring module provides online diagnostics and alarms. The clock module also integrates jitter cleaners and filters to reduce jitter and EMI interference during high-speed differential transmission of high-frequency clock signals, ensuring signal integrity of high-speed interfaces. The processor module is also configured to time-stamp communication response data received during testing based on the high-precision clock signal provided by the clock module. It generates a unified timestamp format that conforms to the system timebase for both the response frames from the CANFD communication module and the standard Ethernet response signals converted from a standard Ethernet transceiver. The generated timestamps are preferably incremented with nanosecond or microsecond precision, and are monotonic, globally unique, and resolvable. The introduction of a unified timestamp enables the processor module to achieve timing alignment and synchronous analysis of response data returned under different communication protocols, thereby supporting the combined analysis of CANFD response frames and automotive Ethernet response signals on the time axis in the same test task, achieving timing matching of cross-protocol events. It can also quickly evaluate the occurrence time, communication delay, and jitter characteristics of specific error frames or packet loss frames by performing statistical calculations on their timestamp information. It can also sort, filter, and replay test response data based on timestamp sequence, providing data support for subsequent presentation of timing diagrams / curve graphs on the HDMI image display interface. To improve the accuracy and consistency of timestamp generation, the processor can also collaborate with the clock module, using a hardware-triggered sampling mechanism or FPGA co-processing to complete timestamp binding at the moment of data reception, avoiding time offsets caused by software delays.

[0085] In some embodiments, the processor and memory modules in the on-board multi-communication protocol test motherboard utilize a modular design architecture that supports integrated plug-and-play replacement, allowing users to quickly upgrade or customize CPU computing power or storage capacity based on different test application requirements, computing load intensity, or system function expansion needs. The modular interface is preferably a standard high-speed interconnect interface with advantages such as hot-swappable capability, strong compatibility, and high signal integrity, significantly improving the test platform's flexible deployment capabilities and subsequent maintainability. The motherboard system software utilizes a layered, decoupled architecture, with application-layer programs and communication protocol stacks interacting via a set of standardized, abstracted interface protocols. This ensures that the protocol processing logic and upper-layer test business logic are independent and uncoupled from each other. The motherboard supports loading or replacing different protocol stacks based on external configuration files, test environments, or FPGA logic changes without modifying the upper-layer application logic. The underlying software driver and hardware abstraction layer are highly versatile and can be quickly ported to different processing platforms or embedded operating systems. The motherboard's various peripheral interfaces, such as PCIe, SPI, UART, and I2C, utilize a unified interface management middleware to enable resource sharing and dynamic scheduling, improving the overall system's IO resource utilization efficiency. By combining modular hardware design with a decoupled software architecture, the test motherboard provided by the present invention has high scalability, high adaptability, and high lifecycle management capabilities, and is suitable for complex in-vehicle electronic system testing tasks involving multiple vehicle models, multiple suppliers, and multiple protocol combinations.

[0086] The in-vehicle multi-communication protocol test motherboard is further supported by a system-level application testing software architecture platform. This platform is deeply integrated with the motherboard's hardware architecture, providing a full-stack software support system from low-level drivers to application-layer test logic. The platform pre-integrates and automatically loads drivers for various functional modules on the vehicle motherboard, supporting both Windows and Linux operating systems to meet the needs of different developers and integrators. Regarding protocol support, the platform encapsulates and abstracts communication protocols at the operating system kernel level. Its communication protocol stack implements complete parsing and management of CAN and CANFD protocols, as well as Ethernet-based TCP, UDP, and IP protocols. It supports multi-protocol parallel operation, data multiplexing, and protocol-level fault detection, and provides a unified call entry point and middleware scheduling mechanism. The software platform also features a multi-language application programming interface layer for developers, supporting programming interfaces in mainstream development languages such as C / C++, Python, Java, and Rust. Developers can quickly build customized test processes, simulation tools, or analysis applications based on this platform, significantly improving system programmability and ease of integration. In terms of test task organization and execution, the platform supports custom test project creation, flexible test case management, and a use case library maintenance mechanism. Test cases have independent description languages or metadata structures to achieve loosely coupled design with hardware interfaces and test frameworks. The test platform supports rapid deployment of test cases to any functional module and automated execution. It has functional modules such as task queue scheduling, error retry, log collection, and result report generation, which significantly reduces the complexity of test script development and system integration. Through the collaborative platform design of software and hardware, the system not only realizes a unified test interface for multiple communication protocols, cross-platform operating environment support, dynamic use case deployment and automated execution, but also has good scalability, maintainability, and engineering implementation capabilities. It is suitable for a variety of scenarios such as production testing, functional verification, and regression testing of automotive electronic systems.

[0087] The vehicle-mounted multi-communication protocol test motherboard also integrates a USB module. The USB3.0 module includes a main control chip that complies with the USB 3.1Gen1 standard, an ultra-high-speed differential signal driving circuit, and a data interaction bus between the processor module or the FPGA module. It can provide a data transmission rate of up to 5Gbps, which is used to achieve high-speed, low-latency external device access and data exchange. The program development of each communication protocol interface of the vehicle-mounted multi-communication protocol test motherboard is implemented based on the Windows or Linux operating system environment. As the basic platform for the operation of the motherboard software, the operating system has the ability to uniformly manage and schedule various hardware resources on the motherboard, and provides stable kernel support and hardware abstraction interfaces to ensure the stable operation and resource isolation of various functional modules in multi-tasking parallel scenarios. The USB interface is used for connection and communication between the vehicle-mounted multi-communication protocol test motherboard and external devices. The USB interface can be connected to devices such as the mouse, keyboard, and USB flash drive.

[0088] The in-vehicle multi-protocol test board integrates eight CAN interfaces and two Gigabit Ethernet interfaces, providing an efficient and flexible solution for testing, monitoring, and data transmission in complex vehicle network environments. The test board is widely applicable in a variety of fields, including automotive R&D, intelligent transportation, and vehicle inspection. It plays a particularly crucial role in the testing and validation of domain controllers. During domain controller testing, the domain controller and the test board exchange signals via the vehicle bus system, involving bidirectional data transmission of CAN signals and 1000Base-T1 Ethernet signals. Specific test programs run within the test board to ensure comprehensive verification of in-vehicle communication protocols, data integrity, and real-time performance. The test board can simulate data exchange between the domain controller and other on-board electronic control units (ECUs) through its eight CAN interfaces and two Gigabit Ethernet interfaces, adapting to the complexity of actual vehicle network environments. Through its flexibly configurable interfaces, the test board can replicate various communication scenarios in vehicle networks, simulating interactions and data flows under different communication protocols. The test board, supporting both CAN and automotive Ethernet protocols, verifies communication protocols between the domain controller and other ECUs, checking data packet accuracy, integrity, and real-time performance. Specifically, when using the CAN FD protocol, the board verifies the high efficiency of data frame transmission and its support for large data volumes, ensuring the stability of the domain controller when handling multiple in-vehicle communication protocols. The test board simulates not only normal communication but also fault conditions, such as communication interruptions, data loss, or error frames, to test the domain controller's responsiveness and error handling mechanisms. Furthermore, the board can perform performance tests under high load, simulating the stability and response time of in-vehicle systems under stressful conditions and verifying the domain controller's reliability under extreme operating conditions. During testing, the board supports automated testing processes, allowing users to customize test cases, which the board will automatically execute and generate detailed reports. During testing, the board records all data exchanges and events in real time for subsequent analysis and problem tracking. This data includes packet content, error frames, and response times transmitted during each test cycle, enabling developers to clearly analyze the domain controller's performance in various scenarios. During testing, the test motherboard simulates the vehicle bus, conducting dual communication via CAN FD and in-vehicle Ethernet, transferring data between the domain controller and other ECUs to ensure compatibility and interoperability between the different protocols. Using dedicated test procedures, the motherboard verifies data packet transmission accuracy, checking data integrity, real-time performance, and transmission reliability, ensuring no packet loss, delays, or corruption. By simulating various fault scenarios, the domain controller's response time and fault recovery capabilities are tested under various abnormal conditions, such as vehicle network failures, communication interruptions, or error frame handling mechanisms.Under high-load conditions, the domain controller's performance is tested when handling large amounts of data, multiple signal channels, and high-frequency interactions, including response time, bandwidth utilization, and stability under extreme loads. All test data is recorded in real time, including packet content, timestamps, test results, and more. This can be used to analyze the domain controller's performance bottlenecks and provide developers with detailed troubleshooting information. Through these testing capabilities, the in-vehicle multi-communication protocol test motherboard can not only efficiently and accurately verify the domain controller's communication capabilities and stability in the vehicle network, but also provide developers with detailed performance data and fault reports to help optimize vehicle system design and improve system reliability.

Claims

1. A vehicle-mounted multi-communication protocol test motherboard, characterized in that: include: CANFD communication module, used to send test frames to the device under test when receiving a CANFD test command; receiving a response frame corresponding to the test frame sent by the device to be tested; The CAN FD communication module includes: an FPGA chip, which is used to generate a test frame when receiving the CAN FD test instruction; a plurality of CAN transceivers, which are used to send the test frame to the device to be tested; receiving a CAN response frame corresponding to the test frame sent by the device to be tested, and converting the CAN response frame into a response frame compatible with the PCIe bus; the CAN FD communication module also includes: an SPI Flash chip, which is used to store the startup firmware configuration information and communication logic configuration information of the FPGA chip; the FPGA chip is also used to perform startup configuration according to the startup firmware configuration information and communication logic configuration information; wherein, the CAN FD communication module supports the generation of test frames with extended data fields, which is used to simulate the high-bandwidth communication scenario of intelligent connected vehicles; The vehicle-mounted Ethernet communication module is used to convert a standard Ethernet test signal into a vehicle-mounted Ethernet test signal, and send the vehicle-mounted Ethernet test signal to the device to be tested; receive a vehicle-mounted Ethernet response signal corresponding to the vehicle-mounted Ethernet test signal sent by the device to be tested, and convert the vehicle-mounted Ethernet response signal into a standard Ethernet response signal; the vehicle-mounted multi-communication protocol test mainboard also includes: an HDMI display interface, used to convert device test digital image data into a high-speed serial differential signal, and send the high-speed serial differential signal to the display; the processor module is also used to convert the device test report into device test digital image data; the vehicle-mounted multi-communication protocol test mainboard also includes: an NVME interface, used to receive configuration information sent by an external storage device, and send the device test report to the external storage device; the processor is also used to configure the vehicle-mounted multi-communication protocol test mainboard according to the configuration information; the vehicle The multi-communication protocol test mainboard also includes: a clock module for generating a clock signal; the processor is also used to generate a unified timestamp for the response frame and the standard Ethernet response signal based on the clock signal; wherein, the clock module synchronizes high-precision clock signals to the FPGA and Ethernet transceiver through the PCIe interface to achieve nanosecond-level time alignment of CANFD and the on-board Ethernet response signal; the on-board Ethernet transceiver supports automatic identification of 100BASE-T1 / 1000BASE-T1 protocol versions and dynamically adjusts signal equalization parameters according to the signal characteristics of the device under test; the NVME interface supports online update of the test instruction library, and the processor module can dynamically reconstruct the FPGA test logic according to the newly imported test case; the processor module is used to generate CANFD test instructions and standard Ethernet test signals; and generates a device test report for the device under test based on the response frame and the standard Ethernet response signal. The test frames include data frames, control instruction frames, fault frames and error frames, and the in-vehicle Ethernet test signals include data packets, control signals, fault signals and error signals.

2. The vehicle-mounted multi-communication protocol test motherboard according to claim 1, characterized in that: The vehicle-mounted Ethernet communication module includes: An in-vehicle Ethernet transceiver, configured to convert the standard Ethernet test signal into an in-vehicle Ethernet test signal and send the in-vehicle Ethernet test signal to the device to be tested; A common Ethernet transceiver is used to receive a vehicle-mounted Ethernet response signal corresponding to the vehicle-mounted Ethernet test signal and sent by the device to be tested, and convert the vehicle-mounted Ethernet response signal into a standard Ethernet response signal.

3. The vehicle-mounted multi-communication protocol test motherboard according to claim 2, characterized in that: The vehicle-mounted Ethernet communication module also includes: The dip switch is used to set the vehicle-mounted Ethernet communication module as a master node when in a first switch state; and to set the vehicle-mounted Ethernet communication module as a slave node when in a second switch state.

4. The vehicle-mounted multi-communication protocol test motherboard according to claim 2, characterized in that: The vehicle-mounted Ethernet communication module also includes: A signal indicator light is configured to be extinguished when the vehicle-mounted Ethernet transceiver loses power, to be illuminated when the vehicle-mounted Ethernet transceiver is powered, and to flash at a preset frequency when the vehicle-mounted Ethernet transceiver is working.

5. The vehicle-mounted multi-communication protocol test motherboard according to claim 1, characterized in that: The vehicle-mounted multi-communication protocol test mainboard also includes: A power conversion module is used to convert an external first voltage into a second voltage based on the pressing state of the start button when the on-board multi-communication protocol test mainboard is configured in the first startup mode, and use the second voltage to power the on-board multi-communication protocol test mainboard; when the on-board multi-communication protocol test mainboard is configured in the second startup mode, based on the external power supply state, convert the external first voltage into the second voltage, and use the second voltage to power the on-board multi-communication protocol test mainboard.

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