Image sensor evaluation method and device and storage medium

Abstract

The invention provides an evaluation method and device for an image sensor and a storage medium, and the method comprises the steps: transmitting multi-channel image data to a data processing module through a plurality of data channels by the image sensor, and enabling the data processing module to process the multi-channel image data according to a preset strategy; and the data processing module sends the processed multi-channel image data to an upper computer, so that the upper computer evaluates the image sensor based on the multi-channel image data. According to the invention, data interface protocols with unified standards can be conveniently set, and products of different manufacturers can be tested by using the same evaluation system, so that the test flexibility is improved, and the working efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of image sensors, and particularly relates to a method, device, and storage medium for evaluating an image sensor. Background Art

[0002] An image sensor uses the photoelectric conversion function of optoelectronic devices to convert the optical image on the photosensitive surface into an electrical signal that is in a corresponding proportional relationship with the optical image. Compared with an image orthicon, a solid-state image sensor has the characteristics of small size, light weight, high integration, high resolution, low power consumption, long life, and low price. Therefore, it has been widely used in various industries. An industrial image sensor is a key component in a machine vision system and is often used in industrial assembly lines to replace the measurement and judgment of the human eye. Compared with image sensors in other fields, industrial image sensors require higher image stability, data transmission capabilities, and anti-interference capabilities. Industrial image sensors have the characteristics of shorter shutter times, higher scanning frequencies, and larger image resolutions.

[0003] During the process of conceiving and forming this application, the applicant found that there is no unified standard data interface protocol for image sensors from various manufacturers in the market. For products from different manufacturers, different evaluation systems are required for testing, lacking flexibility. Summary of the Invention

[0004] To alleviate the above problems, this application provides a method for evaluating an image sensor, which is applied to the evaluation of a line array image sensor. The method for evaluating an image sensor includes: the image sensor transmits multi-channel image data to a data processing module through multiple data channels, enabling the data processing module to process the multi-channel image data according to a preset strategy; the data processing module sends the processed multi-channel image data to a host computer, enabling the host computer to evaluate the image sensor based on the multi-channel image data.

[0005] This application also provides an evaluation device for an image sensor. The evaluation device for an image sensor includes a processor and a storage medium connected to each other, where: the storage medium is used to store a computer program; the processor is used to read and run the computer program to implement the method for evaluating an image sensor as described above; and / or, the evaluation device for an image sensor includes an image data receiving unit, a first data processing unit, a second data processing unit, and a host computer; the image data receiving unit is connected to the image sensor through multiple serial data channels to send the multi-channel image data of the image sensor to the first data processing unit; the first data processing unit is used to perform channel binding on the multiple data channels to achieve data alignment of the multi-channel image data, and decode the multi-channel image data according to a preset data format to send the processed multi-channel image data to the second data processing unit; the second data processing unit is used to send the processed multi-channel image data to the host computer to evaluate the image sensor.

[0006] The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the evaluation method of the image sensor as described above are implemented.

[0007] As described above, the evaluation method, device and storage medium of the image sensor provided by the present application enable the image sensor to transmit multi-channel image data to the data processing module through multiple data channels, and enable the data processing module to process the multi-channel image data according to a preset strategy; the data processing module sends the processed multi-channel image data to the host computer, enabling the host computer to evaluate the image sensor based on the multi-channel image data; it is possible to conveniently set a unified standard data interface protocol, and for products from different manufacturers, the same evaluation system can be used for testing, increasing the test flexibility and improving work efficiency. Description of the Drawings

[0008] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 It is a flowchart of the evaluation method of the image sensor according to an embodiment of the present application.

[0010] Figure 2 It is a block diagram of the evaluation device according to an embodiment of the present application.

[0011] Figure 3 It is a schematic diagram of the evaluation device architecture according to an embodiment of the present application.

[0012] Figure 4 It is a flowchart of channel binding according to an embodiment of the present application.

[0013] Figure 5 It is a schematic diagram of the FPGA architecture of the evaluation device according to an embodiment of the present application.

[0014] Figure 6 It is a schematic diagram of the storage space division according to an embodiment of the present application.

[0015] Figure 7 It is a schematic diagram of the data cache read / write process of the FPGA (TX end) according to an embodiment of the present application.

[0016] Figure 8 It is a schematic diagram of the data cache read / write process of the FPGA (RX end) according to an embodiment of the present application.

[0017] Figure 9 Schematic diagram of the overall evaluation process of the evaluation device according to an embodiment of the present application.

[0018] The realization of the purpose of the present application, functional features and advantages will be further described in conjunction with the embodiments with reference to the accompanying drawings. Through the above-mentioned accompanying drawings, the specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0019] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0020] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context in the specific embodiments.

[0021] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] First Embodiment

[0023] The present application provides an evaluation method for an image sensor, which is applied to the evaluation of a linear array image sensor. Figure 1 Flowchart of the evaluation method for the image sensor according to an embodiment of the present application.

[0024] As Figure 1 shown, in one embodiment, the evaluation method for the image sensor includes:

[0025] S10: The image sensor transmits multi-channel image data to the data processing module through multiple data channels, enabling the data processing module to process the multi-channel image data according to a preset strategy.

[0026] Exemplarily, the image sensor utilizes the photoelectric conversion function of optoelectronic devices to convert the optical image on the photosensitive surface into an electrical signal that is in a corresponding proportional relationship with the optical image. Compared with photosensitive elements such as photodiodes and phototransistors, which are "point" light sources, the image sensor divides the optical image on its light-receiving surface into many small units and converts it into a functional device that can generate usable electrical signals. Image sensors are divided into vidicons and solid-state image sensors. Compared with vidicons, solid-state image sensors have the characteristics of small size, light weight, high integration, high resolution, low power consumption, long lifespan, and low price. Therefore, they have been widely used in various industries.

[0027] Exemplarily, during the process of evaluating the image sensor, in order to be able to handle image sensor products from different manufacturers, a unified data transmission protocol can be configured. Through a data adapter board, different image sensors can all transmit the sensed data to the data adapter board through multiple data channels. The data adapter board is provided with multiple data channels, receives the multi-channel image data of the image sensor, decodes and forwards it to the data processing module according to the data characteristics of different channels. After receiving the data of the image sensor, the data processing module can perform unified encoding processing on the data.

[0028] S20: The data processing module sends the processed multi-channel image data to the host computer, enabling the host computer to evaluate the image sensor based on the multi-channel image data.

[0029] Exemplarily, after encoding and processing the sensed data of the image sensor according to a preset protocol format, the data processing module can forward it to the host computer so that the host computer can perform the required evaluation on the image sensor.

[0030] In this embodiment, enabling the image sensor to transmit multi-channel image data to the data processing module through multiple data channels, enabling the data processing module to process the multi-channel image data according to a preset strategy; the data processing module sends the processed multi-channel image data to the host computer, enabling the host computer to evaluate the image sensor based on the multi-channel image data; it is possible to conveniently set a unified standard data interface protocol. For products from different manufacturers, the same evaluation system can be used for testing, increasing the testing flexibility and improving work efficiency.

[0031] Optionally, the data processing module includes a first data processing unit; the step of the image sensor transmitting multi-channel image data to the data processing module through multiple data channels and enabling the data processing module to process the multi-channel image data according to a preset strategy includes:

[0032] The first data processing unit performs channel binding on the multiple data channels of the image sensor to align the multi-channel image data, so as to obtain first sensor data through the multiple data channels.

[0033] The first data processing unit decodes the first sensor data according to a preset data format and performs image algorithm processing to obtain second sensor data.

[0034] Exemplarily, the first data processing unit respectively obtains the first sensor data collected by the image sensor from multiple data channels. The transmission rate is relatively high, and the wire lengths between the channels are different. Therefore, the first data processing unit first performs channel binding on the data of each channel to achieve data alignment, enabling the data of each channel to reach the receiving end simultaneously in the case of data delay, so as to facilitate the decoding and algorithm processing work of the first data processing unit.

[0035] Optionally, the step of the first data processing unit performing channel binding on the multiple data channels of the image sensor to align the multi-channel image data to obtain first sensor data and the steps before it include:

[0036] Receiving the sampling data of the image sensor, and for each data channel, determining the starting position of the valid data of the sampling data according to the virtual coding.

[0037] Adjusting the phase delay between the data channel and the clock channel according to the starting position of the valid data to ensure that the clock sampling edge is located in the middle of the data segment of the valid data, so as to obtain the valid data of the data channel.

[0038] Determining the frame header position of the valid data according to the valid video start flag and the valid video end flag, so as to intercept the image data of the data channel.

[0039] Exemplarily, for the data channels of the LVDSRX module, during the process of using the LVDSRX module to receive external image data, the high-speed serial data stream can be converted into a parallel data stream through the serial-to-parallel IP (Select IO Interface Wizard Intellectual Property). For each data channel, determine Bitslip (bit slip, used to determine the start of the valid data) according to the virtual coding dummycode (virtual coding, the padding data in the valid data transmission gap), and accordingly finely adjust the phase delay between the data channel and the clock channel to ensure that the clock sampling edge is always located in the middle of the data.

[0040] The adjustment strategy for the phase delay can be as follows: First, adjust the phase delay until the virtual coding can be detected. Subsequently, increment the phase delay starting from this value until no virtual coding can be detected within the specified time. Finally, based on this phase delay, roll back four cycles, end this adjustment, and detect the data sampling situation in real time.

[0041] Subsequently, determine the frame header position according to the SAV / EAV (Start of Active Video / End of Active Video) coding rule, and extract the valid image data therefrom.

[0042] Optionally, in the step of the first data processing unit performing channel binding on multiple data channels of the image sensor to align the multi-channel image data so as to obtain the first sensor data through the multiple data channels, at least one of the following is included:

[0043] Perform data alignment binding on multiple channels inside the image sensor;

[0044] Perform data alignment binding on multiple channels between image sensors.

[0045] Exemplarily, performing data alignment binding on multiple channels inside the image sensor can enable the data of multiple transmission channels of the image sensor to be aligned when reaching the receiver, facilitating the first data processing unit at the receiving end to uniformly process the data of each channel. Exemplarily, performing data alignment binding on the data between image sensors can enable the data between image sensors to be aligned when reaching the receiver, facilitating the first data processing unit at the receiving end to uniformly process the data of each image sensor.

[0046] Optionally, the step of performing data alignment binding on multiple channels inside the image sensor includes:

[0047] Receive the image data of each channel inside the image sensor, perform virtual coding counting on the image data of each channel, and write them into the buffer at the same corresponding starting address simultaneously;

[0048] Based on the virtual coding counting result, correspondingly adjust the read address of the image data of multiple channels inside the image sensor to align the multiple channels inside the image sensor.

[0049] Exemplarily, the first data processing unit can receive the sampled data from each channel of the image sensor and write it into the buffers with the same starting address corresponding thereto simultaneously. When writing data, count the virtual code (dummycode) in the data, increment it when the virtual code (dummycode) appears, and otherwise clear the counter. Set the first data channel as the reference channel. When the count value of the counter corresponding to the reference channel reaches the set threshold, start adjusting the read address of the buffer to achieve data alignment of multiple data channels of a single image sensor.

[0050] Optionally, the step of correspondingly adjusting the read addresses of the image data of multiple channels inside the image sensor based on the virtual code counting result includes:

[0051] When writing data, for the image data of each channel, increment the counting result when the virtual code appears, and otherwise clear the counting result;

[0052] Set any channel as the reference channel. When the count value of the counter corresponding to the reference channel reaches the preset threshold, compare the counting results of each channel:

[0053] When the counting result of the target channel is less than that of the reference channel, reduce the corresponding difference of the read address of the buffer of the target channel;

[0054] When the counting result of the target channel is greater than that of the reference channel, increase the corresponding difference of the read address of the buffer of the target channel.

[0055] Exemplarily, set the first data channel as the reference channel. When the count value of the counter corresponding to the reference channel reaches the set threshold, start adjusting the read address of the buffer. If the count value of this channel is smaller than that of the reference channel, reduce the corresponding difference of the read address of the buffer of this channel; on the contrary, increase the corresponding difference of the read address of the buffer of this channel. By changing the read addresses of the buffers of each channel, the data binding of each data channel of a single image sensor is completed to achieve data alignment.

[0056] Optionally, the steps of performing data alignment and binding on multiple channels between image sensors include:

[0057] Send the image data received by each sensor into the buffer for caching, and count the amount of data stored in each buffer;

[0058] When the amount of data stored in each buffer reaches the set threshold, simultaneously read out the valid data in each buffer so that the multiple data channels between the sensors achieve data alignment.

[0059] Exemplarily, after completing the multi-channel binding inside a single image sensor, the valid data output by each image sensor receiving module is sent to a buffer for caching. When the amount of data stored in each buffer reaches a set threshold, the valid data in each buffer is read out simultaneously to complete the channel binding between the image sensors.

[0060] Optionally, the data processing module includes a second data processing unit, and the second data processing unit is communicatively connected to the first data processing unit based on the Aurora protocol of the fiber optic interface.

[0061] Exemplarily, in order to ensure low latency, high frame rate, and large-size real-time imaging of industrial sensors, the present application adopts the Aurora protocol based on the fiber optic interface to implement image data transmission and control signal communication between the sending end and the receiving end.

[0062] Optionally, when the first data processing unit sends the second sensor data to the second data processing unit, it includes:

[0063] The first data processing unit sends the second sensor data into an asynchronous FIFO for caching, and sends the cached data to the Aurora module according to the AXI4-Stream protocol, and then sends it to the second data processing unit through the fiber optic interface according to the Aurora protocol.

[0064] Exemplarily, when the first data processing unit and the second data processing unit are respectively implemented by FPGA, the FPGA (TX end) of the first data processing unit first sends the image data with CRC check (Cyclic Redundancy Check, used to detect or check errors that may occur after data transmission or storage) into an asynchronous FIFO for caching, and then sends the image data stream to the Aurora 64B / 66B IP according to the AXI4-Stream protocol. After integrating the data according to the aurora protocol, it is sent to the FPGA (RX end) of the second data processing unit through a 10 Gigabit SFP interface, and the FPGA (RX end) detects whether there are bit errors in the transmission of the received data through CRC check.

[0065] Optionally, when the first data processing unit sends the second sensor data to the second data processing unit, it further includes:

[0066] The first data processing unit sends the control information data into an asynchronous FIFO for caching, and sends the cached control information to the user traffic control interface of the Aurora module according to the AXI4-Stream protocol, so as to send it to the second data processing unit together with the second sensor data.

[0067] Exemplarily, when the first data processing unit and the second data processing unit are respectively implemented by FPGAs, the first data processing unit FPGA (TX side) sends the packed 256-byte control information data into an asynchronous FIFO for caching, and then sends the control packet data stream to the UFC (User Flow Control) interface of the Aurora64B / 66B IP according to the AXI4-Stream protocol, and sends it to the FPGA (RX side) of the second data processing unit together with the image data to realize communication between the two parties.

[0068] Optionally, the steps for the data processing module to send the processed multi-channel image data to the host computer so that the host computer evaluates the image sensor based on the multi-channel image data include:

[0069] The host computer accesses the registers of the data processing module by means of interruption or query to read the processed multi-channel image data.

[0070] Exemplarily, the registers of the data cache module are provided with 4-way status flags corresponding to 4 cache pools, which are used to indicate whether the data in the current cache pool has been prepared. In addition, there is also a sequence flag, which is used to indicate the order of arrival of the data in the current four cache pools. When the image data is read from the data cache module, the host computer detects the status flag and the sequence flag by means of interruption or query, determines the address of the read operation, and reads out the image data from the corresponding cache pool.

[0071] Optionally, the data processing module realizes the communication connection with the host computer based on the PCIe protocol;

[0072] The data processing module uses the DMA / Bridge Subsystem for PCI express IP as the bus endpoint in the PCIe protocol bus.

[0073] Exemplarily, in order to realize the high-frame-rate real-time imaging of industrial sensors, this embodiment adopts the PCIE protocol to realize the image data transmission between the host computer and the FPGA (RX side) of the second data processing unit and the interaction of control signals.

[0074] The DMA / Bridge Subsystem for PCI Express IP serves as the Endpoint (bus endpoint) in the PCIE bus of the entire evaluation system. The host computer accesses the relevant registers of the FPGA (RX side) image cache by means of interruption or query, confirms the image data caching situation, and completes the reading of the image data for host computer imaging.

[0076] Optionally, the host computer realizes the interaction of control parameters between the host computer and the data processing module by reading and writing the PCIe base address register space. The control parameters are used for configuring the internal parameters of the data processing module and / or the parameters related to the image sensor.

[0077] Exemplarily, the host computer realizes the interaction of control parameters between the second data processing unit FPGA (RX end) and the host computer by reading and writing the PCIe BAR (Base Address Register) space, which is used to complete the configuration of the internal parameters of the FPGA and the configuration of the parameters related to the Sensor.

[0078] Optionally, the data processing module includes a storage module; before the data processing module sends the processed multi-channel image data to the host computer so that the host computer evaluates the image sensor based on the multi-channel image data, the following steps are included:

[0079] At least divide the storage space of the storage module into a first cache pool and a second cache pool, and set multiple rows of data storage space for each cache pool;

[0080] Cache the multi-channel image data row by row into the first cache pool and the second cache pool to synchronously read multiple rows of decoded data in the multi-channel image data.

[0081] Exemplarily, during the data caching process, the storage space of the DDR storage module can be divided into 4 cache pools, and each cache pool stores 12 rows of images. The RAW format LVDS image data can be cached in the DDR storage module with the above-divided space through the MIG IP (Memory Interface Generator) for subsequent processing.

[0082] Optionally, the step of caching the multi-channel image data row by row into the storage module to synchronously read multiple rows of decoded data in the multi-channel image data includes:

[0083] The first step: Based on the multi-channel image data cached asynchronously, in response to recognizing the first row flag, deposit it into the row data storage space of the first cache pool in sequence according to the set write address, and read the multi-channel image data frame by frame from the row data storage space of the second cache pool of the storage module according to the set read address;

[0084] The second step: Change the write address to the address of the second cache pool, change the read address to the address of the first cache pool, and return to the steps of the first step above.

[0085] Exemplarily, in order to improve the caching efficiency, the LVDS data is first cached in the asynchronous FIFO before being written into the DDR storage module and is written into the DDR storage module by burst transmission, and the same is true for the read operation.

[0086] Optionally, before storing or reading multi-channel image data into / from the cache pool in sequence, it further includes: querying the frame status flag and the frame sequence flag to determine the cache pool serial number for storing or reading the multi-channel image data;

[0087] And / or,

[0088] Before changing the write address or read address of the cache pool, it further includes: querying the frame status flag and the frame sequence flag to determine the cache pool serial number for changing the write address or read address.

[0089] Exemplarily, during the data caching process, there are 4 status flag bits corresponding to 4 cache pools, which are used to indicate whether the data in the current cache pool has been prepared. In addition, there is a sequence flag bit, which is used to indicate the order of arrival of the data in the current four cache pools. When the image data is transmitted into the data cache space, first query the sequence flag bit to find the cache pool where the earliest-arrived but unread image data is located, pull down the status flag bit corresponding to this cache pool, and write the latest input image data into this cache pool. When this image data transmission is completed, raise the status flag bit corresponding to the current cache pool again and update the sequence flag bit.

[0090] During the data reading process, after the data cache space receives the LVDS data, first identify the first row flag. After identifying the flag of the first row, deposit 12 rows of data into the asynchronous FIFO in sequence. The asynchronous FIFO data is deposited into cache pool 0, and at the same time, 12 rows of data are read from cache pool 3 and deposited into the transmit cache asynchronous FIFO. When 12 rows of data are written into the DDR storage module and 12 rows of data are read out from the DDR storage module, re-identify the first row flag and exchange the addresses of cache pools 0, 1, 2, and 3 (set the address of cache pool 3 as the address of cache pool 2, the address of cache pool 2 as the address of cache pool 1, the address of cache pool 1 as the address of cache pool 0, and the address of cache pool 0 as the address of cache pool 3).

[0091] Second Embodiment

[0092] The present application further provides an evaluation device for an image sensor. The evaluation device for the image sensor includes a processor and a storage medium connected to each other, wherein:

[0093] The storage medium is used to store a computer program;

[0094] The processor is used to read and run the computer program to implement the evaluation method for the image sensor as described above.

[0095] Figure 2 It is a block diagram of the evaluation device according to an embodiment of the present application.

[0096] As Figure 2As shown, optionally, the evaluation device of the image sensor includes an image data receiving unit 3, a data processing module 2, and a host computer 1. The data processing module 2 includes a first data processing unit 21 and a second data processing unit 22.

[0097] The image data receiving unit 3 is connected to the image sensor 4 through a multi-channel serial data channel to send the multi-channel image data of the image sensor 4 to the first data processing unit 21.

[0098] The first data processing unit 21 is used to perform channel binding on the multi-channel data channels to achieve data alignment of the multi-channel image data, and decode the multi-channel image data according to a preset data format, so as to send the processed multi-channel image data to the second data processing unit 22.

[0099] The second data processing unit 22 is used to send the processed multi-channel image data to the host computer 1 to evaluate the image sensor 4.

[0100] Exemplarily, during the process of evaluating the image sensor, in order to be able to handle image sensor products from different manufacturers, a unified data transmission protocol is configured. Through a data adapter board, different image sensors can all transmit the sensed data to the data adapter board through multi-channel data channels. The data adapter board is provided with multiple data channels, receives the multi-channel image data of the image sensor, decodes and forwards it to the data processing module according to the data characteristics of different channels. After receiving the data of the image sensor, the data processing module can perform unified encoding processing on the data.

[0101] Exemplarily, after encoding the sensed data of the image sensor according to a preset protocol format, the data processing module can forward it to the host computer so that the host computer can perform the required evaluation on the image sensor.

[0102] In this embodiment, the image sensor can transmit multi-channel image data to the data processing module through multi-channel data channels, and the data processing module can process the multi-channel image data according to a preset strategy; the data processing module can send the processed multi-channel image data to the host computer, enabling the host computer to evaluate the image sensor based on the multi-channel image data; it is possible to conveniently set a unified standard data interface protocol, and for products from different manufacturers, the same evaluation system can be used for testing, increasing the test flexibility and improving work efficiency.

[0103] In one embodiment, in view of the characteristics of high frame rate, large size, and multiple data interface protocols of industrial image sensors, the evaluation device of the image sensor in this embodiment includes a power supply system with adjustable output voltage, 32 LVDS serial data channels, a firmware remote upgrade system, and multiple data output interfaces such as USB3.0, CameraLink, and 10 Gigabit SFP to meet different test requirements.

[0104] Exemplarily, the main modules of the evaluation device of the image sensor are an LVDS (Low-Voltage Differential Signaling) image data receiving module, an FPGA (Field Programmable Gate Array) processing module, a DDR (Double Data Rate) storage module, a power supply module, a USB data output module, a Camera Link data output module, and an SFP (Small Form-factor Pluggable) data output module.

[0105] Figure 3 It is a schematic diagram of the architecture of the evaluation device for an embodiment of this application.

[0106] Due to the large size and high frame rate requirements of industrial image sensors, they usually complete data transmission through multiple channels, and the image transmission rate is relatively high. As Figure 3 shown, the industrial image sensor Sensor in this embodiment outputs image data to the adapter board through 1 to 32 serial data channels in accordance with the LVDS level standard, with higher transmission efficiency.

[0107] Exemplarily, in this application, the data of each channel is first subjected to channel binding to achieve data alignment, avoiding unequal wire lengths between pairs of data channels and a certain gap, so that the data transmission of each channel has no delay and the data can reach the receiving end at the same moment.

[0108] Figure 4 It is a flowchart of channel binding for an embodiment of this application.

[0109] As Figure 4 shown, the channel binding in this embodiment is described as follows:

[0110] (1) Channel binding inside the sensor

[0111] Receive the sampled data from each channel and write it into the buffer with the same starting address corresponding to it simultaneously.

[0112] When writing data, count the virtual codes in the data. When a virtual code appears, increment by one; otherwise, clear the counter.

[0113] Set the first data channel as the reference channel. When the count value of the counter corresponding to the reference channel reaches the set threshold, start adjusting the read address of the buffer. That is, if the count value of this channel is smaller than that of the reference channel, then reduce the corresponding difference in the read address of the buffer of this channel; otherwise, increase the corresponding difference in the read address of the buffer of this channel.

[0114] By changing the read addresses of the buffers of each channel, complete the data binding of each data channel and achieve data alignment.

[0115] (2) Channel binding between sensors

[0116] After completing the multi-channel binding inside a single sensor, send the valid data output by each sensor receiving module into the buffer for caching.

[0117] Until the amount of data stored in each buffer reaches the set threshold, read out the valid data in each buffer simultaneously to complete the channel binding between each sensor.

[0118] After that, the image data and configuration information are transmitted through the adapter board to the FPGA processing module. After the FPGA processes the image data internally, it can be sent to the next module through any one of the USB 3.0 interface, 10 Gigabit SFP optical interface, or CameraLink interface.

[0119] Figure 5 It is a schematic diagram of the FPGA architecture of the evaluation device according to an embodiment of the present application.

[0120] As Figure 5 shown, exemplarily, the Sensor (image sensor) outputs image data to the adapter board through 1 to 32 serial data channels in the LVDS level standard, and the image data and configuration information are transmitted through the adapter board to the FPGA processing module. After the FPGA processes the image data internally, it can be sent to the next module through the 10 Gigabit SFP optical interface.

[0121] LVDS image data receiving module: Consists of an LVDS interface and a resistor network, receives data and sends it to the FPGA.

[0122] DDR storage module: Consists of DDR3 chips for data storage.

[0123] Power supply module: The entire system is powered by a 12V power adapter. It is converted to 5V through a DC-DC power chip and then 3.3V, 1.8V, 1.5V, 1.2V, 1.0V, etc. required by the system are provided through a PMIC (Power Management Integrated Circuit). Among them, the three power supplies for the Sensor, namely the analog power supply, digital power supply, and IO power supply, are supplied by a programmable power supply module, which can meet the different power requirements of most image sensors on the market.

[0124] FPGA processing module: It mainly consists of an FPGA chip, a JTAG interface (Joint Test Action Group for internal testing of input and output signals), and Flash. It can process the data of the image sensor, configure the image sensor through I2C or SPI (Serial Peripheral Interface), and can also verify the algorithms of the image sensor. The specific flowchart is as Figure 5 shown. The descriptions of each module in the FPGA chip are as follows:

[0125] I. FPGA (TX side) module

[0126] 2.1 System clock module

[0127] This module is used to generate clocks with different frequencies (25MHz, 50MHz, 100MHz, 200MHz, 300MHz) for internal processing of the FPGA.

[0128] 2.2 Communication module

[0129] The control data is transmitted between the FPGA chip and the host PC through the USB 3.0 / SFP / CameraLink interface to complete the configuration of relevant parameters of the FPGA processing module, such as basic information like image size parameters, Sensor clock parameters, and PWM (Pulse Width Modulation) parameters, and operations such as FPGA firmware upgrade can also be completed.

[0130] 2.3 SPI / I2C read / write module

[0131] This module parses the control data from the USB3.0 / SFP / Cameralink interface, performs corresponding SPI / I2C read / write operations on external devices, and also switches between the on-board and off-board of the SPI / I2C bus to prevent conflicts between the slave device numbers of industrial sensors and the device numbers of internal devices in the evaluation system.

[0132] 2.4 Sensor Clock Configuration Module

[0133] This module provides a dynamically configurable high-precision and low-jitter clock according to the parameter settings of the host computer, and outputs it to the outside of the FPGA to supply the sensor.

[0134] 2.5 PWM Module

[0135] The PWM module generates a frame synchronization signal EFSYNC with adjustable frequency (0.1 MHz to 150 MHz) and adjustable duty cycle (0% to 100%) and outputs it to the outside of the FPGA to trigger the industrial sensor image sensor.

[0136] 2.6 Firmware Upgrade Module

[0137] In order to adapt to industrial image sensors with different interface protocols, the FPGA chip can perform read and write operations on the Flash module according to the firmware update instructions of the host computer, and reload the project corresponding to the protocol to complete the evaluation.

[0138] (1) Partial Function Reconfiguration

[0139] This module reads the FLASH content at the corresponding address according to the host computer instruction to implement partial function dynamic reconfiguration operation.

[0140] (2) Remote Firmware Upgrade

[0141] This module receives the firmware upgrade file from the host computer, intercepts the data stream from the USB3.0 / SFP / Camera Link module, and writes it into the FLASH through the SPI interface after CRC check to complete the firmware upgrade.

[0142] 2.7 LVDS RX Data Reception Module

[0143] The LVDS RX module receives external image data and converts the high-speed serial data stream into a parallel data stream through a serial-to-parallel IP (SelectIO Interface Wizard). For each data channel, Bitslip (bit slip, determining the start of valid data) is determined according to the virtual coding (virtual coding, the padding data in the valid data transmission gap), and the phase delay between the data channel and the clock channel is finely adjusted accordingly to ensure that the clock sampling edge is always in the middle of the data.

[0144] The adjustment strategy of the phase delay is: first adjust the phase delay to be able to detect the virtual coding, then increment the phase delay from this as the starting point until no virtual coding can be detected within the specified time, and finally back off four cycles based on this phase delay to end this adjustment and detect the data sampling situation in real time.

[0145] Subsequently, the frame header position is determined according to the SAV / EAV (Start of Active Video / End of Active Video) encoding rule, and the valid image data is intercepted from it. At the same time, data alignment between channels is completed through channel binding.

[0146] The decoded image data is re-encoded in the RAW format with the corresponding bit width to achieve the unity of the image data format and is sent to the next module.

[0147] 2.8 Data Cache Module

[0148] The data cache module caches the LVDS image data in the RAW format in the DDR3 through the MIG IP (Memory Interface Generator, an IP core customized by Vivado for calling DDR) for subsequent processing.

[0149] (1) Storage Space Division

[0150] Figure 6 This is a schematic diagram of the storage space division for an embodiment of the present application.

[0151] As Figure 6 shown, in this embodiment, the storage space of the DDR3 is divided into 4 cache pools, and each pool stores 12 rows of images.

[0152] The DDR3 is divided into 3 independent storage spaces to cache the LVDS data of USB3.0, the LVDS data of CameraLink, and the LVDS data of the SFP interface respectively. The LVDS data of each interface is divided into 4 cache pools, and each pool stores 12 rows of images.

[0153] (2) Read / Write Conditions

[0154] To improve the cache efficiency, the LVDS data is first cached in the asynchronous FIFO before being written into the DDR3 and is written into the DDR3 by burst transmission. The same applies to the read operation.

[0155] (3) Write Operation / Read Operation

[0156] Figure 7 This is a schematic diagram of the data cache read / write process of the FPGA (TX side) for an embodiment of the present application.

[0157] As Figure 7As shown in the figure, after the data cache module receives the LVDS data, it first identifies the first row flag. After identifying the flag of the first row, it sequentially stores 12 rows of data into the asynchronous FIFO. The asynchronous FIFO data is stored in cache pool 0. At the same time, 12 rows of data are read from cache pool 3 and stored into the USB3.0 / SFP transmission cache asynchronous FIFO. When 12 rows of data are written to the DDR and 12 rows of data are read from the DDR, the first row flag is identified again, and the addresses of cache pools 0, 1, 2, and 3 are exchanged (the address of cache pool 3 is set to the address of cache pool 2, the address of cache pool 2 is set to the address of cache pool 1, the address of cache pool 1 is set to the address of cache pool 0, and the address of cache pool 0 is set to the address of cache pool 3). The specific timing is as Figure 7 shown.

[0158] 2.9 Algorithm Processing Module

[0159] The algorithm processing module sequentially reads the image data cached in the DDR3 frame by frame, performs relevant image algorithm processing to improve the algorithm processing efficiency, and sends the processed data to the next module.

[0160] The data output interface can include various feasible methods to be compatible with all data output methods.

[0161] 2.10 Aurora Module

[0162] To ensure the low latency, high frame rate, and large-size real-time imaging of industrial sensors, this technical solution adopts the Aurora protocol based on the fiber optic interface to achieve the image data transmission and control signal communication between the transmitter and the receiver.

[0163] The FPGA (TX side) first sends the image data with CRC check (Cyclic Redundancy Check, used to detect or verify possible errors in data transmission or storage) into the asynchronous FIFO for caching, and then sends the image data stream to the Aurora64B / 66B IP according to the AXI4-Stream protocol. After integrating the data according to the aurora protocol, it is sent to the FPGA (RX side) through the 10 Gigabit SFP interface. The FPGA (RX side) then detects whether there are bit errors in the transmission of the received image data through the CRC check.

[0164] The FPGA (TX side) sends the packaged 256-byte control information data into the asynchronous FIFO for caching, and then sends the control packet data stream to the UFC (User Flow Control) interface of the Aurora 64B / 66B IP according to the AXI4-Stream protocol, and sends it to the FPGA (RX side) together with the image data to achieve two-way communication.

[0165] II. FPGA (RX side) Module

[0166] 2.1 System Clock Module

[0167] Similar to the FPGA (TX side).

[0168] 2.2 Firmware Upgrade Module

[0169] Similar to the FPGA (TX side).

[0170] 2.3 Communication Module

[0171] The FPGA chip transmits control data to and from the host PC via the PCIE interface. After packing the host PC data, it is sent to the FPGA (TX side) via the aurora protocol. At the same time, it receives feedback information from the FPGA (TX side), decodes it, and sends it to the host PC.

[0172] 2.4 Aurora Module

[0173] Receives data from the FPGA (RX side). After CRC detection of the image data and verification of error-free transmission, it is sent to the data cache module; receives the control information data packet of the UFC interface, caches it via an asynchronous FIFO, and then sends it to the communication module.

[0174] 2.5 Data Cache Module

[0175] Receives the image data output from the Aurora module, divides the image data into blocks (the maximum block data length is 1024), and caches it in the DDR3 via MIGIP for subsequent processing.

[0176] (1) Storage Space Division

[0177] The division of the storage space is similar to that of the FPGA (TX side).

[0178] (2) Write Operation / Read Operation

[0179] The data cache module has four status flag bits corresponding to four cache pools, which are used to indicate whether the data in the current cache pool is ready. In addition, there is also a sequence flag bit, which is used to indicate the order of arrival of the data in the current four cache pools. When the image data is transmitted into the data cache module, first query the cache pool where the earliest arrived but not yet read image data is located in the sequence flag bit, pull down the status flag bit corresponding to this cache pool, and write the latest input image data to this cache pool. When this image data transmission is completed, raise the status flag bit corresponding to the current cache pool again and update the sequence flag bit.

[0180] Figure 8Schematic diagram of the data cache read and write process of the FPGA (RX end) in an embodiment of the present application.

[0181] As Figure 8 shown, the host computer detects the status flag bit and the sequence flag bit through the interrupt or query method to determine the address of the read operation, and reads the image data from the corresponding cache pool. The specific read and write timing is as Figure 8 shown.

[0182] 2.6 PCIe Module

[0183] In order to achieve high-frame-rate real-time imaging of industrial sensors, this technical solution adopts the PCIe protocol to realize the image data transmission between the host computer and the FPGA (RX end) and the interaction of control signals.

[0184] The FPGA (RX end) serves as the Endpoint (bus terminal) in the PCIE bus of the entire evaluation system through the DMA / Bridge Subsystem for PCI express IP. The host computer accesses the relevant registers of the FPGA (RX end) image cache through the interrupt or query method to confirm the image data cache situation and complete the reading of the image data for host computer imaging.

[0185] The host computer realizes the interaction of control parameters between the FPGA and the host computer by reading and writing the PCIE BAR (Base Address Register) space, which is used to complete the configuration of the internal parameters of the FPGA and the configuration of the Sensor-related parameters.

[0186] Exemplarily, the entire system of the evaluation device of the image sensor in this embodiment mainly consists of this hardware system, the industrial image sensor to be evaluated, a 12V power adapter, a USB cable, an optical fiber cable, a Camera Link cable, and a PC installed with the corresponding driver. First, connect the industrial image sensor to the hardware system. Secondly, connect the optical fiber cable between the hardware system and the PC. Then, connect the 12V power adapter to supply power to the entire hardware system. After the hardware preparation is completed, power on to start the evaluation.

[0187] Figure 9 Schematic diagram of the overall evaluation process of the evaluation device in an embodiment of the present application.

[0188] Exemplarily, at the beginning of the evaluation, the software on the PC is opened, and the "Play" button is clicked. The software will automatically configure the parameters of the sensor and the hardware system according to the configuration file, and then display the sensor image. Using the supporting software, the registers of the sensor and the hardware system can be read and written through the host computer. According to the evaluation regulations, each function of the sensor is verified column by column. When the evaluation is completed, click the "Stop" button, power off the entire evaluation system, and remove the image sensor to complete one evaluation.

[0189] The evaluation device of the image sensor in this embodiment adopts a technical solution based on high-speed and multi-channel data transmission of FPGA, solves the technical problem that the current evaluation system cannot flexibly adapt to various industrial image sensors, and realizes the technical effects of wide evaluation range, stable imaging image, high-efficiency data transmission, and strong anti-interference ability. The evaluation system of the evaluation device of this image sensor based on FPGA has an embedded firmware upgrade function, supports the private protocol of the data interface, and can effectively support the data protocols of industrial image sensors from different manufacturers on the market; the evaluation device of this image sensor uses a high-speed and multi-channel data transmission solution, which can support the frame rates of most industrial image sensors on the market for image output; the power supply voltage of the evaluation device of this image sensor can be dynamically adjusted with high precision, which can meet the power requirements of most industrial image sensors; the evaluation device of this image sensor has an I2C switching function, which can effectively avoid the device number conflicts of the devices inside and outside the board.

[0190] The Third Embodiment

[0191] This application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the evaluation method of the image sensor as described above are implemented.

[0192] As described above, the evaluation method, device and storage medium of the image sensor provided by this application enable the image sensor to transmit multi-channel image data to the data processing module through multiple data channels, and enable the data processing module to process the multi-channel image data according to a preset strategy; the data processing module sends the processed multi-channel image data to the host computer, enabling the host computer to evaluate the image sensor based on the multi-channel image data; it can conveniently set a unified standard data interface protocol, and for products from different manufacturers, the same evaluation system can be used for testing, increasing the testing flexibility and improving work efficiency.

[0193] It should be noted that in this application, step codes such as S10 and S20 are used. The purpose is to more clearly and briefly express the corresponding content, and it does not constitute a substantial limitation in order. Those skilled in the art may execute S20 first and then S10 during specific implementation, etc., but these should all be within the protection scope of this application.

[0194] In the embodiments of the image sensor and storage medium provided in this application, all the technical features of any of the above method embodiments may be included. The extended and explanatory content of the specification is basically the same as that of the above method embodiments and will not be elaborated here.

[0195] The embodiments of this application also provide a computer program product. The computer program product includes computer program code. When the computer program code runs on a computer, the computer is caused to execute the methods in the above various possible implementation manners.

[0196] The embodiments of this application also provide a chip, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device installed with the chip executes the methods in the above various possible implementation manners.

[0197] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as is known to those of ordinary skill in the art, with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0198] The serial numbers of the above embodiments of this application are only for description and do not represent the superiority or inferiority of the embodiments.

[0199] The steps in the method embodiments of this application can be adjusted, combined, and deleted according to actual needs.

[0200] The units in the device embodiments of this application can be combined, divided, and deleted according to actual needs.

[0201] In this application, for the description of the same or similar term concepts, technical solutions, and / or application scenarios, generally only a detailed description is given when it appears for the first time. When it appears repeatedly later, for the sake of brevity, it is generally not elaborated again. When understanding the technical solutions and other contents of this application, for the same or similar term concepts, technical solutions, and / or application scenarios that are not detailed later, reference can be made to the relevant detailed descriptions before.

[0202] In this application, the descriptions of the various embodiments have their own emphases. For parts not elaborated or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0203] The technical features of the technical solutions of this application can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0204] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A method for evaluating an image sensor, characterized in that, Applied to the evaluation of a linear image sensor, the evaluation method of the image sensor includes: The image sensor transmits multi-channel image data to the data processing module through multiple data channels, so that the data processing module processes the multi-channel image data according to a preset strategy; The data processing module sends the processed multi-channel image data to the host computer, so that the host computer evaluates the image sensor based on the multi-channel image data.

2. The evaluation method of an image sensor according to claim 1, characterized in that, The data processing module includes a first data processing unit; the step that the image sensor transmits multi-channel image data to the data processing module through multiple data channels, so that the data processing module processes the multi-channel image data according to a preset strategy includes: The first data processing unit performs channel binding on multiple data channels of the image sensor to align the data of the multi-channel image data, so as to obtain first sensor data through the multiple data channels; The first data processing unit decodes the first sensor data according to a preset data format and performs image algorithm processing to obtain second sensor data.

3. The evaluation method of an image sensor according to claim 2, characterized in that, Before and including the step that the first data processing unit performs channel binding on multiple data channels of the image sensor to align the data of the multi-channel image data, so as to obtain first sensor data through the multiple data channels: Receive the sampling data of the image sensor. For each data channel, determine the starting position of the valid data of the sampling data according to the virtual coding; Adjust the phase delay between the data channel and the clock channel according to the starting position of the valid data to ensure that the clock sampling edge is located in the middle of the data segment of the valid data, so as to obtain the valid data of the data channel; Determine the frame header position of the valid data according to the valid video start flag and the valid video end flag, so as to intercept the image data of the data channel.

4. The evaluation method of an image sensor according to claim 2, wherein The step that the first data processing unit performs channel binding on multiple data channels of the image sensor to align the data of the multi-channel image data, so as to obtain first sensor data through the multiple data channels includes at least one of the following: Perform data alignment binding on multiple channels inside the image sensor; Perform data alignment binding on multiple channels between the image sensors.

5. The evaluation method of an image sensor according to claim 4, characterized in that, The step of performing data alignment binding on multiple channels inside the image sensor includes: Receive the image data of each channel inside the image sensor, perform virtual coding counting on the image data of each channel, and write them into the buffer with the same starting address at the same time; Based on the virtual coding counting result, correspondingly adjust the read address of the image data of multiple channels inside the image sensor, so that the multiple channels inside the image sensor achieve data alignment.

6. The evaluation method of an image sensor according to claim 5, wherein The step of correspondingly adjusting the read address of the image data of multiple channels inside the image sensor based on the virtual coding counting result includes: When writing data, for the image data of each channel, add one to the counting result when the virtual coding appears, otherwise clear the counting result; Set any channel as the reference channel. When the count value of the counter corresponding to the reference channel reaches a preset threshold, compare the counting results of each channel: If the counting result of the target channel is less than that of the reference channel, reduce the corresponding difference of the buffer read address of the target channel; If the counting result of the target channel is greater than that of the reference channel, increase the corresponding difference of the buffer read address of the target channel.

7. The evaluation method of an image sensor according to claim 6, wherein, The step of data alignment and binding for the multiple channels between the image sensors includes: Send the image data received by each sensor into the buffer for caching, and count the amount of data stored in each buffer; When the amount of data stored in each buffer reaches the set threshold, simultaneously read out the valid data in each buffer so that the multiple data channels between the sensors achieve data alignment.

8. The evaluation method of an image sensor according to claim 2, characterized in that, The data processing module includes a second data processing unit, and the second data processing unit is communicatively connected to the first data processing unit based on the Aurora protocol of the optical fiber interface.

9. The evaluation method of an image sensor according to claim 8, wherein, During the process of the first data processing unit sending the second sensor data to the second data processing unit, it includes: The first data processing unit sends the second sensor data into an asynchronous FIFO for caching, and sends the cached data to the Aurora module according to the AXI4-Stream protocol, and sends it to the second data processing unit through the optical fiber interface according to the Aurora protocol.

10. A method for evaluating an image sensor according to claim 9, characterized in that, During the process of the first data processing unit sending the second sensor data to the second data processing unit, it further includes: The first data processing unit sends the control information data into the asynchronous FIFO for caching, and sends the cached control information to the user traffic control interface of the Aurora module according to the AXI4-Stream protocol, and sends it to the second data processing unit together with the second sensor data.

11. A method for evaluating an image sensor according to claim 1, characterized in that, The step of the data processing module sending the processed multi-channel image data to the host computer so that the host computer evaluates the image sensor based on the multi-channel image data includes: The host computer accesses the register of the data processing module by means of interruption or query to read the processed multi-channel image data.

12. The evaluation method of an image sensor according to claim 11, wherein The data processing module realizes the communication connection with the host computer based on the PCIe protocol; The data processing module uses the DMA / Bridge Subsystem for PCI express IP as the bus terminal in the PCIe protocol bus.

13. A method for evaluating an image sensor according to claim 12, wherein The host computer realizes the interaction of control parameters between the host computer and the data processing module by reading and writing the PCIe base address register space, and the control parameters are used for the configuration of the internal parameters of the data processing module and / or the configuration of the relevant parameters of the image sensor.

14. A method for evaluating an image sensor according to any one of claims 2 to 13, characterized in that, The data processing module includes a storage module; before the step of the data processing module sending the processed multi-channel image data to the host computer so that the host computer evaluates the image sensor based on the multi-channel image data, it includes: At least divide the storage space of the storage module into a first cache pool and a second cache pool, and set multiple rows of data storage space for each cache pool; Cache the multi-channel image data row by row into the first cache pool and the second cache pool to synchronously read multiple rows of decoded data in the multi-channel image data.

15. A method for evaluating an image sensor according to claim 14, characterized in that, The step of caching the multi-channel image data row by row into the storage module to synchronously read multiple rows of decoded data in the multi-channel image data includes: The first step: Based on the multi-channel image data cached asynchronously, in response to recognizing the first row flag, deposit it into the row data storage space of the first cache pool in sequence according to the set write address, and read the multi-channel image data frame by frame from the row data storage space of the second cache pool of the storage module according to the set read address; The second step: Change the write address to the address of the second cache pool, change the read address to the address of the first cache pool, and return to the steps of the first step above.

16. The evaluation method of an image sensor according to claim 15, characterized in that, Before depositing or reading the multi-channel image data into or from the cache pool in sequence, it further includes: querying the frame status flag and the frame sequence flag to determine the cache pool serial number for depositing or reading the multi-channel image data; And / or, Before changing the write address or the read address of the cache pool, it further includes: querying the frame status flag and the frame sequence flag to determine the cache pool serial number for changing the write address or the read address.

17. An evaluation device for an image sensor, characterized in that, The evaluation device of the image sensor includes a processor and a storage medium connected to each other, wherein: The storage medium is used to store a computer program; The processor is used to read and run the computer program to implement the evaluation method of the image sensor according to any one of claims 1 to 16; And / or, The evaluation device of the image sensor includes an image data receiving unit, a first data processing unit, a second data processing unit, and a host computer; The image data receiving unit is connected to the image sensor through a multi-channel serial data channel to send the multi-channel image data of the image sensor to the first data processing unit; The first data processing unit is used to perform channel binding on the multi-channel data channels to achieve data alignment of the multi-channel image data, and decode the multi-channel image data according to a preset data format to send the processed multi-channel image data to the second data processing unit; The second data processing unit is used to send the processed multi-channel image data to the host computer to evaluate the image sensor.

18. A storage medium, characterized in that, A computer program is stored on the storage medium, and when the computer program is executed by the processor, it realizes the steps of the evaluation method of the image sensor according to any one of claims 1 to 16.

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