A lighting system and a lighting method

Abstract

The application is suitable for the field of lighting technology, and provides a lighting system and a lighting method.The system comprises a light controller, a plurality of parallel transcode chips and a plurality of display circuits.The light controller is connected with the plurality of parallel transcode chips, and is used for sending a control signal to the plurality of parallel transcode chips.The plurality of parallel transcode chips are respectively connected with the display circuits, and are used for receiving the control signal sent by the light controller, and forwarding the received control signal to the connected display circuits.The plurality of display circuits are used for receiving the control signal forwarded by the parallel transcode chips, and displaying according to the control signal.For the damaged parallel transcode chip or display circuit in the lighting system, targeted replacement can be directly carried out, and other parallel transcode chips or display circuits are not affected, so that the reliability of the lighting system is ensured.

Description

Technical Field

[0001] This application belongs to the field of lighting technology, and in particular relates to a lighting system and lighting method. Background Technology

[0002] Existing LED landscape lighting systems are typically either series systems using Return-Zero (RZ) protocol cascaded chips or parallel systems using DMX512 protocol cascaded chips. RZ is a digital signal encoding method where the signal level returns to zero within each bit cycle. DMX512 (Digital Multiplex with 512 pieces of information) is an industry standard published by the Stage Lighting Association (DLA) specifically for stage lighting control design, enabling digital communication between lighting controllers and lighting equipment. It allows for precise adjustment of parameters such as brightness, color, and motion by controlling lighting equipment through digital signals.

[0003] The series system of cascaded chips using the Return-to-Zero (RZ) protocol is simple with a single-wire connection. However, if one cascaded chip in the system suddenly fails, all subsequent cascaded chips will be uncontrollable. Therefore, while the series system of RZ protocol cascaded chips is low in cost, its reliability is poor. The parallel system of cascaded chips using the DMX512 protocol uses differential DMX512 two-wire parallel connection. A failure in any chip in the system will not affect the application of other chips, resulting in high reliability. However, this system requires multiple wires for connection, including DMX512 protocol differential lines, address lines, power lines, and ground lines, leading to higher costs.

[0004] Therefore, in existing LED landscape lighting systems, how to improve maintenance efficiency and reduce maintenance costs while ensuring system reliability has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a lighting system and lighting method that can solve the technical problem that existing LED landscape lighting systems cannot simultaneously achieve system reliability, maintenance efficiency, and maintenance cost.

[0006] In a first aspect, embodiments of this application provide a lighting system, including: a light controller, multiple parallel transcoding chips, and multiple display circuits, wherein,

[0007] The lighting controller is connected to multiple parallel transcoding chips and is used to send control signals to the multiple parallel transcoding chips;

[0008] Multiple parallel transcoding chips are respectively connected to the display circuit, and are used to receive the control signals sent by the light controller and forward the received control signals to the connected display circuit;

[0009] Multiple display circuits are configured to receive the control signals forwarded by the parallel transcoding chip and to display the data according to the control signals.

[0010] In one possible implementation of the first aspect, the lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit, wherein...

[0011] The DMX512 protocol parallel transcoding chip includes a first signal receiving end and a second signal receiving end, used to receive the control signals sent by the DMX512 protocol controller;

[0012] The DMX512 protocol parallel transcoding chip also includes a first signal transcoding terminal and a second signal transcoding terminal, used to forward the control signal to the DMX512 protocol display circuit through the first signal transcoding terminal or to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0013] In one possible implementation of the first aspect, the DMX512 protocol parallel transcoding chip further includes a transcoding address output terminal and a cascade transcoding terminal, wherein,

[0014] The transcoding address output terminal of the DMX512 protocol parallel transcoding chip is connected to the cascade transcoding terminal of the next-level DMX512 protocol parallel transcoding chip through a third resistor, and is used to forward the control signal to the next-level DMX512 protocol parallel transcoding chip.

[0015] In one possible implementation of the first aspect, the DMX512 protocol parallel transcoding chip includes a transcoding adaptive decoding module, a transcoding address parsing module, a transcoding data parsing module, a transcoding parameter parsing module, and a first memory, wherein,

[0016] The transcoding adaptive decoding module is used to perform adaptive transmission rate decoding on the control signal to obtain decoded data;

[0017] The transcoding address parsing module is connected to the transcoding adaptive decoding module. It is used to parse the address of the decoded data to obtain address data, store the address data in the first memory, and send the address data to the next-level DMX512 protocol parallel transcoding chip through the transcoding address output terminal.

[0018] The transcoding data parsing module is connected to the transcoding adaptive decoding module and is used to perform display analysis on the decoded data to obtain transcoding display data. The transcoding display data is then forwarded to the DMX512 protocol display circuit through the first signal transcoding terminal or to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0019] The transcoding parameter parsing module is connected to the transcoding adaptive decoding module. It is used to perform parameter analysis on the decoded data, obtain parameter data, store the parameter data in the first memory, and forward the parameter data to the DMX512 protocol display circuit through the first signal transcoding terminal or to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0020] In one possible implementation of the first aspect, the DMX512 protocol parallel transcoding chip further includes a second memory, wherein,

[0021] The second memory is used to store the transcoded display data and to cyclically forward the transcoded display data to the first signal transcoding terminal or the second signal transcoding terminal.

[0022] In one possible implementation of the first aspect, the DMX512 protocol controller includes: a first signal transmitter and a second signal transmitter, wherein,

[0023] The first signal transmitting end of the DMX512 protocol controller is connected to the first signal receiving end of the DMX512 protocol parallel transcoding chip through a first resistor;

[0024] The second signal transmitting end of the DMX512 protocol controller is connected to the second signal receiving end of the DMX512 protocol parallel transcoding chip through a second resistor.

[0025] In one possible implementation of the first aspect, the DMX512 protocol display circuit includes: multiple cascaded DMX512 protocol display chips, transcoding resistors, multiple output resistors, and multiple cascaded input resistors, wherein,

[0026] The first display receiver of the DMX512 protocol cascaded display chip is connected to the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip through the transcoding resistor, and receives the control signal forwarded by the DMX512 protocol parallel transcoding chip;

[0027] The first display output terminal of the DMX512 protocol cascaded display chip is connected in series with the output resistor and the cascaded input resistor to the first cascade address terminal of the next cascaded DMX512 protocol cascaded display chip, and forwards the control signal to the next cascaded DMX512 protocol cascaded display chip.

[0028] In one possible implementation of the first aspect, the DMX512 protocol cascaded display chip includes: a DMX512 adaptive decoding module, a DMX512 data parsing module, a DMX512 parameter parsing module, a DMX512 address parsing module, a DMX512 calibration module, and a third memory, wherein,

[0029] The DMX512 adaptive decoding module is used to perform adaptive transmission rate decoding on the transcoded display data to obtain DMX512 protocol display data;

[0030] The DMX512 data parsing module is connected to the DMX512 adaptive decoding module and is used to parse the DMX512 protocol display data to obtain DMX512 protocol parsing data, and send the DMX512 protocol parsing data to the DMX512 correction module.

[0031] The DMX512 parameter parsing module is connected to the DMX512 adaptive decoding module. It is used to perform parameter analysis on the DMX512 protocol display data, obtain DMX512 protocol parameter data, store the DMX512 protocol parameter data in the third memory, and send the DMX512 protocol parameter data to the color display end of the DMX512 protocol cascaded display chip.

[0032] The DMX512 address parsing module is connected to the DMX512 adaptive decoding module. It is used to parse the DMX512 protocol display data to obtain DMX512 protocol address data, store the DMX512 protocol address data in the third memory, and forward the DMX512 protocol address data to the next-level DMX512 protocol cascaded display chip through the first display output terminal of the DMX512 protocol cascaded display chip.

[0033] The DMX512 calibration module is connected to the DMX512 data parsing module and is used to perform gamma calibration on the DMX512 protocol parsing data to obtain calibrated DMX512 protocol parsing data. The calibrated DMX512 protocol parsing data is then sent to the color display end of the DMX512 protocol cascaded display chip so that the color display end of the DMX512 protocol cascaded display chip can display according to the calibrated DMX512 protocol parsing data.

[0034] In one possible implementation of the first aspect, the return-to-zero code protocol display circuit includes multiple cascaded return-to-zero code protocol display chips, wherein,

[0035] The second display receiving end of the zero-code protocol cascaded display chip is connected to the second signal transcoding end of the DMX512 protocol parallel transcoding chip, and receives the control signal forwarded by the DMX512 protocol parallel transcoding chip;

[0036] The second display output terminal of the zero-code protocol cascaded display chip is connected to the second display receiving terminal of the next-level zero-code protocol cascaded display chip, and forwards the control signal to the next-level zero-code protocol cascaded display chip.

[0037] In one possible implementation of the first aspect, the return-to-zero code protocol cascaded display chip includes: a return-to-zero code adaptive decoding module, a return-to-zero code data parsing module, a return-to-zero code forwarding module, and a return-to-zero code correction module, wherein,

[0038] The return-to-zero code adaptive decoding module is used to perform adaptive transmission rate decoding on the transcoded display data to obtain return-to-zero code protocol display data;

[0039] The zero-code data parsing module is connected to the zero-code adaptive decoding module and is used to parse the zero-code protocol display data to obtain zero-code protocol parsing data, and send the zero-code protocol parsing data to the zero-code correction module.

[0040] The zero-code forwarding module is connected to the zero-code adaptive decoding module and is used to send the zero-code protocol display data to the second display output terminal of the zero-code protocol cascaded display chip, so that the second display output terminal of the zero-code protocol cascaded display chip forwards the zero-code protocol display data to the next-level zero-code protocol cascaded display chip.

[0041] The zero-code correction module is connected to the zero-code data parsing module and is used to perform gamma correction on the zero-code protocol parsing data to obtain corrected zero-code protocol parsing data. The corrected zero-code protocol parsing data is then sent to the color display end of the zero-code protocol cascaded display chip so that the color display end of the zero-code protocol cascaded display chip can display according to the corrected zero-code protocol parsing data.

[0042] In a second aspect, embodiments of this application provide a lighting method applied to a parallel transcoding chip in a lighting system as described in any one of the first aspects, the method comprising:

[0043] Receive control signals sent by the lighting controller;

[0044] The control signal is transcoded to obtain transcoded data;

[0045] The transcoded data is forwarded to the connected display circuit so that the display circuit can display the data.

[0046] In one possible implementation of the second aspect, the lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit, and the method includes:

[0047] When the display circuit is the DMX512 protocol display circuit, the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the DMX512 protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the DMX512 protocol display circuit through the first signal transcoding terminal.

[0048] When the display circuit is the return-to-zero code protocol display circuit, the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the return-to-zero code protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0049] In one possible implementation of the second aspect, the method further includes:

[0050] When a first preset number of DMX512 protocol parallel transcoding chips are cascaded, all control signals containing the address data of the current DMX512 protocol parallel transcoding chip are stored in the second memory of the current DMX512 protocol parallel transcoding chip. According to configuration requirements, the control signals are cyclically forwarded to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol parallel transcoding chip, or to multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol parallel transcoding chip.

[0051] In one possible implementation of the second aspect, the method further includes:

[0052] In the case where a second preset number of DMX512 protocol cascaded display chips are cascaded in the DMX512 protocol display circuit or a second preset number of return-to-zero code protocol cascaded display chips are cascaded in the return-to-zero code protocol display circuit,

[0053] All control signals containing the address data of the current DMX512 protocol transcoding chip are forwarded indefinitely to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol transcoding chip, or multiple return-to-zero code cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol transcoding chip, until the last DMX512 protocol cascaded display chip in the DMX512 protocol display circuit or the last return-to-zero code protocol display chip in the return-to-zero code protocol display circuit receives the control signal.

[0054] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the lighting method described in any of the preceding claims.

[0055] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the lighting method described in any of the preceding claims.

[0056] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the lighting method described in any one of the first aspects.

[0057] The beneficial effects of the embodiments in this application compared with the prior art are:

[0058] This application provides a lighting system including a light controller, multiple parallel transcoding chips, and multiple display circuits. The light controller is connected to the multiple parallel transcoding chips and sends control signals to them. Each parallel transcoding chip is connected to a display circuit and receives the control signals from the light controller, forwarding them to the connected display circuits. The multiple display circuits receive the forwarded control signals from the parallel transcoding chips and display information based on them. Damaged parallel transcoding chips or display circuits in the lighting system can be directly replaced without affecting other parallel transcoding chips or display circuits, thus ensuring the reliability of the lighting system. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of the structure of a series system of cascaded chips for a general return-to-zero code protocol, provided in an embodiment of this application.

[0061] Figure 2 This is a schematic diagram of the structure of a series system of a general breakpoint resume return-to-zero code cascade chip provided in an embodiment of this application;

[0062] Figure 3 This is a schematic diagram of the structure of a parallel system of cascaded chips based on a general DMX512 protocol, provided in one embodiment of this application.

[0063] Figure 4 This is a schematic diagram of the structure of a lighting system provided in one embodiment of this application;

[0064] Figure 5 This is a schematic diagram of the structure of a lighting system composed of a parallel transcoding chip and a display circuit based on the DMX512 protocol, provided in one embodiment of this application.

[0065] Figure 6 This is a schematic diagram of the structure of a lighting system composed of a parallel transcoding chip for the DMX512 protocol and a return-to-zero code protocol display circuit, provided in an embodiment of this application.

[0066] Figure 7 This is a schematic diagram of the structure of a parallel transcoding chip for the DMX512 protocol provided in one embodiment of this application;

[0067] Figure 8 This is a schematic diagram of the structure of a cascaded display chip based on the DMX512 protocol, provided in one embodiment of this application.

[0068] Figure 9 This is a schematic diagram of a cascaded display chip based on a return-to-zero code protocol, provided in one embodiment of this application.

[0069] Figure 10 This is a schematic flowchart of a lighting method provided in an embodiment of this application;

[0070] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0071] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0072] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0073] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0074] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0075] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0076] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0077] LED landscape lighting systems are lighting systems that use light-emitting diode (LED) technology as their core, combined with landscape design needs, to enhance the nighttime environment of modern cities and scenic spots through the art of light and shadow. The core of these systems lies in achieving a dynamic presentation of environmental aesthetics and a balance between functional requirements through the intelligent control and artistic design of LED light sources.

[0078] like Figure 1 As shown, Figure 1 This is a schematic diagram of a serial system of a universal return-to-zero code protocol cascaded chip, as provided in one embodiment of this application. Figure 1 In this system, the series connection of the universal return-to-zero (RZ) code protocol cascaded chip uses the RZ code protocol and includes three connection lines: RZ code DIN1 data line, VDD power line, and GND ground line. The connection is simple and the cost is low. However, if one of the cascaded chips in the system suddenly fails, all subsequent cascaded chips will be out of control. Therefore, the series connection of the RZ code protocol cascaded chip is low in cost but has poor reliability.

[0079] Although subsequent developments have led to the development of serial systems using breakpoint resume and return-to-zero code cascading chips, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a series system of a general-purpose breakpoint resume return-to-zero code cascaded chip, provided in one embodiment of this application. For example... Figure 2 In this general-purpose breakpoint resume return-to-zero code cascade chip series system, there are four connecting lines: return-to-zero code DIN1 data line, spare return-to-zero code DIN2 data line, VDD power line and GND ground line. It adds one line to the general-purpose return-to-zero code protocol cascade chip series system. Although this improves the system reliability, if two consecutive cascade chips in the system suddenly fail, all subsequent cascade chips will still be out of control. The reliability of the breakpoint resume return-to-zero code cascade chip series system is improved, but the reliability is still generally low.

[0080] like Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a parallel system of a general-purpose DMX512 protocol cascaded chip provided in one embodiment of this application. Figure 3 In this parallel system of the general-purpose DMX512 protocol cascaded chip, differential DMX512 dual-wire parallel connection is used, which includes five connection lines: DMX512 protocol differential DA line and DB line, address line, VDD power line and GND ground line. The cost is relatively high; however, the failure of any chip in the system will not affect the application of other chips, and the reliability is high.

[0081] However, in LED landscape lighting systems, series systems of cascaded chips using the return-to-zero protocol or parallel systems of cascaded chips using the DMX512 protocol typically involve cascading many display chips. When a display chip malfunctions and needs replacement after a period of use, the replacement process is cumbersome and costly. Therefore, improving maintenance efficiency and reducing maintenance costs while ensuring system reliability is a pressing issue in LED landscape lighting systems. Corresponding to the above problems, this application provides a lighting system that can reduce maintenance costs and improve maintenance efficiency while ensuring system reliability.

[0082] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a lighting system provided in one embodiment of this application. Figure 4 The lighting system 1 includes: a light controller 10, multiple parallel transcoding chips 20, and multiple display circuits 30, wherein...

[0083] The lighting controller 10 is connected to multiple parallel transcoding chips 20 and is used to send control signals to the multiple parallel transcoding chips 20.

[0084] Multiple parallel transcoding chips 20 are each connected to a display circuit 30 to receive control signals sent by the lighting controller and forward the received control signals to the connected display circuit 30.

[0085] Multiple display circuits 30 are used to receive control signals forwarded by the parallel transcoding chip 20 and display them according to the control signals.

[0086] like Figure 4 In this embodiment, the lighting system 1 is a combination of integrated equipment or devices designed, constructed, and integrated to achieve specific lighting functions, and can meet the lighting needs of different scenarios, such as providing appropriate brightness and color. In this embodiment, the lighting system 1 can be an LED landscape lighting system.

[0087] The lighting controller 10 is the core control component of the lighting system 1. It is responsible for generating and sending control signals to other components (such as parallel transcoding chips 20). These control signals may contain instructions regarding the lighting status (such as brightness, color, etc.). The lighting controller 10 can be connected to multiple parallel transcoding chips 20 and then send control signals to them. The lighting controller 10 can dynamically adjust the control signals according to a preset program or external input information, thereby achieving precise control over multiple parallel transcoding chips 20 and subsequent display circuits 30 to meet diverse lighting application scenarios.

[0088] The parallel transcoding chip 20 primarily performs conversion and encoding processing on the received signals. In this lighting system 1, the control signals sent by the light controller 10 may have specific protocols or encoding methods, which the display circuit 30 may not be able to directly recognize and process. In this embodiment, the parallel transcoding chip 20 can decode and analyze the control signals sent by the light controller 10, and then, according to the requirements of the display circuit, re-encode them into a format suitable for the display circuit 30 to receive and process. The converted signal is then forwarded to the corresponding display circuit 30, ensuring that the control signals can be correctly interpreted and executed in the display circuit 30, thereby achieving the expected lighting effect. In this embodiment, the parallel transcoding chips 20 are connected in parallel, meaning each parallel transcoding chip 20 is directly connected to the light controller 10, and each parallel transcoding chip 20 is independent and does not affect the others. It should be understood that the lighting controller 10 can send control signals to multiple parallel transcoding chips 20 simultaneously. Each parallel transcoding chip 20 can receive the complete signal, and the working state of each parallel transcoding chip 20 will not be disturbed by the failure or other working state of other parallel transcoding chips, thereby improving the reliability and stability of the system.

[0089] The display circuit 30 is the component in the lighting system 1 responsible for achieving the lighting effect. The display circuit 30 receives control signals forwarded by the parallel transcoding chip 20 and controls its own light emission state based on these control signals. The display circuit 30 includes a series of light-emitting elements (such as LED beads). By adjusting the current, voltage, and other parameters of these light-emitting elements, their brightness, color, and other characteristics can be controlled, thereby converting the display information expressed by the control signal into a visible lighting effect. Specifically, when the control signal sent by the lighting controller requests increased brightness, the parallel transcoding chip receives the control signal, decodes and converts it, and sends the converted control signal to the display circuit. After receiving the converted control signal, the display circuit correspondingly increases the current supplied to the light-emitting elements, causing the light-emitting elements to emit brighter light.

[0090] In this embodiment, in the lighting system 1, the light controller 10 can be connected in parallel with multiple parallel transcoding chips 20, and each parallel transcoding chip 20 can be connected to a display circuit 30.

[0091] It is understood that this application provides a lighting system including a light controller, multiple parallel transcoding chips, and multiple display circuits. The light controller is connected to the multiple parallel transcoding chips and sends control signals to them. Each parallel transcoding chip is connected to a display circuit and receives the control signals from the light controller, forwarding the received signals to the connected display circuits. The multiple display circuits receive the control signals forwarded by the parallel transcoding chips and display information based on the control signals. Damaged parallel transcoding chips or display circuits in the lighting system can be directly replaced without affecting other parallel transcoding chips or display circuits, thus ensuring the reliability of the lighting system.

[0092] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the structure of a lighting system composed of a parallel DMX512 protocol transcoding chip and a DMX512 protocol display circuit, according to an embodiment of this application. Figure 6 This is a schematic diagram of the structure of a lighting system composed of a parallel transcoding chip for the DMX512 protocol and a return-to-zero code protocol display circuit, according to an embodiment of this application. Figure 5 and Figure 6 In the circuit, the lighting controller 10 is a multi-channel digital transmission DMX512 protocol controller 11, the parallel transcoding chip 20 is a DMX512 protocol parallel transcoding chip 21, and the display circuit 30 includes a DMX512 protocol display circuit 31 or a return-to-zero code protocol display circuit 32.

[0093] The DMX512 protocol parallel transcoding chip 21 includes a first signal receiver UA and a second signal receiver UB, used to receive control signals sent by the DMX512 protocol controller 11.

[0094] The DMX512 protocol parallel transcoding chip 21 also includes a first signal transcoding terminal DMXO and a second signal transcoding terminal RZO, which are used to forward control signals to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO or to forward control signals to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0095] The DMX512 multi-channel digital transmission protocol is a standard communication protocol widely used in stage lighting, architectural lighting, and other fields. It specifies the transmission format, timing, and electrical characteristics of digital signals between the controller and the controlled device. In this embodiment, the lighting controller 10 can be a DMX512 protocol controller 11, which generates control signals conforming to the DMX512 protocol according to a preset program or externally input information, and sends these control signals to the parallel transcoding chip 20, thereby controlling the brightness, color, and other lighting parameters of the display circuit 30 to achieve diverse lighting effects.

[0096] The parallel transcoding chip 20 can be a DMX512 protocol parallel transcoding chip 21, that is, a parallel transcoding chip designed and optimized for the DMX512 protocol. It can decode the signal format of the DMX512 protocol sent by the DMX512 protocol controller 11 and convert it into other protocol formats or signal formats adapted to the needs of different display circuits.

[0097] Display circuit 30 can be either a DMX512 protocol display circuit 31 or a return-to-zero (RZ) code protocol display circuit 32. The DMX512 protocol display circuit 31 is a display circuit capable of directly recognizing and processing DMX512 protocol signals, typically used in lighting scenarios with high signal processing requirements and precise control of multiple parameters. The RZ code protocol display circuit 32 is a display circuit that communicates using the RZ code protocol. The RZ code protocol is a digital signal encoding method where the signal returns to zero level within each symbol interval, thus representing different data. The RZ code protocol display circuit 32 is typically suitable for specific lighting applications and features low cost and simple implementation.

[0098] The DMX512 protocol is designed based on the RS-485 interface and uses DA and DB lines (i.e., positive and negative data lines) for differential voltage signal transmission. The DMX512 protocol parallel transcoding chip 21 includes a first signal receiver UA and a second signal receiver UB. The first signal receiver UA and the second signal receiver UB are interface terminals on the DMX512 protocol parallel transcoding chip 21 used to receive control signals. That is, the DMX512 protocol parallel transcoding chip 21 receives the RS-485 differential voltage signal (i.e., control signal) sent by the DMX512 protocol controller 11 through the first signal receiver UA and the second signal receiver UB, ensuring that the signal can accurately enter the chip for processing.

[0099] The DMX512 protocol parallel transcoding chip 21 also includes a first signal transcoding terminal DMXO and a second signal transcoding terminal RZO. The first signal transcoding terminal DMXO is an interface terminal on the DMX512 protocol parallel transcoding chip 21 used to output signals conforming to the DMX512 protocol; the second signal transcoding terminal RZO is an interface terminal on the DMX512 protocol parallel transcoding chip 21 used to output signals conforming to the return-to-zero code protocol.

[0100] Specifically, the DMX512 protocol parallel transcoding chip 21 can transcode the control signals received from the DMX512 protocol controller 11 according to the type of display circuit. For example... Figure 5 In this configuration, if the DMX512 protocol parallel transcoding chip 21 is subsequently connected to the DMX512 protocol display circuit 31, then the first signal transcoding terminal DMXO of the DMX512 protocol parallel transcoding chip 21 is connected to the DMX512 protocol display circuit 31, and the second signal transcoding terminal RZO is left floating. In this case, the DMX512 protocol parallel transcoding chip 21 forwards the control signal to the corresponding DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO. Figure 6 In this configuration, if the DMX512 protocol parallel transcoding chip 21 is subsequently connected to the return-to-zero (RZO) protocol display circuit 32, then the second signal transcoding terminal RZO of the DMX512 protocol parallel transcoding chip 21 is connected to the RZO protocol display circuit 32, and the first signal transcoding terminal DMXO is left floating. In this case, the DMX512 protocol parallel transcoding chip 21 converts the control signal into a RZO protocol signal through the second signal transcoding terminal RZO and forwards it to the corresponding RZO protocol display circuit 32. This achieves the conversion and adaptation between different protocol signals, enabling the DMX512 protocol controller to control different types of display circuits.

[0101] It should be noted that other IIC protocols can also be used in the lighting system of this embodiment, and no specific limitations are made therein.

[0102] In one possible implementation, the DMX512 protocol parallel transcoding chip 21 also includes a transcoding address output terminal UAO and a cascade transcoding terminal UADFI, wherein...

[0103] The transcoding address output terminal UAO of the DMX512 protocol parallel transcoding chip 21 is connected through the third resistor R. UAO The cascade transcoding terminal UADFI is connected to the next-level DMX512 protocol parallel transcoding chip 22 and is used to forward control signals to the next-level DMX512 protocol parallel transcoding chip 22.

[0104] like Figure 5In the middle, the transcoding address output terminal UAO is an interface terminal on the DMX512 protocol parallel transcoding chip 21 used to output address information. It can send the chip status to the next-level DMX512 protocol parallel transcoding chip 22. For example, a chip status of 0 indicates that the chip address can be configured, and a chip status of 1 indicates that the chip address cannot be configured.

[0105] The cascade transcoding terminal UADFI is an interface terminal on the DMX512 protocol parallel transcoding chip 21 used to receive signals from the previous level chip (such as the DMX512 protocol parallel transcoding chip 21), including control signals and address information.

[0106] Specifically, in large lighting systems that require control of multiple display circuits, a single DMX512 protocol parallel transcoding chip is often insufficient, necessitating the cascading of multiple DMX512 protocol parallel transcoding chips. In this case, the transcoding address output terminal UAO and the cascading transcoding terminal UADFI enable multiple DMX512 protocol parallel transcoding chips to connect and work collaboratively. Specifically, the transcoding address output terminal UAO of the current DMX512 protocol parallel transcoding chip 21 is connected to a third resistor R... UAO The current DMX512 protocol parallel transcoding chip 21 is connected to the next-level DMX512 protocol parallel transcoding chip 22 via the cascade transcoding terminal UADFI. The first signal receiving terminal UA and the second signal receiving terminal UB of the next-level DMX512 protocol parallel transcoding chip 22 are then connected to the DMX512 protocol controller 11. Control signals are forwarded to the DMX512 protocol display circuit 31 via the first signal transcoding terminal DMXO of the next-level DMX512 protocol parallel transcoding chip 22 or to the return-to-zero code protocol display circuit 32 via the second signal transcoding terminal RZO of the next-level DMX512 protocol parallel transcoding chip 22.

[0107] During signal transmission, due to potential differences in the input and output impedances of different chips, direct connection may lead to signal reflection and distortion. Furthermore, abnormal conditions such as overvoltage, overcurrent, or static electricity in the circuit may damage the chip ports. Therefore, a third resistor R is used to address this issue. UAO It can serve as an impedance matcher and protect chip ports, reducing signal reflection and enabling stable and accurate signal transmission to the next-stage DMX512 protocol parallel transcoding chip, thus improving signal transmission quality and reliability. For example... Figure 5 In order to further protect the stability of the chip ports and signals, a third resistor R can also be added. UAO A resistor R is then connected in series between the cascade transcoding terminal UADFI of the next-level DMX512 protocol transcoding chip and the transcoding terminal UADFI.ADFI .

[0108] It should be noted that, in this embodiment, the next-level parallel DMX512 protocol transcoding chip 22 and the parallel DMX512 protocol transcoding chip 21 are DMX512 protocol parallel transcoding chips of the same structure and type.

[0109] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a parallel transcoding chip for the DMX512 protocol provided in one embodiment of this application. Figure 7 In the DMX512 protocol parallel transcoding chip 21, there are transcoding adaptive decoding module 211, transcoding address parsing module 212, transcoding data parsing module 213, transcoding parameter parsing module 214, and first memory 215.

[0110] The transcoding adaptive decoding module 211 is used to perform adaptive transmission rate decoding on the control signal to obtain decoded data.

[0111] The transcoding address parsing module 212 is connected to the transcoding adaptive decoding module 211. It is used to parse the address of the decoded data, obtain the address data, store the address data in the first memory 215, and send the address data to the next-level DMX512 protocol parallel transcoding chip 22 through the transcoding address output terminal UAO.

[0112] The transcoding data parsing module 213 is connected to the transcoding adaptive decoding module 211. It is used to perform display analysis on the decoded data, obtain transcoding display data, and forward the transcoding display data to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO or to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0113] The transcoding parameter parsing module 214 is connected to the transcoding adaptive decoding module 211. It is used to perform parameter analysis on the decoded data, obtain parameter data, store the parameter data in the first memory 215, and forward the parameter data to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO or to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0114] like Figure 7 In the DMX512 protocol parallel transcoding chip 21, the following modules are mainly included: transcoding adaptive decoding module 211, transcoding address parsing module 212, transcoding data parsing module 213, and transcoding parameter parsing module 214. The transcoding address parsing module 212, transcoding data parsing module 213, and transcoding parameter parsing module 214 are respectively connected to the transcoding adaptive decoding module 211.

[0115] The transcoding adaptive decoding module 211 can adaptively decode the input control signal at a transmission rate to obtain the corresponding decoded data. The transcoding address parsing module 212 can parse the decoded data to obtain address data, which can then be written to / read from the first memory 215 via the read-only memory control logic, i.e., the ROM CONTROL module. After parsing the address data, it can also be sent to the next-level DMX512 protocol parallel transcoding chip 22 via the transcoding address output terminal UAO (i.e., the address output module).

[0116] The transcoded data parsing module 213 can analyze the decoded data to obtain transcoded display data, which is the data to be displayed later. After obtaining the transcoded display data, it can be forwarded to the DMX512 protocol display circuit 31 through the first signal transcoding terminal DMXO (i.e., the DMX512 decoding and forwarding module), or forwarded to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO (i.e., the return-to-zero code decoding and forwarding module).

[0117] The transcoding parameter parsing module 214 can perform parameter analysis on the decoded data to obtain parameter data, i.e., set parameters, such as current adjustment amplitude, self-channel addressing, automatic addressing, etc. At this time, the parameter data can be stored in the first memory 215. When forwarding the transcoded display data, the parameter data in the first memory 215 is read at the same time and forwarded to the DMXODMX512 protocol display circuit 31 through the first signal transcoding terminal or to the return-to-zero code protocol display circuit 32 through the second signal transcoding terminal RZO.

[0118] The first memory 215 is an electrically erasable programmable read-only memory, which can be used to store address data and parameter data.

[0119] It should be noted that in the lighting system of this embodiment, when encountering corners, increasing the current of multiple chips to increase brightness, etc., it is necessary to increase or decrease the number of cascaded display chips in the subsequent display circuit 30, or change the number of channels of the subsequent display chips. At this time, the address data to be configured is no longer a fixed value, but a variable value. Therefore, self-channel addressing is introduced into the MX512 protocol parallel transcoding chip 21. By integrating the self-channel addressing technology into the DMX512 protocol parallel transcoding chip 21, the DMX512 protocol parallel transcoding chip 21 can automatically increase the corresponding address according to the number of channels and the number of display chips controlled by the DMX512 protocol parallel transcoding chip 21.

[0120] Furthermore, the DMX512 protocol parallel transcoding chip 21 also includes a second memory 216, wherein,

[0121] The second memory 216 is used to store transcoded display data and to cyclically forward the transcoded display data to the first signal transcoding terminal DMXO or the second signal transcoding terminal RZO.

[0122] It should be noted that after obtaining the transcoded display data, the transcoded display data can be stored in the second memory 216, enabling cyclic forwarding of the transcoded display data to either the first signal transcoding terminal DMXO or the second signal transcoding terminal RZO. Infinite forwarding is also possible. The second memory 216 is a random access memory.

[0123] It should be noted that, in Figure 7 In this circuit, the first signal receiver UA and the second signal receiver UB are RS-485 differential signal read / write circuit modules, transmitting control signals to the transcoding adaptive decoding module 211. The cascaded transcoding terminal UADFI is the write address identifier module, which judges the input chip address to determine whether it is the write address state of this chip. UOSC is an oscillator; UPOR is a power-on reset, an automatic reset operation triggered upon power-on to ensure the initial state of the chip's internal circuitry after power-on reset; UVCC clamp is a power supply voltage clamping circuit. When the system power supply is greater than 5V (e.g., 24V), UVCC clamp can ensure that the chip's operating voltage is within 5V, keeping the chip's operating voltage within a safe range and preventing overvoltage damage to the circuit.

[0124] In one possible implementation, the DMX512 protocol controller 11 includes: a first signal transmitter CA and a second signal transmitter CB, wherein,

[0125] The first signal transmitter CA of the DMX512 protocol controller 11 is connected to the first resistor R. A The first signal receiver UA is connected to the DMX512 protocol parallel transcoding chip 21.

[0126] The second signal transmitter CB of the DMX512 protocol controller 11 is connected to the second resistor R. B The second signal receiver UB is connected to the DMX512 protocol parallel transcoding chip 21.

[0127] like Figure 4 In the diagram, the DMX512 protocol controller 11 has a first signal transmitter CA and a second signal transmitter CB. The first signal transmitter CA and the second signal transmitter CB are interface terminals on the DMX512 protocol controller 11 used to transmit control signals (RS-485 differential voltage signals). This is achieved through a first resistor R... A Connect the first signal transmitting terminal CA of the DMX512 protocol controller 11 to the first signal receiving terminal UA of the DMX512 protocol parallel transcoding chip 21, and connect them through the second resistor R.B The second signal transmitter CB of the DMX512 protocol controller 11 is connected to the second signal receiver UB of the DMX512 protocol parallel transcoding chip 21. That is, the DMX512 protocol controller 11 sends control signals to the first signal receiver UA of the DMX512 protocol parallel transcoding chip 21 through its first signal transmitter CA, and sends control signals to the second signal receiver UB of the DMX512 protocol parallel transcoding chip 21 through its second signal transmitter CB. Through this connection, control signal transmission can be achieved.

[0128] In one possible implementation, the DMX512 protocol display circuit 31 includes: multiple cascaded DMX512 protocol display chips 311, and a transcoding resistor R. C Multiple output resistors R AO and multiple cascaded input resistors R ADF ,in,

[0129] The first display receiver XA of the DMX512 protocol cascaded display chip 311 is connected via a transcoding resistor R. C The first signal transcoding terminal DMXO of the parallel transcoding chip 21 of the DMX512 protocol is connected to receive the control signals forwarded by the parallel transcoding chip 21 of the DMX512 protocol.

[0130] The first display output terminal XAO of the DMX512 protocol cascaded display chip 311 is connected to the output resistor R. AO Cascaded input resistor R ADF After being connected in series, the first cascade address terminal XADFI of the next-level DMX512 protocol cascaded display chip 312 is connected to forward the control signal to the next-level DMX512 protocol cascaded display chip 312.

[0131] like Figure 5 In the DMX512 protocol display circuit 31, multiple DMX512 protocol cascaded display chips 311 can be cascaded. The first display receiver XA is an interface terminal on the DMX512 protocol cascaded display chip 311 used to receive control signals, which is connected to the transcoding resistor R. C The first signal transcoding terminal DMXO of the parallel transcoding chip 21 of the DMX512 protocol is connected to receive the control signals forwarded by the parallel transcoding chip 21 of the DMX512 protocol.

[0132] The first display output terminal XAO is an interface terminal on the DMX512 protocol cascaded display chip 311 used to output address information, and can send chip status to the next cascaded DMX512 protocol cascaded display chip 312. This first display output terminal XAO is connected to the output resistor R. AO Cascaded input resistor R ADFAfter being connected in series, it is then connected to the first display receiver XA of the next-level DMX512 protocol cascaded display chip 312, thereby forwarding control signals to the next-level DMX512 protocol cascaded display chip 312.

[0133] Among them, the transcoding resistor R C Multiple output resistors R AO and multiple cascaded input resistors R ADF These resistors are all designed for impedance matching and protecting the chip ports. By setting these resistors, signal reflections can be reduced, allowing the signal to be transmitted stably and accurately to the next cascaded DMX512 protocol display chip, thereby improving the quality and reliability of signal transmission.

[0134] Specifically, in large lighting systems with diverse display requirements, a single DMX512 protocol cascaded display chip often cannot meet the needs, requiring multiple DMX512 protocol cascaded display chips to perform lighting display. In this case, the first display output terminal XAO and the first cascaded address terminal XADFI enable multiple DMX512 protocol cascaded display chips to connect to each other and work collaboratively. That is, the first display output terminal XAO of the current DMX512 protocol cascaded display chip 311 is connected to the output resistor R... AO Cascaded input resistor R ADF After being connected in series, it is connected to the first cascade address terminal XADFI of the next-level DMX512 protocol cascaded display chip 312, thereby connecting the previous DMX512 protocol cascaded display chip 311 with the next-level DMX512 protocol cascaded display chip 312; then, the first display receiver terminal XA of the next-level DMX512 protocol cascaded display chip 312 is connected through the transcoding resistor R. C The first signal transcoding terminal (DMXO) of the DMX512 protocol parallel transcoding chip 21 is connected to receive control signals forwarded by the first signal transcoding terminal (DMXO) of the DMX512 protocol parallel transcoding chip 21. The DMX512 protocol cascaded display chip 311 and the next-level DMX512 protocol cascaded display chip 312 are DMX512 protocol cascaded display chips of the same structure and type.

[0135] like Figure 5 In the diagram, UGND represents the ground terminal in the DMX512 protocol parallel transcoding chip 21, and UVDD represents the power supply voltage terminal in the DMX512 protocol parallel transcoding chip 21; XGND represents the ground terminal in the DMX512 protocol cascaded display chip 311, and XVDD represents the power supply voltage terminal in the DMX512 protocol cascaded display chip 311. Figure 6In the diagram, DGND represents the ground terminal in the Return-to-Zero Protocol Cascaded Display Chip 321, and DVDD represents the power supply voltage terminal in the Return-to-Zero Protocol Cascaded Display Chip 321.

[0136] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a DMX512 protocol cascaded display chip provided in one embodiment of this application. Figure 8 In the DMX512 protocol cascaded display chip 311, there are: a DMX512 adaptive decoding module 313, a DMX512 data parsing module 314, a DMX512 parameter parsing module 315, a DMX512 address parsing module 316, a DMX512 calibration module 317, and a third memory 318.

[0137] The DMX512 adaptive decoding module 313 is used to perform adaptive transmission rate decoding on the transcoded display data to obtain DMX512 protocol display data.

[0138] The DMX512 data parsing module 314 is connected to the DMX512 adaptive decoding module 313. It is used to parse the DMX512 protocol display data, obtain the DMX512 protocol parsing data, and send the DMX512 protocol parsing data to the DMX512 correction module 317.

[0139] The DMX512 parameter parsing module 315, connected to the DMX512 adaptive decoding module 313, is used to perform parameter analysis on the DMX512 protocol display data, obtain the DMX512 protocol parameter data, store the DMX512 protocol parameter data in the third memory 318, and send the DMX512 protocol parameter data to the color display end of the DMX512 protocol cascaded display chip.

[0140] The DMX512 address parsing module 316, connected to the DMX512 adaptive decoding module 313, is used to parse the DMX512 protocol display data to obtain the DMX512 protocol address data. The DMX512 protocol address data is stored in the third memory 318 and forwarded to the next-level DMX512 protocol cascaded display chip 312 through the first display output terminal XAO of the DMX512 protocol cascaded display chip 311.

[0141] The DMX512 calibration module 317 is connected to the DMX512 data parsing module 314. It is used to perform gamma correction on the DMX512 protocol parsing data to obtain the corrected DMX512 protocol parsing data, and send the corrected DMX512 protocol parsing data to the color display terminal RGBW of the DMX512 protocol cascaded display chip 311 so that the color display terminal RGBW of the DMX512 protocol cascaded display chip 311 can display according to the corrected DMX512 protocol parsing data.

[0142] It should be noted that in lighting systems, the DMX512 protocol parallel transcoding chip supports adaptive decoding from 200kHz to 2MHz. However, this chip experiences oscillation deviations during manufacturing, leading to frequency deviations in the forwarded data. Therefore, the display chips in subsequent display circuits (i.e., DMX512 protocol cascaded display chips and Return-to-Zero (RZ) protocol cascaded display chips) must also have adaptive decoding capabilities to ensure correct data decoding and achieve the preset LED display function. In the DMX512 protocol, the first byte of data is used for self-alignment, enabling adaptive decoding from 200kHz to 2MHz. In the standard RZ protocol, however, there is no dedicated data for self-alignment; it typically uses an 800kHz RZ transmission rate. Therefore, the RZ protocol cascaded display chip is designed to define the RZ transmission rate using the first bit of data, without decoding at this stage. After a certain time delay, the RZ data is decoded according to the determined RZ transmission rate, achieving adaptive decoding of the RZ data.

[0143] like Figure 8 In this cascaded display chip 311, which incorporates the DMX512 protocol, the following modules are included: a DMX512 adaptive decoding module 313, a DMX512 data parsing module 314, a DMX512 parameter parsing module 315, a DMX512 address parsing module 316, and a DMX512 calibration module 317. The DMX512 data parsing module 314, DMX512 parameter parsing module 315, and DMX512 address parsing module 316 are connected to the DMX512 adaptive decoding module 313, while the DMX512 calibration module 317 is connected to the DMX512 data parsing module 314. The DMX512 adaptive decoding module 313 can adaptively decode the transcoded display data forwarded by the parallel transcoding chip 22 to obtain the corresponding DMX512 protocol display data.

[0144] The DMX512 address parsing module 316 can parse the DMX512 protocol display data to obtain the DMX512 protocol address data. Then, through the read-only memory control logic, i.e., the ROM CONTROL module, the address data can be written to / read from the third memory 318. After parsing the DMX512 protocol address data, it can also be sent to the next-level cascaded DMX512 protocol display chip 312 through the first display output terminal XAO (i.e., the address output module).

[0145] The DMX512 data parsing module 314 can parse the DMX512 protocol display data to obtain DMX512 protocol parsing data, which is the data to be displayed subsequently (such as brightness and color). After obtaining the DMX512 protocol parsing data, it can send the DMX512 protocol parsing data to the DMX512 correction module 317. After receiving the DMX512 protocol parsing data, the DMX512 correction module 317 performs gamma correction on the DMX512 protocol parsing data, such as correcting 8 bits (256 levels of brightness) to 16 bits (65536 levels of brightness), thus obtaining the corrected DMX512 protocol parsing data. Finally, the corrected DMX512 protocol parsing data is sent to the color display terminal RGBW (i.e., the port used to control the brightness of different colors) of the DMX512 protocol cascaded display chip 311. At this time, the color display terminal RGBW of the DMX512 protocol cascaded display chip 311 can display according to the corrected DMX512 protocol parsing data, that is, the illumination is realized according to the control signal.

[0146] The DMX512 parameter parsing module 315 can perform parameter analysis on the DMX512 protocol display data to obtain DMX512 protocol parameter data, i.e., set parameters such as current adjustment amplitude, self-channel addressing, and automatic addressing. At this time, the DMX512 protocol parameter data can be stored in the third memory 318. Simultaneously with sending the corrected DMX512 protocol parsing data to the color display terminal RGBW of the DMX512 protocol cascaded display chip 311, the module reads the DMX512 protocol parameter data from the third memory 318, enabling the color display terminal RGBW to display based on the corrected DMX512 protocol parsing data and the DMX512 protocol parameter data. The third memory 318 is an electrically erasable programmable read-only memory (EEPROM) that can be used to store DMX512 protocol address data and DMX512 protocol parameter data.

[0147] It should be noted that, in Figure 8In this embodiment, the first display receiver XA and the other display receiver XB are signal read / write circuit modules that transmit transcoded display data to the DMX512 adaptive decoding module 313. In this embodiment, only the first display receiver XA and the first signal transcoding terminal DMXO of the DMX512 protocol parallel transcoding chip 21 are connected. The first cascaded address terminal XADFI is the write address identifier module, which judges the input of the chip address to determine whether it is the write address state of this chip. XOSC is an oscillator; XPOR is a power-on reset, which is a reset operation automatically triggered when powered on to ensure the initial state of the internal circuit of the chip after power-on reset; XVCC clamp is a power supply voltage clamping circuit to ensure that the chip's operating voltage is within a safe range and to prevent overvoltage damage to the circuit.

[0148] In one possible implementation, the return-to-zero code protocol display circuit 32 includes multiple cascaded return-to-zero code protocol display chips 321, wherein...

[0149] The second display receiver DIN of the zero-code protocol cascaded display chip 321 is connected to the second signal transcoding terminal RZO of the DMX512 protocol parallel transcoding chip 21 to receive the control signals forwarded by the DMX512 protocol parallel transcoding chip 21.

[0150] The second display output terminal DOUT of the zero-code protocol cascaded display chip 321 is connected to the second display receiver terminal DIN of the next-level zero-code protocol cascaded display chip 322, and forwards the control signal to the next-level zero-code protocol cascaded display chip 322.

[0151] like Figure 6 In the Return-to-Zero (RZ) protocol display circuit 32, multiple RZ cascaded display chips 321 can be cascaded, and each RZ cascaded display chip 321 is connected in series. The second display receiver DIN is an interface terminal on the RZ cascaded display chip 321 used to receive control signals. It is connected to the second signal transcoding terminal RZO of the DMX512 protocol parallel transcoding chip 21, thereby receiving the control signals forwarded by the DMX512 protocol parallel transcoding chip 21.

[0152] The second display output terminal DOUT is an interface terminal on the Return-to-Zero (RZ) protocol cascaded display chip 321 used to output address information, and can send chip status to the next-level RZ protocol cascaded display chip 322. This second display output terminal DOUT can be directly connected to the second display receiver terminal DIN of the next-level RZ protocol cascaded display chip 322, thereby forwarding control signals to the next-level RZ protocol cascaded display chip 322. The RZ protocol cascaded display chip 321 and the next-level RZ protocol cascaded display chip 322 are RZ protocol cascaded display chips of the same structure and type.

[0153] Please see Figure 9 , Figure 9 This is a schematic diagram of a cascaded display chip based on a return-to-zero code protocol, provided in one embodiment of this application. Figure 9 In the process, the return-to-zero code protocol cascaded display chip 321 includes: a return-to-zero code adaptive decoding module 323, a return-to-zero code data parsing module 324, a return-to-zero code forwarding module 325, and a return-to-zero code correction module 326, wherein,

[0154] The Return-to-Zero (RZ) code adaptive decoding module 323 is used to perform adaptive transmission rate decoding on the transcoded display data to obtain RZ code protocol display data.

[0155] The zero-code data parsing module 324 is connected to the zero-code adaptive decoding module 323. It is used to parse the zero-code protocol display data, obtain the zero-code protocol parsing data, and send the zero-code protocol parsing data to the zero-code correction module 326.

[0156] The return-to-zero code forwarding module 325, connected to the return-to-zero code adaptive decoding module 323, is used to send the return-to-zero code protocol display data to the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321, so that the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321 forwards the return-to-zero code protocol display data to the next level of the return-to-zero code protocol cascaded display chip 322.

[0157] The return-to-zero code correction module 326 is connected to the return-to-zero code data parsing module 324. It is used to perform gamma correction on the return-to-zero code protocol parsing data to obtain the corrected return-to-zero code protocol parsing data, and send the corrected return-to-zero code protocol parsing data to the color display terminal RGB of the return-to-zero code protocol cascaded display chip 321 so that the color display terminal RGB of the return-to-zero code protocol cascaded display chip 321 can display according to the corrected return-to-zero code protocol parsing data.

[0158] like Figure 9 In the cascaded display chip 321 for the return-to-zero code protocol, the following modules are mainly included: a return-to-zero code adaptive decoding module 323, a return-to-zero code data parsing module 324, a return-to-zero code forwarding module 325, and a return-to-zero code correction module 326. The return-to-zero code data parsing module 324 and the return-to-zero code forwarding module 325 are respectively connected to the return-to-zero code adaptive decoding module 323, and the return-to-zero code correction module 326 is connected to the return-to-zero code data parsing module 324.

[0159] Among them, the return-to-zero code adaptive decoding module 323 can perform adaptive transmission rate decoding on the transcoded display data forwarded by the DMX512 protocol parallel transcoding chip 22 to obtain the corresponding return-to-zero code protocol display data.

[0160] The return-to-zero code forwarding module 325 can send the return-to-zero code protocol display data to the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321, so that the second display output terminal DOUT of the return-to-zero code protocol cascaded display chip 321 will forward the return-to-zero code protocol display data to the next level of the return-to-zero code protocol cascaded display chip 322.

[0161] The Return-to-Zero (RZ) code data parsing module 324 can parse the RZ code protocol display data to obtain RZ code protocol parsing data, which is the data to be displayed subsequently (such as brightness and color). After obtaining the RZ code protocol parsing data, it can send the RZ code protocol parsing data to the RZ code correction module 326. After receiving the RZ code protocol parsing data, the RZ code correction module 326 performs gamma correction on the RZ code protocol parsing data to obtain corrected RZ code protocol parsing data. Finally, it sends the corrected RZ code protocol parsing data to the color display terminal RGB (i.e., the port used to control the brightness of different colors) of the RZ code protocol cascaded display chip 321. At this time, the color display terminal RGB of the RZ code protocol cascaded display chip 321 can display according to the corrected RZ code protocol parsing data, that is, the illumination is realized according to the control signal.

[0162] It should be noted that, in Figure 9 In this circuit, DOSC stands for oscillator; DPOR stands for power-on reset, an automatic reset operation triggered upon power-on to ensure the initial state of the chip's internal circuitry after power-on reset; and DVCC clamp is a power supply voltage clamping circuit to ensure that the chip's operating voltage is within a safe range and to prevent overvoltage damage to the circuitry.

[0163] It should be noted that in the lighting system of this embodiment, if a DMX512 protocol parallel transcoding chip fails, the failed chip can be simply replaced, the system data reconfigured, and the data of subsequent cascaded DMX512 protocol parallel transcoding chips reconfigured using methods such as self-channel addressing and automatic addressing. Similarly, if a DMX512 protocol cascaded display chip in a DMX512 protocol display circuit or a return-to-zero code protocol cascaded display chip in a return-to-zero code display circuit fails, the entire display chip can be replaced directly, and the data of subsequent cascaded chips reconfigured using methods such as self-channel addressing and automatic addressing. This ensures system reliability, improves maintenance efficiency, and reduces system costs. Especially noteworthy is the attached... Figure 6 The lighting system, composed of a parallel transcoding chip based on the DMX512 protocol and a return-to-zero code protocol display circuit, requires only three connecting wires, allowing the circuit board to be made narrower and further reducing production costs.

[0164] A lighting system corresponding to the above embodiment, Figure 10A schematic flowchart of a lighting method according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to the embodiment of this application are shown. Figure 10 In this context, the lighting method is applied to a parallel transcoding chip in a lighting system as described in any of the preceding claims, and the method includes:

[0165] S101, Receives control signals sent by the lighting controller.

[0166] S102. Transcode the control signal to obtain transcoded data.

[0167] S103. Forward the transcoded data to the connected display circuit so that the display circuit can display the data according to the transcoded data.

[0168] It should be noted that this method can be applied to parallel transcoding chips in lighting systems. In this embodiment, the parallel transcoding chip can receive control signals sent by the lighting controller, convert and encode the received control signals according to preset rules, generate transcoded data suitable for subsequent display circuit reception and processing, and then accurately forward the transcoded data to the display circuit. In a lighting system, multiple parallel transcoding chips can interact with the lighting controller in a parallel connection manner, solving the problem of signal format incompatibility between different devices and achieving efficient and stable signal transmission.

[0169] The lighting controller is the core control component of a lighting system. It integrates control logic and a communication module, generating corresponding control information based on user operations and sending these control signals to the controlled lighting equipment or related relay devices (such as parallel transcoding chips) to achieve precise lighting control. Control signals are specific information generated and sent by the lighting controller to control the lighting equipment. Control signals are typically transmitted using specific encoding formats and communication protocols (such as DMX512 protocol, return-to-zero code protocol, etc.), and contain various instructions and parameters required to control the lighting equipment. For example, a control signal might indicate adjusting the brightness of a certain area to 50%, setting the color to red, or activating a certain flashing mode.

[0170] The transcoded data is the data obtained after the control signals sent by the lighting controller have been transcoded by a parallel transcoding chip. The purpose of transcoding is to convert the original control signals into a format suitable for the display circuit to receive and process, so that the display circuit can correctly parse and execute the corresponding display operations.

[0171] A display circuit can be understood as a lighting device or a circuit directly connected to a lighting device. It receives transcoded signals and displays or drives the lighting device to display. The display circuit can be integrated within a single lighting device or a centralized control circuit shared by multiple lighting devices. The display circuit contains a series of light-emitting elements (such as LED beads). By adjusting the current, voltage, and other parameters of these light-emitting elements, their brightness, color, and other characteristics can be controlled, thereby converting the display information expressed by the control signal into a visible lighting effect. Specifically, when the lighting controller sends a control signal requesting increased brightness, the parallel transcoding chip receives the control signal, decodes and converts it to obtain transcoded data, and sends the converted transcoded data to the display circuit. After receiving the converted transcoded data, the display circuit correspondingly increases the current supplied to the light-emitting elements, causing the light-emitting elements to emit brighter light.

[0172] It is understood that this application provides a lighting method, which includes receiving a control signal sent by a lighting controller; transcoding the control signal to obtain transcoded data; and forwarding the transcoded data to a connected display circuit so that the display circuit can display based on the transcoded data. This method can ensure the reliability of the system, and at the same time, improve system maintenance efficiency and reduce system maintenance costs.

[0173] In one possible implementation, the lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit. The method includes:

[0174] When the display circuit is a DMX512 protocol display circuit, the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the DMX512 protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the DMX512 protocol display circuit through the first signal transcoding terminal.

[0175] When the display circuit is a return-to-zero code protocol display circuit, the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the return-to-zero code protocol display circuit, and the control signal sent by the received DMX512 protocol controller is forwarded to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

[0176] It should be noted that the lighting controller can be a DMX512 protocol controller, the parallel transcoding chip can be a DMX512 protocol parallel transcoding chip, and the display circuit can be a DMX512 protocol display circuit or a return-to-zero (RZ) protocol display circuit. A DMX512 protocol display circuit is capable of directly recognizing and processing DMX512 protocol signals and is typically used in lighting scenarios with high signal processing requirements and precise control of multiple parameters. A RZ protocol display circuit uses the RZ protocol for communication. RZ protocol display circuits are generally suitable for specific lighting applications and are characterized by lower cost and simpler implementation.

[0177] Specifically, the DMX512 protocol parallel transcoding chip includes a first signal transcoding terminal and a second signal transcoding terminal. When the lighting system requires high reliability and precise control, the display circuit can be a DMX512 protocol display circuit. In this case, the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the DMX512 protocol display circuit, and the control signals received from the DMX512 protocol controller are forwarded to the DMX512 protocol display circuit through the first signal transcoding terminal. When the lighting system requires low cost and simple implementation, the display circuit can be a return-to-zero (RZ) protocol display circuit. In this case, the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the RZ protocol display circuit, and the control signals received from the DMX512 protocol controller are forwarded to the RZ protocol display circuit through the second signal transcoding terminal.

[0178] It should be understood that in this embodiment, the MX512 protocol parallel transcoding chip can transcode the control signals sent by the DMX512 protocol controller according to the type of display circuit, and forward them to the display circuit, thereby realizing the conversion and adaptation between different protocol signals, enabling the DMX512 protocol controller to control different types of display circuits.

[0179] In one possible implementation, the method further includes:

[0180] When a first preset number of DMX512 protocol parallel transcoding chips are cascaded, all control signals containing the address data of the current DMX512 protocol parallel transcoding chip are stored in the second memory of the current DMX512 protocol parallel transcoding chip. According to the configuration requirements, the control signals are cyclically forwarded to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol parallel transcoding chip, or to multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol parallel transcoding chip.

[0181] Specifically, in a lighting system with a first preset number of DMX512 protocol parallel transcoding chips cascaded, such as more than 100 cascaded DMX512 protocol parallel transcoding chips, for the 4096 bytes of data of the DMX512 protocol, the data allocated to each display chip is less than 40 bytes. Therefore, the number of cascaded display chips in the corresponding display circuit is less than 10. However, in practical applications, the number of cascaded display chips in the display circuit is usually greater than 10. The display chips need to increase current to increase brightness, or the display chips need to generate cyclic data such as LED effects flowing through the screen. In this case, the transmitted data needs to be output cyclically. Accordingly, the DMX512 protocol parallel transcoding chip requires data storage and cyclic forwarding functions. After reading the address data related to its own chip, the DMX512 protocol parallel transcoding chip stores all subsequent configuration requirements in its second memory. Based on the configuration of the DMX512 protocol parallel transcoding chip, it cyclically forwards the stored data to subsequent display chips (i.e., multiple cascaded DMX512 protocol display chips or cascaded return-to-zero code protocol display chips). The first preset quantity is a pre-set value, which is not limited in this embodiment.

[0182] In one possible implementation, when a second preset number of DMX512 protocol cascaded display chips are cascaded in a DMX512 protocol display circuit or a second preset number of return-to-zero code protocol cascaded display chips are cascaded in a return-to-zero code protocol display circuit, the method further includes:

[0183] All control signals containing the address data of the current DMX512 protocol transcoding chip are forwarded indefinitely to multiple cascaded DMX512 protocol display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol transcoding chip, or multiple cascaded return-to-zero code protocol display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol transcoding chip, until the last cascaded DMX512 protocol display chip or the last return-to-zero code protocol display chip in the return-to-zero code protocol display circuit receives the control signal.

[0184] Specifically, in a lighting system, when a second preset number of DMX512 protocol cascaded display chips are cascaded in a DMX512 protocol display circuit or a return-to-zero code protocol cascaded display chip are cascaded in a return-to-zero code protocol display circuit, if there are more than 100 DMX512 protocol cascaded display chips or return-to-zero code protocol cascaded display chips, then the DMX512 protocol transcoding chip needs an infinite data forwarding function. That is, after reading the address data of its own chip, the current DMX512 protocol transcoding chip infinitely forwards all subsequent data related to its own chip to the DMX512 protocol cascaded display chips or return-to-zero code protocol cascaded display chips until the last DMX512 protocol cascaded display chip or return-to-zero code protocol display chip in the DMX512 protocol display circuit has received the data. This function is suitable for applications with a large number of cascaded DMX512 protocol cascaded display chips or return-to-zero code protocol cascaded display chips. The second preset number is a pre-set value, which is not limited in this embodiment.

[0185] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0186] This application also provides an electronic device, such as... Figure 11 As shown, Figure 11 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 11 The electronic device 4 in this embodiment includes a memory 41, a processor 42, and a computer program stored in the memory 41 and executable on the processor 42. When the processor 42 executes the computer program, it implements the steps in any of the above-described lighting method embodiments.

[0187] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps described in the various method embodiments above.

[0188] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the above-described method embodiments.

[0189] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographic device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0190] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0191] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0193] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0194] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A lighting system, characterized in that, include: The system comprises a lighting controller, multiple parallel transcoding chips, and multiple display circuits. The lighting controller is connected to multiple parallel transcoding chips and is used to send control signals to the multiple parallel transcoding chips; Multiple parallel transcoding chips are respectively connected to the display circuit, and are used to receive the control signals sent by the light controller and forward the received control signals to the connected display circuit; Multiple display circuits are configured to receive the control signals forwarded by the parallel transcoding chip and display the data according to the control signals. The lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, and the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit. The DMX512 protocol parallel transcoding chip includes a first signal receiving end and a second signal receiving end, used to receive the control signals sent by the DMX512 protocol controller; The DMX512 protocol parallel transcoding chip further includes a first signal transcoding terminal and a second signal transcoding terminal, used to forward the control signal to the DMX512 protocol display circuit through the first signal transcoding terminal or to forward the control signal to the return-to-zero code protocol display circuit through the second signal transcoding terminal; and The DMX512 protocol parallel transcoding chip includes a transcoding adaptive decoding module, wherein the transcoding adaptive decoding module is used to perform adaptive transmission rate decoding on the control signal to obtain decoded data.

2. The lighting system as described in claim 1, characterized in that, The DMX512 protocol parallel transcoding chip also includes a transcoding address output terminal and a cascade transcoding terminal, wherein, The transcoding address output terminal of the DMX512 protocol parallel transcoding chip is connected to the cascade transcoding terminal of the next-level DMX512 protocol parallel transcoding chip through a third resistor, and is used to forward the control signal to the next-level DMX512 protocol parallel transcoding chip.

3. The lighting system as described in claim 2, characterized in that, The DMX512 protocol parallel transcoding chip includes: a transcoding address parsing module, a transcoding data parsing module, a transcoding parameter parsing module, and a first memory, wherein... The transcoding address parsing module is connected to the transcoding adaptive decoding module. It is used to parse the address of the decoded data to obtain address data, store the address data in the first memory, and send the address data to the next-level DMX512 protocol parallel transcoding chip through the transcoding address output terminal. The transcoding data parsing module is connected to the transcoding adaptive decoding module and is used to perform display analysis on the decoded data to obtain transcoding display data. The transcoding display data is then forwarded to the DMX512 protocol display circuit through the first signal transcoding terminal or to the return-to-zero code protocol display circuit through the second signal transcoding terminal. The transcoding parameter parsing module is connected to the transcoding adaptive decoding module. It is used to perform parameter analysis on the decoded data, obtain parameter data, store the parameter data in the first memory, and forward the parameter data to the DMX512 protocol display circuit through the first signal transcoding terminal or to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

4. The lighting system as described in claim 3, characterized in that, The DMX512 protocol parallel transcoding chip also includes a second memory, wherein, The second memory is used to store the transcoded display data and to cyclically forward the transcoded display data to the first signal transcoding terminal or the second signal transcoding terminal.

5. The lighting system as described in claim 4, characterized in that, The DMX512 protocol controller includes: a first signal transmitter and a second signal transmitter, wherein, The first signal transmitting end of the DMX512 protocol controller is connected to the first signal receiving end of the DMX512 protocol parallel transcoding chip through a first resistor; The second signal transmitting end of the DMX512 protocol controller is connected to the second signal receiving end of the DMX512 protocol parallel transcoding chip through a second resistor.

6. The lighting system as described in claim 5, characterized in that, The DMX512 protocol display circuit includes: multiple cascaded DMX512 protocol display chips, transcoding resistors, multiple output resistors, and multiple cascaded input resistors, wherein... The first display receiver of the DMX512 protocol cascaded display chip is connected to the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip through the transcoding resistor, and receives the control signal forwarded by the DMX512 protocol parallel transcoding chip; The first display output terminal of the DMX512 protocol cascaded display chip is connected in series with the output resistor and the cascaded input resistor to the first cascade address terminal of the next cascaded DMX512 protocol cascaded display chip, and forwards the control signal to the next cascaded DMX512 protocol cascaded display chip.

7. The lighting system as claimed in claim 6, characterized in that, The DMX512 protocol cascaded display chip includes: a DMX512 adaptive decoding module, a DMX512 data parsing module, a DMX512 parameter parsing module, a DMX512 address parsing module, a DMX512 calibration module, and a third memory. The DMX512 adaptive decoding module is used to perform adaptive transmission rate decoding on the transcoded display data to obtain DMX512 protocol display data; The DMX512 data parsing module is connected to the DMX512 adaptive decoding module and is used to parse the DMX512 protocol display data to obtain DMX512 protocol parsing data, and send the DMX512 protocol parsing data to the DMX512 correction module. The DMX512 parameter parsing module is connected to the DMX512 adaptive decoding module. It is used to perform parameter analysis on the DMX512 protocol display data, obtain DMX512 protocol parameter data, store the DMX512 protocol parameter data in the third memory, and send the DMX512 protocol parameter data to the color display end of the DMX512 protocol cascaded display chip. The DMX512 address parsing module is connected to the DMX512 adaptive decoding module. It is used to parse the DMX512 protocol display data to obtain DMX512 protocol address data, store the DMX512 protocol address data in the third memory, and forward the DMX512 protocol address data to the next-level DMX512 protocol cascaded display chip through the first display output terminal of the DMX512 protocol cascaded display chip. The DMX512 calibration module is connected to the DMX512 data parsing module and is used to perform gamma calibration on the DMX512 protocol parsing data to obtain calibrated DMX512 protocol parsing data. The calibrated DMX512 protocol parsing data is then sent to the color display end of the DMX512 protocol cascaded display chip so that the color display end of the DMX512 protocol cascaded display chip can display according to the calibrated DMX512 protocol parsing data.

8. The lighting system as described in claim 5, characterized in that, The return-to-zero code protocol display circuit includes multiple cascaded return-to-zero code protocol display chips, wherein, The second display receiving end of the zero-code protocol cascaded display chip is connected to the second signal transcoding end of the DMX512 protocol parallel transcoding chip, and receives the control signal forwarded by the DMX512 protocol parallel transcoding chip; The second display output terminal of the zero-code protocol cascaded display chip is connected to the second display receiving terminal of the next-level zero-code protocol cascaded display chip, and forwards the control signal to the next-level zero-code protocol cascaded display chip.

9. The lighting system as claimed in claim 8, characterized in that, The zero-return code protocol cascaded display chip includes: a zero-return code adaptive decoding module, a zero-return code data parsing module, a zero-return code forwarding module, and a zero-return code correction module, wherein... The return-to-zero code adaptive decoding module is used to perform adaptive transmission rate decoding on the transcoded display data to obtain return-to-zero code protocol display data; The zero-code data parsing module is connected to the zero-code adaptive decoding module and is used to parse the zero-code protocol display data to obtain zero-code protocol parsing data, and send the zero-code protocol parsing data to the zero-code correction module. The zero-code forwarding module is connected to the zero-code adaptive decoding module and is used to send the zero-code protocol display data to the second display output terminal of the zero-code protocol cascaded display chip, so that the second display output terminal of the zero-code protocol cascaded display chip forwards the zero-code protocol display data to the next-level zero-code protocol cascaded display chip. The zero-code correction module is connected to the zero-code data parsing module and is used to perform gamma correction on the zero-code protocol parsing data to obtain corrected zero-code protocol parsing data. The corrected zero-code protocol parsing data is then sent to the color display end of the zero-code protocol cascaded display chip so that the color display end of the zero-code protocol cascaded display chip can display according to the corrected zero-code protocol parsing data.

10. A lighting method, characterized in that, The method, applied to a parallel transcoding chip in a lighting system as described in any one of claims 1-9, comprises: Receive control signals sent by the lighting controller; The control signal is transcoded to obtain transcoded data; The transcoded data is forwarded to the connected display circuit so that the display circuit can display the data. The lighting controller is a multi-channel digital transmission DMX512 protocol controller, the parallel transcoding chip is a DMX512 protocol parallel transcoding chip, the display circuit includes a DMX512 protocol display circuit or a return-to-zero code protocol display circuit, and the method further includes: When the display circuit is the DMX512 protocol display circuit, the first signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the DMX512 protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the DMX512 protocol display circuit through the first signal transcoding terminal. When the display circuit is the return-to-zero code protocol display circuit, the second signal transcoding terminal of the DMX512 protocol parallel transcoding chip is connected to the return-to-zero code protocol display circuit, and the control signal received from the DMX512 protocol controller is forwarded to the return-to-zero code protocol display circuit through the second signal transcoding terminal.

11. The lighting method as described in claim 10, characterized in that, The method further includes: When a first preset number of DMX512 protocol parallel transcoding chips are cascaded, all control signals containing the address data of the current DMX512 protocol parallel transcoding chip are stored in the second memory of the current DMX512 protocol parallel transcoding chip. According to configuration requirements, the control signals are cyclically forwarded to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol parallel transcoding chip, or to multiple return-to-zero code protocol cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol parallel transcoding chip.

12. The lighting method as described in claim 10, characterized in that, The method further includes: In the case where a second preset number of DMX512 protocol cascaded display chips are cascaded in the DMX512 protocol display circuit or a second preset number of return-to-zero code protocol cascaded display chips are cascaded in the return-to-zero code protocol display circuit, All control signals containing the address data of the current DMX512 protocol transcoding chip are forwarded indefinitely to multiple DMX512 protocol cascaded display chips in the DMX512 protocol display circuit connected to the current DMX512 protocol transcoding chip, or multiple return-to-zero code cascaded display chips in the return-to-zero code protocol display circuit connected to the current DMX512 protocol transcoding chip, until the last DMX512 protocol cascaded display chip in the DMX512 protocol display circuit or the last return-to-zero code protocol cascaded display chip in the return-to-zero code protocol display circuit receives the control signal.

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