Semiconductor device, manufacturing method thereof and electronic equipment
By designing semiconductor substructures of different types of doping elements alternately stacked in semiconductor devices, the problems of low yield, poor electrical performance or high manufacturing cost in process production are solved, and the effect of improving electrical performance is achieved.
Patent Information
- Application Number
- CN202311775520.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-21
- Publication Date
- 2025-06-24
AI Technical Summary
In process production, semiconductor devices have problems such as low yield, poor electrical performance or high manufacturing costs, which are mainly due to the impact of slight differences on performance caused by the shrinking of key sizes and the increase in device types.
A semiconductor device is designed, which includes a first transistor arranged on a substrate, and its first semiconductor structure consists of semiconductor substructures of different types of doped elements alternately stacked, through which the electrical performance of the transistor is improved.
By increasing the effective thickness of the depletion region of the first transistor, reducing leakage current and increasing the switching ratio, the electrical performance of the semiconductor device is improved.
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Figure CN120201710A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art
[0002] With the development of semiconductor technology, the critical dimensions of semiconductor devices are increasingly shrinking, and the types and quantities of devices included in a chip are increasing accordingly. This results in that any minor difference in the process production may affect the device performance, leading to problems such as low yield, poor electrical performance, or high manufacturing cost of semiconductor devices. Summary of the Invention
[0003] In view of the disadvantages of the existing methods, this application proposes a semiconductor device, a manufacturing method thereof, and an electronic device, at least to improve the deficiencies in the background art.
[0004] In a first aspect, an embodiment of this application provides a semiconductor device, including: a substrate, and at least one first transistor disposed on the substrate, the first transistor including a first gate and a first dielectric structure, and a first semiconductor structure located on a side of the first dielectric structure away from the first gate;
[0005] The first semiconductor structure includes at least two first semiconductor sub-structures and at least one second semiconductor sub-structure stacked alternately, the first semiconductor sub-structure includes one of a P-type doping element or an N-type doping element, and the second semiconductor sub-structure includes the other of a P-type doping element or an N-type doping element.
[0006] Optionally, the first semiconductor structure includes the first semiconductor sub-structure, the second semiconductor sub-structure, and the first semiconductor sub-structure stacked in a direction away from the substrate;
[0007] The first semiconductor sub-structure includes an N-type doping element, and the second semiconductor sub-structure includes a P-type doping element.
[0008] Optionally, the doping concentration of the second semiconductor sub-structure is not less than 1e15 cm -3 and not greater than 1e21 cm -3 .
[0009] Optionally, the doping concentration of the first semiconductor sub-structure is not less than 1e16 cm -3 and not greater than 1e22 cm -3 ;
[0010] and / or, the doping concentration of the second semiconductor sub-structure is not less than 1e17 cm -3 and not greater than 1e19 cm -3 .
[0011] Optionally, the semiconductor device further includes bit lines and shared bit lines, and a second transistor connecting the bit lines and the shared bit lines;
[0012] Alternatively, the semiconductor device further includes word lines and shared word lines, and a second transistor connecting the word lines and the shared word lines.
[0013] Optionally, the second transistor includes a second semiconductor structure, which is the same as the first semiconductor structure.
[0014] Optionally, the semiconductor device further includes: a multi-layer memory array disposed along a direction away from the substrate, the memory array including at least one memory cell; the memory cell includes the first transistor and a capacitor connected to each other.
[0015] Optionally, the semiconductor device further includes: at least two word lines extending along a second direction parallel to the substrate and electrically connected to the first transistors of a column of memory cells arranged along the second direction in the memory array located in the same layer;
[0016] at least two bit lines extending along a third direction perpendicular to the substrate and electrically connected to the first transistors of a group of memory cells stacked along the third direction;
[0017] Optionally, the semiconductor device further includes: at least two shared word lines stacked and insulated from each other, the shared word lines extending along a first direction parallel to the substrate, and the at least two shared word lines stacked to form a stepped structure; the word lines and the shared word lines disposed in the same layer are electrically connected; the first direction and the second direction intersect.
[0018] Optionally, the semiconductor device further includes:
[0019] at least two word lines extending along a third direction perpendicular to the substrate and electrically connected to the first transistors of a group of memory cells stacked along the third direction;
[0020] at least two bit lines extending along a second direction parallel to the substrate and electrically connected to the first transistors of a column of memory cells arranged along the second direction in the memory array located in the same layer;
[0021] Optionally, the semiconductor device further includes: at least two shared bit lines stacked and insulated from each other, the shared bit lines extending along a first direction parallel to the substrate, and the at least two shared bit lines stacked to form a stepped structure; the bit lines and the shared bit lines disposed in the same layer are electrically connected; the first direction and the second direction intersect.
[0022] In a second aspect, an embodiment of the present application provides an electronic device, including: the semiconductor device as described above.
[0023] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
[0024] Forming a combined film layer including an alternately stacked first sacrificial layer and a first semiconductor layer on one side of a substrate; the first semiconductor layer includes at least two first semiconductor sub-layers and at least one second semiconductor sub-layer that are alternately stacked, the first semiconductor sub-layer includes one of a P-type doping element or an N-type doping element, and the second semiconductor sub-layer includes the other of a P-type doping element or an N-type doping element;
[0025] Forming at least one first transistor based on the combined film layer; the first semiconductor structure of the first transistor includes at least two first semiconductor sub-structures formed based on the first semiconductor sub-layer and at least one second semiconductor sub-structure formed based on the second semiconductor sub-layer that are alternately stacked.
[0026] Optionally, forming a combined film layer including an alternately stacked first sacrificial layer and a first semiconductor layer on one side of a substrate includes:
[0027] Forming one layer of the first sacrificial layer on one side of the substrate based on an epitaxial process;
[0028] Forming one layer of the first semiconductor layer includes: alternately forming at least two layers of the first semiconductor sub-layer and at least one layer of the second semiconductor sub-layer on the side of the first sacrificial layer away from the substrate based on an epitaxial process and an in-situ doping process.
[0029] Optionally, forming at least one first transistor based on the combined film layer includes:
[0030] Patterning the combined film layer to form at least two stacked structures separated by trenches; the stacked structures extend in a first direction parallel to the substrate, and the stacked structures include a first sacrificial structure formed based on the first sacrificial layer and a first initial semiconductor structure formed based on the first semiconductor layer that are alternately stacked;
[0031] Removing the first sacrificial structure in the stacked structure;
[0032] Forming at least one first dielectric structure surrounding the first initial semiconductor structure;
[0033] Forming a first gate surrounding the first dielectric structure and forming at least one word line; the word line extends in a second direction parallel to the substrate and intersecting the first direction, and the word line is electrically connected to a column of the first gates arranged in the second direction in the same layer.
[0034] Optionally, after forming the first gate surrounding the first dielectric structure and forming at least one word line, the method further includes:
[0035] Forming a capacitor in a portion of the first initial semiconductor structure away from the first dielectric structure;
[0036] Forming a bit line penetrating the stacked structure, such that the first initial semiconductor structure is separated into two first semiconductor structures by the bit line.
[0037] Optionally, after patterning the combined film layer to form at least two stacked structures separated by trenches, the method further includes:
[0038] Etching laterally a portion of the first sacrificial structure in the stacked structure, such that adjacent two first semiconductor structures and the first sacrificial structure enclose a groove;
[0039] Forming support structures at two ends of the stacked structure along a first direction; and filling a portion of the groove with the support structures.
[0040] The beneficial technical effects brought by the technical solution provided by the embodiments of the present application include:
[0041] In the semiconductor device provided by the embodiments of the present application, by setting that the first semiconductor structure of at least one first transistor in the semiconductor device includes at least two first semiconductor sub-structures and at least one second semiconductor sub-structure stacked alternately, and the first semiconductor sub-structure and the second semiconductor sub-structure include different types of doping elements, the effective thickness of the depletion region in the first transistor in the off state can be increased, which is beneficial to reducing the leakage current of the first transistor, beneficial to improving the on-off ratio of the first transistor, and further beneficial to improving the electrical performance of the first transistor.
[0042] The additional aspects and advantages of the present application will be given in part in the following description, and these will become obvious from the following description, or can be understood through the practice of the present application. Description of the Drawings
[0043] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, in which:
[0044] Figure 1 is a schematic cross-sectional view taken along a plane parallel to the substrate of a semiconductor device provided by an embodiment of the present application;
[0045] Figure 2 is provided by an embodiment of the present application Figure 1 a cross-sectional view perpendicular to the substrate taken along line AA of the semiconductor device shown;
[0046] Figure 3 A vertical cross-sectional view perpendicular to the substrate taken along line BB of the semiconductor device provided by an embodiment of the present application; Figure 1
[0047] Figure 4 A schematic structural diagram of the first transistor of the semiconductor device shown provided by an embodiment of the present application; Figure 2
[0048] Figure 5 A schematic cross-sectional view taken along a plane parallel to the substrate of another semiconductor device provided by an embodiment of the present application;
[0049] Figure 6 A vertical cross-sectional view perpendicular to the substrate taken along line AA of the semiconductor device shown provided by an embodiment of the present application; Figure 5
[0050] Figure 7 A vertical cross-sectional view perpendicular to the substrate taken along line BB of the semiconductor device shown provided by an embodiment of the present application; Figure 5
[0051] Figure 8 A schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;
[0052] Figure 9 A schematic cross-sectional view taken along a plane perpendicular to the substrate after forming a composite film layer on one side of the substrate in a method for manufacturing a semiconductor device provided by an embodiment of the present application;
[0053] Figure 10 A top view schematic diagram after forming a third dielectric layer in a method for manufacturing a semiconductor device provided by an embodiment of the present application;
[0054] Figure 11 Is Figure 10 A schematic cross-sectional film layer diagram perpendicular to the substrate at DD in the film layer structure shown;
[0055] Figure 12 A schematic cross-sectional film layer diagram perpendicular to the substrate at DD after forming a support structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;
[0056] Figure 13a A schematic cross-sectional film layer diagram perpendicular to the substrate at DD after removing a first sacrificial structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;
[0057] Figure 13b A schematic cross-sectional view taken along a plane parallel to the substrate after removing the first sacrificial structure in a method for manufacturing a semiconductor device provided by an embodiment of the present application;
[0058] Figure 14a In the manufacturing method of a semiconductor device provided by an embodiment of the present application, it is a schematic cross-sectional film layer view perpendicular to the substrate at DD after forming the first transistor;
[0059] Figure 14b In the manufacturing method of a semiconductor device provided by an embodiment of the present application, it is a schematic cross-sectional view taken along a plane parallel to the substrate after forming the first transistor; Figure 15a In the manufacturing method of a semiconductor device provided by an embodiment of the present application, it is a schematic cross-sectional film layer view perpendicular to the substrate at DD after forming the capacitor;
[0060] Figure 15b In the manufacturing method of a semiconductor device provided by an embodiment of the present application, it is a schematic cross-sectional view taken along a plane parallel to the substrate after forming the capacitor;
[0061] Figure 16a In the manufacturing method of a semiconductor device provided by an embodiment of the present application, it is a schematic cross-sectional film layer view perpendicular to the substrate at DD after forming the bit line;
[0062] Figure 16b In the manufacturing method of a semiconductor device provided by an embodiment of the present application, it is a schematic cross-sectional view taken along a plane parallel to the substrate after forming the bit line.
[0063] Description of reference numerals:
[0064] 100 - Substrate; 101 - First sacrificial layer; 1011 - First sacrificial structure; 102 - First semiconductor layer; 1021 - First semiconductor sub-layer; 1022 - Second semiconductor sub-layer; 1023 - First initial semiconductor structure 103 - Stacked structure; 104 - First dielectric layer; 105 - Second dielectric layer;
[0065] 10 - First transistor;
[0066] 11 - First semiconductor structure; 111 - First semiconductor sub-structure; 112 - Second semiconductor sub-structure; 12 - First dielectric structure; 13 - First gate;
[0067] 20 - Capacitor;
[0068] 21 - First electrode structure; 22 - First dielectric structure; 23 - Second electrode structure;
[0069] 30 - Word line; 40 - Bit line; 50 - Shared word line; 60 - Isolation structure; 71 - Second dielectric structure; 72 - Support structure; 721 - First sub-support structure; 722 - Second sub-support structure; 73 - Third dielectric structure; 80 - Switching device; 90 - Shared bit line. Detailed implementation manners
[0070] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions of the embodiments of the present application.
[0071] Those skilled in the art of the present technology can understand that, unless specifically stated otherwise, the singular forms "a", "an", "the", and "said" used herein may also include the plural forms. It should be further understood that the term "including" used in the specification of the present application means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art of the present technology. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or implemented as "B", or implemented as "A and B".
[0072] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings. The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, learned from, or combined with each other. For the same terms, similar features, and similar implementation steps in different embodiments, they will not be described repeatedly.
[0073] The embodiments of the present application provide a semiconductor device, and the structural schematic diagram of the semiconductor device is as shown in Figure 1 , Figure 2 , Figure 3 and Figure 4 . The semiconductor device includes: a substrate 100, and at least one first transistor 10 disposed on the substrate 100. The first transistor 10 includes a first gate 13 and a first dielectric structure 12, and a first semiconductor structure 11 located on a side of the first dielectric structure 12 away from the first gate 13.
[0074] The first semiconductor structure 11 includes at least two first semiconductor sub-structures 111 stacked alternately and at least one second semiconductor sub-structure 112. The first semiconductor sub-structure 111 includes one of a P-type doping element or an N-type doping element, and the second semiconductor sub-structure 112 includes the other of a P-type doping element or an N-type doping element.
[0075] In the semiconductor device provided by the embodiment of the present application, the first semiconductor structure 10 of at least one first transistor is configured to include at least two first semiconductor sub-structures 111 and at least one second semiconductor sub-structure 112 that are alternately stacked, and the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 include different types of doping elements, so that the effective thickness of the depletion region in the first transistor in the off state can be increased, which is beneficial to reducing the leakage current of the first transistor 10, beneficial to improving the switching ratio of the first transistor 10, and further beneficial to improving the electrical performance of the first transistor 10.
[0076] In some embodiments, the semiconductor device may include at least two stacked memory arrays, and each memory array includes at least two memory cells; each memory cell includes a first transistor 10 and a capacitor 20 that are arranged and connected along a first direction parallel to the substrate 100.
[0077] Optionally, in the embodiment of the present application, in combination with Figure 1 and Figure 2 it can be known that each memory cell includes a connected first transistor 10 and a capacitor 20. As Figure 2 shown, in the same memory cell, the first transistor 10 and the capacitor 20 are arranged along the first direction. Optionally, as Figure 2 shown, along the first direction, each layer of the memory array includes two memory cells.
[0078] It should be noted that, for the convenience of readers to intuitively understand the structures of the first transistor 10 and the capacitor 20, as Figure 2 shown, the first transistor 10 and the capacitor 20 are framed by a dashed line box, and the dashed line does not exist in the actual product.
[0079] Optionally, in the embodiment of the present application, as Figure 4 shown, the first semiconductor structure 11 of the first transistor 10 includes at least two first semiconductor sub-structures 111 and at least one second semiconductor sub-structure 112 that are alternately stacked.
[0080] Optionally, in the embodiment of the present application, the first semiconductor sub-structure 111 includes one of a P-type doping element or an N-type doping element, and the second semiconductor sub-structure 112 includes the other of a P-type doping element or an N-type doping element, that is, the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 include different types of doping elements, which is beneficial to reducing the leakage current of the first transistor, beneficial to improving the switching ratio of the first transistor 10, and further beneficial to improving the electrical performance of the first transistor 10.
[0081] Optionally, in the embodiments of the present application, the first semiconductor structure 10 of at least one first transistor 10 is provided to include at least two first semiconductor sub-structures 111 and at least one second semiconductor sub-structure 112 that are alternately stacked, and the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 include different types of doping elements. During the operation of the first transistor 10, the effective thickness of the depletion region in the first transistor in the off state can be increased, thereby helping to improve the electrical performance of the first transistor 10.
[0082] Optionally, as Figure 4 shown, in some embodiments of the present application, the first semiconductor structure 11 includes a first semiconductor sub-structure 111, a second semiconductor sub-structure 112, and a first semiconductor sub-structure 111 stacked in a direction away from the substrate 100; the first semiconductor sub-structure 111 includes an N-type doping element, and the second semiconductor sub-structure 112 includes a P-type doping element.
[0083] In practical applications, the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 may be alternately stacked in a direction away from the substrate 100, or may be alternately stacked in other directions, which is not limited herein.
[0084] Optionally, in the embodiments of the present application, as Figure 4 shown, the first semiconductor structure 11 includes two first semiconductor sub-structures 111 and a second semiconductor sub-structure 112 disposed between the two first semiconductor sub-structures 111.
[0085] Optionally, in the embodiments of the present application, the first semiconductor sub-structure 111 includes an N-type doping element. Optionally, the N-type doping element includes As (arsenic) and P (phosphorus). Optionally, the second semiconductor sub-structure 112 includes a P-type doping element. Optionally, the P-type doping element includes B (boron).
[0086] Those skilled in the art can set the specific number and specific doping elements of the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 according to actual needs.
[0087] Optionally, in the embodiments of the present application, along a third direction perpendicular to the substrate 100, the thicknesses of the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 are the same.
[0088] Optionally, in some embodiments of the present application, the doping concentration of the second semiconductor sub-structure 112 is not less than 1e15 cm -3 and not greater than 1e21 cm -3 .
[0089] Optionally, in the embodiments of the present application, for the first transistor 10 including the N-type-P-type-N-type first semiconductor structure 11, when the N-type doping element in the first semiconductor sub-structure 111 remains unchanged, with the change of the doping concentration of the P-type doping element in the second semiconductor sub-structure 112, the leakage current, on-state current, and switching ratio of the first transistor 10 will all change accordingly.
[0090] Optionally, in the embodiments of the present application, by controlling the doping concentration of the second semiconductor sub-structure 112 between 1e15 cm -3 to 1e21 cm -3 it is possible to ensure that the first transistor 10 has a sufficiently small leakage current and a sufficiently large on-state current, thereby helping to improve the switching ratio of the first transistor 10, and further being beneficial to improving the electrical performance of the first transistor 10.
[0091] Optionally, in some embodiments of the present application, the doping concentration of the first semiconductor sub-structure is not less than 1e16 cm -3 and not greater than 1e22 cm -3 ; and / or, the doping concentration of the second semiconductor sub-structure is not less than 1e17 cm -3 and not greater than 1e19 cm -3 . The above doping concentrations can achieve the best switching ratio.
[0092] Optionally, in some embodiments of the present application, the semiconductor device may further include a bit line 40 and a shared bit line 90, and a second transistor connecting the bit line 40 and the shared bit line 90; or, the semiconductor device further includes a word line 30 and a shared word line 50, and a second transistor connecting the word line 30 and the shared word line 50.
[0093] The semiconductor device includes a plurality of memory cells, the memory cells include at least one first transistor; the second transistor includes a second semiconductor structure, and the second semiconductor structure is the same as the first semiconductor structure.
[0094] By adopting the above solution for the select transistor, the leakage current on the shared bit line 90 or the shared word line 50 can be minimized to improve the performance of the memory array; by adopting the above solution for the transistor of the memory cell, the leakage current of the memory cell can be reduced.
[0095] Optionally, as shown in Figure 1 , Figure 2 and Figure 3 , in some embodiments of the present application, the semiconductor device further includes: at least two word lines 30, two bit lines 40, and at least two shared word lines 50.
[0096] Optionally, in the embodiments of the present application, each layer of the storage array is configured with at least one word line 30, and at least two word lines 30 that are stacked and insulated from each other are included in any two adjacent layers of the storage array.
[0097] Optionally, as Figure 1 and Figure 2 shown, each layer of the storage array includes two columns of storage cells arranged in the second direction, the word line 30 extends in the second direction parallel to the substrate 100, and each word line 30 is electrically connected to the first transistor 10 of a column of storage cells arranged in the second direction in the storage array of the same layer. Optionally, each word line 30 is electrically connected to the first gate 13 of the first transistor 10 of a column of storage cells arranged in the second direction in the storage array of the same layer.
[0098] Optionally, in the embodiments of the present application, the stacked storage arrays are configured with at least two bit lines 40. Optionally, as Figure 1 and Figure 2 shown, the bit lines 40 extend in the third direction perpendicular to the substrate 100; multiple bit lines 40 are arranged at intervals in the second direction.
[0099] Optionally, as Figure 1 and Figure 2 shown, in the third direction, among all the stacked storage cell arrays, the storage cells whose orthographic projections on the substrate 100 overlap form a group of stacked storage cells. As Figure 2 shown, both columns of storage cells in each layer of the storage array are electrically connected to the same bit line 40, and each bit line 40 is electrically connected to the first transistor 10 of the same group of storage cells.
[0100] Optionally, in the embodiments of the present application, some of the bit lines 40 form the source or drain of the first transistor 10, and some of the first electrode structures 21 of the capacitors 20 form the drain or source of the first transistor 10.
[0101] Optionally, in the embodiments of the present application, at least two shared word lines 50 are stacked and insulated from each other, and at least two shared word lines 50 are stacked to form a stepped structure; the word line 30 and the shared word line 50 arranged in the same layer are electrically connected; the first direction and the second direction intersect.
[0102] Optionally, in some embodiments of the present application, all the stacked storage cell arrays are configured with at least one stepped structure formed by stacking all the shared word lines 50.
[0103] Optionally, as Figure 1 and Figure 3 shown, among all the stacked storage cell arrays, the storage cells located in the same column are configured with a stepped structure, and two adjacent stepped structures are insulated from each other by the isolation structure 60. The shared word line 50 in the stepped structure is electrically connected to the word line 30 arranged in the same layer as this shared word line 50.
[0104] Optionally, as Figure 1 and Figure 3 shown, the shared word line 50 extends along a first direction parallel to the substrate 100. As Figure 3 shown, in the same step structure, a second dielectric structure 71 is provided between any two adjacent stacked shared word lines 50, thereby avoiding electrical connection between two adjacent shared word lines 50. As Figure 3 shown, a second dielectric structure 71 is also provided between the substrate 100 and the shared word line 50.
[0105] Optionally, as Figure 1 and Figure 3 shown, two step structures are arranged and opposed along the first direction, which helps to reduce the occupied area of the step structure, is beneficial to increasing the arrangement number of memory cells, and thus helps to improve the storage density of the semiconductor device.
[0106] Optionally, as Figure 1 and Figure 2 shown, the semiconductor device further includes a support structure 72 and a third dielectric structure 73.
[0107] Optionally, as Figure 2 shown, along the first direction, support structures 72 are provided at both ends of the memory array. The support structures 72 are connected to the memory array and play a supporting role during the manufacturing process of the memory array. Specifically, it will be described in detail in the manufacturing method of the semiconductor device hereinafter and will not be elaborated herein.
[0108] Optionally, as Figure 1 shown, the semiconductor device further includes a switching device 80. The switching device 80 includes at least two second transistors stacked along a third direction. The word lines 30 and the shared word lines 50 arranged in the same layer are both electrically connected to the second transistors arranged in the same layer, so as to realize the on / off of the electrical connection between the word lines 30 and the shared word lines 50 through the second transistors.
[0109] Optionally, among the word lines 30 and the shared word lines 50 arranged in the same layer, the word line 30 is electrically connected to one of the source and drain of the second transistor arranged in the same layer, and the shared word line 50 is electrically connected to the other of the source and drain of the second transistor.
[0110] Optionally, as Figure 4 shown, in the embodiment of the present application, the first transistor 10 further includes a first dielectric structure 12 and a first gate 13. Optionally, both the first dielectric structure 12 and the first gate 13 are annular structures. The first dielectric structure 12 at least partially surrounds the outer peripheral wall of part of the first semiconductor structure 11, and the first gate 13 at least partially surrounds the outer peripheral wall of the first dielectric structure 12.
[0111] Optionally, as Figure 2 shown, in the embodiments of the present application, the capacitor 20 includes a first electrode structure 21, a first dielectric structure 22, and a second electrode structure 23. Optionally, the first electrode structure 21, the first dielectric structure 22, and the second electrode structure 23 are all annular structures. The first electrode structure 21 at least partially surrounds the outer peripheral wall of a part of the first semiconductor structure 11. The first dielectric structure 22 at least partially surrounds the outer peripheral wall of the first electrode structure 21. The second electrode structure 23 at least partially surrounds the outer peripheral wall of the first dielectric structure 22.
[0112] Optionally, as Figure 5 , Figure 6 and Figure 7 shown, in some embodiments of the present application, the semiconductor device further includes: at least two word lines 30, two bit lines 40, and at least two shared bit lines 90.
[0113] Optionally, in the embodiments of the present application, each layer of the memory array is configured with at least one bit line 40, and at least two stacked and insulated bit lines 40 are included in any two adjacent layers of the memory array.
[0114] Optionally, in the embodiments of the present application, the stacked memory arrays are configured with at least two word lines 30. Optionally, as Figure 5 and Figure 6 shown, the word lines 30 extend in a third direction perpendicular to the substrate 100.
[0115] Optionally, as Figure 5 and Figure 6 shown, along the third direction, in all the stacked memory cell arrays, the memory cells whose orthographic projections on the substrate 100 overlap form a group of stacked memory cells. As Figure 5 and Figure 6 shown, each word line 30 is electrically connected to the first transistor 10 of the same group of memory cells.
[0116] Optionally, each word line 30 is electrically connected to the first gate 13 of the first transistor 10 of the same group of memory cells.
[0117] Optionally, in the embodiments of the present application, as Figure 6 shown, each layer of the memory array is configured with one bit line 40. Each layer of the memory array includes two columns of memory cells arranged in a second direction, and the two columns of memory cells in each layer of the memory array are both electrically connected to the same bit line 40.
[0118] Optionally, combining Figure 5 and Figure 6 it can be known that the bit lines 40 extend in a second direction parallel to the substrate 100, and each bit line 40 is electrically connected to the first transistor 10 of a column of memory cells arranged in the second direction in the memory array located in the same layer.
[0119] Optionally, in the embodiments of the present application, some bit lines 40 form the source or drain of the first transistor 10, and the first electrode structure 21 of some capacitors 20 forms the drain or source of the first transistor 10.
[0120] Optionally, in the embodiments of the present application, at least two shared bit lines 90 are stacked and insulated from each other, and at least two shared bit lines 90 stacked form a stepped structure; the bit lines 40 and the shared bit lines 90 arranged in the same layer are electrically connected; the first direction and the second direction intersect.
[0121] Optionally, in some embodiments of the present application, as Figure 5 and Figure 7 shown, the shared bit lines 90 extend along a first direction parallel to the substrate 100, and all stacked memory cell arrays are configured with at least one stepped structure formed by stacking all the shared bit lines 90.
[0122] Optionally, as Figure 7 shown, in the same stepped structure, a second dielectric structure 71 is provided between any two adjacent stacked shared bit lines 90, so as to avoid electrical connection between two adjacent shared bit lines 90. As Figure 7 shown, a second dielectric structure 71 is also provided between the substrate 100 and the shared bit lines 90.
[0123] Optionally, the shared bit lines 90 in the stepped structure are electrically connected to the bit lines 40 arranged in the same layer as this shared bit line 90.
[0124] Optionally, in the embodiments of the present application, as Figure 5 shown, the semiconductor device further includes a switching device 80. The switching device 80 includes at least two second transistors stacked along a third direction. The bit lines 40 and the shared bit lines 90 arranged in the same layer are both electrically connected to the second transistors arranged in the same layer, so as to realize the on / off of the electrical connection between the bit lines 40 and the shared bit lines 90 through the second transistors.
[0125] Optionally, among the bit lines 40 and the shared bit lines 90 arranged in the same layer, the bit line 40 is electrically connected to one of the source and drain of the second transistor arranged in the same layer, and the shared bit line 90 is electrically connected to the other of the source and drain of this second transistor. Optionally, in the embodiments of the present application, as Figure 5 and Figure 7 shown, the semiconductor device further includes a support structure 72 and a third dielectric structure 73. For their structures and functions, please refer to the descriptions of the above embodiments and will not be elaborated here.
[0126] Based on the same inventive concept, the embodiments of the present application provide an electronic device, including: any semiconductor device provided in the above embodiments.
[0127] In this embodiment, since the electronic device employs any one of the semiconductor devices provided in the foregoing embodiments, for the principles and technical effects, please refer to the foregoing embodiments and will not be elaborated herein.
[0128] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal.
[0129] It should be noted that the electronic device is not limited to the above several types. Those skilled in the art can, according to actual application requirements, set any one of the semiconductor devices provided in the foregoing embodiments of the present application in different devices, so as to obtain the electronic device provided in the embodiments of the present application.
[0130] Based on the same inventive concept, the embodiments of the present application provide a manufacturing method of a semiconductor device. The schematic flow chart of the manufacturing method is as Figure 8 shown, and the method includes steps S801 to S802.
[0131] S801, forming a combined film layer including an alternately stacked first sacrificial layer and a first semiconductor layer on one side of a substrate; the first semiconductor layer includes at least two alternately stacked first semiconductor sub-layers and at least one second semiconductor sub-layer, and one of the first semiconductor sub-layers includes a P-type doping element or an N-type doping element, and the other of the second semiconductor sub-layers includes a P-type doping element or an N-type doping element.
[0132] S802, forming at least one first transistor based on the combined film layer; the first semiconductor structure of the first transistor includes at least two first semiconductor sub-structures formed based on the first semiconductor sub-layers and at least one second semiconductor sub-structure formed based on the second semiconductor sub-layers that are alternately stacked.
[0133] To facilitate the reader's intuitive understanding of the manufacturing method of the semiconductor device provided in the embodiments of the present application and the advantages of this manufacturing method, the following will be combined with Figures 9 - 16b to elaborate in detail on the manufacturing method of the semiconductor device.
[0134] Optionally, in some embodiments of the present application, forming the combined film layer including the alternately stacked first sacrificial layer 101 and the first semiconductor layer 102 on one side of the substrate 100 in the above step S801 includes: forming a layer of the first sacrificial layer 101 on one side of the substrate 100 based on an epitaxial process; forming a layer of the first semiconductor layer 102 includes: alternately forming at least two first semiconductor sub-layers 1021 and at least one second semiconductor sub-layer 1022 on the side of the first sacrificial layer 101 away from the substrate 100 based on an epitaxial process and an in-situ doping process.
[0135] Optionally, in the embodiments of the present application, the substrate 100 is a silicon substrate. Based on the epitaxial growth process, a plurality of first sacrificial layers 101 and a plurality of first semiconductor layers 102 are alternately formed on one side of the substrate 100, thereby obtaining a combined film layer.
[0136] Optionally, in the embodiments of the present application, the material of the first sacrificial layer 101 is SiGe.
[0137] Optionally, in the embodiments of the present application, after forming one first sacrificial layer 101, it further includes: based on the epitaxial process and the in-situ doping process, a first semiconductor sub-layer 1021 including an N-type doping element, a second semiconductor sub-layer 1022 including a P-type doping element, and a first semiconductor sub-layer 1021 including an N-type doping element are sequentially formed on the side of the first sacrificial layer 101 away from the substrate 100, thereby obtaining the first semiconductor layer 102 including three stacked film layers.
[0138] Optionally, based on the above steps, the first sacrificial layer 101 and the first semiconductor layer 102 are continuously formed until the required number of first semiconductor layers 102 are obtained, thereby obtaining a combined film layer, as Figure 9 shown.
[0139] Optionally, in some embodiments of the present application, forming at least one first transistor based on the combined film layer in step S802 above includes: patterning the combined film layer to form at least two stacked structures 103 separated by trenches; the stacked structures 103 extend in a first direction parallel to the substrate 100, and the stacked structures 103 include first sacrificial structures 1011 formed based on the first sacrificial layer 101 and first initial semiconductor structures 1023 formed based on the first semiconductor layer 102 that are alternately stacked; removing the first sacrificial structures 1011 in the stacked structures 103; forming at least one first dielectric structure 12 surrounding the first initial semiconductor structure 1023; forming a first gate 12 surrounding the first dielectric structure 12 and forming at least one word line 30; the word line 30 extends in a second direction parallel to the substrate 100 and intersecting the first direction, and the word line 30 is electrically connected to a column of first gates 13 arranged in the second direction in the same layer.
[0140] Optionally, in the embodiments of the present application, patterning the combined film layer to form at least two stacked structures 103 separated by trenches includes: processing the combined film layer based on the patterning process to form at least two stacked structures 103, the plurality of stacked structures 103 are arranged in the second direction, and a trench is provided between any two adjacent stacked structures 103.
[0141] Optionally, after patterning the combined film layer to form at least two stacked structures 103 separated by trenches, it further includes: based on the deposition process, forming at least a first dielectric layer 104 filling the trenches, as Figure 10 shown.
[0142] Optionally, as Figure 11 shown, the stacked structure 103 includes a plurality of first sacrificial structures 1011 and a plurality of first initial semiconductor structures 1023 that are alternately stacked.
[0143] Optionally, in some embodiments of the present application, after forming at least two stacked structures 103 separated by trenches in the patterned composite film layer, it further includes: laterally etching a part of the first sacrificial structures 1011 in the stacked structure 103 so that adjacent two first initial semiconductor structures 1023 and the first sacrificial structures 1011 enclose to form a groove; forming support structures 72 at both ends of the stacked structure 103 along the first direction; and filling part of the support structures 72 into the groove.
[0144] Optionally, in the embodiments of the present application, before the above step of laterally etching a part of the first sacrificial structures 1011 in the stacked structure 103 so that adjacent two first initial semiconductor structures 1023 and the first sacrificial structures 1011 enclose to form a groove, it includes: patterning the first dielectric layer 104 based on a patterning process so that both ends of the stacked structure 103 along the first direction are exposed.
[0145] Optionally, in the embodiments of the present application, the above step of laterally etching a part of the first sacrificial structures 1011 in the stacked structure 103 so that adjacent two first initial semiconductor structures 1023 and the first sacrificial structures 1011 enclose to form a groove includes: treating two end walls of the stacked structure 103 along the first direction based on a wet etching process so that part of the first sacrificial structures 1011 exposed in the end walls of the stacked structure 103 are etched, thereby making adjacent two first initial semiconductor structures 1023 and the first sacrificial structures 1011 enclose to form a groove.
[0146] Optionally, in the above step of forming the support structures 72 at both ends of the stacked structure 103 along the first direction, it includes: depositing a dielectric material in the groove based on the ALD (Atomic Layer Deposition) process until the groove is filled, to form a first sub-support structure 721 located in the groove; and forming second sub-support structures 722 at both ends of the initial stacked structure along the first direction based on a deposition process so that the second sub-support structures 722 cover the end walls of the initial stacked structure along the first direction, thereby obtaining the support structure 72 including the first sub-support structure 721 and the second sub-support structures 722, as Figure 12 shown.
[0147] Optionally, the deposition process includes CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc.
[0148] It should be noted that, for the convenience of readers to intuitively understand the structure of the support structure 72, as Figure 12 shown, the boundary line between the first sub-support structure 721 and the second sub-support structure 722 is represented by a dashed line. In the actual product, there is no dashed line.
[0149] Optionally, in the embodiments of the present application, the above step of removing the first sacrificial structure 1011 in the stacked structure 103 includes: based on an etching process, removing the first sacrificial structure 1011 in the stacked structure 103, so that a trench is formed between any two adjacent first initial semiconductor structures 1023, as Figure 13a and Figure 13b shown.
[0150] In the embodiments of the present application, as Figure 13a and Figure 13b shown, after removing the first sacrificial structure 1011, the support structure 72 serves to support the first initial semiconductor structure 1023. Moreover, by setting the first sub-support structure 721, the contact area between the support structure 72 and the first initial semiconductor structure 1023 can be increased, and the support structure 72's support for the first initial semiconductor structure 1023 can be further enhanced, thereby reducing the probability of the first initial semiconductor structure 1023 breaking during subsequent operations.
[0151] Optionally, in the embodiments of the present application, the above step of forming at least one first dielectric structure 12 surrounding the first initial semiconductor structure 1023 includes: forming a second dielectric layer 105 based on a deposition process to fill the trenches between any two adjacent first initial semiconductor structures 1023 and the trenches between the first initial semiconductor structure 1023 and the substrate 100; processing the second dielectric layer 105 based on a patterning process to expose the outer peripheral walls of some of the first initial semiconductor structures 1023; forming at least part of the first dielectric structure 12 surrounding the first initial semiconductor structure 1023 based on a deposition process, as Figure 14a and Figure 14b shown.
[0152] Optionally, in the embodiments of the present application, forming the first gate 13 surrounding the first dielectric structure 12 and forming at least two stacked and insulated word lines 30 in the above steps includes: based on a deposition process, forming the first gate 12 at least partially surrounding the outer peripheral wall of the first dielectric structure 12, and forming the word line 30 electrically connected to a column of first gates 13 arranged in the second direction on the same layer, thereby obtaining the first transistor 10, as Figure 14a and Figure 14b shown.
[0153] Optionally, as Figure 14a and Figure 14b shown, along the first direction, each first initial semiconductor structure 1023 is provided with two first transistors 10, that is, at least two first transistors 10 can be formed simultaneously based on the same first initial semiconductor structure 1023, which helps to improve the manufacturing efficiency of semiconductor devices.
[0154] Optionally, in some embodiments of the present application, after forming the first gate 12 surrounding the first dielectric structure 12 and forming at least one word line 30, it further includes: forming a capacitor 20 in a portion of the first initial semiconductor structure 1023 away from the first dielectric structure 12; forming a bit line penetrating through the stacked structure 103, so that the first initial semiconductor structure 1023 is separated into two first semiconductor structures 11 by the bit line.
[0155] Optionally, in the embodiments of the present application, forming the capacitor 20 in a portion of the first initial semiconductor structure 1023 away from the first dielectric structure 12 in the above steps includes: processing the second dielectric layer 105 based on a patterning process to expose the outer peripheral wall of a portion of the first initial semiconductor structure 1023; based on a deposition process, sequentially forming a first electrode structure 21, a first dielectric structure 22, and a second electrode structure 23 surrounding the first initial semiconductor structure 1023 to obtain the capacitor 20, as Figure 15a and Figure 15b shown.
[0156] Optionally, as Figure 15a and Figure 15b shown, capacitors 20 are provided at both ends of the first initial semiconductor structure 1023 along the first direction, that is, at least two memory cells including a first transistor 10 and a capacitor 20 can be formed simultaneously based on the same first initial semiconductor structure 1023.
[0157] Optionally, as Figure 15a and Figure 15b shown, the third dielectric structure 73 includes: the patterned first dielectric layer 104 and the patterned second dielectric layer 105.
[0158] Optionally, in the embodiments of the present application, in the above steps, the bit line 40 penetrating the stacked structure 103 is formed, so that the first initial semiconductor structure 1023 is separated into two first semiconductor structures 11 by the bit line 40, including: based on a patterning process, vias penetrating all the first initial semiconductor structures 1023 are formed, so that the first initial semiconductor structure 1023 is separated into two first semiconductor structures 11, and a conductive material is deposited in the vias to form the bit line 40, as Figure 16a and Figure 16b shown.
[0159] Based on the same inventive concept, the embodiments of the present application provide an electronic device, which includes: any semiconductor device provided in the above various embodiments.
[0160] In the embodiments of the present application, since the electronic device adopts any one of the semiconductor devices provided in the foregoing embodiments, for the principles and technical effects, please refer to the foregoing embodiments and will not be elaborated herein.
[0161] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.
[0162] It should be noted that the electronic device is not limited to the above several types. Those skilled in the art can, according to actual application requirements, set any one of the semiconductor devices provided in the above various embodiments of the present application in different devices, so as to obtain the electronic device provided in the embodiments of the present application.
[0163] Those skilled in the art of the present technology can understand that the electronic device provided in the embodiments of the present application can be specially designed and manufactured for the required purpose, or can also include known devices in a general computer. These devices have any one of the semiconductor devices provided in the above various embodiments.
[0164] Applying the embodiments of the present application can at least achieve the following beneficial effects:
[0165] In the semiconductor device (which can be used for a memory) provided in the embodiments of the present application, by setting the first semiconductor structure 10 of at least one first transistor 10 to include at least two first semiconductor sub-structures 111 and at least one second semiconductor sub-structure 112 that are alternately stacked, and the first semiconductor sub-structure 111 and the second semiconductor sub-structure 112 include different types of doping elements, the effective thickness of the depletion region in the first transistor in the off state can be increased, which is beneficial to reducing the leakage current of the first transistor 10, beneficial to increasing the on-off ratio of the first transistor 10, and further beneficial to improving the electrical performance of the first transistor 10.
[0166] Those skilled in the art of the present application can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, those in the prior art that have steps, measures, and solutions in the various operations, methods, and processes disclosed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
[0167] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are the exemplary directions or positional relationships based on the drawings, and are for the convenience of describing or simplifying the embodiments of the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.
[0168] The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.
[0169] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0170] In the description of this specification, the specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.
[0171] The above are only some embodiments of the present application. It should be noted that for those of ordinary skill in the art of the present technology, without departing from the technical concept of the solution of the present application, adopting other similar implementation means based on the technical idea of the present application also belongs to the protection scope of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that, Comprising: a substrate, and at least one first transistor disposed on the substrate, the first transistor including a first gate and a first dielectric structure, and a first semiconductor structure located on a side of the first dielectric structure away from the first gate; The first semiconductor structure includes at least two first semiconductor sub-structures and at least one second semiconductor sub-structure stacked alternately, the first semiconductor sub-structure includes one of a P-type doping element or an N-type doping element, and the second semiconductor sub-structure includes the other of the P-type doping element or the N-type doping element.
2. The semiconductor device according to claim 1, wherein The first semiconductor structure includes the first semiconductor sub-structure, the second semiconductor sub-structure, and the first semiconductor sub-structure stacked in a direction away from the substrate; The first semiconductor sub-structure includes an N-type doping element, and the second semiconductor sub-structure includes a P-type doping element.
3. The semiconductor device according to claim 2, wherein, The doping concentration of the second semiconductor sub-structure is not less than 1e15 cm -3 and not greater than 1e21 cm -3 .
4. The semiconductor device according to claim 3, wherein The doping concentration of the first semiconductor substructure is not less than 1e16 cm -3 and not greater than 1e22 cm -3 ; and / or, the doping concentration of the second semiconductor sub-structure is not less than 1e17 cm -3 and not greater than 1e19 cm -3 .
5. The semiconductor device according to claim 1, wherein The semiconductor device further includes a bit line and a shared bit line, and a second transistor connecting the bit line and the shared bit line; Alternatively, the semiconductor device further includes a word line and a shared word line, and a second transistor connecting the word line and the shared word line.
6. The semiconductor device according to claim 5, wherein, The second transistor includes a second semiconductor structure, and the second semiconductor structure is the same as the first semiconductor structure.
7. The semiconductor device according to claim 1, wherein Further comprising: A multi-layer memory array disposed in a direction away from the substrate, the memory array including at least one memory cell; the memory cell includes the first transistor and a capacitor connected to each other.
8. The semiconductor device according to claim 7, wherein, Further comprising: At least two word lines extending in a second direction parallel to the substrate and electrically connected to the first transistors of a column of memory cells arranged in the second direction in the memory array of the same layer; At least two bit lines extending in a third direction perpendicular to the substrate and electrically connected to the first transistors of a group of memory cells stacked in the third direction.
9. The semiconductor device according to claim 8, wherein Further comprising: At least two shared word lines stacked and insulated from each other, the shared word lines extending in a first direction parallel to the substrate, the at least two shared word lines stacked to form a stepped structure; the word lines and the shared word lines of the same layer are electrically connected; the first direction and the second direction intersect.
10. The semiconductor device according to claim 7, wherein Further comprising: At least two word lines extending in a third direction perpendicular to the substrate and electrically connected to the first transistors of a group of memory cells stacked in the third direction; At least two bit lines extending in a second direction parallel to the substrate and electrically connected to the first transistors of a column of memory cells arranged in the second direction in the memory array of the same layer.
11. The semiconductor device according to claim 10, wherein, Further comprising: At least two shared bit lines stacked and insulated from each other, the shared bit lines extending in a first direction parallel to the substrate, the at least two shared bit lines stacked to form a stepped structure; the bit lines and the shared bit lines of the same layer are electrically connected; the first direction and the second direction intersect.
12. An electronic device, characterized in that, Comprising: The semiconductor device according to any one of claims 1 to 11.
13. A method for manufacturing a semiconductor device, characterized in that, Comprising: A combined film layer including an alternately stacked first sacrificial layer and a first semiconductor layer is formed on one side of a substrate; the first semiconductor layer includes at least two alternately stacked first semiconductor sub-layers and at least one second semiconductor sub-layer, one of the first semiconductor sub-layers includes one of a P-type doping element or an N-type doping element, and the second semiconductor sub-layer includes the other of the P-type doping element or the N-type doping element; At least one first transistor is formed based on the combined film layer; the first semiconductor structure of the first transistor includes at least two first semiconductor sub-structures formed based on the first semiconductor sub-layers and at least one second semiconductor sub-structure formed based on the second semiconductor sub-layer, which are alternately stacked.
14. The manufacturing method of the semiconductor device according to claim 13, wherein, Forming a combined film layer including an alternately stacked first sacrificial layer and a first semiconductor layer on one side of a substrate includes: Forming one layer of the first sacrificial layer on one side of the substrate based on an epitaxial process; Forming one layer of the first semiconductor layer includes: alternately forming at least two layers of the first semiconductor sub-layers and at least one layer of the second semiconductor sub-layers on the side of the first sacrificial layer away from the substrate based on an epitaxial process and an in-situ doping process.
15. The manufacturing method of the semiconductor device according to claim 13, characterized in that, Forming at least one first transistor based on the combined film layer includes: Patterning the combined film layer to form at least two stacked structures separated by trenches; the stacked structures extend along a first direction parallel to the substrate, and the stacked structures include alternately stacked first sacrificial structures formed based on the first sacrificial layer and first initial semiconductor structures formed based on the first semiconductor layer; Removing the first sacrificial structures in the stacked structures; Forming at least one first dielectric structure surrounding the first initial semiconductor structure; Forming a first gate surrounding the first dielectric structure and forming at least one word line; the word line extends along a second direction parallel to the substrate and intersecting the first direction, and the word line is electrically connected to a column of the first gates arranged along the second direction in the same layer.
16. The manufacturing method of the semiconductor device according to claim 15, characterized in that, After forming a first gate surrounding the first dielectric structure and forming at least one word line, it further includes: Forming a capacitor in a part of the first initial semiconductor structure away from the first dielectric structure; Forming a bit line penetrating the stacked structures such that the first initial semiconductor structure is separated into two first semiconductor structures by the bit line.
17. The manufacturing method of the semiconductor device according to claim 15, characterized in that, After patterning the combined film layer to form at least two stacked structures separated by trenches, it further includes: Laterally etching part of the first sacrificial structures in the stacked structures such that adjacent two first semiconductor structures and the first sacrificial structures enclose a groove; Forming support structures at two ends of the stacked structures along the first direction; part of the support structures fills the groove.