Memory, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a memory, a manufacturing method thereof and electronic equipment. The memory comprises a memory cell array which is located on a substrate and periodically stacked in the direction perpendicular to the substrate; each storage unit comprises a transistor and a capacitor which are sequentially distributed in the first direction; the capacitor comprises an inner electrode extending in the first direction, and a dielectric layer and an outer electrode which sequentially cover the inner electrode; the transistor comprises a first electrode connected with the internal circuit and a second electrode connected with the bit line; a dielectric layer is arranged between any two layers of memory cell arrays; wherein the inner electrode is formed by replacing a sacrificial layer between two adjacent dielectric layers; the first electrode, the second electrode and the bit line are formed by replacing the sacrificial layer between the two adjacent dielectric layers after the inner electrode is formed.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design and manufacturing technologies, and particularly to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous development of integrated circuit manufacturing processes, the market has put forward higher requirements for the storage capacity and storage performance of DRAM memories. The three-dimensional stacked DRAM (abbreviated as 3D DRAM) has gradually attracted attention, and this technology provides the possibility to further improve the storage performance of DRAM memories and increase the storage density. Summary of the Invention

[0003] Based on this, the present disclosure provides a memory, a manufacturing method thereof, and an electronic device, which can effectively improve the mechanical reliability of the memory during the manufacturing process.

[0004] According to various embodiments of the present disclosure, on the one hand, a memory is provided, including:

[0005] A memory cell array stacked on a substrate in a direction perpendicular to the substrate; each layer of the memory cell array includes memory cells distributed in rows and columns in a first direction and a second direction; the first direction is the row direction, and the second direction is the column direction;

[0006] Multiple word lines extending in a direction perpendicular to the substrate and penetrating through each layer of the memory cell array, and each word line is connected to multiple memory cells;

[0007] Multiple bit lines extending in the second direction, and each bit line is connected to at least one column of memory cells in a memory cell array;

[0008] Each memory cell includes a transistor and a capacitor distributed in sequence in the first direction; the capacitor includes an inner electrode extending in the first direction, a dielectric layer covering the inner electrode in sequence, and an outer electrode; the transistor includes a first electrode electrically connected to the inner electrode and a second electrode connected to the bit line;

[0009] A dielectric layer is included between any two layers of the memory cell array;

[0010] Wherein, the inner electrode is formed by replacing a sacrificial layer between adjacent two layers of the dielectric layer; the first electrode, the second electrode, and the bit line are formed by replacing the sacrificial layer between adjacent two layers of the dielectric layer after the inner electrode is formed.

[0011] In some embodiments, the inner electrode and the first electrode are formed by patterning different conductive layers;

[0012] The first electrode, the second electrode, and the bit line are formed by patterning the same conductive layer.

[0013] In some embodiments, the memory cell further includes a channel layer located between the first electrode and the second electrode and surrounding the sidewall of the word line, and the channel layer is insulated from the word line by a gate dielectric layer.

[0014] In some embodiments, one bit line is connected to the second electrodes of each of two adjacent columns of memory cells; the two adjacent columns of memory cells are symmetrically distributed with respect to the bit line in a mirror image manner;

[0015] The bit lines, the second electrodes, and the first electrodes of the two columns of memory cells are formed by replacing a sacrificial layer between two adjacent dielectric layers once; the first electrodes, the second electrodes, and the bit line are formed by patterning the same conductive layer.

[0016] In some embodiments, the dielectric layer and the outer electrode are formed after forming the inner electrode and before forming the bit line, and the outer electrode serves as a support frame.

[0017] In some embodiments, the dielectric layer and the outer electrode cover a column of memory cells and the inner electrodes of each of the memory cells stacked in the vertical direction of the column of memory cells; the dielectric layer and the outer electrode are formed by replacing the dielectric layer in the capacitor region.

[0018] In some embodiments, the dielectric layer is silicon oxide, and the sacrificial layer is silicon nitride or silicon oxynitride.

[0019] An embodiment of the present application provides an electronic device, including the memory according to any one of the above embodiments.

[0020] An embodiment of the present application provides a manufacturing method of a memory, including:

[0021] Providing a substrate, and forming a plurality of dielectric layers and a plurality of sacrificial layers on the substrate, the dielectric layers and the sacrificial layers being alternately distributed;

[0022] Performing a patterning process on the dielectric layer and the sacrificial layer to form a plurality of trenches perpendicular to the substrate; between the trenches, there are included a plurality of first sacrificial bars corresponding to the memory cells one by one, extending in a first direction and spaced apart in a second direction, and second sacrificial bars intersecting with the plurality of first sacrificial bars; between the trenches, there is also included a dielectric layer stacked with the plurality of first sacrificial bars and the second sacrificial bars of each layer; the first direction is the row direction, the second direction is the column direction, and both the row direction and the column direction are parallel to the substrate;

[0023] The first sacrificial bar sequentially includes a capacitor region and a transistor region in the first direction, and the transistor region is close to the second sacrificial bar;

[0024] The capacitive region of the first sacrificial strip is removed by an etching process to expose the dielectric layers adjacent in the vertical direction, and the transistor region of the first sacrificial strip is retained;

[0025] A conductive layer is filled between the exposed dielectric layers to replace the capacitive region of the first sacrificial strip, forming an inner electrode;

[0026] After forming the inner electrode, the transistor region of the first sacrificial strip and the second sacrificial strip are removed by an etching process to expose the dielectric layers adjacent in the vertical direction, and a conductive layer is filled between the adjacent dielectric layers to replace the transistor region and the second sacrificial strip, forming a first electrode, a second electrode, and a bit line in contact with the inner electrode.

[0027] In some embodiments, before forming the inner electrode, the trench is filled with a material the same as that of the dielectric layer, a word line hole penetrating through each dielectric layer and each sacrificial layer is formed in the transistor region of the first sacrificial strip, and a dummy word line is filled in the word line hole.

[0028] In some embodiments, the plurality of first sacrificial strips and the second sacrificial strips of each layer are of an integral structure; the first electrode and the second electrode are spaced apart from each other; the second electrode and the bit line are of an integral structure.

[0029] In some embodiments, removing the first sacrificial strip of each capacitive region by an etching process to expose the dielectric layers adjacent in the vertical direction and retaining the first sacrificial strip of the transistor region includes:

[0030] Removing the dielectric layer between the capacitive regions adjacent in the column direction in the trench region to expose the capacitive region of the first sacrificial strip; removing the capacitive region of the first sacrificial strip between the dielectric layers adjacent in the vertical substrate direction, and sequentially filling a first conductive layer between the adjacent dielectric layers as the inner electrode.

[0031] In some embodiments, before fabricating the first electrode, the second electrode, and the bit line after fabricating the inner electrode, it further includes:

[0032] A dielectric layer and a conductive layer are sequentially deposited on the exposed inner electrode, the conductive layer is the outer electrode of the capacitor; the outer electrode serves as a support frame.

[0033] In some embodiments, removing the transistor region of the first sacrificial strip and the second sacrificial strip to expose the adjacent dielectric layers includes:

[0034] Removing the dielectric layer between the transistor regions adjacent in the trench region by a dry etching process; removing the sacrificial layer between the dielectric layers adjacent in the vertical direction by a wet process to expose the dielectric layers in the regions of the first electrode, the second electrode, and the bit line.

[0035] The memory and manufacturing method provided by the embodiments of the present application replace the sacrificial layer with a conductive layer after the sacrificial layer and the dielectric layer are stacked to implement the transistor and capacitor of the memory cell. Among them, the sacrificial layer in the capacitor region is first replaced with a conductive layer, and the sacrificial layer in the transistor region is then replaced with a conductive layer by using the conductive layer and the dielectric layer in the capacitor region as a support. This can improve the mechanical stability of forming the capacitor and the transistor in the sacrificial layer and dielectric layer stacking process and avoid the risk of collapse. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figures 1 - 11 Schematic diagrams of the three-dimensional structures obtained in different steps in a manufacturing method of a memory provided in an embodiment of the present disclosure;

[0038] Among them, the ox direction can be the first direction, the oy direction can be the second direction, and the oz direction can be the vertical direction.

[0039] Description of the reference numerals:

[0040] 100, substrate; 11, dielectric layer; 12, sacrificial layer; 121, first sacrificial strip; 122, second sacrificial strip; 123, third sacrificial strip; 20, dummy word line; 40, capacitor; 90, isolation layer; 41, inner electrode; 42, intermediate dielectric layer; 43, outer electrode; 50, conductive layer; 13, patterned mask layer; 14, isolation trench; 15, first groove; 16, intermediate trench; 17, interlayer groove; 18, bit line groove; 501, bit line; 19, side groove; 60, common bit line. Detailed Embodiments

[0041] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0043] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0045] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0046] Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, one or more of the presence of insulating materials, insulating gas, or gaps between the two.

[0047] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although only the components related to the present disclosure are shown in the diagrams and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0048] Note that the mutual insulation between the two described in the embodiments of the present disclosure includes, but is not limited to, at least one of the presence of an insulating material layer, insulating gas, or gaps between the two; the "conformal coverage" or "conformal overlay" of A and B formed on the substrate in the embodiments of the present disclosure is intended to express the meaning that the orthographic projection of A on the top surface of the substrate completely overlaps with the orthographic projection of B on the top surface of the substrate.

[0049] In the manufacturing process of 3D DRAM devices, in some embodiments, a dielectric layer and a sacrificial layer (generally an insulating layer) are stacked, and then the sacrificial layer is replaced with a conductive layer in the capacitor region and the transistor region to form a capacitor and a transistor. In this application scenario, there are prone to problems with the mechanical stability of the entire 3D stack when replacing the sacrificial layer. For example, the film layer of 3D-DRAM is prone to collapse after the sacrificial layer is hollowed out. Some embodiments will fabricate a support frame independent of the capacitor and the transistor as a support.

[0050] This application proposes a memory, a manufacturing method thereof, and an electronic device that can improve mechanical stability.

[0051] In some embodiments, a manufacturing method of a memory is provided, including:

[0052] Providing a substrate, and forming a plurality of dielectric layers and a plurality of sacrificial layers on the substrate, the dielectric layers and the sacrificial layers being alternately distributed;

[0053] Performing a patterning process on the dielectric layers and the sacrificial layers to form a plurality of trenches perpendicular to the substrate; between the trenches, there are included a plurality of first sacrificial bars extending in a first direction and spaced apart in a second direction, and second sacrificial bars intersecting with the plurality of first sacrificial bars. The plurality of first sacrificial bars and the second sacrificial bars in each layer are of an integral structure; between the trenches, there are also included dielectric layers stacked with the plurality of first sacrificial bars and the second sacrificial bars in each layer; the first direction is the row direction, the second direction is the column direction, and both the row direction and the column direction are parallel to the substrate;

[0054] The first sacrificial bar sequentially includes a capacitor region and a transistor region in the first direction, and the transistor region is close to the second sacrificial bar;

[0055] Remove the first sacrificial strip in each capacitor region by an etching process to expose the dielectric layers adjacent in the vertical direction, and retain the first sacrificial strip in the transistor region;

[0056] Fill a conductive layer between the adjacent exposed dielectric layers to replace the capacitor region of the first sacrificial strip and form an inner electrode;

[0057] After forming the inner electrode, remove the transistor region of the first sacrificial strip and the second sacrificial strip by an etching process to expose the dielectric layers adjacent in the vertical direction, and fill a conductive layer between the adjacent dielectric layers to replace the transistor region and the second sacrificial strip, forming a first electrode in contact with the inner electrode, and a second electrode and a bit line of an integrated structure, with the second electrode and the first electrode spaced apart from each other.

[0058] In some embodiments, before forming the inner electrode, fill the trench with the same material as the dielectric layer, form a word line hole penetrating through each dielectric layer and each sacrificial layer in the transistor region of the first sacrificial strip, and fill a dummy word line in the word line hole.

[0059] In some embodiments, removing the first sacrificial strip in each capacitor region by an etching process to expose the dielectric layers adjacent in the vertical direction and retaining the first sacrificial strip in the transistor region includes:

[0060] Remove the dielectric layer between the capacitor regions adjacent in the column direction in the trench region to expose the capacitor region of the first sacrificial strip; remove the capacitor region of the first sacrificial strip between the dielectric layers adjacent in the vertical substrate direction, and sequentially fill a first conductive layer between the adjacent dielectric layers as the inner electrode.

[0061] In some embodiments, before fabricating the first electrode, the second electrode, and the bit line after fabricating the inner electrode, further include:

[0062] Deposit a dielectric layer and a second conductive layer on the exposed inner electrode in sequence, with the second conductive layer being the outer electrode of the capacitor; the dielectric layer and the outer electrode serve as a support frame.

[0063] In some embodiments, removing the transistor region of the first sacrificial strip and the second sacrificial strip to expose the adjacent dielectric layers includes:

[0064] Use a dry etching process to remove the dielectric layer between the adjacent transistor regions in the trench region; remove the sacrificial layer between the dielectric layers adjacent in the vertical direction by a wet process to expose the dielectric layers in the regions of the first electrode, the second electrode, and the bit line.

[0065] The memory and manufacturing method provided by the embodiments of the present application replace the sacrificial layer with a conductive layer after the sacrificial layer and the dielectric layer are stacked to implement the transistor and capacitor of the memory cell. Among them, the sacrificial layer in the capacitor region is first replaced with a conductive layer, and the sacrificial layer in the transistor region is then replaced with a conductive layer by using the conductive layer and the dielectric layer in the capacitor region as a support. In this way, the mechanical stability of forming the capacitor and the transistor by the stacking process of the sacrificial layer and the dielectric layer can be improved, and the risk of collapse can be avoided.

[0066] The above-mentioned memory manufacturing method and the device characteristics of the memory will be described in detail below with reference to the accompanying drawings.

[0067] A manufacturing method of a memory includes:

[0068] Step S20: Provide a substrate (such as a silicon substrate), and sequentially form a dielectric layer and a sacrificial layer on the substrate, which are alternately stacked in a direction perpendicular to the substrate to form a stacked film layer. Each adjacent two dielectric layers and sacrificial layers form a cycle. For example, an alternating cyclic distribution of a silicon nitride film layer and a silicon oxide film layer is formed on the substrate. The silicon nitride can be several layers or dozens of layers, and the silicon oxide is located between any two adjacent silicon nitride film layers. The silicon oxide is the dielectric layer, and the silicon nitride is the sacrificial layer. The silicon oxide and the silicon nitride are only used to illustrate the elements included in the film layer material, and the element ratio of the film layer material is not limited.

[0069] Etch the stacked film layer through a mask to form a trench in a direction perpendicular to the substrate. The dielectric layer and the sacrificial layer outside the trench are the patterned film layers. Among them, the sacrificial layer includes a plurality of first sacrificial bars extending in a first direction (row direction) and spaced apart in a second direction (column direction), and a second sacrificial bar extending in the column direction and intersecting with the plurality of first sacrificial bars; the first sacrificial bar is used to form a capacitor and a transistor, and the second sacrificial bar is used to form a bit line;

[0070] One second sacrificial bar can connect two columns of first sacrificial bars at the same time, or one second sacrificial bar can only connect one column of first sacrificial bars.

[0071] In addition, the second sacrificial bar and each of the connected first sacrificial bars are of an integral structure.

[0072] Step S40: Fill the trench with an isolation layer. The isolation layer can be a film layer of the same material as the dielectric layer, and can also be called a dielectric layer, or can be understood as forming an isolation layer between the first sacrificial bars adjacent in the second direction. Then, a word line hole penetrating the dielectric layer and the first sacrificial bar is formed in the transistor region of the first sacrificial bar, and polysilicon is filled in the word line hole as a dummy word line, which can also be understood as a temporary word line or a sacrificial word line, and will be replaced by a real word line later. The second sacrificial bar is located between the dummy word lines adjacent in the first direction; the first direction intersects with the second direction and is parallel to the substrate.

[0073] Step S60: Extend the first sacrificial strip in the row direction, and include adjacent capacitor regions and transistor regions in the row direction. The transistor region is close to the bit line region, and the capacitor is connected to the bit line through the transistor.

[0074] Replace the capacitor region of the first sacrificial strip with an inner electrode, then remove the dielectric layer in contact with the inner electrode to expose the side surface of the inner electrode extending in the row direction, and sequentially form a dielectric layer and an outer electrode on the side surface.

[0075] When removing the dielectric layer in contact with the inner electrode, simultaneously remove a column of memory cells and the dielectric layers in contact with the inner electrodes of each of the stacked memory cells to expose the inner electrodes of the stacked multiple columns of memory cells. In one process, form a dielectric layer serving as a capacitive dielectric layer on the side surfaces of the inner electrodes, and in one process, form a conductive layer to replace the removed dielectric layer. The conductive layer serves as the outer electrode of the capacitor. This conductive layer is a mutually connected film layer that simultaneously covers the side surfaces of the inner electrodes. Of course, the dielectric layer and the conductive layer serving as the outer electrode can simultaneously cover the side surfaces and end faces of the inner electrodes.

[0076] This outer electrode simultaneously acts as a support frame and plays the role of a support frame when subsequently hollowing out the sacrificial layer.

[0077] For each memory cell array, every two columns of memory cells are mirror-symmetrically distributed as a repeating unit. The capacitors of adjacent repeating units are adjacent.

[0078] Step S80: Remove the isolation layer located between the outer electrodes adjacent in the first direction, which can be understood as removing the isolation layer between adjacent repeating units;

[0079] Step S100: Fill a conductive layer in the isolation layer removed in Step S80. This conductive layer serves as a common outer electrode for adjacent capacitors in two repeating units, and this common outer electrode is connected to the outer electrode of the capacitor region.

[0080] As an example, please refer to Figure 1 , the substrate 100 provided in Step S20 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 100 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the substrate 100 should not limit the protection scope of the present disclosure.

[0081] Exemplarily,Figure 1 In the Figure 1 , the ox direction is the first direction, the oy direction is the second direction, and the oz direction is the vertical direction (i.e., the direction perpendicular to the substrate). In the embodiment, the first direction may be the row direction and the second direction may be the column direction.

[0082] As an example, refer to Figure 1 , in step S20, a deposition process may be used to sequentially form a dielectric layer and a sacrificial layer on the substrate 100 that are alternately stacked in the direction perpendicular to the substrate 100, and then an etching process may be used to obtain a trench perpendicular to the substrate, obtaining the patterned dielectric layer 11 and sacrificial layer 12 that are alternately stacked in the direction perpendicular to the substrate 100.

[0083] Among them, see Figure 1 , the shapes of the patterned dielectric layer 11 and the sacrificial layer 12 are the same.

[0084] The sacrificial layer 12 includes a plurality of first sacrificial strips 121 that extend in the first direction and are spaced apart in the second direction, and each sacrificial strip corresponds to a memory cell region.

[0085] The sacrificial layer 12 further includes second sacrificial strips 122 where the plurality of first sacrificial strips 121 intersect. The second sacrificial strips 122 connect two columns of first sacrificial strips 121 and are integrally provided with the first sacrificial strips 121.

[0086] The sacrificial layer 12 may further include third sacrificial strips 123 on the same side in the second direction of the plurality of first sacrificial strips 121, so as to facilitate replacing the third sacrificial strips 123 with common bit lines in the subsequent process.

[0087] The first sacrificial strips, the second sacrificial strips, and the third sacrificial strips are integrally provided.

[0088] The material of the dielectric layer 11 may include, but is not limited to, silicon oxide; the material of the sacrificial layer 12 may include, but is not limited to, silicon oxynitride or silicon nitride and other film layers containing silicon and nitrogen. Since the insulating layer stack structure including nitride and oxide is more convenient during deposition and has a relatively low etching selectivity ratio during the etching process, the etching process is less difficult. Therefore, the manufacturing efficiency of the memory can be improved and the cost can be reduced. The etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high density plasma etching (HDP). The deposition process may include, but is not limited to, one or more of chemical vapor deposition process (Chemical Vapor Deposition, CVD), atomic layer deposition process (Atomic Layer Deposition, ALD), high density plasma deposition (High Density Plasma, HDP) process, plasma enhanced deposition process, and spin-on dielectric (SOD) process.

[0089] As an example, see Figure 2 In step S40, a deposition process may be used. Figure 1 An isolation layer 90 is formed in the groove of the three-dimensional structure, and the isolation layer 90 can fill the groove between the patterned dielectric layer 11 and the sacrificial layer 12. After the isolation layer 90 is formed, a planarization process such as a chemical mechanical polishing process can be used to expose the top dielectric layer 11.

[0090] The isolation layer may be made of the same material as the dielectric layer, for example, a silicon oxide film layer may be formed by using the same material as the silicon oxide of the dielectric layer between the sacrificial layers.

[0091] As an example, please refer to Figure 2 After forming the isolation layer 90 whose top surface is flush with the dielectric layer 11, a plurality of first holes (also referred to as word line holes) are formed in step S40 by dry etching process, which penetrate the dielectric layer 11 and the sacrificial layer 12 in the direction perpendicular to the substrate 100. The plurality of first holes are located in the transistor region of the first sacrificial strip 121. One first hole corresponds to one word line and each memory cell stacking layer in a memory cell region. The second sacrificial strip 122 is located between the two first holes on the first sacrificial strip 121 as a bit line region to be formed. The first hole can expose part of the top surface of the substrate 100; then, an insulating or conductive material (such as polysilicon) can be filled in the first hole by a deposition process to form a dummy word line 20 in the first hole. The second sacrificial strip 122 is located between the adjacent dummy word lines 20 along the first direction, so as to form two bit lines or a common bit line between two adjacent memory cells along the first direction.

[0092] In step S40 , after forming the dummy word line 20 , a planarization process may be used to process the top surface of the dummy word line 20 , so that the top surface of the dummy word line 20 is flush with the top surface of the isolation layer 90 .

[0093] As an example, see Figures 3 - 8 In step S60, the end of the first sacrificial strip 121 away from the dummy word line 20 along the first direction is replaced with the inner electrode of the capacitor, including:

[0094] Step S61: forming a mask layer 13 for defining a capacitor region on the top of the stacked film layer;

[0095] Step S62: Using the mask layer 13 as a mask, etch and remove the portion of the isolation layer 90 that deviates from the dummy word line 20 in the first direction, to obtain isolation trenches 14. It can be understood that the mask layer 13 covers the bit line region, the transistor region, and the isolation layer region between adjacent transistor regions in the column direction. The region between two adjacent capacitor regions in the column direction in the isolation layer 90 is exposed. Of course, the isolation layer in the vertical direction of this region is removed, and at the same time, the side walls of the patterned dielectric layer and the sacrificial layer are exposed. It can also be understood that trenches (isolation trenches 14) are dug again in the trench region filled with the isolation layer, and these trenches (isolation trenches 14) only expose the portion between the capacitor regions and retain the portion between the transistor regions. The isolation layer between the capacitor regions is removed and the side walls of the patterned dielectric layer and the sacrificial layer are exposed.

[0096] Step S63: Through the isolation trenches 14, remove the portion of the plurality of first sacrificial bars 121 that deviates from the dummy word line 20 in the first direction, to obtain first grooves 15.

[0097] It can be understood that after the side walls of the dielectric layer and the sacrificial layer are exposed, the sacrificial layer is etched and removed by a selective etching solution to expose the inner surface (the surface that has contacted the sacrificial layer) of the dielectric layer in the capacitor region. At this time, the sacrificial layer in the transistor region will still be retained, which can be achieved by controlling the etching depth of the sacrificial layer through the etching time. At this time, the upper, lower, and side surfaces of any dielectric layer in the capacitor region are exposed, and the opening between two adjacent dielectric layers can be referred to as the first groove 15.

[0098] Step S64: Form a conductive layer in the opening between two adjacent dielectric layers as the inner electrode of the capacitor. That is Figure 6 as shown, form the inner electrode 41 in the first groove 15. At this time, the inner electrodes 41 are independent of each other and isolated by the dielectric layer.

[0099] As an example, please continue to refer to Figure 3 In step S61, a patterned photoresist layer (not shown) and a hard mask layer located between the patterned photoresist layer and the isolation layer 90 can be formed on the top surface of the three-dimensional structure shown. The hard mask layer can be a single-layer structure or a multi-layer stacked structure, and its material can be silicon oxide; then a photoresist is coated on the hard mask layer, and through a series of steps such as exposure and development, a patterned photoresist layer is formed, and then an etching process is used to transfer the pattern on the patterned photoresist layer to the hard mask layer, so as to Figure 2 form a patterned mask layer 13 on the top surface of the three-dimensional structure shown. The patterned mask layer 13 has an opening pattern (not shown) for defining the shape, size, and position of the capacitor. Figure 2

[0100] Figure 4 As an example, please continue to refer to Figure 4, in step S62, a dry etching process may be employed to etch and remove, using the patterned mask layer 13 as a mask, the portion of the isolation layer 90 that deviates from the dummy word line 20 in the first direction, thereby obtaining isolation trenches 14. It can be understood that when removing the silicon oxide of the isolation layer filled in the trench formed for the first time, a dry etching process may be combined with the mask layer 13 to only remove the isolation layer between the capacitor regions, with the aim of only exposing the capacitor regions without exposing the transistor regions.

[0101] As an example, please continue to refer to Figure 5 , in step S63, a wet etching process may be employed to remove, via the isolation trenches 14, the portion of the plurality of first sacrificial bars 121 that deviates from the dummy word line 20 in the first direction, thereby obtaining first grooves 15, so as to form the inner electrodes 41 within the first grooves 15. It can be understood that after dry-etching the silicon oxide of the isolation layer, the exposed silicon nitride or silicon oxide N layer is removed by wet etching.

[0102] As an example, please continue to refer to Figures 6 - 8 , forming a capacitor within the first grooves 15 in step S64 includes:

[0103] Step S641: Forming the inner electrodes 41 within the first grooves 15;

[0104] Step S642: Removing the dielectric layer 11 between the inner electrodes, exposing the upper, lower, and side surfaces of the inner electrodes 41;

[0105] Step S643: Forming an intermediate dielectric layer 42 surrounding the upper, lower, and side surfaces of the inner electrodes 41;

[0106] Step S644: Forming outer electrodes 43 filling the region where the dielectric layer 11 is located, the outer electrodes 43 being located between adjacent intermediate dielectric layers 42 in the second direction and the direction perpendicular to the substrate 100; adjacent inner electrodes 41 in the second direction and the direction perpendicular to the substrate 100 are insulated from each other via the intermediate dielectric layer 42. The outer electrodes 43 serve as the common outer electrodes for each memory cell.

[0107] As an example, please continue to refer to Figure 6 , in step S641, a deposition process may be employed to form the inner electrodes 41 of the capacitor within the first grooves 15, adjacent inner electrodes 41 in the oz direction being insulated from each other via the dielectric layer 11, and adjacent inner electrodes 41 in the oy direction being insulated from each other via the isolation trenches 14.

[0108] As an example, please continue to refer to Figure 7 , in step S642, a wet etching process may be employed to remove the dielectric layer 11 between the inner electrodes 41, exposing the upper, lower, and side surfaces of the inner electrodes 41. The material of the inner electrodes 41 may be selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, tantalum nitride, and combinations thereof.

[0109] As an example, please continue to refer to Figure 8 , in step S643, an atomic layer deposition process and / or a plasma vapor deposition process can be used to form the intermediate dielectric layer 42; the material of the intermediate dielectric layer 42 can be a high-k dielectric material (for example, a dielectric material with a dielectric constant greater than or equal to 3.9).

[0110] As an example, please continue to refer to Figure 8 , in step S644, an atomic layer deposition process and / or a plasma vapor deposition process can be used to form the outer electrode 43, and the outer electrode 43 is located between the intermediate dielectric layers 42 adjacent along the second direction and perpendicular to the substrate 100; the inner electrodes 41 adjacent along the second direction and perpendicular to the substrate 100 are insulated by the intermediate dielectric layer 42. The outer electrode 43 is shared by the capacitors 40 adjacent along the second direction and perpendicular to the substrate 100, which can reduce the manufacturing process and cost of the capacitor 40. The materials of the inner electrode 41 and the outer electrode 43 can be the same or different. For example, the materials of the inner electrode 41 and the outer electrode 43 can both be selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, tantalum nitride and their combinations. The inner electrode 41, the intermediate dielectric layer 42 and the outer electrode 43 are used to jointly form the capacitor 40.

[0111] As an example, please refer to Figure 9 , in step S80, removing the isolation layer 90 located between the capacitors adjacent along the first direction includes:

[0112] Step S81: Using a dry etching process to etch the isolation layer 90 between the capacitors adjacent along the first direction in a direction perpendicular to the substrate 100 to obtain an intermediate trench 16, so as to remove the sacrificial layer 12 between the capacitors adjacent along the first direction through the intermediate trench 16.

[0113] As an example, please refer to Figures 10 - 11 , in step S100, replacing the sacrificial layer 12 located between the capacitors adjacent along the first direction with a conductive layer 50 includes:

[0114] Step S101: Using a wet etching process to remove the sacrificial layer 12 between the capacitors adjacent along the first direction to obtain an interlayer groove 17;

[0115] Step S102: Forming a conductive layer 50 in the interlayer groove 17.

[0116] As an example, please continue to refer to Figures 10 - 11, in the process of removing the sacrificial layer 12 between adjacent capacitors along the first direction by using a wet etching process in step S101, the second sacrificial strip 122 is removed to obtain a bit line groove 18; in step S102, a conductive layer 50 can be formed in the interlayer groove 17 by using a deposition process. During the formation of the conductive layer 50, a bit line 501 is formed in the bit line groove 18; adjacent bit lines along the direction perpendicular to the substrate 100 are insulated by the dielectric layer 11. The material of the bit line 501 is selected from copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, tantalum nitride, tantalum nitride, and combinations thereof. The material of the conductive layer 50 is selected from copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, tantalum nitride, tantalum nitride, and combinations thereof.

[0117] As an example, please continue to refer to Figures 10 - 11 , in the process of removing the sacrificial layer 12 between adjacent capacitors along the first direction by using a wet etching process in step S101, the third sacrificial strip 123 is removed to obtain a side groove 19; in step S102, during the formation of the conductive layer 50, a common bit line 60 is formed in the side groove 19, and the common bit line 60 is electrically connected to the bit lines in the same layer; adjacent common bit lines 60 along the direction perpendicular to the substrate 100 are insulated by the dielectric layer 11.

[0118] As an example, please continue to refer to Figure 11 , after the formation of the conductive layer 50, it further includes:

[0119] Step S111: Remove the dummy word line 20 to form a word line hole;

[0120] Step S112: Form a word line extending along the direction perpendicular to the substrate 100 and a channel layer (not shown) located between the word line (not shown), the gate dielectric layer (not shown), and the gate dielectric layer and the conductive layer in the word line hole. The gate dielectric layer circumferentially surrounds the corresponding word line, the channel layer circumferentially surrounds the corresponding gate dielectric layer, and adjacent channel layers along the vertical direction are insulated from each other through the gate dielectric layer.

[0121] As an example, please continue to refer to Figure 11 , after removing the dummy word line 20 in step S111, an initial word line hole is obtained, and then the dielectric layer 11 is etched laterally through the initial word line hole to increase the size of the initial word line hole in the etched dielectric layer 11, so that the size of the initial word line hole in the etched dielectric layer 11 is larger than the size of the initial word line hole in the conductive layer 50, and a word line hole is obtained. This word line hole disconnects the first electrode (one of the source and drain electrodes) and the second electrode (the other of the source and drain electrodes) of the transistor connected during the second replacement of the sacrificial layer.

[0122] Then, a channel layer is formed on the inner surface of the word line hole in the conductive layer 50. Then, a gate dielectric layer covering the channel layer and extending along the oz direction is formed in the word line hole. Then, a word line extending along the oz direction is formed in the word line hole. The channel layers adjacent to each other along the oz direction are insulated from each other via the gate dielectric layer to reduce the parasitic capacitance and leakage current, thereby improving the working efficiency of the transistor and increasing the yield of the vertical oxide channel device. The material of the channel layer can be indium tin oxide, i.e., an ITO (Indium Tin Oxide) thin film. The material of the gate conductive layer is selected from indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, tantalum nitride, tantalum nitride and combinations thereof. The material of the gate dielectric layer can be selected from silicon dioxide (silicon oxide 2), silicon oxynitride (silicon oxide N), silicon nitride, aluminum oxide (Al2O3), aluminum oxynitride (AlON) and combinations thereof. The gate dielectric layer can also be a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), or a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an antiferroelectric material, silicon carbide (SiC) or any combination thereof. The material of the word line is selected from copper, tungsten, aluminum, copper alloy and combinations thereof.

[0123] In the memory and manufacturing method provided by the embodiments of the present application, after the sacrificial layer and the dielectric layer are stacked, the sacrificial layer is replaced with a conductive layer to implement the transistor and capacitor of the memory cell. Among them, the sacrificial layer in the capacitor region is first replaced with a conductive layer, and the sacrificial layer in the transistor region is then replaced with a conductive layer with the conductive layer and the dielectric layer in the capacitor region as a support. In this way, the mechanical stability of forming the capacitor and the transistor by the sacrificial layer and the dielectric layer stacking process can be improved, and the risk of collapse can be avoided.

[0124] In addition, after the inner electrode of the capacitor is formed, the outer electrode is then formed. Then, the sacrificial layer is replaced with the electrode and bit line of the transistor. The outer electrode of the capacitor or the entire capacitor serves as a support frame for forming the electrode and bit line of the transistor, and no additional support frame needs to be fabricated.

[0125] In some embodiments, please continue to refer to Figure 11, provides a memory, including a substrate 100, a word line, a bit line 501 and a memory cell array stacked along a vertical direction perpendicular to the substrate 100; a layer of the memory cell array includes memory cells arranged in rows and columns along a first direction and a second direction; the first direction and the second direction intersect and are both parallel to the substrate 100; memory cells adjacent to each other along the second direction in a layer of the memory cell array share a bit line 501 extending along the second direction; the capacitor of the memory cell is located on the side of the corresponding word line away from the corresponding bit line 501 along the first direction, and the capacitor includes an inner electrode 41, an intermediate dielectric layer 42 surrounding the side surface of the inner electrode 41 in a circumferential direction, and an outer electrode 43 surrounding the side surface of the intermediate dielectric layer 42 in a circumferential direction; the inner electrode 41 is connected to the corresponding bit line 501 via the corresponding conductive layer 50, and a word line penetrates the conductive layer 50 adjacent to each other in the vertical direction in a vertical direction; memory cells adjacent to each other along the second direction and the vertical direction share an outer electrode 43, and the outer electrode 43 extends to the substrate 100 in the vertical direction.

[0126] As an example, please refer to Figure 11 By setting the memory cells adjacent in the vertical direction to share a word line extending in the vertical direction, and setting the memory cells adjacent in the second direction in a layer of memory cell array to share a bit line 501 extending in the second direction, it is convenient to form a capacitor with a common external electrode 43 extending in the second direction and the vertical direction on the side of the word line away from the corresponding bit line 501 along the first direction. The capacitors adjacent in the first direction are used as a support frame. In the case of no additional manufacturing of a support frame, the mechanical support performance of the capacitor support frame for the multiple memory cells stacked in three dimensions is guaranteed, thereby improving the performance and reliability of the manufactured memory.

[0127] As an example, please refer to Figure 11 The inner electrode and the first electrode are formed by patterning different conductive film layers. This is because the first electrode and the inner electrode are formed by replacing the conductive layer twice, and they cannot be formed by the same film layer. Different film layers can also be film layers of the same material or film layers of different materials.

[0128] The first electrode, the second electrode and the bit line are formed by patterning the same conductive film layer. This is because when the sacrificial layer is replaced with the conductive layer for the second time, the sacrificial layer of the transistor area of ​​the two storage cells and the sacrificial layer of the bit line area are etched away at one time, and then the conductive layer is filled. The conductive layer is a whole film layer, and the first and second electrodes as the source and drain are disconnected by patterning. The first electrode contacts the inner electrode of the capacitor, and the second electrode and the bit line are an integrated structure. At this time, if the bit line area is not isolated, the bit line is connected to two columns of storage cells at the same time. If the bit line is patterned, it can be divided into two bit lines, each of which is connected to a column of storage cells.

[0129] The storage unit further includes a channel layer located between the first electrode and the second electrode and surrounding the sidewall of the word line, and the channel layer is insulated from the word line by a gate dielectric layer.

[0130] Exemplarily, one of the bit lines is connected to the second electrodes of each of two adjacent columns of storage units; the two adjacent columns of storage units are symmetrically distributed with respect to the bit line in a mirror image manner;

[0131] The bit lines, the second electrodes, and the first electrodes of the two columns of storage units are formed by replacing a sacrificial layer between two adjacent layers of the dielectric layer once;

[0132] The first electrodes, the second electrodes, and the bit line are formed by patterning the same conductive film layer.

[0133] Exemplarily, the dielectric layer and the outer electrode are formed after forming the inner electrode and before forming the bit line, and the dielectric layer and the outer electrode serve as a support frame.

[0134] Exemplarily, the dielectric layer and the outer electrode cover the inner electrodes of each of the storage units stacked in the area where the storage units connected to the bit line are located; each of the inner electrodes connected to the same bit line has an upper surface, a lower surface, a side surface, and an end surface away from the bit line, and the dielectric layer and the outer electrode only cover the upper surface, the lower surface, and the side surface of each inner electrode;

[0135] The dielectric layer and the outer electrode are formed by replacing the dielectric layer in the capacitor region.

[0136] As an example, please continue to refer to Figure 11 , in a layer of the storage unit array, the storage units adjacent to each other in the first direction share a bit line 501 extending in the second direction, so as to reduce the volume of the storage unit array and reduce the complexity and cost of manufacturing the bit line 501.

[0137] As an example, please continue to refer to Figure 11 , the memory further includes a common bit line 60 located on one side of the storage unit array in the second direction, and the common bit line 60 is electrically connected to the bit lines 501 of the same layer, facilitating leading out all the bit lines 501 of the same layer via the corresponding common bit line 60, so that all the bit lines 501 of each layer can be simultaneously selected via the common bit line 60 of each layer, reducing the complexity of the internal circuit wiring of the memory while reducing the volume of the memory.

[0138] As an example, please continue to refer to Figure 11 , the size of the common bit line 60 in the first direction is larger than the size of the bit line 501 in the first direction, so as to reduce the connection impedance between the common bit line 60 and the bit lines 501 of the same layer.

[0139] As an example, please continue to refer to Figure 11The area of ​​the inner electrode 41 covered by the intermediate dielectric layer 42 is greater than or equal to the area of ​​the inner electrode 41 covered by the outer electrode 43, so that the inner electrodes 41 adjacent to each other along the second direction and the vertical direction are insulated from each other via the intermediate dielectric layer 42.

[0140] As an example, please refer to Figure 11 The intermediate dielectric layer 42 has an opening (not shown), which exposes the target end surface 41a of the inner electrode 41. The target end surface 41a is the end surface of the inner electrode 41 located on the side of the corresponding word line away from the corresponding bit line 501 along the first direction, which facilitates the electrical connection of the target end surface of the inner electrode 41 with the ground line, thereby reducing the volume and manufacturing complexity of the memory while improving the performance and reliability of the memory.

[0141] As an example, please refer to Figure 11 The material of the inner electrode 41 is selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride and combinations thereof.

[0142] As an example, please refer to Figure 11 The material of the conductive layer 50 is selected from copper, tungsten, aluminum, copper alloy and combinations thereof.

[0143] As an example, please refer to Figure 11 The material of the external electrode 43 is selected from doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride and combinations thereof.

[0144] In some embodiments, the present disclosure provides an electronic device, including a memory as described in any one of the embodiments of the present disclosure. The electronic device is, for example but not limited to, a suitable type of electronic product such as a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, etc. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0145] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0146] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0147] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0148] The above embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the disclosed patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A memory, characterized in that, Comprising: A memory cell array stacked on a substrate in a direction perpendicular to the substrate; each layer of the memory cell array includes memory cells arranged in rows and columns in a first direction and a second direction; the first direction is the row direction and the second direction is the column direction; A plurality of word lines extending in a direction perpendicular to the substrate and penetrating through each layer of the memory cell array, each word line being connected to a plurality of memory cells; A plurality of bit lines extending in the second direction, each bit line being connected to at least one column of memory cells in a memory cell array; Each memory cell includes a transistor and a capacitor arranged in sequence in the first direction; the capacitor includes an inner electrode extending in the first direction, a dielectric layer covering the inner electrode in sequence, and an outer electrode; the transistor includes a first electrode connected to the inner electrode and a second electrode connected to the bit line; A dielectric layer is included between any two layers of the memory cell array; Wherein, the inner electrode is formed by replacing a sacrificial layer between two adjacent dielectric layers; the first electrode, the second electrode, and the bit line are formed by replacing a sacrificial layer between two adjacent dielectric layers after forming the inner electrode.

2. The memory according to claim 1, wherein The inner electrode and the first electrode are formed by patterning different conductive layers; The first electrode, the second electrode, and the bit line are formed by patterning the same conductive layer.

3. The memory according to claim 1, wherein The memory cell further includes a channel layer located between the first electrode and the second electrode and surrounding the sidewall of the word line, and the channel layer is insulated from the word line by a gate dielectric layer.

4. The memory according to claim 1, wherein One bit line is connected to the second electrodes of each of two adjacent columns of memory cells; the two adjacent columns of memory cells are symmetrically distributed with respect to the bit line; The bit lines, the second electrodes, and the first electrodes of the two columns of memory cells are formed by replacing a sacrificial layer between two adjacent dielectric layers once; the first electrodes, the second electrodes, and the bit line are formed by patterning the same conductive layer.

5. The memory according to claim 4, wherein, The dielectric layer and the outer electrode are formed after forming the inner electrode and before forming the bit line, and the outer electrode serves as a support frame.

6. The memory according to claim 5, wherein The dielectric layer and the outer electrode cover a column of memory cells and the inner electrodes of each of the memory cells stacked vertically in the column direction; the dielectric layer and the outer electrode are formed by replacing the dielectric layer in the capacitor region.

7. The memory according to claim 1, wherein The dielectric layer is silicon oxide, and the sacrificial layer is silicon nitride or silicon oxynitride.

8. An electronic device, characterized in that, Including the memory according to any one of claims 1-7.

9. A manufacturing method of a memory, characterized in that, Comprising: Providing a substrate, forming a plurality of dielectric layers and a plurality of sacrificial layers on the substrate, the dielectric layers and the sacrificial layers being alternately distributed; Performing a patterning process on the dielectric layers and the sacrificial layers to form a plurality of trenches perpendicular to the substrate; Between the trenches, there are included a plurality of first sacrificial strips corresponding to the memory cells one by one, extending in the first direction and spaced apart in the second direction, and second sacrificial strips intersecting with the plurality of first sacrificial strips; The space between the trenches further includes a dielectric layer stacked with a plurality of first sacrificial bars and the second sacrificial bar of each layer; the first direction is the row direction, the second direction is the column direction, and both the row direction and the column direction are parallel to the substrate; The first sacrificial bar sequentially includes a capacitor region and a transistor region in the first direction, and the transistor region is close to the second sacrificial bar; The capacitor region of the first sacrificial bar is removed by an etching process to expose the dielectric layer adjacent in the vertical direction, and the transistor region of the first sacrificial bar is retained; A conductive layer is filled between the exposed dielectric layers to replace the capacitor region of the first sacrificial bar, forming an inner electrode; After forming the inner electrode, the transistor region of the first sacrificial bar and the second sacrificial bar are removed by an etching process to expose the dielectric layer adjacent in the vertical direction, and a conductive layer is filled between the adjacent dielectric layers to replace the transistor region and the second sacrificial bar, forming a first electrode, a second electrode, and a bit line in contact with the inner electrode.

10. The manufacturing method of the memory according to claim 9, characterized in that, Before forming the inner electrode, the trenches are filled with the same material as the dielectric layer, a word line hole penetrating through each dielectric layer and each sacrificial layer is formed in the transistor region of the first sacrificial bar, and a dummy word line is filled in the word line hole.

11. The manufacturing method of the memory according to claim 9, characterized in that, The plurality of first sacrificial bars and the second sacrificial bar of each layer are of an integral structure; the first electrode and the second electrode are spaced apart from each other; the second electrode and the bit line are of an integral structure.

12. The manufacturing method of the memory according to claim 10, characterized in that, Removing the first sacrificial bar of each capacitor region by an etching process to expose the dielectric layer adjacent in the vertical direction and retaining the first sacrificial bar of the transistor region includes: Removing the dielectric layer between the capacitor regions adjacent in the column direction in the trench region to expose the capacitor region of the first sacrificial bar; removing the capacitor region of the first sacrificial bar between the dielectric layers adjacent in the direction perpendicular to the substrate, and sequentially filling a first conductive layer between the adjacent dielectric layers as the inner electrode.

13. The manufacturing method of the memory according to claim 12, wherein Before fabricating the first electrode, the second electrode, and the bit line after fabricating the inner electrode, it further includes: A dielectric layer and a conductive layer are sequentially deposited on the exposed inner electrode, and the conductive layer is the outer electrode of the capacitor; the outer electrode serves as a support frame.

14. The manufacturing method of the memory according to claim 10, wherein Removing the transistor region of the first sacrificial bar and the second sacrificial bar to expose the adjacent dielectric layer includes: Removing the dielectric layer between the transistor regions adjacent in the trench region by a dry etching process; removing the sacrificial layer between the dielectric layers adjacent in the vertical direction by a wet process to expose the dielectric layer in the regions of the first electrode, the second electrode, and the bit line.

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