Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and electronic equipment. The semiconductor structure comprises at least one storage unit located on a substrate, and the storage unit comprises a write transistor and a read transistor which are distributed on the substrate at an interval; the read transistor comprises a back gate extending along a first direction, a main gate extending along a direction vertical to the substrate, and a first semiconductor layer surrounding the back gate and the main gate; wherein the first semiconductor layer comprises a first part surrounding the main gate and a second part surrounding the back gate, and the first semiconductor layer is insulated from the main gate and the back gate; the write transistor comprises a grid electrode extending in the direction perpendicular to the substrate and a second semiconductor layer surrounding the grid electrode; wherein the back gate of the read transistor is connected with the second semiconductor layer; and the back gate is positioned between the main gate and the gate of the write transistor. The invention provides a novel semiconductor structure, and the manufacturing difficulty of a storage unit is reduced.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, making any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, it is desired to make as many device units as possible on a limited substrate. Since Moore's Law came out, the industry has proposed various semiconductor structure designs and process optimizations to meet the needs of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this article. This overview is not intended to limit the protection scope of this application.

[0005] In one aspect, an exemplary embodiment of the present application provides a semiconductor structure, including:

[0006] At least one memory cell located on a substrate, the memory cell including a write transistor and a read transistor spaced apart on the substrate;

[0007] The read transistor includes a back gate extending along a first direction, a main gate extending along a direction perpendicular to the substrate, and a first semiconductor layer surrounding the back gate and the main gate; wherein, the first semiconductor layer includes a first portion surrounding the main gate and a second portion surrounding the back gate, and the first semiconductor layer is insulated from the main gate and the back gate;

[0008] The write transistor includes a gate extending along a direction perpendicular to the substrate, and a second semiconductor layer surrounding the gate and insulated from the gate;

[0009] Wherein the back gate of the read transistor is connected to the second semiconductor layer; the back gate is located between the main gate and the gate of the write transistor.

[0010] In some embodiments, it further includes a reference signal line extending along a direction perpendicular to the substrate, and a read bit line extending along a second direction parallel to the substrate, the reference signal line is connected to the first portion of the first semiconductor layer, the read bit line is connected to the second portion of the first semiconductor layer, the reference signal line and the read bit line are spaced apart from each other, and the first direction and the second direction intersect.

[0011] In some embodiments, the read bit line is further connected to the second portion of the first semiconductor layer.

[0012] In some embodiments, the first part and the second part of the first semiconductor layer are sequentially distributed in the second direction. The first part includes an annular part extending towards the substrate, and the second part includes an annular part extending towards the second semiconductor layer of the read bit line and the write transistor and an end in contact with the read bit line. The annular parts of the first part and the second part are in contact with each other.

[0013] In some embodiments, the read transistor further includes a barrier layer. The second part of the first semiconductor layer extends towards the second semiconductor layer of the write transistor and is insulated from the second semiconductor layer through the barrier layer.

[0014] In some embodiments, the write transistor and the second part of the first semiconductor layer are sequentially distributed in the first direction;

[0015] The second semiconductor layer is an annular shape extending towards the substrate; further included is a write bit line extending in the second direction, and the write bit line is connected to the outer sidewall of the second semiconductor layer;

[0016] The end of the back gate is connected to the outer sidewall of the second semiconductor layer; the write bit line and the back gate are spaced apart and distributed on the outer sidewall of the second semiconductor layer.

[0017] In some embodiments, it includes multiple layers of periodically distributed memory cells stacked in the direction perpendicular to the substrate; each layer of memory cells contains a memory cell array distributed in an array in the first direction and the second direction;

[0018] The read bit line is connected to the first semiconductor layer of a column of memory cells;

[0019] The reference signal line is connected to the first semiconductor layers of the memory cells stacked at the same position in the vertical direction;

[0020] Further included is a read word line, which extends vertically through the read transistors stacked at the same position. The first parts of the first semiconductor layers of the respective read transistors surround different regions of the read word line, and the main gate is a part of the read word line;

[0021] Further included is a write word line, which extends vertically through the write transistors stacked at the same position. The second semiconductor layers of the respective write transistors surround different regions of the write word line, and the gate of the write transistor is a part of the write word line.

[0022] In some embodiments, a dielectric layer surrounds the sidewall of the reference signal line. The dielectric layer contacts a second portion of the first semiconductor layer. The region of the dielectric layer facing the first semiconductor layer includes an opening, and the reference signal line contacts a first portion of the first semiconductor layer through the opening.

[0023] In some embodiments, the back gates of the read transistors stacked in different layers are insulated from each other by an insulating layer, and the back gates are formed by replacing a sacrificial layer between adjacent insulating layers.

[0024] In some embodiments, the first portions of the first semiconductor layers of the read transistors stacked in different layers surround the same read word line and are spaced apart from each other in the vertical direction; the second semiconductor layers of the write transistors stacked in different layers surround the same write word line and are spaced apart from each other in the vertical direction.

[0025] In some embodiments, the first semiconductor layer and the second semiconductor layer are metal oxide semiconductor layers.

[0026] An embodiment of the present application provides a manufacturing method of a semiconductor structure, including the following steps:

[0027] Provide a substrate;

[0028] Deposit an insulating layer and a sacrificial layer alternately in a direction perpendicular to the substrate on the substrate to form a stacked structure including a plurality of insulating layers and sacrificial layers;

[0029] Pattern the stacked structure to form a plurality of isolation layers arranged at intervals along a second direction parallel to the substrate and arranged at intervals along a first direction parallel to the substrate in the stacked structure, where the first direction intersects the second direction and both are perpendicular to the substrate;

[0030] Form a reference signal line hole in the region between the isolation layers adjacent to each other in the second direction and in the isolation layer, and sequentially fill a dielectric layer and a reference signal line in the reference signal line hole;

[0031] Form a read word line hole exposing the reference signal line on one side of the reference signal line along the first direction, and sequentially deposit a first portion of the first semiconductor layer, a gate insulating layer, and a read word line in the read word line hole;

[0032] Form a first bit line trench penetrating the stacked structure and extending along the second direction between the isolation layers adjacent to each other in the first direction, and form a read bit line extending along the second direction and connected to the first portion of the first semiconductor layer in the first bit line trench;

[0033] On a side of the read word line away from the read bit line, and between adjacent isolation layers in the first direction, a second bit line trench is formed that penetrates the stacked structure and extends along the second direction; the side walls of the second bit line trench expose the stacked insulating layers and the sacrificial layer, and each layer of the sacrificial layer in the region between two adjacent memory cells in the column direction is etched back until the first semiconductor layer and the read bit line of the corresponding memory cell are exposed, forming a first lateral groove extending in the first direction; in the first lateral groove, a second portion of the first semiconductor layer, a gate insulating layer, and a back gate are sequentially deposited.

[0034] The second bit line trench is used to etch back the first semiconductor layer, the gate insulating layer, and the back gate in the first lateral groove and fill it with a sacrificial layer.

[0035] A write word line hole is formed in the region filled with the sacrificial layer to penetrate the stacked structure and expose the back gate, and a second semiconductor layer connected to the back gate, a gate insulating layer, and a write word line are sequentially deposited in the write word line hole.

[0036] In the second bit line trench, a plurality of write bit lines extending in the second direction are formed, and each write bit line is connected to the second semiconductor layer of the corresponding layer of memory cells.

[0037] In some embodiments, forming a read bit line extending along the second direction and connected to the first portion of the first semiconductor layer in the first bit line trench includes:

[0038] For the insulating layer and the sacrificial layer exposed in the first bit line trench, the sacrificial layer is etched back along a direction parallel to the substrate to form a first bit line lateral groove at the sacrificial layer.

[0039] The first bit line trench and the first bit line lateral groove are filled with a conductive material.

[0040] The conductive material in the first bit line trench is removed, and the conductive material in the first bit line lateral groove is retained to form a plurality of mutually isolated read bit lines extending along the second direction.

[0041] In another aspect, some embodiments of the present application provide an electronic device including the semiconductor structure described in any one of the above.

[0042] The present application provides a new semiconductor structure, which reduces the difficulty of fabricating memory cells.

[0043] Other features and advantages of the present application will be described in the subsequent specification, and part of them will be obvious from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. Description of the Drawings

[0044] The accompanying drawings are used to provide an understanding of the technical solutions of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application and do not constitute a limitation to the technical solutions of the present application.

[0045] Figure 1A A three-dimensional structure schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application;

[0046] Figure 1B A horizontal cross-sectional schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0047] Figure 1C For Figure 1B A cross-sectional schematic diagram perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0048] Figure 1D For Figure 1B A cross-sectional schematic diagram perpendicular to the substrate, taken along the section line BB' in the structure shown;

[0049] Figure 2 An equivalent circuit schematic diagram of a semiconductor structure provided for an exemplary embodiment of the present application;

[0050] Figure 3A A horizontal cross-sectional schematic diagram of a stacked structure formed in the initial step of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0051] Figure 3B For Figure 3A A cross-sectional schematic diagram perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0052] Figure 3C For Figure 3A A cross-sectional schematic diagram perpendicular to the substrate, taken along the section line BB' in the structure shown;

[0053] Figure 4A A horizontal cross-sectional schematic diagram of an intermediate product formed in an intermediate step of a manufacturing method of a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0054] Figure 4B For Figure 4A A cross-sectional schematic diagram perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0055] Figure 5ASchematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0056] Figure 5B For the cross-section along Figure 5A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0057] Figure 6A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0058] Figure 6B For the cross-section along Figure 6A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0059] Figure 7A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0060] Figure 7B For the cross-section along Figure 7A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0061] Figure 8A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0062] Figure 8B For the cross-section along Figure 8A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0063] Figure 8C For the cross-section along Figure 8A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line BB' in the structure shown;

[0064] Figure 9A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0065] Figure 9B For the cross-section along Figure 9A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0066] Figure 9C For the cross-section along Figure 9ASchematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0067] Figure 10A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0068] Figure 10B Along Figure 10A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0069] Figure 10C Along Figure 10A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0070] Figure 11A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0071] Figure 11B Along Figure 11A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0072] Figure 11C Along Figure 11A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0073] Figure 12A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0074] Figure 12B Along Figure 12A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0075] Figure 12C Along Figure 12A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0076] Figure 13A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0077] Figure 13B Along Figure 13A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0078] Figure 13C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Figure 13A as shown in

[0079] Figure 14A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0080] Figure 14B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Figure 14A as shown in

[0081] Figure 14C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Figure 14A as shown in

[0082] Figure 15A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0083] Figure 15B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Figure 15A as shown in

[0084] Figure 15C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Figure 15A as shown in

[0085] Figure 16A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0086] Figure 16B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Figure 16A as shown in

[0087] Figure 17A A schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0088] Figure 17B A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown; Figure 17A as shown in

[0089] Figure 17C is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown; Figure 17A

[0090] Figure 18A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0091] Figure 18B is along Figure 18A is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0092] Figure 18C is along Figure 18A is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0093] Figure 19A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0094] Figure 19B is along Figure 19A is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0095] Figure 19C is along Figure 19A is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0096] Figure 20A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0097] Figure 20B is along Figure 20A is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' in the structure shown;

[0098] Figure 20C is along Figure 20A is a schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line BB' in the structure shown;

[0099] Figure 21A is a schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0100] Figure 21B is along Figure 21A ​Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0101] Figure 21C For along Figure 21A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0102] Figure 22A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a memory provided by an exemplary embodiment of the present application;

[0103] Figure 22B For the formed intermediate product is along Figure 22A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0104] Figure 22C For along Figure 22A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line BB' in the shown structure;

[0105] Figure 23A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0106] Figure 23B For along Figure 23A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0107] Figure 24A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0108] Figure 24B For along Figure 24A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0109] Figure 25A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0110] Figure 25B For along Figure 25A Schematic cross-sectional view perpendicular to the substrate taken along the cross-section line AA' in the shown structure;

[0111] Figure 26ASchematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0112] Figure 26B For the cross-section along Figure 26A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0113] Figure 26C For the cross-section along Figure 26A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line BB' in the structure shown;

[0114] Figure 27A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0115] Figure 27B For the cross-section along Figure 27A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0116] Figure 27C For the cross-section along Figure 27A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line BB' in the structure shown;

[0117] Figure 28A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0118] Figure 28B For the cross-section along Figure 28A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0119] Figure 28C For the cross-section along Figure 28A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line BB' in the structure shown;

[0120] Figure 29A Schematic horizontal cross-sectional view of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to the substrate;

[0121] Figure 29B For the cross-section along Figure 29A Schematic vertical cross-sectional view perpendicular to the substrate, taken along the section line AA' in the structure shown;

[0122] Figure 29C For the cross-section along Figure 29ASchematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0123] Figure 30A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0124] Figure 30B For along Figure 30A Schematic cross-sectional view perpendicular to the substrate taken along the section line AA' in the structure shown;

[0125] Figure 30C For along Figure 30A Schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0126] Figure 31A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0127] Figure 31B For along Figure 31A Schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0128] Figure 32A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0129] Figure 32B For along Figure 32A Schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0130] Figure 33A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0131] Figure 33B For along Figure 33A Schematic cross-sectional view perpendicular to the substrate taken along the section line BB' in the structure shown;

[0132] Figure 34A Schematic horizontal cross-sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0133] Figure 34B For along Figure 34ASchematic cross - sectional view perpendicular to the substrate taken along the cross - sectional line BB' in the shown structure;

[0134] Figure 35A Schematic horizontal cross - sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0135] Figure 35B Along Figure 35A Schematic cross - sectional view perpendicular to the substrate taken along the cross - sectional line AA' in the shown structure;

[0136] Figure 35C Along Figure 35A Schematic cross - sectional view perpendicular to the substrate taken along the cross - sectional line BB' in the shown structure;

[0137] Figure 36A Schematic horizontal cross - sectional view taken along a plane parallel to the substrate of an intermediate product formed in an intermediate step of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;

[0138] Figure 36B Along Figure 36A Schematic cross - sectional view perpendicular to the substrate taken along the cross - sectional line AA' in the shown structure; and

[0139] Figure 36C Along Figure 36A Schematic cross - sectional view perpendicular to the substrate taken along the cross - sectional line BB' in the shown structure. Detailed implementation manners

[0140] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily.

[0141] The embodiments herein can be implemented in many different forms. Those of ordinary skill in the art can easily understand the fact that the implementation manners and contents can be transformed into various forms without departing from the spirit and scope of the present application. Therefore, the present application should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily.

[0142] The size and proportional relationships between various film layers or components in the accompanying drawings of this application can be used as a reference in actual processes, which are implementation manners with good technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The accompanying drawings described in this application are only schematic structural diagrams, and one implementation manner of this application is not limited to the shapes, values, etc. shown in the accompanying drawings.

[0143] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The positional relationships of the constituent elements are appropriately changed according to the directions describing each constituent element. Therefore, it is not limited to the terms described in the specification, and can be appropriately replaced according to the circumstances.

[0144] In this specification, unless otherwise clearly specified and limited, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0145] In the description of this application, ordinal numbers such as "first" and "second" are set to avoid confusion of the constituent elements, rather than to limit in terms of quantity.

[0146] As used in the embodiments of this disclosure, the term "first direction" X is defined as the direction parallel to the back gate extension direction; the term "second direction" Y is defined as intersecting with the "first direction" X, for example, the first direction and the second direction are perpendicular; the term "third direction" Z is defined as perpendicular to the substrate.

[0147] The embodiments of this application provide a structural schematic diagram of a 2T memory cell, and also provide an array of multiple vertically stacked 2T memory cells. The structural design of a 2T memory cell will be introduced first below. The 2T memory cell described in this application corresponds to Figure 2 the logic circuit shown.

[0148] In Figure 2Among them, the storage unit includes a read transistor and a write transistor. The read transistor has a double-gate structure, including a back gate and a read word line connected to the main gate. The back gate serves as the storage node SN and is connected to the write transistor. The channels of the read transistor are respectively connected to the read bit line RBL and the reference signal line (e.g., the ground terminal GND). The channels of the write transistor are respectively connected to the storage node SN and the write bit line WBL, and the write word line WWL is connected to the gate of the write transistor.

[0149] Such as Figures 1A - 1D As shown is a 3D stacked storage unit. The semiconductor structure includes at least one of the above-mentioned 2T storage units located on the substrate. The storage unit includes a write transistor and a read transistor spaced apart on the substrate.

[0150] See Figures 1A - 1D Referring to, the read transistor includes a back gate 150 extending along a first direction, a main gate 120 extending along a direction perpendicular to the substrate, and a first semiconductor layer surrounding the back gate 150 and the main gate 120. Among them, the first semiconductor layer includes a first portion 121 surrounding the main gate 120 and a second portion 130 surrounding the back gate 150. The first semiconductor layer is insulated from the main gate 120 and the back gate 150.

[0151] The write transistor includes a gate 250 extending along a direction perpendicular to the substrate and a second semiconductor layer 230 surrounding the gate 250 and insulated from the gate 250.

[0152] Among them, the back gate 150 of the read transistor is connected to the second semiconductor layer 230. The back gate 150 is located between the main gate 120 and the gate 250 of the write transistor.

[0153] In some embodiments, it further includes: a reference signal line 350 extending along a direction perpendicular to the substrate, and a first bit line 160 (read bit line) extending along a second direction parallel to the substrate. The reference signal line 350 is connected to the first portion 121 of the first semiconductor layer, and the read bit line 160 is connected to the second portion 130 of the first semiconductor layer. The reference signal line 350 and the first bit line 160 are spaced apart from each other, and the first direction and the second direction intersect.

[0154] In some embodiments, the reference signal line 350 is further connected to the second portion 130 of the first semiconductor layer.

[0155] The first semiconductor layer is respectively connected to a first source / drain 110 and a second source / drain. The second source / drain is a part of the reference signal line 350, and the first source / drain 110 is a part of the first bit line 160.

[0156] The writing transistor includes a third source / drain 210 and a fourth source / drain 220 connected to the second semiconductor layer 230.

[0157] In some embodiments, a first portion 121 and a second portion 130 of the first semiconductor layer are sequentially distributed in the second direction (e.g., column direction). The first portion 121 includes an annular portion extending toward the substrate. The second portion 130 includes an annular portion extending toward the first bit line 160 (read bit line) and the second semiconductor layer 230 of the writing transistor, and an end portion in contact with the read bit line. The annular portions of the first portion and the second portion are in contact with each other.

[0158] It can be understood that the first portion 121 at least includes an annular structure extending in the vertical direction. The second portion 130 at least includes an annular structure extending in the horizontal direction. When approaching the first bit line, there is a bottom as the above-mentioned end portion. The bottom and the annular structure form a cylindrical structure.

[0159] In the present application, surrounding can be understood as partial or complete surrounding. In some embodiments, the first portion 121 of the first semiconductor layer completely surrounds the main gate 120, the second portion 130 of the first semiconductor layer completely surrounds the back gate 150, and the second semiconductor layer 230 completely surrounds the gate 250.

[0160] In some embodiments, the surrounding can be a complete surrounding as a whole. The cross-section of the surrounded channel layer can be a closed ring, and the shape of the ring is adapted to the outer contour shape of the cross-section of the back gate 150 or the gate 250. Exemplarily, the cross-section of the back gate 150 or the gate 250 is, for example, a square, circular or elliptical structure, etc. The cross-section is intercepted along a direction perpendicular to the substrate. In an exemplary embodiment, the surrounding can be partial surrounding, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0161] From Figure 1D it can be known that the back gate 150 and the third source / drain 210 can be an integral structure. In the present application, by connecting the back gate of the read transistor to the third source / drain of the writing transistor or to the second semiconductor layer of the writing transistor, a memory of a capacitorless 2T memory cell is obtained.

[0162] As Figures 1A - 1D shown, the first bit line 160 is electrically connected to the second portion 130 and the first portion 121 of the first semiconductor layer in the first direction X. The main gate 120 is electrically connected to the second portion 130 of the first semiconductor layer in a second direction Y parallel to the substrate. The reference signal line 350 is electrically connected to the second portion 130 of the first semiconductor layer in the second direction Y. It can be understood that, referring to Figure 1D, the writing transistor and the second portion 130 of the first semiconductor layer are sequentially distributed in the first direction;

[0163] The second semiconductor layer 230 is annular and extends in the direction towards the substrate; it further includes a second bit line 260 (writing bit line) extending in the second direction, and the second bit line 260 is connected to the outer sidewall of the second semiconductor layer 230;

[0164] The end of the back gate 150 is connected to the outer sidewall of the second semiconductor layer 230; the second bit line 260 and the back gate 150 are spaced apart on the outer sidewall of the second semiconductor layer 230.

[0165] The back gate 150 includes two ends, one facing the first bit line 160 and the other facing the second semiconductor layer 230, and the end of the back gate 150 facing the second semiconductor layer 230 is connected to the outer sidewall of the second semiconductor layer 230.

[0166] The first portion 121 of the first semiconductor layer surrounds the main gate 120, and the first portion 121 of the first semiconductor layer contacts the reference signal line 350 in the first direction X.

[0167] As Figure 1D shown, the read transistor may further include a back gate insulating layer 140 surrounding the back gate 150 and located between the back gate 150 and the second portion 130 of the first semiconductor layer; it may further include a barrier layer 151, and the barrier layer is located on the circumferential sidewall of the end of the back gate close to the gate and between the second portion 130 of the first semiconductor layer and the second semiconductor layer 230. Due to the setting of the barrier layer 151, the second portion 130 of the first semiconductor layer does not contact the second semiconductor layer 230, and the side of the back gate 150 close to the gate 250 contacts the side of the second semiconductor layer 230 close to the back gate 150 in the first direction X.

[0168] The barrier layer 151 may be an insulating layer, and the insulating layer may be an insulating layer deposited alternately with a sacrificial layer in a direction perpendicular to the substrate on the substrate, or a film layer of the same material as the insulating layer, for example, a silicon oxide film layer. In a specific process, the second portion of the first semiconductor layer can be etched back so that a certain distance is maintained between the second portion of the first semiconductor layer and the second semiconductor layer, and the etched-back area is filled with an insulating layer, and the filled insulating layer is the barrier layer; or it can be understood that any insulating layer or dielectric layer between the second portion of the first semiconductor layer and the second semiconductor layer is the barrier layer.

[0169] In an exemplary embodiment, the barrier layer includes a material different from that of the back gate insulating layer, for example, it can be silicon oxide.

[0170] As Figure 1D shown, the write transistor further includes a gate insulating layer 240 surrounding the gate 250 and located between the gate 250 and the second semiconductor layer 230.

[0171] The above storage cell focuses on the situation of one storage cell. The following will focus on the 3D memory structure.

[0172] In an exemplary embodiment, the semiconductor structure includes: a plurality of periodically distributed storage cells stacked in the vertical substrate direction; each layer of the storage cells includes a storage cell array distributed in an array in the first direction and the second direction;

[0173] As Figures 1A - 1D shown, the first bit line 160 is connected to the first semiconductor layer of a column of storage cells;

[0174] The reference signal line 350 is connected to the first semiconductor layers of the storage cells stacked at the same position in the vertical direction;

[0175] It further includes a first word line 170 (read word line) extending vertically through the read transistors stacked at the same position. The first part of the first semiconductor layer of each read transistor surrounds different regions of the read word line, and the main gate is a part of the read word line;

[0176] It further includes a second word line 270 (write word line) extending vertically through the write transistors stacked at the same position. The second semiconductor layer of each write transistor surrounds different regions of the second word line 270, and the gate 250 of the write transistor is a part of the second word line 270.

[0177] The first parts of the first semiconductor layers of the read transistors stacked in different layers surround the same read word line and are spaced apart from each other in the vertical direction; the second semiconductor layers of the write transistors stacked in different layers surround the same write word line and are spaced apart from each other in the vertical direction.

[0178] In some embodiments, the first semiconductor layer and the second semiconductor layer are metal oxide semiconductor layers. Such as semiconductor materials selected from IGZO, ITO, IZO, IGO, etc.

[0179] In an exemplary embodiment, the first source / drain electrodes 110 of a plurality of read transistors arranged at intervals along the second direction Y can be commonly connected to a first bit line 160 extending along the second direction Y; the fourth source / drain electrodes 220 of a plurality of write transistors arranged at intervals along the second direction Y can be commonly connected to a second bit line 260 extending along the second direction Y.

[0180] In an exemplary embodiment, the main gates 120 of a plurality of read transistors arranged at intervals along the third direction Z are commonly connected to a first word line 170. In some embodiments, each main gate 120 is a part of the first word line 170. The gates 250 of a plurality of write transistors arranged at intervals along the third direction Z are commonly connected to a second word line 270. In some embodiments, each gate 250 is a part of the second word line 270.

[0181] Continue to refer to Figure 1B and Figure 1D The write transistor may further include a gate protection layer 40 which can surround the sidewalls of the second word line 270 and is discontinuously arranged in the third direction Z. The gate protection layer 40 can be used to protect the gate insulating layer and the gate from being etched away when the protection layer is etched away in subsequent steps.

[0182] It can be seen from Figure 1D that the back gates of the read transistors stacked in different layers are insulated by an insulating layer. The second parts 130 of the first semiconductor layers of the read transistors stacked in different layers are arranged at intervals in the third direction Z and are insulated by an insulating layer. Both the back gate and the second part 130 of the first semiconductor layer are formed by replacing the sacrificial layer between adjacent insulating layers.

[0183] In an exemplary embodiment, a method for manufacturing a semiconductor structure may include the following steps:

[0184] Deposit insulating layers and sacrificial layers alternately in a direction perpendicular to the substrate on the substrate to form a stacked structure including a plurality of insulating layers and sacrificial layers;

[0185] Pattern the stacked structure to form a plurality of isolation layers arranged at intervals along a second direction parallel to the substrate and arranged at intervals along a first direction parallel to the substrate in the stacked structure. The first direction intersects with the second direction and both are perpendicular to the substrate;

[0186] Form reference signal line holes in the regions between adjacent isolation layers in the second direction and within the isolation layers, and sequentially fill a dielectric layer and a reference signal line in the reference signal line holes;

[0187] Form read word line holes exposing the reference signal line on one side of the reference signal line along the first direction, and sequentially deposit a first part of the first semiconductor layer, a gate insulating layer, and a read word line in the read word line holes;

[0188] A first bit line trench that penetrates the stacked structure and extends along the second direction is formed between the isolation layers adjacent in the first direction, and a read bit line that extends along the second direction and is connected to a first portion of the first semiconductor layer is formed in the first bit line trench;

[0189] A second bit line trench that penetrates the stacked structure and extends along the second direction is formed on a side of the read word line away from the read bit line and between the isolation layers adjacent in the first direction; the side walls of the second bit line trench expose the stacked insulating layer and the sacrificial layer, and each layer of the sacrificial layer in the region between two adjacent memory cells in the column direction is etched back until the first semiconductor layer and the read bit line of the corresponding memory cell are exposed, forming a first lateral groove that extends in the first direction; a second portion of the first semiconductor layer, a gate insulating layer, and a back gate are sequentially deposited in the first lateral groove;

[0190] The second bit line trench is used to etch back the first semiconductor layer, the gate insulating layer, and the back gate in the first lateral groove and fill the sacrificial layer;

[0191] A write line hole that penetrates the stacked structure is formed in the region filled with the sacrificial layer to expose the back gate, and a second semiconductor layer, a gate insulating layer, and a write line that are connected to the back gate are sequentially deposited in the write line hole;

[0192] A plurality of write bit lines that extend in the second direction are formed in the second bit line trench, and each write bit line is connected to the second semiconductor layer of the corresponding layer of memory cells.

[0193] In some embodiments, forming a read bit line that extends along the second direction and is connected to a first portion of the first semiconductor layer in the first bit line trench includes:

[0194] For the insulating layer and the sacrificial layer exposed in the first bit line trench, the sacrificial layer is etched back along a direction parallel to the substrate to form a first bit line lateral groove at the sacrificial layer;

[0195] The first bit line trench and the first bit line lateral groove are filled with a conductive material;

[0196] The conductive material in the first bit line trench is removed, and the conductive material in the first bit line lateral groove is retained to form a plurality of mutually isolated read bit lines that extend along the second direction.

[0197] The above steps are specifically described as follows:

[0198] S101: Form a stacked structure.

[0199] Exemplary steps may include: providing a substrate (not shown), alternately depositing thin films of insulating material and sacrificial layer on the substrate along a third direction Z to form a stacked structure including an insulating layer 10 and a sacrificial layer 20, as shown in Figure 3A , 3B and as shown in 3C.

[0200] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0201] In an exemplary embodiment, the insulating layer 10 may be independently selected from any one or more of silicon oxide (such as SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), and SiGe. In an exemplary embodiment, the insulating layer 10 may be silicon dioxide. In an exemplary embodiment, the sacrificial layer 20 may be silicon nitride (SiN).

[0202] Figure 3B and 3C The stacked structure 1 shown in may include 4 insulating layers 10 and 3 sacrificial layers 20. In other exemplary embodiments, the stacked structure may further include more or fewer alternately arranged insulating layers 10 and sacrificial layers 20.

[0203] S102: Pattern the stacked structure.

[0204] Exemplary steps may include: etching (such as dry etching) the stacked structure to form a preset pattern, and the preset pattern may include a plurality of isolation grooves (not shown) penetrating through the stacked structure 1; filling an insulating material into each isolation groove to form an isolation layer 11.

[0205] Referring to Figure 4A it can be seen that the preset pattern may include 1 column of 3 isolation layers 11 arranged at intervals along the second direction Y, and a total of 3 columns of isolation layers 11 are shown. The distance between two adjacent isolation layers 11 in the second direction Y is W; 1 row of 3 isolation layers 11 arranged at intervals along the first direction X, and a total of 3 rows of isolation layers are shown. Figure 4AIt is also shown that one column of isolation layers 11 in the middle can be set as the word line region 100 (i.e., each column includes three isolation layers), which is used to form the first word line (i.e., read word line RWL) of the read transistor and the second word line (i.e., write word line WWL) of the write transistor subsequently; the region between one column of isolation layers 11 on the opposite side of the middle one column of isolation layers 11 along the first direction X can be set as the write bit line region 200, which is used to form the second bit line (i.e., write bit line WBL) of the write transistor subsequently; the region between one column of isolation layers 11 on one side of the middle one column of isolation layers 11 along the first direction X can be set as the read bit line region 300, which is used to form the first bit line (i.e., read bit line RBL) of the read transistor. That is to say, the preset pattern can include the word line region 100, the write bit line region 200 located on the opposite side of the word line region 100 along the first direction X, and the read bit line region 300 located on one side of the word line region 100 along the first direction X.

[0206] In an exemplary embodiment, the insulating layer 10 and the isolation layer 11 can be made of the same or different insulating materials. Figure 4B It is shown that the insulating layer 10 and the isolation layer 11 are made of the same material, such as silicon dioxide.

[0207] S103: Form a reference signal line hole.

[0208] Exemplary steps may include: in the word line region 100, dry-etching the stacked structure to form a reference signal line hole P, as Figure 5A and 5B shown.

[0209] S104: Form a reference signal line.

[0210] Exemplary steps may include: sequentially depositing a high-k material and a conductive material along the inner wall of the reference signal line hole P, and filling the reference signal line hole with the conductive material to form a dielectric layer 340 and a reference signal line 350, as Figure 6A and 6B shown.

[0211] In an exemplary embodiment, the dielectric layer 340 can be made of a high-k material, that is, a material with K≥3.9. The dielectric 340 can be any one or more of silicon dioxide, aluminum oxide (Al2O3), hafnium oxide.

[0212] In an exemplary embodiment, the material of the reference signal line 350 can be tungsten W, molybdenum, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride, etc.

[0213] S105: Form the first word line of the read transistor.

[0214] Exemplary steps may include: forming a first word line hole K1 of the read transistor on a side of the main gate close to the read bit line region and contacting the main gate; sequentially depositing a semiconductor material, a high-k dielectric material, and a conductive material along the inner wall of the first word line hole K1, filling the first word line hole K1 with the conductive material, and planarizing the surface of the stacked structure to form the main gate 120, the main gate insulating layer 122, and the first part 121 of the first semiconductor layer of the read transistor, as Figure 7A and 7B shown.

[0215] In an exemplary embodiment, the conductive material may be filled into the first word line hole K1 by atomic layer deposition (ALD). The conductive material includes but is not limited to W, ITO, etc.

[0216] In an exemplary embodiment, the planarization process may be performed by chemical mechanical polishing (CMP).

[0217] S106: Form a first bit line trench and a first bit line lateral slot.

[0218] Exemplary steps may include: within the range of the read bit line region 300, etching the stacked structure 1 to form a first bit line trench T1 of the read transistor that penetrates the stacked structure 1 and extends along the second direction Y, exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20; laterally etching (such as wet etching) each sacrificial layer 20 along the direction parallel to the substrate with the aid of the first bit line trench T1 until reaching the position of the first part of the first semiconductor layer on both sides of the first bit line trench T1 along the first direction X, continuing to etch and remove the semiconductor layer at the sacrificial layer 20 until reaching the position of the first part 121 of the first semiconductor layer and stopping etching, forming a first bit line lateral slot R1 that extends along the second direction Y and has a length L in the first direction X, exposing the sidewalls of each isolation layer 11, exposing the upper and lower surfaces of each insulating layer, and exposing the sidewalls of the sacrificial layer; along the third direction Z, forming the first part 121 of the first semiconductor layer at the position of the remaining semiconductor layer, that is, along the third direction, the first part 121 of the first semiconductor layer is discontinuously arranged, as Figure 8A , Figure 8B and Figure 8C shown.

[0219] S107: Fill the first bit line lateral slot.

[0220] Exemplary steps may include: sequentially depositing a semiconductor material and a conductive material along the inner walls of the first bit line lateral slot R1 and the first bit line trench T1, filling the first bit line lateral slot R1 with the conductive material, and partially filling the first bit line trench T1, as Figure 9A ,Figure 9B and Figure 9C as shown

[0221] In an exemplary embodiment, an Atomic Layer Deposition (ALD) method may be used to fill the first bit line trench T1 and the first bit line lateral groove R1 with a conductive material, which may include but is not limited to W, ITO, etc.

[0222] S108: Form the first bit line of the read transistor.

[0223] Exemplary steps may include: etching away all the conductive material in the first bit line trench T1, leaving only the conductive material in the first bit line lateral groove R1, thereby forming the first bit line of the read transistor at each first bit line lateral groove R1, such that the formed first bit line is disconnected in the third direction Z; depositing and planarizing an insulating layer material in the first bit line trench T1, as Figure 10A , 10B and as shown in 10C.

[0224] S109: Form the second bit line trench (write bit line trench).

[0225] Exemplary steps may include: within the range of the write bit line region 200, etching the stack structure 1 to form the second bit line trench T2 of the write transistor that penetrates the stack structure 1 and extends along the second direction Y, exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20, as Figure 11A , 11B and as shown in 11C.

[0226] S110: Form the second bit line lateral groove and the first lateral groove.

[0227] Exemplary steps may include: by means of the second bit line trench T2, laterally etching (such as wet etching) each sacrificial layer 20 along a direction parallel to the substrate. At the position of the cross-sectional line AA', the lateral etching terminates at the position of the isolation layer 11 on both sides of the second bit line trench T2 along the first direction X, forming the second bit line lateral groove R2, exposing the sidewalls of the isolation layer 11; at the position of the cross-sectional line BB', that is, at the middle position between two adjacent isolation layers 11 along the second direction Y, the lateral etching terminates at the first bit line 160 of the read transistor, that is, the region where the read word line and the read bit line of the read transistor are connected, forming the first lateral groove S1, exposing the upper and lower surfaces of the insulating layer 10, exposing the sidewall of the first bit line 160 close to the second bit line trench T2, and the size of the first lateral groove S1 along the first direction X is larger than the size of the second bit line lateral groove R2 along the first direction X, as Figure 12A , 12B and as shown in 12C.

[0228] S111: Fill the second bit line trench, the second bit line lateral trench, and the first lateral groove.

[0229] Exemplary steps may include: depositing a semiconductor material and an insulating material covering the semiconductor material along the inner walls of the second bit line trench T2, the second bit line lateral trench R2, and the first lateral groove S1; filling the second bit line trench T2, the second bit line lateral trench R2, and the first lateral groove S1 with a conductive material and then planarizing to make the upper surface of the stacked structure flush, as Figure 13A , 13B and shown in 13C.

[0230] In an exemplary embodiment, the conductive material may be a metal material for SN (storage node), including but not limited to W, TiN.

[0231] S112: Form the back gate of the read transistor and the second part of the first semiconductor layer.

[0232] Exemplary steps may include: within the range of the write bit line region 200, etching away all the semiconductor material, insulating layer material, and conductive material within the second bit line trench T2 to re-form the second bit line trench T2, and exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20 again; by means of the second bit line trench T2, laterally etching (such as wet etching) the materials filled in the second bit line lateral trench R2 and the first lateral groove S1 in a direction parallel to the substrate. At the position of the cross-section line AA', the lateral etching terminates at the position of the isolation layer 11 on both sides of the second bit line trench T2, that is, removing all the materials filled in the second bit line lateral trench R2; at the position of the cross-section line BB', laterally etching a distance to remove part of the semiconductor material, insulating layer material, and conductive material filled in the first lateral groove S1, and forming a second lateral groove S2 within the first lateral groove S1 after removing part of the materials. Obviously, the size of the second lateral groove S2 along the first direction X is smaller than the size of the first lateral groove S1 along the first direction X; the semiconductor material, insulating layer material, and conductive material that are not removed within the first lateral groove S1 respectively form the back gate 150, the back gate insulating layer 140, and the second part 130 of the first semiconductor layer, and one end of the back gate 150, the back gate insulating layer 140, and the second part 130 of the first semiconductor layer is exposed by the second lateral groove S2; continue to laterally etch away part of the material of the second part 130 of the first semiconductor layer in a direction parallel to the substrate, and fill an insulating material to form a barrier layer 151 surrounding the circumferential sidewall of the end of the back gate 150 away from the first source / drain 110, as Figure 14A , 14B and shown in 14C.

[0233] In an exemplary embodiment, the second portion 130 of the first semiconductor layer may be made of a metal oxide semiconductor material. In an exemplary embodiment, the metal oxide semiconductor material may be an amorphous or polycrystalline metal oxide semiconductor material, and the corrosion rate of the metal oxide semiconductor material in a weakly acidic or weakly alkaline solution is relatively slow. In an exemplary embodiment, the metal oxide semiconductor material may be an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, etc. These metal oxide materials such as Indium Gallium Zinc Oxide (IGZO) may be used as channel materials.

[0234] In an exemplary embodiment, when the metal oxide material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the metal oxide material may also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, and specific adjustments can be made according to the actual situation.

[0235] In an exemplary embodiment, the back gate insulating layer 140 (which may also be referred to as the gate insulating layer) may be a high-k dielectric layer, that is, a dielectric layer with K≥3.9. The high-k dielectric layer may be used as the gate oxide. The back gate insulating layer 140 may be made of any one or more of silicon oxide, aluminum oxide (Al2O3), hafnium oxide.

[0236] In an exemplary embodiment, the material of the back gate 150 may be P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride, etc.

[0237] S113: Form an isolation layer.

[0238] Exemplary steps may include: depositing nitride on all inner walls of the second bit line trench T2, the second bit line lateral groove R2, and the second lateral groove S2 to form the isolation layer 30; filling the second bit line trench T2, the second bit line lateral groove R2, and the second lateral groove S2 with an insulating material to cover the isolation layer 30 and fill the second bit line trench T2, the second bit line lateral groove R2, and the second lateral groove S2, and planarizing by CMP to make the surface of the stacked structure flat, as Figure 15A , 15B and as shown in 15C.

[0239] S114: Form the gate (write word line) and the gate insulating layer of the write transistor.

[0240] Exemplary steps may include: in the word line region 100, by etching (such as dry etching) the stacked structure, in the region between two adjacent isolation layers 11 in the second direction Y, forming a second word line hole K2 penetrating the stacked structure 1 on the side of the main gate 120 away from the first bit line 160; sequentially depositing nitride, insulating layer material, and conductive material on the inner wall surrounding the second word line hole K2 to form the gate 250 of the write transistor, the gate insulating layer 240, and the gate protection layer 40 surrounding the gate insulating layer, as Figure 16A and 16B shown.

[0241] In an exemplary embodiment, the size of the second word line hole K2 in the second direction Y is smaller than the distance W between two adjacent isolation layers 11 in the second direction Y, that is, the orthographic projection of the second word line hole K2 on the substrate falls within the orthographic projection of the sacrificial layer between two adjacent isolation layers 11 in the second direction Y on the substrate. The gate protection layer 40 can be used to protect the gate insulating layer 240 and the gate 250 from being etched away when etching away the isolation layer 30 in subsequent steps.

[0242] S115: Form the second bit line trench (write bit line trench).

[0243] Exemplary steps may include: within the range of the write bit line region 200, etching away all the material of the isolation layer 30 and the material of the insulating layer filled in the second bit line trench T2 in the foregoing step to re-form the second bit line trench T2; by means of the second bit line trench T2, removing all the material of the isolation layer and the material of the insulating layer filled in the second bit line lateral groove R2 in the foregoing step and removing all the material of the isolation layer and the material of the insulating layer filled in the second lateral groove S2 in the foregoing step, and at the same time removing all the material of the outermost gate protection layer 40 surrounding the second word line hole K2 located in the second lateral groove S2, so that the gate insulating layer 240 becomes the outermost of the second word line hole K2 in the second lateral groove S2, as Figure 17A , 17B and as shown in 17C.

[0244] S116: Fill the second bit line trench T2, the second bit line lateral groove R2, and the second lateral groove S2.

[0245] Exemplary steps may include: depositing semiconductor material along the inner walls of the second bit line trench T2, the second bit line lateral groove R2, and the second lateral groove S2, and depositing semiconductor material around the gate insulating layer 240 exposed in the second lateral groove S2 such that the gate insulating layer 240 is completely covered, and filling the region between the gate insulating layer 240 and the back gate 150 of the read transistor with semiconductor material on the side close to the back gate 150, such that the exposed back gate 150, the back gate insulating layer 140, and one end of the second portion 130 of the first semiconductor layer in the second lateral groove S2 are completely covered, thereby forming the second semiconductor layer 230 of the write transistor; continuing to deposit conductive material on the surfaces of the semiconductor materials in the second bit line trench T2 and the second lateral groove S2 until the second bit line trench T2 and the second lateral groove S2 are filled, as Figure 18A 、 18B and as shown in 18C.

[0246] S117: Form the fourth source / drain of the write transistor and the write bit line.

[0247] Exemplary steps may include: within the range of the write bit line region 200, removing only all the semiconductor material and conductive material in the second bit line trench T2, while retaining the semiconductor material and conductive material in the second lateral groove S2; refilling the second bit line trench T2 with an insulating material, thereby forming the fourth source / drain 220 (write bit line) of the write transistor and the semiconductor layer semi-surrounding the fourth source / drain at each second lateral groove, and the fourth source / drains 220 at two adjacent sacrificial layers along the third direction Z are discontinuous or disconnected, as Figure 19A 、 19B and as shown in 19C.

[0248] In another exemplary embodiment, a method for manufacturing a semiconductor structure may include the following steps:

[0249] Steps S201 - S202 are the same as steps S101 - S102 in the foregoing method.

[0250] S203: Form the first bit line trench and the first bit line lateral groove.

[0251] Exemplary steps may include: within the range of the bit line region 300, lithographically etching the stacked structure 1 to form a first bit line trench T1 of the read transistor that penetrates the stacked structure 1 and extends along the second direction Y, exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20; laterally etching (such as wet etching) each sacrificial layer 20 along a direction parallel to the substrate through the first bit line trench T1 until the etching stops at the position of the isolation layer 11 on both sides of the first bit line trench T1 along the first direction X, forming a first bit line lateral groove R1 that extends along the second direction Y and has a length L in the first direction X, exposing the sidewalls of each isolation layer 11, exposing the upper and lower surfaces of each insulating layer 10, and exposing the sidewalls of the sacrificial layer, as Figure 20A 、 20B as shown in 20C.

[0252] S204: Fill the first bit line trench and the first bit line lateral groove.

[0253] Exemplary steps may include: filling the first bit line trench T1 and the first bit line lateral groove R1 with a conductive material and planarizing, so that the first bit line trench T1 and the first bit line lateral groove R1 are filled with the conductive material and the upper surface of the stacked structure is flush, as Figure 21A 、 21B as shown in 21C.

[0254] S205: Form the first source / drain electrode and the first bit line of the read transistor.

[0255] Exemplary steps may include: etching away the conductive material in the first bit line trench T1 to reform the first bit line trench T1, only retaining the conductive material in the first bit line lateral groove R1, thereby forming the first bit line 160 of the read transistor at each first bit line lateral groove R1, making the formed first bit line 160 disconnected in the third direction Z; depositing an insulating material film in the first bit line trench T1 and planarizing, as Figure 22A 、 22B as shown in 22C.

[0256] S206: Form the reference signal line hole.

[0257] Exemplary steps may include: within the word line region 100, dry etching the stacked structure to form the reference signal line hole P, as Figure 23A and 23B shown.

[0258] S207: Form the reference signal line.

[0259] Exemplary steps may include: sequentially depositing a high-k material and a conductive material along the inner wall of the reference signal line hole P, and filling the reference signal line hole with the conductive material to form the dielectric layer 340 and the reference signal line 350, as Figure 24A and24B as shown

[0260] S208: Form a read word line or a first word line of the read transistor.

[0261] Exemplary steps may include: in the word line region, forming a first word line hole K1 of the read transistor on one side of the first word line close to the read bit line region; sequentially depositing a semiconductor material, a high-k dielectric material, and a conductive material along the inner wall of the first word line hole K1, filling the first word line hole K1 with the conductive material, and planarizing the surface of the stacked structure to form a first word line of the read transistor, a main gate insulating layer 122, and a first portion 121 of the first semiconductor layer, as Figure 25A and 25B as shown

[0262] S209: Form a second bit line trench.

[0263] Exemplary steps may include: within the range of the write bit line region 200, etching the stacked structure 1 to form a second bit line trench T2 of the write transistor that penetrates the stacked structure 1 and extends along the second direction Y, exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20, as Figure 26A , Figure 26B and Figure 26C as shown

[0264] S210: Form a second bit line lateral groove and a first lateral groove.

[0265] Exemplary steps may include: by means of the second bit line trench T2, laterally etching (such as wet etching) each sacrificial layer 20 along a direction parallel to the substrate, at the position of the cross-sectional line AA', the lateral etching terminates at the position of the isolation layer 11 on both sides of the second bit line trench T2 along the first direction X, forming a second bit line lateral groove R2, exposing the sidewalls of the isolation layer 11; at the position of the cross-sectional line BB', that is, at the position between two adjacent isolation layers 11 along the second direction Y, the lateral etching terminates at the first bit line 160 of the read transistor, that is, the region where the read word line and the read bit line of the read transistor are connected, forming a first lateral groove S1, exposing the upper and lower surfaces of the insulating layer 10, exposing the sidewall of the first bit line 160 close to the second bit line trench T2, and the size of the first lateral groove S1 along the first direction X is greater than the size of the second bit line lateral groove R2 along the first direction X, as Figure 27A , Figure 27B and Figure 27C as shown

[0266] S211: Fill the second bit line trench, the second bit line lateral groove, and the first lateral groove.

[0267] Exemplary steps may include: depositing a semiconductor material and an insulating material covering the semiconductor material along the inner walls of the second bit line trench T2, the second bit line lateral groove R2, and the first lateral groove S1; filling the second bit line trench T2, the second bit line lateral groove R2, and the first lateral groove S1 with a conductive material and then planarizing to make the upper surface of the stacked structure flush, as Figure 28A , Figure 28B and Figure 28C shown.

[0268] S212: Form the back gate of the read transistor and the second portion of the first semiconductor layer.

[0269] Exemplary steps may include: within the range of the write bit line region 200, etching away all the semiconductor material, insulating layer material, and conductive material within the second bit line trench T2 to reform the second bit line trench T2, and exposing the sidewalls of the insulating layer 10 and the sacrificial layer 20 again; by means of the second bit line trench T2, laterally etching (such as wet etching) the materials filled in the second bit line lateral groove R2 and the first lateral groove S1 in a direction parallel to the substrate. At the position of the cross-sectional line AA', the lateral etching terminates at the position of the isolation layer 11 on both sides of the second bit line trench T2, that is, all the materials filled in the second bit line lateral groove R2 are removed; at the position of the cross-sectional line BB', laterally etch a distance to remove a part of the semiconductor material, insulating layer material, and conductive material filled in the first lateral groove S1, and form a second lateral groove S2 in the first lateral groove S1 after removing the part of the materials. Obviously, the size of the second lateral groove S2 along the first direction X is smaller than the size of the first lateral groove S1 along the first direction X; the semiconductor material, insulating layer material, and conductive material that are not removed in the first lateral groove S1 respectively form the back gate 150, the back gate insulating layer 140, and the second portion 130 of the first semiconductor layer, and one end of the back gate 150, the back gate insulating layer 140, and the second portion 130 of the first semiconductor layer is exposed by the second lateral groove S2; continue to laterally etch away a part of the material of the second portion 130 of the first semiconductor layer in a direction parallel to the substrate, and fill with an insulating material to form a barrier layer 151 surrounding the circumferential sidewall of the end of the back gate 150 away from the first source / drain 110, as Figure 29A , 29B and 29C shown.

[0270] S213: Fill the second bit line lateral groove and the second lateral groove.

[0271] Exemplary steps may include: filling the second bit line trench T2, the second bit line lateral groove R2, and the second lateral groove S2 with a nitride material to reform the sacrificial layer, as Figure 30A , 30B and 30C shown.

[0272] S214: Form a second word line hole.

[0273] Exemplary steps may include: In the word line region 100, by etching (such as dry etching) the stacked structure 1, in the region between two adjacent isolation layers 11 in the second direction Y, a second word line hole K2 penetrating the stacked structure 1 is formed on the side of the second bit line trench close to the main gate, as Figure 31A and 31B shown.

[0274] S215: Form a second word line lateral groove.

[0275] Exemplary steps may include: By means of the second word line hole K2, the sacrificial layer is etched transversely along a direction parallel to the substrate to form a second word line lateral groove R3, thereby exposing the upper and lower surfaces of each insulating layer and the side walls of the sacrificial layer, as Figure 32A and 32B shown.

[0276] S216: Fill the second word line lateral groove.

[0277] Exemplary steps may include: Sequentially depositing a semiconductor material, an insulating material, and a conductive material along the inner walls of the second word line hole K2 and the second word line lateral groove R3 to respectively form a preset second semiconductor layer 230', a preset gate insulating layer 240', and a preset second word line 270', as Figure 33A and 33B shown.

[0278] S217: Form a second word line and a second semiconductor layer.

[0279] Exemplary steps may include: Using wet etching to remove all materials (including semiconductor material, insulating material, and conductive material) in the second word line hole K2, and reforming the second word line hole K2; Continuing to etch and remove part of the material of the preset second semiconductor layer 230' and part of the material of the preset gate insulating layer 240' transversely along a direction parallel to the substrate at each sacrificial layer to form isolation grooves (not shown, which are used to form gate barrier layers subsequently); Filling the isolation grooves at each sacrificial layer with an insulating material and etching away the excess insulating material to make the side walls of the sacrificial layer and the insulating layer flush, forming a gate barrier layer 251, and then forming a second semiconductor layer 230 and a gate insulating layer 240; Filling the second word line hole K2 with a conductive material to form a second word line 270, the second word line 270 having a vertical portion 271 extending perpendicular to the substrate and an extending portion 272 extending transversely along a direction parallel to the substrate from the vertical portion 271, as Figure 34A and 34B shown.

[0280] Writing the second word line structure of the transistor to form such a specific structure and having a gate blocking layer makes it easier to remove parasitic MOS.

[0281] In an exemplary embodiment, the gate blocking layer 251 can be made of the same material as the insulating layer, such as silicon dioxide, but cannot be made of the same material as the gate insulating layer 240.

[0282] S218: Form the second bit line trench again.

[0283] Exemplary steps may include: within the range of the write bit line region 200, etching away all the isolation layer material within the second bit line trench T2 to form the second bit line trench T2 again, and exposing the sidewalls of the insulating layer and the sacrificial layer again; by means of the second bit line trench T2, laterally etching the sacrificial layer along a direction parallel to the substrate to form the second bit line lateral groove R2 again, as Figure 35A 、 35B and as shown in 35C.

[0284] S218: Form the fourth source / drain.

[0285] Exemplary steps may include: filling the second bit line trench T2 and the second bit line lateral groove R2 with a conductive material and planarizing by CMP process; etching away the conductive material within the second bit line trench T2 and only retaining the conductive material within the second bit line lateral groove R2; filling the second bit line trench T2 with an insulating material, thereby forming the fourth source / drain 220 at each second bit line lateral groove R2, as Figure 36A 、 36B and as shown in 36C.

[0286] An exemplary embodiment of the present application also provides an electronic device, including the semiconductor structure provided by the exemplary embodiment of the present application as above.

[0287] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

[0288] Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for the convenience of understanding the present application and is not intended to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: At least one memory cell located on a substrate, the memory cell including a write transistor and a read transistor spaced apart and distributed on the substrate; The read transistor includes a back gate extending along a first direction, a main gate extending along a direction perpendicular to the substrate, and a first semiconductor layer surrounding the back gate and the main gate; wherein, the first semiconductor layer includes a first portion surrounding the main gate and a second portion surrounding the back gate, and the first semiconductor layer is insulated from the main gate and the back gate; The write transistor includes a gate extending along a direction perpendicular to the substrate, and a second semiconductor layer surrounding the gate and insulated from the gate; Wherein the back gate of the read transistor is connected to the second semiconductor layer; the back gate is located between the main gate and the gate of the write transistor.

2. The semiconductor structure according to claim 1, wherein Further comprising: A reference signal line extending along a direction perpendicular to the substrate, and a read bit line extending along a second direction parallel to the substrate, the reference signal line is connected to the first portion of the first semiconductor layer, the read bit line is connected to the second portion of the first semiconductor layer, the reference signal line and the read bit line are spaced apart from each other, and the first direction and the second direction intersect.

3. The semiconductor structure according to claim 2, wherein, The read bit line is also connected to the second portion of the first semiconductor layer.

4. The semiconductor structure according to claim 3, wherein, The first portion and the second portion of the first semiconductor layer are sequentially distributed in the second direction, the first portion includes an annular portion extending in a direction towards the substrate, the second portion includes an annular portion extending in a direction towards the read bit line and the second semiconductor layer of the write transistor and an end portion in contact with the read bit line, and the annular portion of the first portion is in contact with the annular portion of the second portion.

5. The semiconductor structure according to claim 4, wherein The read transistor further includes a barrier layer, and the second portion of the first semiconductor layer extends towards the second semiconductor layer of the write transistor and is insulated from the second semiconductor layer through the barrier layer.

6. The semiconductor structure according to claim 4, wherein The write transistor and the second portion of the first semiconductor layer are sequentially distributed in the first direction; The second semiconductor layer is annular and extends in a direction towards the substrate; further comprising a write bit line extending along the second direction, the write bit line is connected to the outer sidewall of the second semiconductor layer; The end portion of the back gate is connected to the outer sidewall of the second semiconductor layer; the write bit line and the back gate are spaced apart and distributed on the outer sidewall of the second semiconductor layer.

7. The semiconductor structure according to claim 2 or 6, characterized in that Comprising a plurality of layers of the memory cells stacked in a direction perpendicular to the substrate and periodically distributed; each layer of the memory cells includes a memory cell array distributed in an array in the first direction and the second direction; The read bit line is connected to the first semiconductor layers of a column of memory cells; The reference signal line is connected to the first semiconductor layers of the memory cells stacked at the same position in the vertical direction; Further comprising a read word line extending vertically through the read transistors stacked at the same position, different regions of the read word line are surrounded by the first portions of the first semiconductor layers of the respective read transistors, and the main gate is a part of the read word line; It further includes a write line that extends vertically through each write transistor stacked at the same position. The second semiconductor layer of each write transistor surrounds different regions of the write line, and the gate of the write transistor is a part of the write line.

8. The semiconductor structure according to claim 2, wherein The sidewall of the reference signal line is surrounded by a dielectric layer that contacts the second part of the first semiconductor layer. The region of the dielectric layer facing the first semiconductor layer contains an opening, and the reference signal line contacts the first part of the first semiconductor layer through the opening.

9. The semiconductor structure according to claim 1, wherein The back gates of the read transistors stacked in different layers are insulated from each other by an insulating layer, and the back gates are formed by replacing the sacrificial layer between adjacent insulating layers.

10. The semiconductor structure according to claim 7, wherein The first parts of the first semiconductor layers of the read transistors stacked in different layers surround the same read word line and are spaced apart from each other in the vertical direction; the second semiconductor layers of the write transistors stacked in different layers surround the same write line and are spaced apart from each other in the vertical direction.

11. The semiconductor structure according to claim 1, wherein The first semiconductor layer and the second semiconductor layer are metal oxide semiconductor layers.

12. A manufacturing method of a semiconductor structure, characterized in that, It includes the following steps: Deposit an insulating layer and a sacrificial layer alternately in a direction perpendicular to the substrate on the substrate to form a stacked structure including a plurality of insulating layers and sacrificial layers. Pattern the stacked structure to form a plurality of isolation layers arranged at intervals along a second direction parallel to the substrate and at intervals along a first direction parallel to the substrate in the stacked structure. The first direction intersects with the second direction and is perpendicular to the substrate. Form a reference signal line hole in the region between the isolation layers adjacent in the second direction and in the isolation layer, and sequentially fill a dielectric layer and a reference signal line in the reference signal line hole. Form a read word line hole exposing the reference signal line on one side of the reference signal line along the first direction, and sequentially deposit the first part of the first semiconductor layer, a gate insulating layer, and a read word line in the read word line hole. Form a first bit line trench penetrating the stacked structure and extending along the second direction between the isolation layers adjacent in the first direction, and form a read bit line extending along the second direction and connected to the first part of the first semiconductor layer in the first bit line trench. Form a second bit line trench penetrating the stacked structure and extending along the second direction on the side of the read word line away from the read bit line and between the isolation layers adjacent in the first direction. The sidewalls of the second bit line trench expose the stacked insulating layer and sacrificial layer. Etch back each layer of the sacrificial layer in the region between two adjacent memory cells in the column direction until the first semiconductor layer and the read bit line of the corresponding memory cell are exposed, forming a first lateral groove extending in the first direction; sequentially deposit the second part of the first semiconductor layer, a gate insulating layer, and a back gate in the first lateral groove. Etch back the first semiconductor layer, the gate insulating layer, and the back gate in the first lateral groove in the second bit line trench and fill with a sacrificial layer. A writing line hole penetrating the stacked structure is formed in the region filled with the sacrificial layer to expose the back gate, and a second semiconductor layer connected to the back gate, a gate insulating layer, and a writing line are sequentially deposited in the writing line hole; A plurality of write bit lines extending in a second direction are formed in the second bit line trench, and each write bit line is connected to the second semiconductor layer of the corresponding layer storage unit.

13. The manufacturing method according to claim 12, characterized in that, A read bit line extending along the second direction and connected to a first portion of the first semiconductor layer is formed in the first bit line trench, including: The insulating layer and the sacrificial layer exposed in the first bit line trench are etched back in a direction parallel to the substrate to form a first bit line lateral groove at the sacrificial layer; The first bit line trench and the first bit line lateral groove are filled with a conductive material; The conductive material in the first bit line trench is removed, and the conductive material in the first bit line lateral groove is retained to form a plurality of mutually isolated read bit lines extending along the second direction.

14. An electronic device, characterized in that, Comprising a semiconductor structure according to any one of claims 1-11.

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