Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, which are at least beneficial to improving the reliability of the semiconductor device. The semiconductor device comprises a plurality of active parts which are sequentially arranged in a stacked mode in the first direction, a first spacer region and a second spacer region are located on the two opposite sides of the same active part in the first direction respectively, and each active part comprises a first doping region, a channel region and a second doping region which are sequentially distributed in the second direction; the word line structures extending in the third direction are located on the side, facing the first spacer region, of the channel region and further located on the two opposite sides, in the third direction, of the channel region; bit line structures extending along the first direction are in electrical contact with the first doped regions of the plurality of active parts; the capacitor structure extending along the second direction is electrically contacted with the second doped region of the active part; the isolation layer is at least filled in the first interval region; the air gap is located in the second spacer region and at least exposes a side surface of the bit line structure facing the second spacer region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor device and a manufacturing method thereof. Background Art

[0002] A memory is a memory component for storing programs and various data information. The random access memory (RAM) used in a general computer system can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). The dynamic random access memory is a commonly used semiconductor storage device in a computer and is composed of many repeated storage units.

[0003] A storage unit usually includes a capacitor and a transistor. The drain of the transistor is connected to a bit line, and the source is connected to the capacitor. The word line of the storage unit can control the opening or closing of the channel region of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0004] Currently, the reliability of semiconductor structures needs to be improved. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, which are at least beneficial to improving the reliability of the semiconductor device.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor device, including: a plurality of active portions stacked in sequence along a first direction, a first spacer region and a second spacer region are provided between adjacent active portions along the first direction, the first spacer region and the second spacer region are respectively located on opposite sides of the same active portion along the first direction, and the active portion includes a first doped region, a channel region, and a second doped region distributed in sequence along a second direction; a word line structure extending along a third direction, the word line structure is located on a side of the channel region facing the first spacer region, and the word line structure is also located on opposite sides of the channel region along the third direction; a bit line structure extending along the first direction and electrically contacting the first doped regions of the plurality of active portions; a capacitor structure extending along the second direction and electrically contacting the second doped regions of the active portions; an isolation layer at least filling the first spacer region; an air gap located in the second spacer region and at least exposing a side surface of the bit line structure facing the second spacer region.

[0007] In some embodiments, the air gap also exposes a side surface of the capacitor structure facing the second spacer region.

[0008] In some embodiments, the semiconductor device further includes: an insulating layer located in the second spacer region and in contact with the side surfaces of the capacitor structure, and the air gap and the insulating layer together fill the second spacer region.

[0009] In some embodiments, in a first direction, the width of the first spacer region is greater than the width of the second spacer region.

[0010] In some embodiments, the semiconductor device includes: a plurality of active portions arranged at intervals in a third direction and disposed on the same layer; the air gap extends in the third direction and is opposite to the plurality of active portions arranged at intervals in the third direction.

[0011] In some embodiments, the bit line structure includes: a bit line conductive pillar extending in the first direction; a bit line contact layer covering the outer side surface of the bit line conductive pillar and in electrical contact with the end surface of the first doped region facing the bit line conductive pillar; wherein, a part of the surface of the isolation layer facing the second spacer region is exposed by the first doped region, and the bit line contact layer also covers the surface of the isolation layer facing the second spacer region and exposed by the first doped region.

[0012] In some embodiments, the side wall of the bit line structure opposite to the second spacer region protrudes towards the air gap.

[0013] In some embodiments, the semiconductor device includes a plurality of active portions arranged at intervals in a second direction, and in the second direction, the first doped regions of adjacent active portions are opposite to each other, and the opposite first doped regions share the same bit line structure.

[0014] According to some embodiments of the present disclosure, on the other hand, the present disclosure also provides a method for manufacturing a semiconductor device, including: providing a substrate, forming a plurality of active portions stacked in sequence in a first direction on the substrate, there are a first spacer region and a second spacer region between adjacent active portions in the first direction, the first spacer region and the second spacer region are respectively located on opposite sides of the same active portion in the first direction, and the active portion includes a first doped region, a channel region, and a second doped region sequentially distributed in a second direction; forming an insulating layer, the insulating layer is at least filled in the second spacer region; forming a word line structure, the word line structure is located on the side of the channel region facing the first spacer region, and the word line structure is also located on opposite sides of the channel region in the third direction; forming an isolation layer, the isolation layer is at least filled in the first spacer region; forming a bit line hole, the bit line hole extends in the first direction and exposes the end surface of the first doped region and the side wall of the insulating layer; performing lateral etching on the insulating layer to remove at least part of the insulating layer, and after the lateral etching, forming a bit line structure filling the bit line hole, the bit line structure and the adjacent active portions enclose an air gap; forming a capacitor structure, the capacitor structure extends in the second direction and is in electrical contact with the second doped region of the active portion.

[0015] In some embodiments, in a first direction, the width of the first spacer is greater than the width of the second spacer; the process steps for forming the insulating layer include: forming an initial insulating film that fills both the first spacer and the second spacer; and performing wet etching on the initial insulating film to etch away the initial insulating film located in the first spacer, and retaining the initial insulating film located in the second spacer as the insulating layer.

[0016] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0017] In the semiconductor device provided by the embodiments of the present disclosure, there is a first spacer or a second spacer between adjacent active portions in a first direction. The word line structure is located on a side of the channel region facing the first spacer, and an air gap is located in the second spacer of the active portion. In this way, in the first spacer between adjacent active portions, the word line structures corresponding to different active portions can shield each other to avoid the gate-overlap effect between the active portion and the word line structure of another active portion; in the second spacer between adjacent active portions, the air gap can play a shielding role to avoid the gate-overlap effect between the active portion and the word line structure of another active portion, thereby improving the reliability of the semiconductor device. The word line structure is located on the surface of the channel region of the active portion close to the first spacer and on opposite sides of the active portion in a third direction to form a fin field-effect transistor structure surrounded on three sides. The fin field-effect transistor structure can increase the channel width, thereby increasing the on-state current. Multiple active portions are arranged at intervals in the first direction and the third direction. The capacitor structure is in electrical contact with the second doped region of the active portion to form a memory cell. The multiple memory cells arranged in a spatial array are beneficial to improving the space utilization rate. The word line structure extends in the third direction, and multiple transistor structures arranged in the third direction share the same word line structure to improve the control ability of the word line structure; the bit line structure extends in the first direction, and multiple transistors arranged in the first direction share the same bit line structure to improve the efficiency of the bit line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0020] Figure 2 is Figure 1 A schematic cross-sectional structure diagram along the AA1 direction;

[0021] Figures 3 to 9 It is a schematic structure diagram corresponding to each step of the manufacturing method of the semiconductor device provided by the present disclosure.

[0022] Explanation of reference numerals:

[0023] X, the first direction; Y, the second direction; Z, the third direction; I, the first doping region; II, the second doping region; III, the channel region; 101, the active part; 102, the air gap; 103, the word line structure; 104, the bit line structure; 105, the capacitor structure; 106, the isolation layer; 107, the insulating layer; 111, the first spacer region; 121, the second spacer region; 201, the semiconductor layer; 204, the bit line hole; 211, the segmentation hole; 216, the first isolation layer. Detailed implementation manners

[0024] As can be seen from the background art, the reliability of semiconductor devices needs to be improved.

[0025] With the increasing demand for high performance and low cost of semiconductor devices, higher requirements are also put forward for the integration density of semiconductor devices. The 3D Dynamic Random Access Memory (3D DRAM) structure stacks memory cells (Cells) to achieve higher yields per unit wafer area. Compared with the ordinary planar DRAM structure, the 3D DRAM structure can effectively reduce the unit cost of DRAM.

[0026] In the current 3D DRAM structure, a word line structure is usually arranged to surround the channel region of the active part to form a gate-all-around structure. The gate-all-around structure is beneficial to improving the control ability of the word line structure. However, the process of the gate-all-around structure is difficult, and due to the close distance between the stacked active parts, the gate-all-around structure makes the distance between the word line structures corresponding to different active parts closer, resulting in a large coupling effect between adjacent word line structures. If the thickness of the word line structure in the gate-all-around structure is thinned, it is easy to cause a large resistance of the word line structure, resulting in serious delay in the semiconductor device and affecting the read / write effect of the device. If the word line structure is arranged only on one side of the active part to form a single-gate structure, it is beneficial to increase the size of the word line structure and reduce the process difficulty, but there is still a problem of the through-gate effect between the word line structure of one active part and the adjacent other active part, resulting in low reliability of the semiconductor device.

[0027] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. In the semiconductor device, a plurality of active portions are stacked along a first direction, and a first spacer region or a second spacer region is provided between adjacent active portions. A word line structure is provided in the first spacer region, and an air gap is provided in the second spacer region. In the first spacer region between adjacent active portions, the word line structures corresponding to different active portions can shield each other to avoid a crosstalk effect between the active portion and the word line structure of another active portion; the air gap in the second spacer region between adjacent active portions can play a shielding role to avoid a crosstalk effect between the active portion and the word line structure of another active portion, thereby improving the reliability of the semiconductor device. In addition, the word line structure is located on the surface of the channel region of the active portion close to the first spacer and on the opposite sides of the active portion along a third direction to form a three-sided surrounding FinFET (Fin Field-Effect Transistor) structure. The FinFET structure can increase the channel width, thereby increasing the on-state current.

[0028] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0029] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 is Figure 1 A cross-sectional structural diagram along the AA1 direction.

[0030] On the one hand, embodiments of the present disclosure provide a semiconductor device. Referring to Figure 1 and Figure 2 , the semiconductor device includes: an active portion 101, a word line structure 103, a bit line structure 104, a capacitor structure 105, an isolation layer 106, and an air gap 102.

[0031] A plurality of active portions 101 are sequentially stacked along a first direction X. A first spacer region 111 and a second spacer region 121 are provided between adjacent active portions 101 along the first direction X. The first spacer region 111 and the second spacer region 121 are respectively located on opposite sides of the same active portion 101 along the first direction X. The active portion 101 includes a first doped region I, a channel region III, and a second doped region II that are sequentially distributed along a second direction Y.

[0032] The word line structure 103 extends along the third direction Z. The word line structure 103 is located on the side of the channel region III facing the first spacer region 111, and the word line structure 103 is also located on the opposite sides of the channel region III along the third direction Z.

[0033] The bit line structure 104 extends along the first direction X, and the bit line structure 104 is in electrical contact with the first doped region I of the plurality of active portions 101.

[0034] The capacitor structure 105 extends along the second direction Y, and the capacitor structure 105 is in electrical contact with the second doped region II of the active portion 101.

[0035] The isolation layer 106 is at least filled in the first spacer region 111.

[0036] The air gap 102 is located in the second spacer region 121, and the air gap 102 at least exposes the side surface of the bit line structure 104 facing the second spacer region 121.

[0037] In the semiconductor device provided by the embodiment of the present disclosure, there is a first spacer region 111 or a second spacer region 121 between the active portions 101 adjacent along the first direction X. The word line structure 103 is located on the side of the channel region III facing the first spacer region 111, and the air gap 102 is located in the second spacer region 121 of the active portion 101. Thus, in the first spacer region between adjacent active portions 101, the word line structures 103 corresponding to different active portions 101 can play a role of mutual shielding to avoid the generation of a punch-through effect between the active portion 101 and the word line structure 103 of another active portion 101; in the second spacer region 121 between adjacent active portions 101, the air gap 102 can play a shielding role to avoid the generation of a punch-through effect between the active portion 101 and the word line structure 103 of another active portion 101, thereby improving the reliability of the semiconductor device. The word line structure 103 is located on the surface of the channel region III of the active portion 101 close to the first spacer region 111 and on the opposite sides of the active portion 101 along the third direction Z to form a three-sided surrounding FinFET (Fin Field-Effect Transistor) structure. The FinFET structure can increase the channel width, thereby increasing the on-state current. The plurality of active portions 101 are arranged at intervals along the first direction X and the third direction Z. The capacitor structure 105 is in electrical contact with the second doped region II of the active portion 101 to form a memory cell. The plurality of memory cells arranged in a spatial array are beneficial to improving the space utilization rate. The word line structure 103 extends along the third direction Z, and the same word line structure 103 is shared by the plurality of transistor structures arranged along the third direction Z to improve the control ability of the word line structure 103; the bit line structure 104 extends along the first direction X, and the same bit line structure 104 is shared by the plurality of transistors arranged along the first direction X to improve the efficiency of the bit line structure 104.

[0038] The material of the active part 101 may include semiconductor materials such as silicon, gallium arsenide, silicon carbide, or gallium nitride. The material of the active part 101 may also include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Indium Tungsten Oxide), or ITO (Indium Tin Oxide).

[0039] In some embodiments, along the first direction X, the width of the first spacer 111 is greater than the width of the second spacer 121. In this way, when the air gap 102 can effectively suppress the crosstalk effect between the active part 101 and the word line structure 103 corresponding to another adjacent active part 101, more space can be provided for the word line structure 103 to reduce the resistance of the word line structure 103 and improve the transmission efficiency of the semiconductor device.

[0040] The word line structure includes: a word line conductive part (not shown in the figure), the word line conductive part is located on the side of the channel region facing the first spacer, and the word line conductive part extends along the second direction; a gate dielectric layer (not shown in the figure), the gate dielectric layer is at least located between the channel region and the word line conductive part.

[0041] In some embodiments, the gate dielectric layer is also located on the surface of the first doped region facing the first spacer. During the formation of the gate dielectric layer, the gate dielectric layer covers the first doped region of the active part and the surface of the channel region. After the formation of the word line conductive part, only the word line conductive part of the first doped region can be removed, and the gate dielectric layer of the first doped region can be retained, omitting a process step and improving the manufacturing efficiency of the semiconductor device.

[0042] The material of the word line conductive part includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0043] The material of the gate dielectric layer includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof. For example, the gate dielectric layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON, etc.

[0044] The isolation layer 106 is filled between the word line structures 103 corresponding to two active parts 101 in the first spacer 111 for isolating adjacent word line structures 103. The material of the isolation layer 106 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0045] The semiconductor device may further include: an insulating layer 107, which is located within the second spacer 121 and is in contact with the side surfaces of the capacitor structure 105, and the air gap 102 and the insulating layer 107 together fill the second spacer 121. In some other embodiments, the air gap also exposes the side surface of the capacitor structure facing the second spacer.

[0046] The material of the insulating layer 107 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0047] In some embodiments, the semiconductor device includes: a plurality of active portions 101 that are arranged in the same layer and spaced apart along the third direction Z; the air gap 102 extends along the third direction Z and is aligned with the plurality of active portions 101 spaced apart along the third direction Z. This can facilitate the process formation, reduce the process difficulty, and improve the manufacturing efficiency of the semiconductor device.

[0048] The gas in the air gap 102 can be one of air or nitrogen.

[0049] The bit line structure may include: a bit line conductive pillar (not shown in the figure), the bit line conductive pillar extending along the first direction; a bit line contact layer (not shown in the figure), the bit line contact layer covering the outer side surface of the bit line conductive pillar and being in electrical contact with the end surface of the first doped region facing the bit line conductive pillar; wherein, the first doped region exposes a partial surface of the isolation layer facing the second spacer, and the bit line contact layer also covers the surface of the isolation layer facing the second spacer and exposed by the first doped region. When forming the bit line structure, the first doped region of the active portion may be recessed towards the channel region side relative to the isolation layer, and the bit line contact layer also covers the surface of the isolation layer facing the second spacer and exposed by the first doped region, which can ensure that the bit line contact layer is fully in contact with the first doped region, thereby realizing the electrical connection between the bit line structure and the active portion.

[0050] The material of the bit line conductive pillar includes single metal, metal compound, or alloy. Among them, the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound can be tungsten nitride, tantalum nitride, or titanium nitride; the alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0051] The material of the bit line contact layer includes single metal, metal compound, or alloy. Among them, the single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound can be tungsten nitride, tantalum nitride, or titanium nitride; the alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0052] In some embodiments, the sidewall of the bit line structure 104 facing the second spacer 121 protrudes towards the air gap 102. When forming the bit line structure 104, in order to retain part of the second spacer 121 as the air gap 102, the forming speed of the bit line structure 104 needs to be relatively fast, and the degree of accumulation of the bit line structure 104 at the air gap 102 is greater. Therefore, the sidewall of the bit line structure 104 will bulge towards the air gap 102.

[0053] In some embodiments, the semiconductor device includes a plurality of active parts 101 arranged at intervals along the second direction Y, and along the second direction Y, the first doped regions I of adjacent active parts 101 face each other, and the facing first doped regions I share the same bit line structure 104. This can further improve the space utilization rate of the semiconductor device along the second direction Y, and along the second direction Y, the facing first doped regions I of adjacent active parts 101 share the same bit line structure 104, which can further improve the control ability of the bit line structure 104.

[0054] A plurality of active parts 101 arranged in the third direction Z and the first direction X can share the upper electrode layer of the capacitor structure 105, so as to improve the charge storage ability of the capacitor structure 105 while the capacitor structure 105 occupies a smaller space volume.

[0055] The capacitor structure may include: a lower electrode layer that covers the surface of the end of the second doped region and also covers the surface of the isolation layer and the insulating layer facing the active part, wherein the lower electrode layers corresponding to the second doped regions adjacent in the first direction are disconnected from each other; a capacitor dielectric layer that is located on the surface of the lower electrode layer and also on the side surfaces of the isolation layer and the insulating layer, and the capacitor dielectric layer encloses a hollow ring extending in the first direction to form a groove; an upper electrode layer that is located on the surface of the capacitor dielectric layer; and a conductive filling layer that is located on the surface of the upper electrode layer and fills the groove. The lower electrode layers in the capacitor structures corresponding to different active parts are disconnected from each other, and the upper electrode layers are shared, so that the space utilization rate and charge storage ability of the capacitor structure can be improved.

[0056] The material of the lower electrode layer includes at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium.

[0057] The material of the capacitor dielectric layer includes high-k materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate.

[0058] The material of the upper electrode layer includes at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium.

[0059] The materials of the conductive filling layer include copper, silver, gold, tungsten, tin or lead.

[0060] In some embodiments, taking the lower electrode layer as a U-shaped structure as an example, the upper electrode layer is located inside the U-shaped structure of the lower electrode layer; in other embodiments, the upper electrode layer may be a U-shaped structure, and the lower electrode layer is located inside the U-shaped structure of the upper electrode layer.

[0061] In the semiconductor device provided by the embodiments of the present disclosure, there is a first spacer 111 or a second spacer 121 between the active portions 101 adjacent in the first direction X. The word line structure 103 is located on the side of the channel region III facing the first spacer 111, and the air gap 102 is located in the second spacer 121 of the active portion 101. In this way, in the first spacer between adjacent active portions 101, the word line structures 103 corresponding to different active portions 101 can play a mutual shielding role to avoid the occurrence of the crosstalk effect between the active portion 101 and the word line structure 103 of another active portion 101; in the second spacer 121 between adjacent active portions 101, the air gap 102 can play a shielding role to avoid the occurrence of the crosstalk effect between the active portion 101 and the word line structure 103 of another active portion 101, thereby improving the reliability of the semiconductor device. The word line structure 103 is located on the surface of the channel region III of the active portion 101 close to the first spacer 111 and on the opposite sides of the active portion 101 along the third direction Z to form a three-sided surrounding FinFET (Fin Field-Effect Transistor) structure. The FinFET structure can increase the channel width, thereby increasing the on-state current. A plurality of active portions 101 are arranged at intervals along the first direction X and the third direction Z. The capacitor structure 105 is in electrical contact with the second doped region II of the active portion 101 to form a storage unit. The plurality of storage units arranged in a spatial array are conducive to improving the space utilization rate. The word line structure 103 extends along the third direction Z, and a plurality of transistor structures arranged along the third direction Z share the same word line structure 103 to improve the control ability of the word line structure 103; the bit line structure 104 extends along the first direction X, and a plurality of transistors arranged along the first direction X share the same bit line structure 104 to improve the efficiency of the bit line structure 104.

[0062] Another embodiment of the present disclosure provides a manufacturing method of a semiconductor device, which can be used to form the above-mentioned semiconductor device to improve the performance of the semiconductor device. It should be noted that for the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, and details will not be described in the following.

[0063] Figures 3 to 9 It is a schematic structural diagram corresponding to each step of the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure.

[0064] Another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor device, including:

[0065] Referring to Figure 3 , a substrate 100 is provided, and a plurality of active portions 101 are sequentially stacked on the substrate 100 in the first direction X. There are a first spacer 111 and a second spacer 121 between adjacent active portions 101 along the first direction X. The first spacer 111 and the second spacer 121 are respectively located on opposite sides of the same active portion 101 along the first direction X. The active portion 101 includes a first doped region I, a channel region III, and a second doped region II that are sequentially distributed in the second direction Y; an insulating layer 107 is formed, and the insulating layer 107 is filled in the second spacer 121.

[0066] Specifically, referring to Figures 4 to 8 , the steps of providing the substrate 100 and forming the insulating layer 107 include:

[0067] Referring to Figure 4 and Figure 5 , Figure 5 For Figure 4 the schematic cross-sectional structures along the directions of BB1, CC1, and DD1, a sacrificial layer and a semiconductor layer 201 are alternately stacked on the substrate 100. Along the first direction X, the thicknesses of the sacrificial layers on both sides of the semiconductor layer 201 are different; the sacrificial layer and the semiconductor layer 201 are etched along the thickness direction of the substrate 100 to form a plurality of dividing holes 211. The dividing holes 211 extend along the first direction X and are arranged at intervals in the second direction Y and the third direction Z. An insulating material is filled in the dividing holes 211; a bit line hole 204 is formed between a group of dividing holes 211 along the third direction Z, and the bit line hole 204 extends along the first direction X; based on the bit line hole 204, the sacrificial layer is removed, and the first spacer 111 and the second spacer 121 are formed on both sides of the semiconductor layer 201 along the first direction X.

[0068] Based on the different thicknesses of the sacrificial layers on both sides of the semiconductor layer 201, along the first direction X, the width of the first spacer 111 is greater than the width of the second spacer 121. Referring to Figure 6 , the process steps for forming the insulating layer 107 include: forming an initial insulating film that fills the first spacer 111 and the second spacer 121; performing wet etching on the initial insulating film to etch and remove the initial insulating film located in the first spacer 111, and retaining the initial insulating film located in the second spacer 121 as the insulating layer 107.

[0069] Since the width of the first spacer 111 is larger, after forming the initial insulating film with the same thickness, the first spacer 111 is filled, and there are still gaps in the initial insulating film between the second spacers 121. After further removing the initial insulating film by wet etching, the initial insulating film in the second spacer 121 is removed faster, and the initial insulating film in the first spacer 111 can be retained as the insulating layer 107.

[0070] Reference Figure 7 , a first isolation layer 216 is formed in the second spacer 121. The first isolation layer 216 covers the surface of the semiconductor layer 201 facing the first spacer 111 and the inner wall of the bit line hole 204; an insulating material is filled between the first isolation layers 216 in the first spacer 111, and an insulating material is filled in the bit line hole 204.

[0071] Reference Figure 8 , the insulating materials in the dividing hole 211 and the bit line hole 204 are removed along the thickness direction of the substrate 100; the semiconductor layer 201 is laterally etched, and the remaining semiconductor layer 201 serves as the active part 101; a first isolation layer 216 is formed on the side wall of the active part 101; insulating materials are filled back in the dividing hole 211 and the bit line hole 204. During the lateral etching process, the semiconductor layer 201 between the adjacent dividing holes 211 along the second direction Y is removed, so that the semiconductor layer 201 is divided into a plurality of active parts 101 extending along the second direction Y and spaced apart along the third direction Z.

[0072] In other embodiments, an insulating layer can also be formed in the second spacer by setting different sacrificial layer materials on both sides of the semiconductor layer along the first direction, so that the width of the first spacer can be less than or equal to the width of the second spacer.

[0073] Figure 9 For Figure 3 the corresponding structural schematic diagrams along the DD1 direction and the EE1 direction in

[0074] Reference Figure 9, a word line structure 103 and an isolation layer are formed. The word line structure 103 is located on one side of the channel region III facing the first spacer region 111, and the word line structure 103 is also located on opposite sides of the channel region III along the third direction Z. The isolation layer is at least filled in the first spacer region 111; a bit line hole 204 is formed. The bit line hole 204 extends along the first direction X and exposes the end face of the first doped region I and the side wall of the insulating layer 107; the insulating layer 107 is laterally etched to remove at least part of the insulating layer 107, and after the lateral etching, a bit line structure 104 that fills the bit line hole 204 is formed. The bit line structure 104 and the adjacent active portion 101 enclose an air gap 102; a capacitor structure 105 is formed. The capacitor structure 105 extends along the second direction Y and is in electrical contact with the second doped region II of the active portion 101.

[0075] The specific steps for forming the word line structure 103 include: removing the insulating material in the bit line hole 204 and removing the first isolation layer 216 adjacent to the bit line hole 204 based on the bit line hole 204; after forming the initial word line structure, the initial word line structure is re-etched, and the remaining initial word line structure serves as the word line structure 103 so that the word line structure 103 faces the channel region III; the first isolation layer 216 is refilled in the first spacer region 111, and the first isolation layer 216 and the insulating material in the first spacer region 111 serve as the isolation layer. Since after the active portion 101 is formed, the first isolation layer 216 is formed on the side wall of the active portion 101, the word line structure 103 can also cover opposite sides of the channel region III along the third direction Z.

[0076] During the process of forming the air gap 102 and the bit line structure 104, after the insulating layer 107 is laterally etched based on the bit line hole 204, the second spacer regions 121 between adjacent active portions 101 are spaced apart from each other. When the forming speed of the bit line structure 104 is relatively fast, the bit line structure 104 can be piled up at the end of the first doped region I, and then the second spacer regions 121 are enclosed to form the air gap 102.

[0077] The specific steps for forming the capacitor structure include: forming a capacitor hole on the side of the second doped region of the active portion away from the channel region; removing part of the length of the second doped region based on the capacitor hole; forming a lower electrode layer on the inner wall of the capacitor hole. The lower electrode layer covers the surface of the end of the second doped region and also covers the surfaces of the isolation layer and the insulating layer facing the active portion; the lower electrode layer on the side walls of the isolation layer and the insulating layer is etched along the thickness direction of the substrate so that the lower electrode layers corresponding to the second doped regions adjacent in the first direction are disconnected from each other; forming a capacitor dielectric layer. The capacitor dielectric layer is located on the surface of the lower electrode layer and is also located on the sides of the isolation layer and the insulating layer. The capacitor dielectric layer encloses a hollow ring extending along the first direction to form a groove; forming an upper electrode layer. The upper electrode layer is located on the surface of the capacitor dielectric layer; forming a conductive filling layer. The conductive filling layer is located on the surface of the upper electrode layer and fills the groove.

[0078] In some embodiments, the capacitor vias extend in the third direction. After the capacitor structure is formed, the capacitor structures corresponding to the plurality of active portions along the first direction and the third direction can share the upper electrode layer of the capacitor structure, thereby improving the space utilization rate and storage efficiency of the capacitor structure.

[0079] In the manufacturing method of the semiconductor device provided by the embodiments of the present disclosure, a first spacer 111 or a second spacer 121 is formed between the active portions 101 adjacent to each other along the first direction X. The word line structure 103 is formed on the side of the channel region III facing the first spacer 111, and the air gap 102 is formed in the second spacer 121 of the active portion 101. Thus, in the first spacer between the adjacent active portions 101, the word line structures 103 corresponding to different active portions 101 can shield each other to avoid the crosstalk effect between the active portion 101 and the word line structure 103 of another active portion 101; in the second spacer 121 between the adjacent active portions 101, the air gap 102 can play a shielding role to avoid the crosstalk effect between the active portion 101 and the word line structure 103 of another active portion 101, thereby improving the reliability of the semiconductor device. The word line structure 103 is formed on the surface of the channel region III of the active portion 101 close to the first spacer 111 and on the opposite sides of the active portion 101 along the third direction Z to form a three-sided surrounding FinFET (Fin Field-Effect Transistor) structure. The FinFET structure can increase the channel width, thereby increasing the on-state current. The plurality of active portions 101 are arranged at intervals along the first direction X and the third direction Z. The formed capacitor structure 105 is in electrical contact with the second doped region II of the active portion 101 to form a storage unit. The plurality of storage units arranged in a spatial array are beneficial to improving the space utilization rate. The formed word line structure 103 extends along the third direction Z, and the plurality of transistor structures arranged along the third direction Z share the same word line structure 103 to improve the control ability of the word line structure 103; the formed bit line structure 104 extends along the first direction X, and the plurality of transistors arranged along the first direction X share the same bit line structure 104 to improve the efficiency of the bit line structure 104.

[0080] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: A plurality of active portions stacked in sequence along a first direction, a first spacing region and a second spacing region between the active portions adjacent to each other along the first direction, the first spacing region and the second spacing region are respectively located at opposite sides of the same active portion along the first direction, and the active portion comprises a first doping region, a channel region and a second doping region sequentially distributed along the second direction; a word line structure extending along a third direction, the word line structure being located on a side of the channel region facing the first spacer region, and the word line structure being also located on two opposite sides of the channel region along the third direction; a bit line structure extending along the first direction and electrically contacting the first doped regions of the plurality of active portions; a capacitor structure extending along the second direction and electrically contacting the second doped region of the active portion; an isolation layer, wherein the isolation layer is filled at least in the first spacing area; An air gap is located in the second spacing region and at least exposes a side surface of the bit line structure facing the second spacing region.

2. The semiconductor device according to claim 1, wherein: The air gap also exposes a side surface of the capacitor structure facing the second spacing region.

3. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: An insulating layer is located in the second spacing area and contacts the side surface of the capacitor structure, and the air gap and the insulating layer together fill the second spacing area.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: Along the first direction, the width of the first spaced region is greater than the width of the second spaced region.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device comprises: a plurality of active portions arranged in the same layer and spaced apart along the third direction; and the air gap extends along the third direction and faces the plurality of active portions spaced apart along the third direction.

6. The semiconductor device according to claim 1, wherein: The bit line structure comprises: A bit line conductive pillar extending along the first direction; A bit line contact layer, the bit line contact layer covers the outer side surface of the bit line conductive pillar and is in electrical contact with the end surface of the first doped region facing the bit line conductive pillar; The first doped region exposes a portion of the surface of the isolation layer facing the second spacing region, and the bit line contact layer further covers the surface of the isolation layer facing the second spacing region and exposed by the first doped region.

7. The semiconductor device according to claim 1 or 6, characterized in that: The sidewall of the bit line structure directly facing the second spacing region protrudes toward the air gap.

8. The semiconductor device according to claim 1, wherein: The semiconductor device includes a plurality of active portions arranged at intervals along the second direction, and the first doped regions of adjacent active portions are directly opposite to each other along the second direction, and the directly opposite first doped regions share the same bit line structure.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a plurality of active portions stacked in sequence in a first direction are formed, a first spacing region and a second spacing region are provided between the active portions adjacent to each other in the first direction, the first spacing region and the second spacing region are respectively located at two opposite sides of the same active portion in the first direction, and the active portion comprises a first doping region, a channel region, and a second doping region sequentially distributed in a second direction; forming an insulating layer, wherein the insulating layer is filled at least in the second spacing area; forming a word line structure, wherein the word line structure is located on a side of the channel region facing the first spacer region, and the word line structure is also located on two opposite sides of the channel region along a third direction; forming an isolation layer, wherein the isolation layer is filled at least in the first spacing area; forming a bit line hole, wherein the bit line hole extends along the first direction and exposes an end surface of the first doping region and a side wall of the insulating layer; Performing lateral etching on the insulating layer to remove at least a portion of the insulating layer, and after the lateral etching, forming a bit line structure that fills the bit line hole, wherein the bit line structure and the adjacent active portion enclose an air gap; A capacitor structure is formed, wherein the capacitor structure extends along the second direction and is electrically in contact with the second doping region of the active portion.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Along the first direction, the width of the first spacing area is greater than the width of the second spacing area; The process steps of forming the insulating layer include: forming an initial insulating film that fills the first spacing region and the second spacing region; The initial insulating film is wet-etched to remove the initial insulating film located in the first spacing region by etching, and the initial insulating film located in the second spacing region is retained as the insulating layer.

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