Memory device of ferroelectric field effect transistor based on gate-all-around structure
By filling the low dielectric constant material into the trench region in the memory device of the ferroelectric field effect transistor based on the ring gate structure, the problem of low storage reliability in the memory device is solved, and higher data stability is achieved.
Patent Information
- Application Number
- CN202311744340.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2025-06-24
AI Technical Summary
Currently, the memory devices of ferroelectric field effect transistors based on ring gate structure have too low storage reliability during data retention, which is mainly due to the coupling effect between adjacent memory cells and series, resulting in data instability.
The coupling effect between memory cells is reduced by filling the trench region between each adjacent two memory cells in the same stack layer.
The coupling effect between the memory cells on both sides of the trench area is effectively reduced, and the storage reliability of the memory devices of the ferroelectric field effect transistor based on the ring gate structure in the data holding process is significantly improved.
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Figure CN120201724A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronics technology, and in particular to a memory device based on a ferroelectric field effect transistor with a gate-all-around structure. Background Art
[0002] With the development of semiconductor technology and microelectronics technology, memory devices using ferroelectric field effect transistors (FeFETs) as memory cells have received increasing attention. Among many memory devices, a memory device based on a ferroelectric field effect transistor with a gate-all-around (GAA) structure fabricated using a 3D NAND architecture can operate at lower power, higher durability, and faster operation speed while maintaining full CMOS compatibility and high density, and is expected to be used in next-generation memory devices.
[0003] However, in the current memory device based on a ferroelectric field effect transistor with a gate-all-around structure, during the programming or erasing process, the memory cells between adjacent memory cell strings in the same stacked layer are affected by the gate voltage of the programming cell, resulting in programming interference, which greatly affects the reliability of the data in the memory device. Specifically, in the current memory device based on a ferroelectric field effect transistor with a gate-all-around structure, there is a trench region between adjacent memory cell strings. When the memory cells in the memory cell strings on both sides of the trench region perform memory operations, due to the coupling effect between adjacent ferroelectric field effect transistors, the memory state of the memory cells on the other side also changes, resulting in a serious reduction in the storage reliability of the memory device during the data retention process. Summary of the Invention
[0004] In view of this, the present application provides a memory device based on a ferroelectric field effect transistor with a gate-all-around structure, mainly aiming to solve the technical problem of too low storage reliability of the current memory device based on a ferroelectric field effect transistor with a gate-all-around structure during the data retention process.
[0005] According to a first aspect of the present invention, there is provided a memory device based on a ferroelectric field effect transistor with a gate-all-around structure, wherein the memory device uses a ferroelectric field effect transistor as a memory cell, and the memory device based on a ferroelectric field effect transistor with a gate-all-around structure includes a plurality of memory cell strings;
[0006] Each of the memory cell strings includes a plurality of the ferroelectric field effect transistors. In the memory device based on a ferroelectric field effect transistor with a gate-all-around structure, there is a trench region formed by etching between every two adjacent memory cell strings in the same stacked layer;
[0007] The trench region is filled with a low dielectric constant material to reduce the coupling effect between the memory cells in the adjacent memory cell strings.
[0008] Optionally, each of the storage cell strings includes a plurality of ferroelectric field effect transistors serving as storage cells, and among the plurality of ferroelectric field effect transistors of the storage cell string, there are cut ferroelectric field effect transistors divided by the trench region; the low dielectric constant material is disposed on the cut ferroelectric field effect transistor facing the trench region.
[0009] Optionally, the ferroelectric field effect transistor includes an oxide filling layer, a polysilicon channel, and a hafnium-based ferroelectric layer; the polysilicon channel surrounds the oxide filling layer within the polysilicon channel, and the hafnium-based ferroelectric layer surrounds the oxide filling layer and the polysilicon channel within the hafnium-based ferroelectric layer.
[0010] Optionally, the dielectric constant of the low dielectric constant material is less than or equal to 4.
[0011] Optionally, the low dielectric constant material includes an inorganic insulating material.
[0012] Optionally, the low dielectric constant material includes a carbon-doped oxide.
[0013] Optionally, the low dielectric constant material includes a low dielectric constant material based on carbon-doped silicon oxide.
[0014] Optionally, the distance between every two adjacent storage cell strings in the same stacked layer is greater than or equal to a preset interval length.
[0015] Optionally, the oxide filling layer, the polysilicon channel, and the hafnium-based ferroelectric layer are nested layer by layer in the form of concentric circles.
[0016] Optionally, the storage device of the ferroelectric field effect transistor based on the surrounding gate structure includes a plurality of stacked layers, and each of the stacked layers includes a plurality of storage cells.
[0017] A storage device of a ferroelectric field effect transistor based on the surrounding gate structure provided by the present invention, by filling a low dielectric constant material (Low-k dielectric, Low-K) into the trench region between every two adjacent storage cell strings in the same stacked layer of the storage device of the ferroelectric field effect transistor based on the surrounding gate structure, based on the characteristic of the low dielectric constant of the low dielectric constant material, can effectively reduce the coupling effect between adjacent storage cells on both sides of the trench region, and can significantly improve the storage reliability of the storage device of the ferroelectric field effect transistor based on the surrounding gate structure during data retention.
[0018] The above description is only an overview of the technical solution of the present application. In order to better understand the technical means of the present application, it can be implemented according to the content of the specification. In order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the specific embodiments of the present application are hereinafter specifically described. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0020] Figure 1 shows a schematic structural diagram of a storage device of a ferroelectric field-effect transistor based on a surrounding gate structure provided by an embodiment of the present invention;
[0021] Figure 2 shows a schematic structural diagram of another storage device of a ferroelectric field-effect transistor based on a surrounding gate structure provided by an embodiment of the present invention;
[0022] Figure 3 shows a schematic plan view of the structure of a ferroelectric field-effect transistor provided by an embodiment of the present invention;
[0023] Figure 4 shows a schematic plan view of the structure of a ferroelectric field-effect transistor divided by a trench region provided by an embodiment of the present invention;
[0024] Figure 5 shows a schematic structural diagram of an adjacent storage cell string and adjacent cut ferroelectric field-effect transistors in the adjacent storage cell string provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0025] The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0026] In the current storage device of a ferroelectric field-effect transistor based on a surrounding gate structure, during the programming or erasing process, the storage cells between adjacent storage cell strings in the same stacked layer are affected by the gate voltage of the programming cell, resulting in programming or erasing interference, which greatly affects the reliability of the data in the storage device. Specifically, in the current storage device of a ferroelectric field-effect transistor based on a surrounding gate structure, there is a trench region between adjacent storage cell strings. When performing a storage operation on the storage cells in the storage cell strings on both sides of the trench region, due to the coupling effect between adjacent ferroelectric field-effect transistors, the storage state of the storage cells on the other side will also change, resulting in a serious reduction in the storage reliability of the storage device during the data retention process.
[0027] In one embodiment, to address the above problems, as Figure 1 shown, a storage device based on a ferroelectric field-effect transistor with a gate-all-around structure is provided. The storage device uses the ferroelectric field-effect transistor 100 as a storage unit. The storage device based on the ferroelectric field-effect transistor with a gate-all-around structure includes a plurality of storage cell strings 300. Among them, the storage device based on the ferroelectric field-effect transistor with a gate-all-around structure may include multiple stacked layers, and each stacked layer includes a plurality of storage cell strings 300. Adjacent storage cell strings 300 are separated by a trench region. Here, each storage cell string 300 can serve as an FeFET array, and the storage device based on the ferroelectric field-effect transistor with a gate-all-around structure can be a three-dimensional storage array based on the ferroelectric field-effect transistor with a gate-all-around structure.
[0028] Specifically, each of the storage cell strings 300 includes a plurality of the ferroelectric field-effect transistors 100. In the storage device based on the ferroelectric field-effect transistor with a gate-all-around structure, a trench region (cut region) formed after etching is provided between every two adjacent storage cell strings 300 in the same stacked layer.
[0029] The current storage array based on the ferroelectric field-effect transistor with a gate-all-around structure uses silicon dioxide (SiO2) material as the filling material for the cut region. However, the dielectric constant of silicon dioxide is too high, resulting in a relatively high coupling effect between the storage cells of the storage cell strings on both sides of the cut region in the same stacked layer of the storage array, which is not conducive to the stability of data storage. Here, the lower the dielectric constant of the filling material for the cut region, the weaker the coupling effect between the two adjacent storage cells, and the more stable the data stored in the storage cells. Further, the trench region is filled with a low-dielectric-constant material 200 so that the trench region between two adjacent storage cell strings 300 is filled with the low-dielectric-constant material 200, reducing the coupling effect between the storage cells 100 in the adjacent storage cell strings 300. Here, the dielectric constant of the filling material for the Cut region determines the coupling effect between the storage cells on its adjacent two sides. The low-dielectric-constant material 200 can be materials such as fluorinated silicon dioxide, which is not limited here.
[0030] The memory device of the ferroelectric field-effect transistor based on the gate-all-around structure provided by this embodiment can effectively reduce the coupling effect between adjacent memory cell strings in the same stacked layer of the memory device of the ferroelectric field-effect transistor based on the gate-all-around structure by filling the trench area between every two adjacent memory cell strings with a low dielectric constant material (Low-k dielectric, Low-K). Based on the characteristic of the low dielectric constant of the low dielectric constant material, the memory reliability of the memory device of the ferroelectric field-effect transistor based on the gate-all-around structure can be significantly improved during the data retention process.
[0031] In one embodiment, each of the memory cell strings includes a plurality of ferroelectric field-effect transistors serving as memory cells. As Figure 2 shown, among the plurality of ferroelectric field-effect transistors 100 of the memory cell string 300, there are cut ferroelectric field-effect transistors 110 divided by the trench area. Here, when manufacturing the memory cell string 300, the whole semiconductor material including the ferroelectric field-effect transistors 100 is cut by cutting to obtain a plurality of memory cell strings 300. During the cutting, some of the ferroelectric field-effect transistors 100 will be cut, and the ferroelectric field-effect transistors 100 remaining on one side of the memory cell string 300 after being cut are the cut ferroelectric field-effect transistors 110. Further, the low dielectric constant material 200 is disposed on the side of the cut ferroelectric field-effect transistor 110 facing the trench area. In the embodiment provided by this application, the low dielectric constant material is disposed at the cut surface of the cut ferroelectric field-effect transistor. After the cut ferroelectric field-effect transistor is in the storage state, the low dielectric constant material disposed at the cut surface of the cut ferroelectric field-effect transistor can reduce the coupling effect caused by the cut ferroelectric field-effect transistor, avoid affecting the ferroelectric field-effect transistors of the adjacent memory cell strings, and improve the stability of the memory device of the ferroelectric field-effect transistor based on the gate-all-around structure.
[0032] In one embodiment, Figure 3 The structural plan view of the ferroelectric field-effect transistor 100 is given. As Figure 3As shown, the ferroelectric field-effect transistor 100 includes an oxide filling layer 111, a polysilicon channel 112, and a hafnium-based ferroelectric layer 113. Among them, the polysilicon channel 112 surrounds the oxide filling layer 111 within the polysilicon channel 112, and the hafnium-based ferroelectric layer 113 surrounds the oxide filling layer 111 and the polysilicon channel 112 within the hafnium-based ferroelectric layer 113. Further, the oxide filling layer 111, the polysilicon channel 112, and the hafnium-based ferroelectric layer 113 are nested layer by layer in the form of concentric circles, with the center of the concentric circles being the oxide filling layer 111. Outside the hafnium-based ferroelectric layer 113 is the Block, and outside the Block is the gate metal Gate.
[0033] Further, as Figure 4 shown, in the current memory device of the ferroelectric field-effect transistor based on the gate-all-around structure, the trench region is filled with silicon dioxide SiO2, and the dielectric constant of this material is too high, which easily causes a coupling effect between ferroelectric field-effect transistors. Further, as Figure 5 shown, Figure 5 On the right side is a pair of adjacent memory cell strings 300, Figure 5 and on the left side are a pair of cut ferroelectric field-effect transistors 110 in this pair of memory cell strings 300. The trench region between the cut ferroelectric field-effect transistors 110 is filled with a low dielectric constant material 200. Each of the cut ferroelectric field-effect transistors 110 also includes an oxide filling layer 111, a polysilicon channel 112, and a hafnium-based ferroelectric layer 113. Filling the trench region with the low dielectric constant material 200 can significantly reduce the coupling effect between adjacent memory cell strings 300. In this embodiment, filling the trench region with the low dielectric constant material 200 can significantly reduce the coupling effect between the cut ferroelectric field-effect transistor 110 and the cut ferroelectric field-effect transistor 110 in the adjacent memory cell string. The embodiment provided by the present application can significantly reduce the coupling effect between adjacent memory cell strings, thereby improving the storage reliability of the memory array during data retention.
[0034] In one embodiment, the dielectric constant of the low dielectric constant material is less than or equal to 4 to meet the purpose of reducing the coupling effect between adjacent memory cell strings. Specifically, the low dielectric constant material can be a low dielectric constant material based on a silicon-based polymer; further, the low dielectric constant material can also include an air-gap, where the air-gap has the lowest dielectric constant, up to 1.0; here, if the requirement for the structural stability of the memory array is relatively low, the air-gap can be used as the low dielectric constant material to achieve a better effect of reducing the coupling effect. Further, the low dielectric constant material can include a low dielectric constant material based on carbon-doped silicon oxide. Further, the low dielectric constant material can also be one of an inorganic insulating material, a carbon-doped oxide, porous silicon dioxide, and a spin-on silicon-based polymer dielectric. The embodiments provided in the present application provide a variety of materials as the low dielectric constant material, which can adapt to the requirements of different memory devices for materials, and improve the adaptability of the memory device based on the gate-all-around structure ferroelectric field effect transistor to different usage requirements.
[0035] In one embodiment, the distance between every two adjacent memory cell strings in the same stacked layer is greater than or equal to a preset interval length. Here, the distance between every two adjacent memory cell strings can be the width of the trench region or the thickness of the low dielectric constant material; the interval length can be determined in advance according to tests or experiments. Through tests or experiments, the thickness that the low dielectric constant material needs to reach to minimize the coupling effect is determined. The embodiments provided in the present application can design the distance between two adjacent memory cell strings according to the thickness required for the low dielectric constant material to minimize the coupling effect, so as to better reduce the coupling effect between the memory cells on both sides of the trench region and improve the storage reliability of the memory array of the memory device during data retention.
[0036] In one embodiment, the memory device based on the gate-all-around structure ferroelectric field effect transistor includes a plurality of stacked layers, and each of the stacked layers includes a plurality of memory cells. Specifically, a plurality of stacked layers are stacked to form a three-dimensional memory device. Each stacked layer includes a plurality of memory cell strings. In the plurality of memory cell strings in the same stacked layer, the trench region between any two adjacent memory cell strings is filled with a low dielectric constant material, effectively reducing the coupling effect between the memory cells on both sides of the trench region and improving the storage reliability of the memory device based on the gate-all-around structure ferroelectric field effect transistor during data retention.
[0037] The above serial numbers of the present application are only for description and do not represent the advantages or disadvantages of the implementation scenarios. The above-disclosed are only several specific implementation scenarios of the present application. However, the present application is not limited thereto, and any changes that can be thought of by those skilled in the art should fall within the protection scope of the present application.
Claims
1. A memory device based on a ferroelectric field-effect transistor with a gate-all-around structure, wherein the memory device uses a ferroelectric field-effect transistor as a memory cell, and is characterized in that, The memory device of the ferroelectric field-effect transistor based on a gate-all-around structure includes a plurality of memory cell strings; Each of the memory cell strings includes a plurality of the ferroelectric field-effect transistors. In the memory device of the ferroelectric field-effect transistor based on a gate-all-around structure, a trench region formed after etching is provided between every two adjacent memory cell strings in the same stacked layer; The trench region is filled with a low-k dielectric material to reduce the coupling effect between the memory cells in the adjacent memory cell strings.
2. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 1, wherein Each of the memory cell strings includes a plurality of ferroelectric field-effect transistors serving as memory cells. Among the plurality of ferroelectric field-effect transistors in the memory cell string, there are cut ferroelectric field-effect transistors divided by the trench region; The low-k dielectric material is disposed on a side of the cut ferroelectric field-effect transistor facing the trench region.
3. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 2, wherein The ferroelectric field-effect transistor includes an oxide filling layer, a polysilicon channel, and a hafnium-based ferroelectric layer; The polysilicon channel surrounds the oxide filling layer therein, and the hafnium-based ferroelectric layer surrounds the oxide filling layer and the polysilicon channel therein.
4. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 1, characterized in that The dielectric constant of the low-k dielectric material is less than or equal to 4.
5. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 4, wherein The low-k dielectric material includes an inorganic insulating material.
6. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 4, characterized in that, The low-k dielectric material includes a carbon-doped oxide.
7. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 4, characterized in that, The low-k dielectric material includes a low-k dielectric material based on carbon-doped silicon oxide.
8. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 3, wherein, The oxide filling layer, the polysilicon channel, and the hafnium-based ferroelectric layer are nested layer by layer in a concentric circle form.
9. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to claim 1, characterized in that, The distance between every two adjacent memory cell strings in the same stacked layer is greater than or equal to a preset interval length.
10. The memory device of the ferroelectric field effect transistor based on a gate-all-around structure according to any one of claims 1-9, characterized in that, The memory device of the ferroelectric field-effect transistor based on a gate-all-around structure includes a plurality of stacked layers, and each of the stacked layers includes a plurality of memory cells.