Cross point memory device

Abstract

There is provided a cross-point memory device including: a first access line and a second access line defining a plurality of cross-points; a memory cell connected between the first access line and the second access line at each intersection point and including a resistive memory element switchable between a first resistive state and a second resistive state; wherein each first access line includes a metal layer and a semiconductor layer continuously extending in a first direction to define a distributed Schottky diode forming a selector device of the memory cell; and wherein the internal nodes of each pair of consecutive memory cells along each respective first access line are connected by a respective segment of the semiconductor layer defining a semiconductor channel configured to gate through the metal layer of its associated first access line; and a read circuit configured to read the resistive memory elements of the selected memory cells connected to the selected first access line and the selected second access line.

Description

Technical Field

[0001] The present invention generally relates to a cross-point memory device. Background Art

[0002] A cross-point memory array includes a plurality of parallel word lines and a plurality of parallel bit lines, which are arranged to extend over and across each other to define a cross-point array. Resistive memory elements (such as phase change memory (PCM), magnetic tunnel junctions (MTJ) with voltage-controlled magnetic anisotropy (VCMA), or other unipolar memory elements) can be connected between the word line and the bit line at each cross-point to implement a dense memory cell array with a small area footprint.

[0003] However, a significant drawback of such a cross-point memory array is that during write and read operations, significant leakage current is generated through the semi-selected memory cells. This is shown in Figure 1 a schematic diagram of a cross-point memory array including word line WL and bit line BL and memory elements at each cross-point. The solid line path indicates the sense current, and the dashed line path indicates the sneak current through the non-selected memory cells.

[0004] To suppress these so-called sneak currents, a highly non-linear two-terminal selector device can be stacked and connected in series with the resistive memory element at each cross-point to define a 1D1R memory cell (D - diode, R - resistive memory element) at each cross-point. In the case of unipolar memory technologies such as PCM or VCMA MTJ, a Schottky diode is generally considered a good and reasonable choice. Figure 2 An example of two 1D1R memory cells at adjacent cross-points between a word line WL and two bit lines BL and BL +1 is schematically shown, with each memory cell including a Schottky diode as the selector device stacked on top of the VCMA - MTJ memory element.

[0005] While the use of a Schottky diode eliminates the need for a select transistor in each memory cell (which incurs a significant area penalty), the challenge with 1D1R memory cells is the loss of read margin (e.g., tunneling magnetoresistance ratio (TMR) in the case of VCMA). The reduced read margin can be attributed to the voltage drop across the Schottky diode selector device, which will tend to differently affect the sense current through the memory cell depending on the resistance state, thereby reducing the effective resistance ratio between the high-resistance state and the low-resistance state of the memory element.

[0006] Therefore, there is a need for an improved design of a cross-point memory device that realizes the area benefits and small leakage current of a 1D1R implementation, but avoids or mitigates the reduction in read margin. Summary of the Invention

[0007] The object of the present invention is to solve at least some of the above problems. Accordingly, the above object is to provide an improved design of a 1D1R-based cross-point memory device to reduce or limit the read margin degradation.

[0008] Accordingly, in a first aspect of the present invention, there is provided a cross-point memory device, comprising:

[0009] a first access line and a second access line, the first access line extending in a first direction and the second access line extending in a second direction across the first direction to define a plurality of cross-points between the first and second access lines; and

[0010] memory cells, each connected between the first access line and the second access line at each cross-point and including a resistive memory element switchable between a first resistance state and a second resistance state;

[0011] wherein each first access line includes a metal layer and a semiconductor layer, the semiconductor layer extending continuously in the first direction to define a distributed Schottky diode forming a respective selector device of each memory cell, wherein the selector device and the resistive memory element of each memory cell are connected in series between the associated first and second access lines via an internal node of the respective memory cell; and

[0012] wherein the internal nodes of each pair of consecutive memory cells along each respective first access line are connected by a respective segment of the semiconductor layer, the segment defining a semiconductor channel configured to be gated through the metal layer of its associated first access line;

[0013] the memory device further includes a read circuit configured to read the resistive memory element of a selected memory cell connected to a selected first access line and a selected second access line by applying a select voltage to the metal layer of the selected first access line, a reference voltage to the selected second access line, a first deselect voltage to the metal layer of a non-selected first access line, and a second deselect voltage to the non-selected second access line,

[0014] wherein the select voltage, the reference voltage, and the first and second deselect voltages are set such that:

[0015] the selector device of the selected memory cell is forward biased at a voltage exceeding the threshold voltage of the selector device,

[0016] the selector device of the non-selected memory cell is either forward biased at a sub-threshold voltage, or substantially zero biased, or reverse biased, and

[0017] The offset current flows from the unselected second access line into the internal node of the selected memory cell via the semiconductor channel connected to the selected memory cell.

[0018] The cross-point memory device of the first aspect is based on the idea that by extending the semiconductor layer of the Schottky diode selector (usually used separately for each memory cell) of each memory cell along the length of each first access line, each first access line can provide the following dual functions: defining a separate Schottky diode selector for each memory cell along the first access line, and defining a corresponding metal-semiconductor field-effect transistor MESFET having a lateral semiconductor channel, interconnecting the internal nodes of each pair of consecutive memory cells along the first access line, and having a variable resistance controllable by the voltage applied to the first access line (more specifically, the voltage applied to the associated gate / metal line of the first access line).

[0019] Although the diode selector of the memory cell contributes to selective read and sneak current suppression, the lateral semiconductor channel of the MESFET can provide a controllable offset current to the internal node of the selected memory cell to compensate for the voltage drop across the selector device, thereby increasing the difference between the sensed currents obtained in the high-resistance state and the low-resistance state of the memory element. Therefore, the select voltage applied to the metal line of the selected first access line will serve both as the select voltage for the selector device of the selected memory cell and as the gate voltage for the MESFET along the selected first access line.

[0020] Since the selector device of the selected memory cell is forward-biased at a voltage exceeding the threshold voltage of the selector device, the sensed current (interchangeably referred to as the read current) can be conducted through the selected first access line to and through the memory cell. The total current through the selected memory cell will be the sum of the offset current received from the unselected second access line via the MESFET channel and the sensed current received from the selected first access line via the selector device of the selected memory cell. Therefore, due to the internal gain of the selected memory cell, even a small resistance (and thus voltage) difference between the resistance states of the resistive memory element may be amplified.

[0021] The semiconductor channel defined along the corresponding first access line can generally exhibit a channel resistance that decreases as the gate voltage increases. The term "gate voltage" herein refers to the voltage between the metal layer configured to gate the corresponding lateral semiconductor channel and any one of the interconnected internal nodes. Referring to the selected memory cell, the gate voltage can more specifically refer to the voltage between the metal layer of the selected first access line and the internal node of the selected memory cell. In view of the foregoing discussion of the MESFET, the first access line can define an n-channel type MESFET, where the internal node of the selected memory cell can serve as the source of the MESFET to which it is connected.

[0022] Since the selector devices of the non-selected memory cells are either forward-biased at sub-threshold voltages, or substantially zero-biased, or reverse-biased, the sneak current through the selector devices of the non-selected memory cells can be effectively suppressed.

[0023] Accordingly, with appropriate selection of the select voltage, reference voltage, and first and second deselected voltages, the cross-point memory device of the first aspect can provide sneak current suppression associated with conventional 1D1R memory cells while avoiding or mitigating the read margin degradation associated with such memory cells. In fact, as can be understood from the following, the memory device is even capable of amplifying the read margin beyond the resistance ratio that would be provided by the resistive memory element of a 1R memory cell.

[0024] Since the bias current is provided via the adjacent non-selected memory cells along the selected first access line and the MESFET is integrally formed with the first access line, the above technical effects can be provided without increasing the area occupation.

[0025] In addition, from the perspective of manufacturability, note that since etching of the Schottky diode stack is required, conventional 1D1R cells may encounter material-related scaling issues. For example, semiconductor layers such as InGaZnO (IGZO) may suffer from sidewall damage caused by etching, which results in an increase in reverse leakage current. For aggressively scaled dimensions, this problem becomes particularly evident, where the perimeter contribution easily overwhelms the normal area-related diode current. In this regard, the distributed Schottky diode configuration of the memory device of the present aspect can be beneficial since the resulting diode structure is only limited in orientation. This can significantly improve the overall diode characteristics without affecting the area occupation. In a sense, the distributed Schottky diode selector can be useful for certain semiconductor materials (e.g., oxide semiconductors such as IGZO), even without the additional benefit of read margin amplification.

[0026] The term "internal node" of a memory cell herein refers to a circuit node between or shared by the selector device and the memory element of the memory cell. The internal node can, for example, correspond to an electrode of the memory element arranged in ohmic contact with the semiconductor layer of the corresponding Schottky diode selector.

[0027] As used herein, the term "selected" in "selected memory cell" refers to any one of the memory cells of the memory device that is selected for reading (or writing) during a read operation (or a write operation as described below). Thus, the "selected" first and second access lines correspond to the respective first and second access lines among the plurality of first and second access lines that are connected to the selected memory cell (i.e., the memory cell that is selected for reading (or writing)).

[0028] The term "reference voltage" as used herein refers to a voltage relative to which select and deselect voltages are defined. The reference voltage can typically correspond to a ground reference voltage (GND, i.e., approximately 0 V), but more generally can correspond to a low-level supply voltage (e.g., VSS).

[0029] The term "resistive memory element" as used herein refers to any conventional type of memory element that can be switched between a high-resistance state and a low-resistance state, such as a unipolar resistive memory element, such as a voltage-controlled magnetic anisotropy (VCMA) resistive memory element or a phase-change memory element.

[0030] In some embodiments, the gate threshold voltage of each lateral semiconductor channel is lower than the threshold voltage of the selector device, where the select voltage, reference voltage, and first and second deselect voltages are set such that the gate voltage of the lateral semiconductor channel along the selected first access line exceeds the gate threshold voltage, and such that the gate voltage of the lateral semiconductor channel along the non-selected first access line is less than the gate threshold voltage.

[0031] The "gate threshold voltage" of a lateral semiconductor channel as used herein refers to the minimum gate voltage required to form a lateral conductive channel between interconnect internal nodes. When the MESFET defined along the selected first access line is turned on, the selector device of the non-selected memory cell along the selected first access line will be forward-biased, substantially zero-biased, or reverse-biased at a sub-threshold voltage. At the same time, the MESFET along the non-selected first access line can be turned off to effectively suppress the lateral sneak current between memory cells along the non-selected first access line.

[0032] In some embodiments, the first and second resistance states of the resistive memory element are associated with a first resistance and a second resistance that exceeds the first resistance, respectively, and wherein, in response to the select voltage, reference voltage, first deselect voltage, and second deselect voltage applied to the first and second access lines by the read circuit during a read of a selected memory cell, each lateral semiconductor channel connected to the internal node of the selected memory cell exhibits a first channel resistance that exceeds the second resistance of the second resistance state, and the channel resistance of each other lateral semiconductor channel along the selected first access line exceeds the first channel resistance.

[0033] Thus, the semiconductor channels defined along the respective first access lines can exhibit channel resistance depending on the associated gate voltage such that the select and deselect voltages applied by the read circuit during a read result in a lower channel resistance in the lateral semiconductor channels connected to the selected memory cell than in the other lateral semiconductor channels along the selected first access line. Thus, lateral current conduction into the internal nodes of non-selected memory cells can be restricted or reduced.

[0034] In some embodiments, the first channel resistance is at least twice the second resistance of the second resistance state of the resistive memory element. Accordingly, the risk of disturbing non-selected memory cells adjacent to the selected memory cell (which correspondingly provides a bias current) can be reduced. In addition, the influence of the (variable) resistance of the memory elements of non-selected adjacent memory cells on the bias current can be limited.

[0035] In embodiments where the lateral semiconductor channel is configured to exhibit different threshold voltages (as described above), the first channel resistance can be defined by the on-state resistance of the lateral semiconductor channel. Correspondingly, the channel resistances of other lateral semiconductor channels can be defined by the off-state resistance. Here, the "on-state resistance" and "off-state resistance" respectively refer to the corresponding resistances (or resistance values) of the corresponding lateral semiconductor channels when the gate voltage exceeds the threshold voltage and when the gate voltage is less than the threshold voltage. The "off-state resistance" can particularly refer to the resistance of the corresponding lateral semiconductor channel when the gate voltage is lower than the threshold voltage by a certain amount such that the subthreshold leakage is substantially zero. Since the bias conditions of non-selected memory cells along the selected and non-selected second access lines may be different, it should be understood that the off-state resistance may vary between lateral semiconductor channels.

[0036] In some embodiments, the second deselected voltage corresponds to or is greater than the selected voltage. This achieves substantially zero biasing or reverse biasing of non-selected selector devices. More specifically, if the second non-selected voltage corresponds to the selected voltage, the non-selected selector devices along the selected first access line can be substantially zero-biased. At the same time, the non-selected selector devices along the non-selected first access line can be reverse-biased (under the reasonable assumption that the first deselected voltage does not exceed the selected voltage). On the other hand, if the second deselected voltage is greater than the selected voltage (and assuming this also applies to the first deselected voltage), all non-selected selector devices can be reverse-biased. In the case where the MESFET is not fully turned off at zero gate bias, this may further help to avoid or minimize the subthreshold leakage through the MESFET. That is, the second deselected voltage can exceed the selected voltage by a certain amount such that the subthreshold leakage through the lateral semiconductor channel is substantially zero.

[0037] A voltage (such as a second deselect voltage) “corresponding to” another voltage (such as a select voltage) herein means that the voltages are substantially matched or substantially equal. That is, “corresponding” voltages means that the voltages are not necessarily exactly equal to each other, but may differ from each other to some extent. For example, such differences may be at least partially attributed to process voltage temperature (PVT) variations. For example, the “corresponding” voltages may differ from each other by at most 10%, at most 5%, or at most 2%. Thus, voltages with differences within these ranges can be considered “corresponding” (i.e., substantially matched or substantially equal) because these differences will be small enough so as not to fundamentally change the read (and write) operations of the memory device.

[0038] In some embodiments, the first deselect voltage corresponds to or is lower than a reference voltage. By biasing the metal layer of the unselected first access line, the lateral resistance of the lateral semiconductor channel between the unselected memory cells can be further increased to further mitigate the sneak current. Assuming the reference voltage corresponds to ground, the first deselect voltage can accordingly be a negative voltage.

[0039] Providing a distributed Schottky diode and MESFET formed integrally with the first access line further allows selective programming of individual memory cells to be achieved through a biasing scheme similar to the biasing scheme during read, and effective sneak current suppression through the unselected memory cells.

[0040] Thus, in some embodiments, the memory device further includes a write circuit configured to program the resistance state of the resistive memory element of the memory cells selected for writing (hereinafter referred to as “second selected memory cells”) by: applying a write voltage to the corresponding first access line connected to the second selected memory cells, applying a reference voltage to the corresponding second access line connected to the second selected memory cells, applying a first write deselect voltage to the unselected first access lines, and applying a second write deselect voltage to the unselected second access lines (i.e., the first and second access lines not connected to the selected second memory cells),

[0041] wherein the select voltage, the reference voltage, and the first and second write deselect voltages are set such that: the selector device of the memory cells selected for writing is forward biased at a voltage exceeding the threshold voltage of the selector device, the resistive memory element of the memory cells is biased at a voltage exceeding the resistance state switching threshold voltage of the resistive memory element, and the selector devices of the unselected memory cells are either forward biased at a subthreshold voltage, substantially zero biased, or reverse biased.

[0042] Accordingly, selective programming of the resistive memory elements of the second selected memory can be provided while limiting the sneak current through the non-selected memory cells, which may tend to reduce the power efficiency of the write operation.

[0043] In view of the above discussion of the meaning of the term "selected memory cell", it can be understood that the label "second" in "second selected memory cell" is merely a label introduced for convenience of reference to the memory cell selected for writing. That is, the "second selected memory cell" can be any memory cell of the cross-point memory device, i.e., a memory cell different from the above-mentioned "selected memory cell" (which can be correspondingly referred to as the "first selected memory cell") referred to in the discussion of the read operation or the same memory cell as the first selected memory cell.

[0044] The reference voltage applied to the second access line connected to the second selected memory cell can generally be (but is not limited to) the same reference voltage as that applied to the selected second access line connected to the first selected memory cell during reading. This can reduce the complexity of the read / write scheme and the number of bias generators required to generate the various voltages of the read / write scheme.

[0045] By specifically setting the second write deselect voltage to correspond to the write voltage, the selector device of the non-selected memory cell connected to the same first access line as the second selected memory cell can be substantially zero-biased, thereby suppressing the leakage current therethrough.

[0046] In some embodiments, the first write deselect voltage corresponds to or is lower than the reference voltage. In view of the above discussion of the effect of the gate voltage on the lateral channel resistance, it can be understood that the first write deselect voltage corresponding to or being lower than the reference voltage can increase the channel resistance, thereby suppressing leakage.

[0047] In some embodiments, each segment of the semiconductor layer extends between a pair of electrode contact portions of the semiconductor layer, and each electrode contact portion makes an ohmic contact with the electrode of the corresponding resistive memory device, wherein the thickness dimension of the electrode contact portion exceeds the thickness dimension of the segment.

[0048] The thickness dimension of the semiconductor layer is changed along the length of the first access line such that the local thickness of the semiconductor layer at the diode selector of each memory cell is greater than the local thickness along the segment, thereby allowing the diode selector and the lateral semiconductor channel of the MESFET to be optimized separately. Thereby, the off-state leakage of the selector device can be effectively suppressed while the on-state current of the selector device remains substantially unaffected and the lateral channel thickness (and thus the channel resistance) can be kept constant.

[0049] In some embodiments, each segment of the semiconductor layer of each first access line extends between a pair of electrode contact portions of the semiconductor layer, each electrode contact portion being in ohmic contact with an electrode of a corresponding resistive memory device, wherein the doping concentration of the segment is lower than that of the electrode portion. Thus, the channel resistance of the lateral semiconductor channel of the MESFET can be increased without reducing the on-state current of the selector device.

[0050] In some embodiments, the semiconductor layer of each first access line comprises an oxide semiconductor layer. Oxide semiconductors enable a back-end-of-line compatible implementation and are present in many compositions having a mobility suitable for providing a lateral bias current between memory cells as described above. A suitable example is an InGaZnO (IGZO) layer.

[0051] In some embodiments, the metal layer of the first access line comprises a continuous first metal sublayer and a continuous second metal sublayer of a work function metal, the continuous second metal sublayer of the work function metal being disposed between the first metal sublayer and the semiconductor layer and defining a distributed Schottky diode together with the semiconductor layer. Thus, a metal layer with a suitable work function can be provided for Schottky contact with the semiconductor layer, while a separate low-resistance metal can be provided to reduce the resistance of the first access line. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] This and other aspects of the invention will now be described in more detail with reference to the drawings showing embodiments of the invention.

[0053] Figure 1 is a schematic perspective view of a conventional cross-point memory array.

[0054] Figure 2 is a schematic diagram of a conventional 1D1R memory cell.

[0055] Figure 3a -c respectively show a circuit diagram of a conventional 1D1R memory cell, a graphical bias point analysis of the 1D1R memory cell in two resistive memory element states, and an estimation of the TMR drop due to the voltage drop across the selector diode.

[0056] Figure 4 is a schematic perspective view of a cross-point memory device according to an embodiment.

[0057] Figure 5 is along Figure 4 a representative detailed schematic cross-section of a first access line of the cross-point memory device.

[0058] Figure 6Shows the simulation of the drain-to-source current of a MESFET defined along a first access line and the diode selector current due to the gate-to-source voltage of the metal layer applied to the first access line.

[0059] Figure 7 Is a circuit diagram showing the flow of the bias current into the internal node of the selected memory cell during a read operation.

[0060] Figure 8 Is a simplified circuit diagram showing the effect of providing a bias current to the internal node of the memory cell.

[0061] Figure 9 Shows the simulation of the current through the selected memory cell and its five nearest neighbor memory cells along the selected first access line under an example read bias scheme.

[0062] Figure 10 Is a schematic perspective view of a cross-point memory device during a write mode according to an embodiment. Detailed Description

[0063] Figure 3a Is a circuit diagram of a conventional 1D1R memory cell. In the depicted example, the resistive memory element (hereinafter abbreviated as ME) is a magnetic tunnel junction (MTJ) having voltage-controlled magnetic anisotropy (VCMA), which means that the ME can be switched between a lower resistance state P and a higher resistance state AP. However, the following description equally applies to any other unipolar ME that can be switched between low and high resistance states, such as a PCM-based ME. For the sake of simplicity, assume that the resistance R VMCA Of the example ME is 100 kΩ in the low resistance state and 200 kΩ in the high resistance state, which translates to a resistance ratio (equivalent to the TMR of the MTJ) of 100%. However, when reading a 1D1R cell, due to the additional voltage drop across the diode selector, the effective resistance ratio will become much less than this intrinsic resistance ratio. In Figure 3a The arrow without a filled pattern indicates the magnitude of the sense current I Read In the high resistance state (where I Read Is approximately 1.3 μA), and the arrow with diagonal shading indicates the magnitude of the sense current I Read In the low resistance state (where I Read Is approximately 2.0 μA). As shown in Figure 3bAs shown in the bias point analysis, the decrease in read margin can be quite significant. For example, assuming the selector diode has a diode ideality factor n = 5, and assuming a read voltage of 0.8V, the voltage offset between the low resistance state and the high resistance state can be as small as 60mV. Thus, the effective resistance ratio is reduced by 46%, rather than the initial resistance ratio of 100%. More specifically, when the ME switches from the high resistance state (200 kΩ) to the low resistance state (100 kΩ), this voltage offset corresponds to an additional voltage drop across the diode selector, where the voltage across the ME is effectively reduced (since the total 1D1R voltage remains constant at 0.8V). Therefore, the current through the 1D1R will be less than the expected doubling. Although a smaller diode ideality factor n reduces the decrease in the resistance ratio, this effect still exists even for an ideal diode (n = 1).

[0064] Figure 4 is a schematic perspective view of a cross-point memory device 100 having a design for mitigating the Figure 3a read margin degradation shown in -c according to one embodiment.

[0065] The cross-point memory device is a memory device including a cross-point array. As depicted, the cross-point array of the memory device 100 includes a plurality of first access lines WL extending in parallel in a first direction X and spaced apart (e.g., equidistantly) in a second direction Y transverse to the first direction X. As shown, the first and second directions X, Y define respective horizontal directions, where "horizontal" means a direction parallel to the plane of extension of the substrate 101 of the memory device 100. The array further includes a plurality of second access lines BL extending in parallel in the second direction Y. A plurality of cross-points are thus defined between the first and second access lines WL, BL, each cross-point being defined at the intersection between a respective first access line and a respective second access line. The first and second access lines can be Figure 4 as indicated by their respective names "WL" and "BL", defining the word lines and bit lines of the cross-point array. Figure 4 Only a small number of the first access lines WL1, WL2, WL3 and the second access lines BL1, BL2, BL3, BL4, BL5 are shown, however the memory device 100 typically may include a much larger number of first and second access lines.

[0066] The memory device 100 further includes being arranged at each cross-point and connected between the first access line WL and the second access line BL at the cross-point 102. As Figure 5As more clearly shown in the detailed view, a cross-section of a first access line WL representative of any one of the first access lines WL1 - WL3 shown in FIG. 3 is shown. Each memory cell 103 includes a resistive memory element (ME) 104. The ME 104 can be switched between a first resistive state and a second resistive state. The ME 104 can be, for example, a unipolar resistive memory element such as a VCMA-based ME or a PCM-based ME.

[0067] Each memory cell 103 also includes a corresponding Schottky diode selector 105, which is connected in series with the ME 104 of the memory cell 104 between the associated first and second access lines WL, BL. Thus, each memory cell 104 is a 1D1R cell. In contrast to this implementation of the memory cell, the corresponding diode selectors along each respective first access line WL instead form part of a distributed Schottky diode selector memory device 100. As shown, in Figure 5 each first access line includes a metal layer 106 and a semiconductor layer 108, which extends continuously in a first direction X to define a distributed Schottky diode forming the corresponding selector device 105 of each memory cell 103. The selector device 105 and the ME 104 of each memory cell 103 are connected in series between the first and second access lines WL, BL via an internal node 103i of the respective memory cell 103. In addition, the internal nodes 103i of each pair of consecutive memory cells 103 along each respective first access line WL are connected by a corresponding segment 108a of the semiconductor layer 108. The segment 108a defines a lateral semiconductor channel (also indicated hereinafter by the reference numeral 108a) configured to be gated by the associated metal layer 106 of the first access line WL. Thus, as Figure 5 shown, the first access line WL includes a plurality of MESFETs, which are integrally formed with the first access line WL1 and include a lateral semiconductor channel 108a formed by the segment of the semiconductor layer 108 and a gate formed by the metal layer 106 of the first access line WL. The internal nodes 103i of each pair of consecutive memory cells 103 along the first access line WL are interconnected by the lateral semiconductor channel 108a of a corresponding one of these MESFETs.

[0068] Each of the segments and channels 108a shown can extend between a pair of electrode contacts 108b of the semiconductor layer 108 (schematically represented by the dashed regions). Each electrode contact 108b makes an ohmic contact with an electrode 104a (the top electrode in the example shown) of the corresponding ME 104. This pair of electrode contacts 108b can define the source and drain of the corresponding MESFET. In Figure 5In the schematic diagram, the internal node 103i is indicated to be at a certain distance from the top electrode 104a of the corresponding ME 104 within the electrode contact portion 108b. However, it can be understood that this position is somewhat arbitrary and can also be considered to be only juxtaposed with the top electrode 104a.

[0069] Using an appropriate biasing scheme, the selector device 105 of the memory cell 103 allows selective readout and suppresses sneak current. At the same time, as will be further described below, the lateral semiconductor channel 108a of the MESFETs interconnecting the memory elements 103 can provide a controllable bias current to the internal node 103i of the selected memory cell 103s during a read operation to compensate for the voltage drop across the selector device 105 and thereby increase the total current through the memory element 104 of the selected memory cell 103s. Therefore, the select voltage applied to the metal line 106 of the selected first access line will serve both as the select voltage for the selector device 105 of the selected memory cell 103s and as the gate voltage for the MESFETs along the selected first access line.

[0070] The semiconductor layer 108 of the first access line WL can generally be an n-type semiconductor layer, where the lateral semiconductor channel 108a can define an n-type semiconductor channel. It will be assumed hereinafter that the MESFET includes an n-type lateral semiconductor channel 108a, the channel resistance of which decreases as the gate voltage increases. The MESFET can be configured to operate in enhancement mode (meaning the threshold voltage is about 0V or higher) or depletion mode (meaning the threshold voltage is below 0V). The semiconductor layer 108 can include an oxide semiconductor layer. Non-limiting examples include InGaZnO (IGZO), ZnO, InWO, InSnO, or GaZnO layers. The thickness of the semiconductor layer 108 can be selected in view of the target biasing conditions, on-state current, off-state current, etc.

[0071] As Figure 5As shown, the metal layer 106 may include a first metal sub-layer 106a and a continuous second metal sub-layer 106b of a work function metal (WFM). The continuous second metal sub-layer 106b of the work function metal is disposed between the first metal sub-layer 106a and the semiconductor layer 108 and together with the semiconductor layer 108 defines a distributed Schottky diode. The second metal sub-layer 106b may be formed of a metal having an appropriate work function (e.g., higher than the electron affinity of the semiconductor layer 108) to obtain a desired Schottky barrier height. For the IGZO semiconductor layer 108, a non-limiting example of the second metal sub-layer 106b is Pt. The first metal sub-layer 106a may be selected to achieve a low-resistance connection along the first access line WL to the memory cell 103. The first metal sub-layer 106a may be formed of one or more metals commonly used for metal line interconnections in the back-end-of-line, such as W, Al, Cu, etc. However, a single metal layer composition of the metal layer 106 is also possible as long as a WFM with a suitable work function and sufficiently low resistance is found.

[0072] Optionally, the doping concentration of the semiconductor layer 108 may vary along its length such that the doping concentration in the segment 108a is lower than the doping density in the electrode portion 108b. Thus, the channel resistance of the semiconductor channel 108a of the MESFET can be tuned without reducing the on-state current of the selector device 105.

[0073] Figure 5 An alternative variation of the first access line WL is further shown, where the thickness dimension t of the electrode contact portion 108b e exceeds the thickness dimension t of the segment 108a c . This design variation may be applied alone or in combination with different doping concentrations to optimize the diode selector and the lateral semiconductor channel of the MESFET separately.

[0074] A cross-point array including the first and second access lines WL, BL and the memory cell 103 may be included in the interconnect structure of the memory device 100. The first and second access lines WL, BL may be disposed in respective interconnect layers (metallization layers) of the interconnect structure. In the example shown, the first access line WL is disposed above the second access line BL, however the opposite configuration is also possible. In this case, the memory cell 103 will be disposed correspondingly above the first access line WL, and the second metal sub-layer 106b will be formed above the first metal sub-layer 106a. Additionally, the selector device 105 will be connected to the bottom electrode 104b of the ME 104.

[0075] Figure 6 Uploaded by along Figure 5The drain-to-source current I of the lateral semiconductor channel of the MESFET between a pair of consecutive memory elements of the first access line WL shown DS is simulated, and this current varies with the gate voltage Vg (i.e., the gate-to-source voltage). Further shown is the selector current (i.e., the gate-to-source current) I GS through the Schottky diode selector of one of the memory cells, which varies with the gate voltage. It can be seen that both the MESFET and the Schottky diode selector can exhibit their respective different gate threshold voltages, beyond which the drain-to-source current I DS and the selector current suddenly increase respectively. In the simulation shown, the gate threshold voltage of the MESFET is a negative voltage and lower than the threshold voltage of the diode selector. However, in general, the specific values of the gate threshold voltage and the selector threshold voltage depend on parameters such as the doping concentration of the semiconductor layer, the thickness of the semiconductor layer, and the Schottky barrier height. In any case, Figure 6 indicates that the first access line WL having the configuration as Figure 5 shown can simultaneously define a MESFET and a Schottky diode selector, which have their respective different threshold voltages that separate their respective off and on states. However, if the threshold voltages of the MESFET and the diode selector are substantially equal, the read and write operations described herein will also work.

[0076] Figure 7 is a circuit diagram showing how the MESFET of the first access line WL can conduct a bias current to the internal node of the selected memory cell 103s during a read. The selected memory cell 103s is located at the intersection between the first access line WL and the second access line BL that can correspond to the Figure 4 first and second access lines shown. The selected memory cell is biased by a selection voltage V read . By also applying the selection voltage V read to the non-selected bit lines BL -1 , BL +1 , BL -2 , BL +2 , the non-selected memory cells are substantially zero-biased. For simplicity, the MESFET circuit symbol is replaced here by a resistor symbol, where R lateral represents the channel resistance of the lateral semiconductor channel under the shown bias conditions. The consecutive internal nodes are interconnected along the first access line WL. Assuming that R lateral is quite large (e.g., comparable to or larger than the resistance of ME 104), the total bias current flowing into the internal node 103i will be composed of the currents from the two nearest neighboring bit lines (i.e., 2×I biasdominant because the resistance between the more distant bit line and the internal node 103i will be significantly greater. This may further help to limit the lateral current flow between the unselected memory cells 103 along the selected first access line WL. Thus, the lateral semiconductor channel 103 can be configured to exhibit a lateral channel resistance R equivalent to or exceeding the resistance of the high resistance state of the ME both in the on-state and the off-state of the MESFET lateral . More specifically, the "first channel resistance" R lateral,on represents the resistance of the lateral semiconductor channel of the MESFET in the on-state and the "second channel resistance" R lateral,off represents the resistance of the lateral semiconductor channel of the MESFET in the off-state. Each of the first channel resistance R lateral,on and the second channel resistance R lateral,off can exceed the resistance of the high resistance state of the ME, i.e., R lateral,on >R AP and R lateral,off >R AP . For example, R lateral,on and R lateral,off can each be at least 2 times R AP . On the other hand, if the first channel resistance R lateral,on is at most 15 times R AP , it can provide sufficient bias current for the actual range of read bias voltages. As another example, for R VCMA =R P or R VCMA =R AP , the ratio of the first channel resistance R lateral,on of the lateral semiconductor channel to the resistance R VCMA of the ME can be in the range of 5 - 10. This can achieve a reasonable balance between low read interference and sufficient bias current.

[0077] To facilitate understanding of the effect of providing bias current to the internal node of the selected memory cell, refer to Figure 8 , Figure 8 which shows a memory cell circuit diagram that is simplified to consider only a single bias current from one adjacent memory element instead of Figure 8 the two in Read . In the figure, the arrows without filled patterns respectively indicate the magnitudes of the sense current I bias received from the access line and the bias current I' Read in the high resistance state, and the arrows with diagonal shading respectively indicate the magnitudes of the sense voltage I bias and the bias current l'

[0078] As can be seen from the circuit diagram, the voltage V at the internal node VCMA is given by:

[0079]

[0080] where R VCMA represents the resistance of ME as before (e.g., R VCMA = R AP or R VCMA = R P ), and V bias corresponds to the voltage at the internal node of the adjacent memory element. The expression is a valid approximation when the current I Read through the diode selector is small compared to the bias current I' bias . The sense current I Read is then given by:

[0081]

[0082] The effective resistance ratio is then proportional to the following factors:

[0083]

[0083] TMR ~ exp(qΔV VCMA / nkT)

[0084] where ΔV VCMA is the difference in V VCMA = R AP and R VCMA = R P respectively. Table 1 shows the values of the bias current I' VCMA , V Read = 0.8V, the bias voltage V bias = V Read , R P = 100 kΩ and R AP = 200 kΩ. bias , I VCMA and TMR. Read

[0085]

[0086] Table 1

[0087] Therefore, as can be seen, the bias current can significantly increase the resistance ratio during reading.

[0088] Referring again to Figure 4, which shows a biasing scheme for reading selected memory cells 103s of a cross-point array. In the depicted example, the selected memory cells 103s are the memory cells among the memory cells 103 that are connected between a first access line WL2 and a second access line BL3. The biasing voltage for this read scheme can be provided by read circuits 110, 112. As is known in the art itself, the read circuits 110, 112 can include word line and bit line drivers, sense amplifier circuits, etc. The read circuits 110, 112 can be implemented by CMOS circuits in a manner known in the art. The active devices of the write circuits 110, 112 can be formed on the front side of the substrate 101, below the cross-point array.

[0089] In the figure, V Read represents the select voltage (or read voltage) applied to the selected first access line WL2, more specifically to its associated metal layer 106 (such as the first metal sub-layer 106a). V Ref represents the reference voltage applied to the selected second access line BL3. The reference voltage V Ref can typically be the ground reference voltage GND (i.e., approximately 0V). V WL-uns represents the first deselect voltage applied to the non-selected first access lines WL1, WL3, more specifically to its associated metal layer 106 (such as the first metal sub-layer 106a). V BL-uns represents the second deselect voltage applied to the non-selected second access lines BL1, BL2, BL4, BL5.

[0090] According to the read biasing scheme implemented by the read circuits 110, 112, the select voltage V Read , the reference voltage V Ref , and the first and second deselect voltages V WL-uns , V BL-uns are set such that:

[0091] - The selector device 105 of the selected memory cells 103s is forward biased at a voltage exceeding the threshold voltage of the selector device 105,

[0092] - The selector device 105 of the non-selected memory cells 103 is either forward biased at a sub-threshold voltage, or substantially zero biased, or reverse biased, and

[0093] - A sufficient bias current I bias flows from the non-selected second access lines BL1, BL2, BL4, BL5 through the lateral semiconductor channel 108a of the MESFET connected to the selected memory cells 103s into the internal node 103i of the selected memory cells 103s (see Figure 5 ).

[0094] In one example implementation, the reference voltage V Ref may correspond to ground (~0V), the select voltage V Read may be a positive voltage that exceeds the gate threshold voltage of the MESFET and the threshold voltage of the selector device 105, the first deselected voltage may be set to V WL-uns ≤V Ref and the second deselected voltage may be set to V BL-uns ≈V Read .

[0095] With this biasing scheme, the selector device 105 of the selected memory cells 103s can be turned on and forward biased so that the sense current can flow from the selected first access line WL2 into the selected memory cells 103s. At the same time, the selector device 105 of the non-selected memory cells 103 along the selected first access line WL2 can be forward biased at a subthreshold voltage or substantially zero biased (depending on the voltage drop across the associated ME 104) and thus remain off.

[0096] If V WL-uns ≈V Ref , the selector device 105 of the non-selected memory cells 103 along the non-selected first access lines WL1, WL3 can be reverse biased. If V WL-uns <V Ref , the selector device 105 of the non-selected memory cells 103 along the non-selected first access lines WL1, WL3 may be even more strongly reverse biased. Additionally, by setting the first deselected voltage V Ref less than V WL-uns , the gate voltage of the MESFETs along the non-selected first access lines WL1, WL3 can be negative, thereby increasing the lateral channel resistance R lateral along the non-selected first access lines WL1, WL3. This can further suppress the lateral sneak current between the memory cells 103 along the non-selected first access lines WL1, WL3 during a read.

[0097] Additionally, in response to the second deselected voltage V BL-uns ≈V Read acting as the gate voltage of the MESFETs along the selected first access line WL2 in combination with the select voltage V Read , a bias current can be provided to the internal node 103i of the selected memory cells 103s. As discussed above, the bias current will typically be dominated by the contribution of the nearest neighboring second access lines BL2 and BL4 to the selected second access line BL3.

[0098] Figure 9 Illustrates for the select voltage V ReadSimulation of the current through the selected memory cells along the first access line WL in an example read bias scheme. The lateral semiconductor channel is modeled as a fixed resistor R lateral = 2 MΩ. The ME of each memory cell is assumed to be in the first / low resistance state such that R VCMA = R P = 100 kΩ. The resulting bias current supplied to the internal node 103 of the selected memory cell is shown as 0.57 μA. This gives a sense current of 1.49 μA along the selected first access line. For R VCMA = R AP = 200 kΩ, the corresponding simulation is performed, giving a bias current of 0.54 μA and a sense current of 0.63 μA, which translates to a TMR of approximately 138%. Assuming the less favorable condition where the ME of all non-selected memory cells are set to the second / high resistance state, the bias currents and sense currents in the P and AP states become 0.55 μA / 0.52 μA and 1.51 μA / 0.64 μA respectively, which translates to a TMR of 134%.

[0099] From Figure 8 the derived expression for the internal node voltage V VCMA it can be seen that by increasing the ratio R VCMA / R lateral , the bias of the memory cell can be increased. Additionally, the internal node voltage V BL-uns can be increased by increasing the voltage V VCMA on the non-selected second access line. Specifically, as Figure 9 shown, V BL-uns can be increased by more than V Read by up to Δ. Thus, the selector device of the non-selected memory cell becomes reverse-biased. Therefore, the practical limit of Δ is determined by the maximum reverse-bias voltage that the selector device can withstand.

[0100] From Figure 8 the derived expression for the internal node voltage V VCMA it can be seen that by increasing the ratio R VCMA / R lateral , the bias of the memory cell can be increased. Additionally, the internal node voltage V BL-uns can be increased by increasing the voltage V VCMA on the non-selected second access line. Specifically, as Figure 9 shown, V BL-uns can be increased by more than V Read by up to Δ. Thus, the selector device of the non-selected memory cell becomes reverse-biased. Therefore, the practical limit of Δ is determined by the maximum reverse-bias voltage that the selector device can withstand.

[0101] In the figure, VWrite Denotes the write voltage (or program voltage) applied to the selected first access line WL2, more specifically to its associated metal layer 106 (e.g., the first metal sub-layer 106a). V Ref Denotes the reference voltage applied to the selected second access line BL3. The reference voltage V Ref Can typically be a ground reference voltage GND (i.e., approximately 0V). V WWL-uns Denotes the first write deselection voltage applied to the non-selected first access lines WL1, WL3, more specifically to its associated metal layer 106 (e.g., the first metal sub-layer 106a). V WBL-uns Denotes the second write deselection voltage applied to the non-selected second access lines BL1, BL2, BL4, BL5.

[0102] According to the write bias scheme implemented by the write circuits 110, 112, the write voltage V Write , the reference voltage V Ref and the first and second write deselection voltages V WWL-uns , V WBL-uns are set such that:

[0103] - The selector device 105 of the selected memory cell 103s is forward biased at a voltage exceeding the threshold voltage of the selector device 105,

[0104] - The ME 104 of the selected memory cell 103s is biased at a voltage exceeding the resistance state switching threshold voltage of the ME 104.

[0105] - The selector device 105 of the non-selected memory cell 103 is either forward biased at a sub-threshold voltage, or substantially zero biased, or reverse biased.

[0106] In one example implementation, the reference voltage V Ref can correspond to ground (~0V), the write voltage V Write can be a positive voltage exceeding the resistance state switching threshold voltage of the ME 104 and the threshold voltage of the selector device 105, the first write deselection voltage can be set to V WWL-uns ≤V Ref , and the second deselection voltage can be set to V WBL-uns ≈V Write .

[0107] With this biasing scheme, the selector device 105 of the selected memory cell 103s can be turned on and forward biased so that the write current can flow from the selected first access line WL2 into the selected memory cell 103s and through the ME 104. At the same time, the selector device 105 of the non-selected memory cell 103 along the selected first access line WL2 can be forward biased at a sub-threshold voltage or substantially zero biased (depending on the voltage drop across the associated ME 104) and thus remain off.

[0108] However, setting V WBL-uns ≈V Write results in a voltage difference that will drive a leakage current through the lateral semiconductor channel 108a of the MESFET ( Figure 5 shown) connected to the internal node 103e from the second access lines BL2, BL4 into the internal node 103i of the selected memory cell 103s. However, it is conceivable that when the lateral semiconductor channel of the MESFET is gated by a voltage at a typical level (e.g., 1 - 2V) for writing to the resistive memory element, the channel resistance R lateral of the lateral semiconductor channel of the MESFET is equivalent to or exceeds the resistance of the resistive memory element during programming so that the leakage current can be kept small enough to avoid write interference. Since during the write operation, the voltage of the internal node 103i of the selected cell 103s will increase significantly, resulting in a reduced voltage drop between the source and drain of the MESFET, low leakage is further achieved.

[0109] Turning to the first write deselection voltage, if V WLL-uns ≈V Ref , the selector devices 105 of the non-selected memory cells 103 along the non-selected first access lines WL1, WL3 can be reverse biased. If V WWL-uns <V Ref , the selector devices 105 of the non-selected memory cells 103 along the non-selected first access lines WL1, WL3 can be more strongly reverse biased and thus remain off. Additionally, by setting the first deselection voltage V Ref less than V WL-uns , the gate voltage of the MESFETs along the non-selected first access lines WL1, WL3 can be negative, thereby increasing the lateral channel resistance R lateral . This can further suppress the lateral sneak current between the memory cells 103 along the non-selected first access lines WL1, WL3 during writing.

[0110] Those skilled in the art will recognize that the present invention is in no way limited to the above-described embodiments. On the contrary, many modifications and variations are possible within the scope of the appended claims.

Claims

1. A cross-point memory device, comprising: a first access line and a second access line, the first access line extending in a first direction and the second access line extending in a second direction across the first direction to define a plurality of intersections between the first access line and the second access line; as well as a memory cell connected between the first access line and the second access line at each cross point and comprising a resistive memory element switchable between a first resistance state and a second resistance state; wherein each first access line comprises a metal layer and a semiconductor layer, the semiconductor layer extending continuously in the first direction to define a distributed Schottky diode, the distributed Schottky diode forming a corresponding selector device of each memory cell, wherein the selector device and the resistive memory element of each memory cell are connected in series between an associated first access line and a second access line via an internal node of the corresponding memory cell; and wherein the internal nodes of each pair of consecutive memory cells along each respective first access line are connected by respective segments of the semiconductor layer, the segments defining lateral semiconductor channels configured to be gated by the metal layer of their associated first access lines; The memory device further includes a read circuit configured to read the resistance memory element of the selected memory cell connected to the selected first access line and the selected second access line by applying a selection voltage to a metal layer of the selected first access line, applying a reference voltage to the selected second access line, applying a first deselection voltage to a metal layer of a non-selected first access line, and applying a second deselection voltage to a non-selected second access line, The selection voltage, the reference voltage, the first deselection voltage and the second deselection voltage are set such that: a selector device of the selected memory cell is forward biased at a voltage exceeding a threshold voltage of the selector device, The selector devices for the non-selected memory cells are either forward biased at a subthreshold voltage, substantially zero biased, or reverse biased, and A bias current flows from the non-selected second access line into the internal node of the selected memory cell via a semiconductor channel connected to the selected memory cell.

2. The memory device of claim 1 , wherein a gate threshold voltage of each lateral semiconductor channel is lower than a threshold voltage of the selector device, and wherein the selection voltage, the reference voltage, and the first and second deselection voltages are set so that a gate voltage of the lateral semiconductor channels along the selected first access line exceeds the gate threshold voltage and so that a gate voltage of the lateral semiconductor channels along the non-selected first access line is less than the gate threshold voltage.

3. The memory device of claim 1 , wherein the first resistance state and the second resistance state of the resistive memory element are respectively associated with a first resistance and a second resistance exceeding the first resistance, and wherein in response to application of the voltage by the read circuit during reading of the selected memory cell, each lateral semiconductor channel connected to the internal node of the selected memory cell exhibits a first channel resistance exceeding a second resistance of the second resistance state, and a channel resistance of each other lateral semiconductor channel along the selected first access line exceeds the first channel resistance.

4. The memory device of claim 3, wherein the first channel resistance is at least 2 times the second resistance value.

5. The memory device of claim 3, wherein the first channel resistance is an on-state resistance of the lateral semiconductor channel. 6 . The memory device of claim 1 , wherein the second deselect voltage corresponds to or is greater than the select voltage. 7 . The memory device of claim 1 , wherein the first deselection voltage corresponds to or is lower than the reference voltage.

8. The memory device of claim 1 , further comprising a write circuit configured to program a resistance state of a resistive memory element of a memory cell selected for writing by applying a write voltage to a corresponding first access line connected to the memory cell, applying a reference voltage to a corresponding second access line connected to the memory cell, applying a first write deselect voltage to a non-selected first access line, and applying a second write deselect voltage to a non-selected second access line, The selection voltage, the reference voltage, the first write deselect voltage and the second write deselect voltage are set so that: the selector device of the memory cell selected for writing is forward biased at a voltage exceeding the threshold voltage of the selector device, the resistance memory element of the memory cell is biased at a voltage exceeding the resistance state switching threshold voltage of the resistance memory element, and the selector devices of the non-selected memory cells are either forward biased at a subthreshold voltage, substantially zero biased, or reverse biased. 9 . The memory device of claim 8 , wherein the second write deselect voltage corresponds to the write voltage. 10 . The memory device of claim 9 , wherein the first write deselect voltage corresponds to or is lower than the reference voltage.

11. The memory device of claim 1 , wherein each segment extends between a pair of electrode contacts of the semiconductor layer, each electrode contact being in ohmic contact with an electrode of a corresponding resistive memory device, wherein a thickness dimension of the electrode contacts exceeds a thickness dimension of the segment.

12. The memory device of claim 1, wherein each segment extends between a pair of electrode contacts of the semiconductor layer, each electrode contact being in ohmic contact with an electrode of a corresponding resistive memory device, wherein a doping concentration of the segment is lower than a doping concentration of the electrode contacts. 13 . The memory device of claim 1 , wherein the semiconductor layer of each first access line comprises an oxide semiconductor layer, such as an IGZO layer.

14. A memory device as described in claim 1, wherein the metal layer includes a continuous first metal sublayer and a continuous second metal sublayer of a work function metal, and the continuous second metal sublayer of the work function metal is arranged between the first metal sublayer and the semiconductor layer, and together with the semiconductor layer defines the distributed Schottky diode.

15. The memory device of claim 1, wherein each memory device is a unipolar resistance memory element, such as a voltage-controlled magnetic anisotropic resistance memory element or a phase change memory element.

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